A B C D E F G H J K

0 VDD 0

VPP_MCLR
U1
VPP_MCLR 1 MCLR AVDD 40
RB0 2 AN0/VREF+/CN2/RB0 AVSS 39
VDD 3 38
RB1 AN1/VREF-/CN3/RB1 AN9/RB9 LCD_RS
J1 RB2 4 AN2/SS1/LVDIN/CN4/RB2 AN10/RB10 37 LCD_RW
5 36 VDD
1 RB3
6
AN3/CN5/RB3 AN11/RB11
35
LCD_E J2
1 2 RB4 AN4/CN6/RB4 AN121/RB12 LCD16x2 1
VDD 7 34
3 RB5 AN5/CN7/RB5 EMUC2/OC1/RDO LCD_D4
RB6_PGC 8 PGC/EMUC/AN6/OCFA/RB6 EMUD2/OC2/RD1 33 LCD_D5
4 RB7_PGD
RB7_PGD 9 PGD/EMUD/AN7/RB7 VDD 32
5 RB6_PGC VDD
10 AN8/RB8 VSS 31
6
11 VDD RF0 30 RF0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
12 VSS RF1 29 RF1
SIL6
OSC1 13 OSC1/CLKIN U2RX/CN17/RF4 28 RF4
OSC2 14 OSC2/CLKO/RC15 U2TX/CN18/RF5 27 RF5
15 EMUD1/SOSC1/T2CK/U1ATX/CN1/RC13 U1RX/SDI1/SDA/RF2 26 RF2 R11
16 25 47
2 17
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD3/U1TX/SDO/SCL/RF3
24
RF3 2
INT0/RA11 EMUC3/SCK1/RF6 RF6
18 IC2/INT2/RD9 IC1/INT1/RD8 23
LCD_D7 19 RD3 RD2 22 LCD_D6

VDD
20 VSS VDD 21

Vpot

LCD_D4
LCD_D5
LCD_D6
LCD_D7
LCD_RS

LCD_E
LCD_RW
VDD DSPIC30F4013

3 3

Vpot
VDD
R1
OSC1

OSC2
10k VDD

3
R2 2 45% 1
VPP_MCLR X1
1k
1

4 10k 4
B1 C1 RV1
12MHz
100nF
C2 C3
3

15pF 15pF

5 5
RB6_PGC

RB7_PGD

RF0

RF1

RF2

RF3

RF4

RF5

RF6
RB0

RB1

RB2

RB3

RB4

RB5

6 6
R3 R4 R5 R6 R7 R8 R9 R10 R19
330 330 330 330 330 330 330
330
20k
R20 R21 R22 R23 R24 R25
20k 20k 20k 20k 20k 20k

D0 D1 D2 D3 D4 D5 D6 D7
1

LED LED LED LED LED LED LED LED

R12 R13 R14 R15 R16 R17 R18
Señal de salida
7 20k 10k 10k 10k 10k 10k 10k 7
2

8 8

FILE NAME: DSPIC30F4013 DATE:

DESIGN TITLE: ESQUEMATICO 23/05/2017

9 9
PAGE:
PATH: ESQUEMATICO.pdrj 1 of 1
BY: Juan Vega M. REV: 0.2 TIME: 11:31:28 a. m.

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