TEA1716T: 1. General Description

TEA1716T
Resonant power supply control IC with PFC

Rev. 3 — 30 November 2012 Product data sheet
1. General description
The TEA1716T integrates a Power Factor Corrector (PFC) controller and a controller for a
Half-Bridge resonant Converter (HBC) in a multi-chip IC. It provides the drive function for
the discrete MOSFET in an up-converter and for the two discrete power MOSFETs in a
resonant half-bridge configuration.
Efficient PFC operation is achieved by implementing functions for Quasi-Resonant (QR)

operation at high-power levels and QR operation with valley skipping at lower power
levels. OverCurrent Protection (OCP), OverVoltage Protection (OVP) and
demagnetization sensing ensure safe operation under all conditions.
The HBC module is a high-voltage controller for a zero-voltage switching LLC resonant
converter. It contains a high-voltage level shift circuit and several protection circuits
including OCP, open-loop protection, capacitive mode protection and a general purpose
latched protection input.
The high-voltage chip is fabricated using a proprietary high-voltage Bipolar-CMOS-DMOS

power logic process enabling efficient direct start-up from the rectified universal mains
voltage. The low-voltage Silicon-On-Insulator (SOI) chip is used for accurate, high-speed
protection functions and control.
TEA1716T controlled PFC circuit and resonant converter are very flexible. It can be used
for a broad range of applications over a wide mains voltage range. Combining PFC and
HBC controllers in a single IC makes the TEA1716T ideal for controlling power supplies in
LCD and plasma televisions.
Using the TEA1716T highly efficient and reliable power supplies providing from 90 W to
500 W can be designed easily using the TEA1716T, with a minimum of external
components.
The integrated Burst mode and power management functionality of TEA1716T enable
resonant applications that meet the Energy Using Product Directive (EuP) lot 6
(< 0.5 W in Standby mode).
Remark: Unless otherwise stated, all values are typical.

NXP Semiconductors TEA1716T
2. Features and benefits
2.1 General features

 Integrated PFC and HBC controllers
 Universal mains supply operation from 70 V to 276 V (AC)
 High level of integration resulting in a low external component count and a cost
effective design
 Integrated Burst mode sensing
 Compliant with Energy Using Product Directive (EuP) lot 6
 Enable input to enable only the PFC or both the PFC and HBC controllers
 On-chip high-voltage start-up source
 Stand-alone operation or IC supplied from external DC source
2.2 PFC controller features

 Boundary mode operation with on-time control
 Valley/zero-voltage switching for minimum switching losses
 Frequency limiting to reduce switching losses
 Accurate boost voltage regulation
 Burst mode switching with soft-start and soft stop
2.3 HBC controller features

 Integrated high-voltage level shifter
 Adjustable minimum and maximum frequency
 Maximum 500 kHz half-bridge switching frequency
 Adaptive non-overlap time
 Burst mode switching
2.4 Protection features

 Safe restart mode for system fault conditions
 General latched protection input for output overvoltage protection or external
temperature protection
 Protection timer for time-out and restart
 Overtemperature protection
 Soft (re)start for both controllers
 Undervoltage protection for mains (brownout), boost, IC supply and output voltage
 Overcurrent regulation and protection for both controllers
 Accurate overvoltage protection for the boost voltage
 Capacitive mode protection for the HBC controller
TEA1716T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 30 November 2012 2 of 47

3. Applications
 LCD television
 Plasma television
 Notebook adapter
 Desktop and all-in-one PCs
4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
TEA1716T/2 SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

5. Block diagram
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Fig 1. TEA1716T block diagram

6. Pinning information
6.1 Pinning

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Fig 2. TEA1716T pin configuration
6.2 Pin description

Table 2. Pin description
Symbol Pin Description
COMPPFC 1 PFC controller frequency compensation; externally connected to filter
SNSMAINS 2 mains voltage sense input; externally connected to resistive divided mains
voltage
SNSAUXPFC 3 PFC demagnetization timing sense input; externally connected to auxiliary
winding of PFC
SNSCURPFC 4 PFC controller sense input for momentary current and soft-start; externally
connected to current sense resistor and soft-start filter
SNSOUT 5 sense input for monitoring the HBC output voltage; externally connected to
the auxiliary winding
SUPIC 6 SUPIC input low-voltage and output of internal HV start-up source;
externally connected to auxiliary winding of HBC or to external DC supply
GATEPFC 7 PFC MOSFET gate driver output
PGND 8 power ground; HBC low-side and PFC driver reference (ground)
SUPREG 9 regulated SUPREG IC supply; internal regulator output; input for drivers;
externally connected to SUPREG buffer capacitor
GATELS 10 HBC low-side MOSFET gate driver output
n.c. 11 not connected; high-voltage spacer.
SUPHV 12 internal HV start-up source source high-voltage supply input; externally
connected to boost voltage
GATEHS 13 HBC high-side MOSFET gate driver output
SUPHS 14 high-side driver supply input; externally connected to bootstrap capacitor
(CSUPHS)

Table 2. Pin description …continued

Symbol Pin Description
HB 15 reference for high-side driver and input for half-bridge slope detection;
externally connected to half-bridge node HB between HBC MOSFETs
(see Figure 17)
n.c. 16 not connected; high-voltage spacer
SNSCURHBC 17 momentary HBC current sense input; externally connected to resonant
current sense resistor
SGND 18 signal ground and IC reference (ground)
CFMIN 19 HBC minimum frequency setting; externally connected to capacitor
SNSBURST 20 burst stop activation sense input; externally connected to resistive divided
SNSFB voltage
SNSFB 21 output voltage regulation feedback sense input; externally connected to
optocoupler and pull-up resistor
SSHBC/EN 22 HBC soft-start timing of HBC and IC enable input; enables PFC or PFC
only or both PFC and HBC controllers; externally connected to soft-start
capacitor and enable pull-down signal
RCPROT 23 protection timer setting for time-out and restart; externally connected to
resistor and capacitor
SNSBOOST 24 sense input for boost voltage regulation; externally connected to resistive
divided boost voltage
7. Functional description
7.1 Overview of IC modules

The functionality of the TEA1716T can be grouped as follows:
• Supply module:
Supply management for the IC. Includes the restart and (latched) shutdown states
• Protection and restart timer:
An externally adjustable timer used for delayed protection and restart timing
• Enable input:
Control input for enabling and disabling the controllers; when disabled has very low
current consumption
• PFC controller:
Controls and protects the Power Factor (PF) converter. Generates a 400 V (DC)
boost voltage from the rectified AC mains input with a high PF
• HBC controller:
Controls and protects the resonant converter; generates a regulated mains isolated
output voltage from the 400 V (DC) boost voltage
• Burst input:
Control input for Burst mode operation; activates the Burst stop state in which the
current consumption is low
Figure 1 shows the block diagram of the TEA1716T. A typical application is illustrated in
Figure 17.

7.2 Power supply

The TEA1716T contains several supply-related pins SUPIC, SUPREG, SUPHS and
SUPHV. These pins are described in Section 7.2.1 to Section 7.2.4.
7.2.1 Low-voltage supply input (SUPIC pin)

The SUPIC pin is the main low-voltage supply input to the IC. All internal circuits are
supplied from this pin directly or indirectly using the SUPREG pin. The high-voltage
circuit, however, is not supplied from the SUPIC pin. The SUPIC pin is connected
externally to a buffer capacitor CSUPIC. This buffer capacitor can be charged in several
ways:
• from the internal high-voltage start-up source

• from the HBC transformer auxiliary winding
• from the e switching half-bridge node capacitive supply
• from an external DC supply, for example, a standby supply
The IC starts operating when the voltage on the SUPIC pin reaches the start level,
provided the voltage on the SUPREG pin has also reached the start level. The start level
depends on the condition of the SUPHV pin:
• High voltage present on the SUPHV pin (VSUPHV > Vdet(SUPHV)).

In a stand-alone application this is the case because CSUPIC is initially charged from
the HV start-up source. The start level is Vstart(hvd)(SUPIC) (20 V). The wide difference
between the start and stop (Vuvp(SUPIC)) levels allows sufficient energy to be drawn
from the SUPIC buffer capacitor until the output voltage stabilizes.
• Not connected or no voltage present at SUPHV (VSUPHV < Vdet(SUPHV)).
When the TEA1716T is supplied from an external DC source, this is the case. The
start level is Vstart(nohvd)(SUPIC) (15 V). The IC is supplied from the DC supply during
start-up. To minimize power dissipation the DC supply to the SUPIC pin must be
higher than, but close to Vuvp(SUPIC) (13 V).
The IC stops operating when VSUPIC < Vuvp(SUPIC). Vuvp(SUPIC). This voltage is the SUPIC
pin UnderVoltage Protection (UVP) voltage (UVP-SUPIC; see Section 7.9). The PFC
controller stops switching immediately but the HBC controller continues operating until the
low-side MOSFET is active.
The current consumption depends on the state of the IC. The TEA1716T operating states
are described in Section 7.3.
• Disabled IC state
When the IC is disabled using the SSHBC/EN pin, the current consumption
(Idism(SUPIC)) is very low.
• SUPIC charge, SUPREG charge, Thermal hold, Restart and Protection shutdown
states
Only a small section of the IC is active while CSUPIC and CSUPREG are charging during
a restart sequence before start-up or during shutdown after a protection function has
been activated. The PFC and HBC controllers are disabled. Current consumption is
limited to Iprotm(SUPIC).

• Boost charge state

The PFC controller is switching; the HBC controller is off. The current from the
high-voltage start-up source is large enough to supply the SUPIC pin
(current consumption < Ich(nom)(SUPIC)).
• Operational supply state
Both the PFC and HBC controllers are switching. Current consumption is Ioper(SUPIC).
When the HBC controller is enabled, the switching frequency is high initially and the
HBC MOSFET drivers current consumption is dominant. The stored energy in CSUPIC
supplies the initial SUPIC current before the SUPIC supply source takes over.
• Burst stop mode
Only a small section of the IC is active while CSUPREG is kept charged and the sensing
of the SNSBURST input is active. The PFC and HBC controllers are stopped. Current
consumption is limited to Iburstm(SUPIC).
The SUPIC pin has a low short circuit detection voltage (Vscp(SUPIC) = 0.65 V). The current
dissipated in the HV start-up source is limited while VSUPIC < Vscp(SUPIC)
(see Section 7.2.4).
7.2.2 Regulated supply (SUPREG pin)

The voltage range on the SUPIC pin exceeds that of the external MOSFETs gate
voltages. The TEA1716T contains an integrated series stabilizer. The series stabilizer
creates an accurate regulated voltage (Vreg(SUPREG) = 11.3 V) at the buffer capacitor
CSUPREG. This stabilized voltage is used to:
• Supply the internal PFC driver

• Supply the internal low-side HBC driver
• Supply the internal high-side driver using external components
• As a reference voltage for optional external circuits
The SUPREG series stabilizer is enabled after CSUPIC has been fully charged. Enabling
the stabilizer after charging ensures that any optional external circuitry connected to
SUPREG does not dissipate any of the start-up current.
To ensure that the external MOSFETs receive sufficient gate drive current, the voltage on
the SUPREG pin must reach Vstart(SUPREG). In addition, the voltage on the SUPIC pin
must reach the start level. The IC starts operating when both voltages reach their start
levels.
SUPREG is provided with undervoltage protection (UVP-SUPREG; see Section 7.9).

When VSUPREG < Vuvp(SUPREG) (10 V), two events are triggered:
• The IC stops operating to prevent unreliable switching because the gate driver voltage
is too low. The PFC controller stops switching immediately, but the HBC controller
continues until the low-side stroke is active.
• The maximum current from the internal SUPREG series stabilizer is reduced to
Ich(red)(SUPREG) (5.4 mA). This feature reduces the dissipation in the series stabilizer
when an overload occurs at the SUPREG pin while the SUPIC pin is supplied from an
external DC supply.

7.2.3 High-side driver floating supply (SUPHS pin)

The high-side driver is supplied by an external bootstrap buffer capacitor, CSUPHS. The
bootstrap capacitor is connected between the high-side reference, the HB pin, and the
high-side driver supply input the SUPHS pin. CSUPHS is charged from the SUPREG pin
using an external diode DSUPHS.
Careful selection of the appropriate diode minimizes the voltage drop between SUPREG
and SUPHS, especially when large MOSFETs and high switching frequencies are used.
7.2.4 High-voltage supply input (SUPHV pin)

In a stand-alone power supply application, the SUPHV pin is connected to the boost
voltage. The HV start-up source (which delivers a constant current from SUPHV to
SUPIC) charges CSUPIC and CSUPREG using this pin.
Short circuit protection on the SUPIC pin (SCP-SUPIC; see Section 7.9) limits dissipation
in the HV start-up source when SUPIC is shorted to ground. SCP-SUPIC limits the current
on SUPHV to Ired(SUPHV) when the voltage on SUPIC is less than Vscp(SUPIC).
Under normal operating conditions, the voltage on the SUPIC pin exceeds Vscp(SUPIC) very
quickly after start-up and the HV start-up source switches to Inom(SUPHV).
During start-up and restart, the HV start-up source charges CSUPIC and regulates the
voltage on SUPIC using hysteretic control. The start level has a small amount of
hysteresis Vstart(hys)(SUPIC). The HV start-up source switches off when VSUPIC exceeds the
start level Vstart(hvd)(SUPIC). Current consumption through the SUPHV pin (Itko(SUPHV)) is
low.
Once start-up is complete and the HBC controller is operating, SUPIC is supplied from the
HBC transformer auxiliary winding. In this operational state, the HV start-up source is
disabled.
7.3 Flow diagram

The operation of the TEA1716T can be divided into a number of states - see Figure 3. The
abbreviations used in Figure 3 are explained in Table 8.

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Fig 3. Flow diagram of the TEA1716T

Table 3. Operating states

State Description
No supply Supply voltages on SUPIC and SUPHV are too low to provide any functionality. Undervoltage
protection (UVP-supplies; see Section 7.9) is active when VSUPHV < Vrst(SUPHV) and
VSUPIC < Vrst(SUPIC). The IC is reset.
Disabled IC IC is disabled because the SSHBC/EN pin is LOW.
Thermal hold Activated as long as OTP is active. IC is not operating. PFC and HBC controllers are disabled
and CSUPIC and CSUPREG are not charged.
SUPIC charge HV start-up source charges IC supply capacitor (CSUPIC). CSUPREG is not charged.
SUPREG charge Series regulator charges stabilized supply capacitor (CSUPREG).
Boost charge Operational PFC builds up boost voltage.
Operational supply Output voltage is generated. Both PFC and HBC controllers are fully operational.
Burst stop Power-saving state for Burst mode operation. PFC and HBC controllers are disabled and CSUPIC
is not charged. CSUPREG is charged.
Restart Activated when a protection function is triggered. Restart timer is activated. During this time,
PFC and HBC controllers are disabled and CSUPREG is not charged. CSUPIC is charged.
Protection shut-down Activated when a protection function is triggered. IC is not operational. PFC and HBC controllers
are disabled and CSUPIC and CSUPREG are not charged.
7.4 Enable input (SSHBC/EN pin)

The power supply application is disabled by pulling the SSHBC/EN pin LOW.
Figure 4 shows the internal functionality. When a voltage is present on the SUPHV pin or
on the SUPIC pin, a current Ipu(EN) (42 A) flows from the SSHBC/EN pin. If the pin is not
pulled down, the current increases the voltage up to Vpu(EN) (3 V). Since the voltage is
above both Ven(PFC)(EN) (1.2 V) and Ven(IC)(EN) (2.2 V), the IC is enabled.
The IC is disabled when the voltage on the SSHBC/EN pin is pulled down under both
Ven(PFC)(EN) and Ven(IC)(EN) via an optocoupler. The optocoupler is driven from the HBC
transformer secondary side (see Figure 4). The PFC controller stops switching
immediately, but the HBC controller continues switching until the low-side stroke is active.
It is also possible to control the voltage on the SSHBC/EN pin from another circuit on the
secondary side via a diode. The external pull-down current must be larger than the
internal soft-start charge current Iss(hf)(SSHBC).
If the voltage on the SSHBC/EN pin is pulled down under Ven(IC)(EN), but not under
Ven(PFC)(EN), only the HBC is disabled. This feature is useful when another power
converter is connected to the PFC boost voltage.
The low-side power switch of the HBC is on when the HBC is disabled using the
SSHBC/EN pin.

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7.5 IC protection
7.5.1 IC restart and shutdown

In addition to the protection functions influencing the PFC and HBC controller operation,
several protection functions are provided to disable both controllers. See the protection
overview in Section 7.9 for details on which protection functions trigger a restart or
protection shutdown.
• Restart
When the TEA1716T enters the Restart state, the PFC and HBC controllers are
switched off. After a period defined by the Restart timer, the IC automatically restarts
following the normal start-up cycle.
• Protection shutdown
When the TEA1716T enters the Protection shutdown state, the PFC and HBC
controllers are switched off. The Protection shutdown state is latched, so the IC does
not automatically start up again. It can be restarted by resetting the Protection
shutdown state in one of the following ways:
– Lowering VSUPIC and VSUPHV below their respective reset levels, Vrst(SUPIC) and
Vrst(SUPHV)
– Using a fast shutdown reset (see Section 7.5.3).
– Using the enable pin (see Section 7.4)
• Thermal hold
In the Thermal hold state, the PFC and HBC controllers are switched off. The Thermal
hold state remains active until the IC junction temperature drops to approximately
10 C below Totp (see Section 7.5.6).

7.5.2 Protection and restart timer

The TEA1716T contains a programmable timer which can be used for timing several
protection functions. The timer can be used in two ways as a protection timer and as a
restart timer. The timing of the timers is set independently using an external resistor Rprot
and capacitor Cprot connected to the RCPROT pin.
7.5.2.1 Protection timer

Certain error conditions are allowed to persist for a time period before protective action is
must be taken. The protection timer defines the protection period (how long the error can
persist before the protection function is triggered). The protection functions that use the
protection timer aree found in the protection overview in Section 7.9.
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present
Error
none
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IRCPROT 0
Vu(RCPROT)
VRCPROT
passed
Protection time
t
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Fig 5. Operation of the protection timer
Figure 5 shows the operation of the protection timer. When an error condition occurs, a
fixed current Ich(slow)(RCPROT) (100 A) flows from the RCPROT pin and charges Cprot.
Rprot causes the voltage to increase exponentially. The protection time elapses when the
voltage on the RCPROT pin reaches the upper switching level Vu(RCPROT) (4 V). When the
protection time has elapsed, the appropriate protective action is taken and Cprot is
discharged.
If the error condition is removed before the voltage on the RCPROT pin reaches
Vu(RCPROT), Cprot is discharged using Rprot and no action is taken.
An external circuit to force a restart can increase the RCPROT voltage to exceed
Vu(RCPROT).
7.5.2.2 Restart timer

The IC must be disabled for a time period on certain error conditions. Particularly when
the error condition causes components to overheat. In such cases, the IC is disabled to
allow the power supply to cool down, before restarting automatically. The restart timer
determines the restart time. The restart timer is active in the Restart state. The protection
functions which trigger a restart are found in the protection overview in Section 7.9.

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no
Vu(RCPROT)
VRCPROT
Vl(RCPROT)
0
passed
Restart time
t
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Fig 6. Operation of the restart timer
Figure 6 shows the operation of the restart timer. Normally Cprot is discharged to 0 V.
When a restart is requested, Cprot is quickly charged to the upper switching level
Vu(RCPROT). Then the RCPROT pin becomes high ohmic and Cprot discharges through
Rprot. The restart time has elapsed when VRCPROT reaches the lower switching level
Vl(RCPROT) (0.5 V). The IC restarts and Cprot is discharged.
7.5.3 Fast shutdown reset (SNSMAINS pin)

The latched Protection shutdown state is reset when VSUPIC and VSUPHV drop below their
respective reset levels, Vrst(SUPIC) and Vrst(SUPHV). Typically, the PFC boost capacitor,
Cboost, must discharge before VSUPIC and VSUPHV drop below their reset levels.
Discharging Cboost can take a long time.
Fast shutdown reset causes a faster reset. When the mains supply is interrupted, the
voltage on the SNSMAINS pin falls. When VSNSMAINS falls below Vrst(SNSMAINS) and then
increases again by a hysteresis value, the IC leaves the Protection shutdown state. The
boost capacitor Cboost does not require discharging to trigger a new start-up.
The Protection shutdown state can also be ended by pulling down the enable input
(the SSHBC/EN pin).
7.5.4 Output overvoltage protection (SNSOUT pin)

The TEA1716T outputs are provided with overvoltage protection (OVP-output;
see Section 7.9). The output voltage is measured using the resonant transformer auxiliary
winding. The voltage is sensed on the SNSOUT pin using an external rectifier and
resistive divider. An overvoltage is detected when the SNSOUT voltage exceeds
Vovp(SNSOUT) (3.5 V). When an overvoltage is detected, the TEA1716T enters the
Protection shutdown state.
Additional external protection circuits, such as an external OTP circuit, can be connected
to this pin. Connect them to the SNSOUT pin using a diode to ensure that an error
condition triggers an OVP event.
7.5.5 Output failed start protection, FSP-output (SNSOUT pin)

The TEA1716T outputs are provided with failed start protection (FSP output;
see Section 7.9). During start-up, the output voltage is less than Vfsp(SNSOUT) for a time.
This voltage drop is not considered an error condition if it does not last longer than
expected. The protection timer is started when VSNSOUT < Vfsp(SNSOUT) for this reason.

Under normal conditions, the output voltage is present before the protection time is
expired and no protective action is taken. The Restart state is activated if the FSP output
event is still active when the protection time has expired.
7.5.6 OverTemperature Protection (OTP)

Accurate internal overtemperature protection is provided in the TEA1716T. When the
junction temperature exceeds the overtemperature protection activation temperature, Totp
(Totp = 150 C), the IC enters the Thermal hold state. The TEA1716T exits the Thermal
hold state when the temperature falls again to approximately Totp  10 C.
7.6 Burst mode operation (SNSBURST pin)

The HBC and PFC controllers can be operated in Burst mode. In Burst mode, the
controllers are on for a period, then off for a period. Burst mode operation increases
efficiency under low-load conditions.
The voltage on the SNSBURST pin defines the transition from Operational supply state
(= burst-on period) to Burst stop state (= burst-off period) and back).
The voltage on the SNSFB pin represents the level of power that is converted. The
voltage on the SNSBURST pin can be related to the SNSFB pin using an external resistor
divider. The SNSBURST pin has an internal switching level Vburst(SNSBURST) (3.5 V) and a
fixed hysteresis Vburst(hys)(SNSBURST) (24 mV). In addition, a switched current flowing into
the SNSBURST pin, Iburst(hys)(SNSBURST) (3 A) and the resistance of the external divider
determine the effective hysteresis. The current flows when the SNSBURST voltage is less
than Vburst(SNSBURST).
The PFC and HBC controller operation is suspended when the voltage on the
SNSBURST pin falls under Vburst(SNSBURST). The PFC continues as long as the boost
voltage is still below the regulation level. Then it stops with a soft-stop. The HBC stops
almost directly when the GATELS pin becomes active. The Burst stop state is entered
when both PFC and HBC have stopped switching. In the Burst stop state, the current
consumption of the IC is low and the SNSOUT pin is pulled low. The SNSOUT signal can
be used for additional functionality in the application.
When the voltage on SNSBURST increases to exceed

Vburst(SNSBURST) + Vburst(hys)(SNSBURST), the TEA1716T leaves the Burst stop state and
enters the Operational supply state. The PFC starts its operation with a soft-start. The
HBC resumes without a soft-start sequence.
Burst mode operation is not enabled until the SNSOUT pin has reached the Vfsp(SNSOUT)
level once to avoid unwanted activation of the burst mode during start-up.
7.7 PFC controller

The PFC controller converts the rectified universal mains voltage into an accurately
regulated boost voltage of 400 V (DC). It operates in Quasi-Resonant (QR) mode or
Discontinuous Conducting Mode (DCM) and is controlled using an on-time control
system. The resulting mains harmonic current emissions of a typical application can meet
the class-D MHR requirements.

The PFC controller uses valley switching to minimize losses. A primary stroke is only
started once the previous secondary stroke ends and the voltage across the PFC
MOSFET reaches a minimum value.
7.7.1 PFC gate driver (GATEPFC pin)

The circuit driving the gate of the power MOSFET has a high current sourcing capability
Isource(GATEPFC) of 0.6 A. It also has a high current sink capability Isink(GATEPFC) of 1.2 A.
The source and sink capabilities enable fast switch-on and switch-off to ensure efficient
operation. The driver is supplied from the regulated SUPREG supply.
7.7.2 PFC on-time control

The PFC operates under on-time control. The following determine the PFC MOSFET
on-time:
• The error amplifier and the loop compensation using the voltage on the COMPPFC
pin
At Vton(COMPPFC)zero (3.5 V), the on-time is reduced to zero. At Vton(COMPPFC)max the
on-time is at a maximum
• Mains compensation using the voltage on the SNSMAINS pin
7.7.2.1 PFC error amplifier (COMPPFC and SNSBOOST pins)
The boost voltage is divided using a high-ohmic resistive divider. It is supplied to the
SNSBOOST pin. The transconductance error amplifier, which compares the SNSBOOST
voltage with an accurate trimmed reference voltage Vreg(SNSBOOST), is connected to this
pin. The external loop compensation network on the COMPPFC pin filters the output
current. In a typical application, a resistor and two capacitors set the regulation loop
bandwidth.
The transconductance of the error amplifier is not constant, which improves the start-up
behavior and transient response. The transconductance significantly increases when the
SNSBOOST voltage is more than 80 mV above or below the reference voltage. The result
is a higher output current to the COMPPFC pin. Figure 7 shows the behavior of the
transconductance amplifier.

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Fig 7. Transconductance of the PFC error amplifier
The COMPPFC voltage is clamped at a maximum of Vclamp(COMPPFC). This clamp avoids a

long recovery time if the boost voltage exceeds the regulation level for a period.
7.7.2.2 PFC mains compensation (SNSMAINS pin)

The mathematical equation for the transfer function of a power factor corrector contains
the square of the mains input voltage. In a typical application, this results in a low
bandwidth for low mains input voltages. At high mains input voltages the MHR
requirements are hard to meet.
The TEA1716T contains a correction circuit to compensate for this effect. The average
mains voltage is measured using the SNSMAINS pin. The information is supplied to an
internal compensation circuit.
Figure 8 shows the relationship between the SNSMAINS voltage, the COMPPFC voltage,
and the on-time. It is possible to keep the regulation loop bandwidth constant over the full
mains input range using this compensation. This feature provides a fast transient
response on load steps, while still meeting the class-D MHR requirements.

ton(max)(lowmains)
VSNSMAINS = 0.97 V
on-time
VSNSMAINS = 3.3 V
ton(max)(highmains)
0
Vton(COMPPFC)max Vton(COMPPFC)zero VCOMPPFC
014aaa855
Fig 8. Relationship between on-time, SNSMAINS voltage and COMPPFC voltage
7.7.3 PFC demagnetization sensing (SNSAUXPFC pin)

The voltage on the SNSAUXPFC pin is used to detect transformer demagnetization.
During the secondary stroke, the transformer is magnetized and current flows in the boost
output. During this time, VSNSAUXPFC < Vdemag(SNSAUXPFC) (100 mV) and the PFC
MOSFET remains switched off.
After some time, the transformer becomes demagnetized and current stops flowing in the
boost output. From that moment, VSNSAUXPFC > Vdemag(SNSAUXPFC) and valley detection is
started. The MOSFET remains off.
To ensure that switching continues under all circumstances, the MOSFET is forced to
switch on if the magnetizing of the transformer (VSNSAUXPFC < Vdemag(SNSAUXPFC)) is not
detected within tto(mag) (50 s) after the GATEPFC pin goes LOW.
connect a 5 k series resistor to this pin to protect the internal circuitry, against for
example lightning. Place the resistor close to the IC on the PCB to prevent incorrect
switching due to external disturbances.
7.7.4 PFC valley sensing (SNSAUXPFC pin)

If the voltage at the MOSFET drain is at its minimum (valley switching), the PFC MOSFET
is switched on for the next stroke. This action reduces switching losses and EMI
(see Figure 9).

on
GATEPFC
off
Vboost
VRect
Dr(PFC)
0
VRect/N
Aux(PFC)
0
Vdemag(SNSAUXPFC)
(Vboost - VRect)/N
lTPFC
0
demagnetized
Demagnetization
magnetized
Valley
(= top for detection)
t
014aaa856
Fig 9. Demagnetization and valley detection
The valley sensing block connected to the SNSAUXPFC pin detects the valleys. This
block measures the PFC transformer auxiliary winding voltage, which is a reduced and
inverted copy of the MOSFET drain voltage. When a valley of the drain voltage (= top at
SNSAUXPFC voltage) is detected, the MOSFET is switched on.
If a top is not detected on the SNSAUXPFC pin (= a valley at the drain) within tto(vrec)
(4 s) after demagnetization is detected, the MOSFET is forced to switch on.
7.7.5 PFC frequency and off-time limiting

The switching frequency is limited to fmax(PFC) for transformer optimization and to minimize
switching losses. If the frequency for quasi-resonant operation exceeds fmax(PFC), the
system switches to DCM. The PFC MOSFET is switched on when the drain-source
voltage is at a minimum (valley switching).
The minimum off-time is limited at toff(PFC)min to ensure correct control of the PFC
MOSFET under all circumstances.
7.7.6 PFC soft-start and soft-stop (SNSCURPFC pin)

The PFC controller features a soft-start function. The function slowly increases the
primary peak current during start-up. The soft-stop function slowly decreases the
transformer peak current before operations are halted. These functions prevent
transformer rattle at start-up or during burst mode operation.

Connecting a resistor Rss(PFC) and capacitor Css(PFC) between the SNSCURPFC pin and
the current sense resistor Rcur(PFC) achieves this. During start-up, an internal current
source, Ich(ss)(PFC), charges the capacitor to VSNSCURPFC = Ich(ss)(PFC)  Rss(PFC).
The voltage is limited to the maximum PFC soft-start clamp voltage, Vclamp(ss)PFC. The
additional voltage across the charged capacitor reduces the peak current. After start-up,
the internal current source is switched-off, capacitor Css(PFC) discharges across Rss(PFC)
and the peak current increases.
The start level and the time constant of the rising primary current can be adjusted
externally by changing the values of Rss(PFC) and Css(PFC).
V ocr  PFC  –  I ch  ss   PFC   R ss  PFC  

I Cur  PFC   pk  = ---------------------------------------------------------------------------------------------
R cur  PFC 
 = R ss  PFC   C ss  PFC 
Switching on the internal current source Ich(ss)(PFC) starts a soft-stop. Ich(ss)(PFC) charges
Css(PFC). The increasing capacitor voltage decreases the peak current. The charge current
flows when the voltage on the SNSCURPFC pin is less than the maximum PFC soft-start
voltage (0.5 V). If VSNSCURPFC exceeds the maximum PFC soft-start voltage, the soft-start
current source starts limiting the charge current. To determine accurately if the capacitor is
charged, the voltage is only measured during the PFC power switch off-time. The PFC
operation is stopped when VSNSCURPFC > Vstop(ss)(PFC).
In the Burst stop state with the PFC not operating, the SNSCURPFC pin is kept at the
maximum PFC soft-start voltage, enabling an immediate start of the soft-start sequence
when the PFC must operate after the Burst stop state.
7.7.7 PFC overcurrent regulation, OCR-PFC (SNSCURPFC pin)

The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor (Rcur(PFC)) connected to the source of the external MOSFET. The
voltage is measured via the SNSCURPFC pin and is limited to Vocr(PFC).
A voltage peak appears on VSNSCURPFC when the PFC MOSFET is switched on due to the
discharging of the drain capacitance. The leading-edge blanking time (tleb(PFC)) ensures
that the overcurrent sensing block does not react to this transitory peak.
7.7.8 PFC mains undervoltage protection/brownout protection, UVP-mains

(SNSMAINS pin)
The voltage on the SNSMAINS pin is continuously sensed to prevent the PFC trying to
operate at very low mains input voltages. PFC switching stops when
VSNSMAINS < Vuvp(SNSMAINS). Mains undervoltage protection is also called brownout
protection.
VSNSMAINS is clamped to a minimum value of Vpu(SNSMAINS) for fast restart as soon as the
mains input voltage recovers after a mains-dropout. The PFC starts or restarts when
VSNSMAINS exceeds the start level Vstart(SNSMAINS).

7.7.9 PFC boost overvoltage protection, OVP-boost (SNSBOOST pin)

An overvoltage protection circuit has been built in to prevent boost overvoltage during load
steps and mains transients. Switching of the power factor correction circuit is inhibited
when the voltage on the SNSBOOST pin > Vovp(SNSBOOST).
PFC switching resumes when VSNSBOOST < Vovp(SNSBOOST) again.
Overvoltage protection is also triggered when an open circuit at the resistor connected
between the SNSBOOST pin and ground.
7.7.10 PFC short circuit/open-loop protection, SCP/OLP-PFC (SNSBOOST pin)

The PFC circuit does not start switching until the voltage on the SNSBOOST pin exceeds
Vscp(SNSBOOST). This acts as short circuit protection for the boost voltage (SCP-boost).
The SNSBOOST pin draws a small input current Iprot(SNSBOOST). If this pin gets
disconnected, the residual current pulls down VSNSBOOST, triggering short circuit
protection (SCP-boost). This combination creates an open-loop protection (OLP-PFC).
7.8 HBC controller

The HBC controller converts the 400 V boost voltage from the PFC into one or more
regulated DC output voltages and drives two external MOSFETs in a half-bridge
configuration connected to a transformer. The transformer forms the resonant circuit in
combination with the resonant capacitor and the load at the output. The transformer has a
leakage inductance and a magnetizing inductance. The regulation is realized using
frequency control.
7.8.1 HBC high-side and low-side driver (GATEHS and GATELS pins)
Both drivers have an identical driving capability. The output of each driver is connected to
the equivalent gate of an external high-voltage power MOSFET.
The low-side driver is referenced to the PGND pin and is supplied from the SUPREG pin.
The high-side driver is floating. The reference for the high-side driver is the HB pin,
connected to the midpoint of the external half-bridge. The high-side driver is supplied from
the SUPHS pin which is connected to the external bootstrap capacitor CSUPHS. When the
low-side MOSFET is on, the bootstrap capacitor is charged from the SUPREG pin using
the external diode DSUPHS.
7.8.2 HBC boost undervoltage protection, UVP-boost (SNSBOOST pin)

The voltage on the SNSBOOST pin is sensed continuously to prevent the HBC controller
trying to operate at very low boost input voltages. When VSNSBOOST < Vuvp(SNSBOOST),
HBC switching stops the next time the GATELS pin goes HIGH. HBC switching resumes
when VSNSBOOST > Vstart(SNSBOOST).

7.8.3 HBC switch control

HBC switch control determines when the MOSFETs switch on and off. It uses the output
from several other blocks.
• A divider is used for alternate switching of the high and low-side MOSFETs for each
oscillator cycle. The oscillator frequency is twice the half-bridge frequency.
• The controlled oscillator determines the switch-off point.
• Adaptive non-overlap time sensing determines the switch-on point. This function is
the adaptive non-overlap time.
• Several protection circuits and the state of the SSHBC/EN input specify if the
resonant converter is allowed to start switching.
• At start-up pin GATELS is HIGH. Node HB is pulled to ground and the bootstrap
capacitor CSUPHS is charged.
• During the burst off-time, both GATELS and GATEHS are LOW. The disabled
MOSFETs prevent the discharge of the resonant tank.
Figure 10 provides an overview of typical switching behavior.
GATEHS
GATELS
Vboost
HB
ITr(HBC) 0
CFMIN
t
014aaa857
Fig 10. Switching behavior of the HBC
7.8.4 HBC Adaptive Non-Overlap (ANO) time function (HB pin)
7.8.4.1 Inductive mode (normal operation)

The high efficiency characteristic of a resonant converter is the result of Zero-Voltage
Switching (ZVS) of the power MOSFETs. ZVS is also called soft switching. To allow soft
switching, a small non-overlap time is required between the high-side on-times and
low-side MOSFETs. During this non-overlap time, the primary resonant current charges or
discharges the half-bridge capacitance between ground and the boost voltage.

After the charge or discharge cycles, the body diode of the MOSFET starts conducting.
Because the voltage across the MOSFET is zero, there are no switching losses when the
MOSFET is switched on. This operating mode is called inductive mode. In inductive mode
the switching frequency is above the resonance frequency and the resonant tank has an
inductive impedance.
The HB transition time depends on resonant current amplitude when switching starts.
There is a complex relationship between this amplitude, the frequency, the boost voltage
and the output voltage. Ideally, the IC switches on the MOSFET when the HB transition is
complete. If it waits any longer, the HP voltage can swing back, especially at high output
loads. The advanced adaptive non-overlap time makes it unnecessary to choose a fixed
dead time (which is always a compromise). This saves on external components.
Adaptive non-overlap time sensing measures the HB slope after one MOSFET has been
switched off. Normally, the HB slope starts immediately (the voltage starts rising or falling).
Once the transition at the HB node is complete, the slope ends (the voltage stops
rising/falling). This slope end is detected by the ANO time sensor and the other MOSFET
is switched on. In this way, the non-overlap time is automatically optimized even when the
HB transition cannot be fully completed, which minimizes losses.
Figure 11 illustrates the operation of the adaptive non-overlap time function in Inductive
mode.
GATEHS
GATELS
Vboost
HB
0 t
fast HB slope slow HB slope incomplete HB slope
014aaa858
Fig 11. Adaptive non-overlap time function (normal inductive operation)
The non-overlap time depends on the HB slope but it has upper and lower limits.
An integrated minimum non-overlap time (tno(min)) prevents cross conduction occurring

under any circumstances.
The maximum non-overlap time is limited to the oscillator charge time. If the HB slope is
longer than the oscillator charge time (1⁄4 of HB switching period), the MOSFET is forced
to switch on. In this case, the MOSFET is not soft switching. This limitation ensures that,
the MOSFET on-time is at least 1⁄4 of the HB switching period.

7.8.4.2 Capacitive mode

The statements in Section 7.8.4.1 are true for normal operation with a switching frequency
higher than the resonance frequency. When an error condition occurs (for example output
short, load pulse too high) the switching frequency is lower than the resonance frequency.
The resonant tank then has a capacitive impedance. In Capacitive mode, the HB slope
does not start after the MOSFET switches off. Switching on the other MOSFET is not
recommended in this situation. The absence of soft switching increases dissipation in the
MOSFETs. In Capacitive mode, the body diode in the switched off MOSFET can start
conducting. Switching on the other MOSFET at this instant can result in the immediate
destruction of the MOSFETs.
The advanced adaptive non-overlap time of the TEA1716T always waits until the slope at
the half-bridge node starts. It guarantees safe switching of the MOSFETs in all
circumstances. Figure 12 shows the adaptive non-overlap time function operation in
Capacitive mode.
In Capacitive mode, half the resonance period can elapse before the resonant current
changes back to the correct polarity and starts charging the half-bridge node. The
oscillator is slowed down until the half-bridge slope starts to allow this relatively long
waiting time. See Section 7.8.5 for more details on the oscillator.
GATEHS
0
GATELS
0
Vboost
no HB slope
HB
wrong polarity
ITr(HBC) 0
CFMIN
0 t
delayed
oscillator
014aaa939
delayed switch-on
during capacitive mode
Fig 12. Adaptive non-overlap time function (capacitive operation)
The MOSFET is forced to switch on when the half-bridge slope fails to start and the
oscillator voltage reaches Vu(CFMIN).
The switching frequency is increased to eliminate the problems associated with

Capacitive mode operation (see Section 7.8.11).

7.8.5 HBC slope controlled oscillator (pin CFMIN)

The slope-controlled oscillator determines the half-bridge switching frequency. The
oscillator generates a triangular waveform between Vu(CFMIN) and Vl(CFMIN) at the external
capacitor Cfmin.
Figure 13 shows how the frequency is determined.
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Fig 13. Determination of oscillator current
Two external components determine the frequency range:
• Capacitor Cfmin connected between the CFMIN pin and ground sets the minimum
frequency in combination with an internally trimmed current source Iosc(min)
• Internal resistor Rfmax sets the frequency range and thus the maximum frequency.
Resistor Rfmax has a fixed value (18 k typical)
The oscillator frequency depends on the charge and discharge currents of Cfmin. The
charge and discharge current contains a fixed component, Iosc(min), which determines the
minimum frequency. In addition, it contains a variable component that is 4.9 times greater
than the current flowing through resistor Rfmax:
• The voltage across resistor Rfmax is Vfmin(RFMAX) (0 V) at the minimum frequency

• The voltage across resistor Rfmax is Vfmax(fb)(RFMAX) (1.5 V at the maximum feedback
frequency
• The voltage across resistor Rfmax is Vfmax(ss)(RFMAX) (2.5 V) at the maximum soft-start
frequency
The maximum frequency of the oscillator is internally limited. The HB frequency is limited
to flimit(HB) (minimum 500 kHz).
The half-bridge slope controls the oscillator. The oscillator charge current is initially set to
a low value Iosc(red) (30 A). When the start of the half-bridge slope is detected, the charge
current is increased to its normal value. This feature is used in combination with the
adaptive non-overlap time function as described in Section 7.8.4.2 and Figure 12.

The length of time the oscillator current is low is negligible under normal operating
conditions because the half-bridge slope normally starts directly after the MOSFET is
switched off.
7.8.6 HBC feedback input (SNSFB pin)

In a typical power supply application, the output voltage is compared and amplified on the
secondary side. The error amplifier output is transferred to the primary side using an
optocoupler. The optocoupler can be connected directly to the SNSFB pin. The current
setting of the optocoupler can be selected using the external pull-up resistor.
The SNSFB pin is a voltage input. At an SNSFB voltage of Vfmin(SNSFB) (6.4 V) the
frequency is at a minimum. The maximum frequency is reached at Vfmax(SNSFB) (4.1 V).
The maximum frequency that can be reached using the SNSFB pin is lower (70 %) than
the maximum frequency that can be reached using the SSHBC/EN pin.
7.8.7 HBC open-loop protection, OLP-HBC (SNSFB pin)

Under normal operating conditions, the optocoupler current is between Ifmin(SNSFB) and
Ifmax(SNSFB) and pulls down the voltage at the SNSFB pin. Due to an error in the feedback
loop, the current can be less than Ifmin(SNSFB) with the HBC controller delivering maximum
output power.
The HBC controller features Open-Loop Protection (OLP), which monitors the SNSFB
voltage. When VSNSFB exceeds Volp(SNSFB), the protection timer is started. The Restart
state is activated if the OLP condition is still present after the protection time has elapsed.
7.8.8 HBC soft-start (pin SSHBC/EN)

The relationship between switching frequency and output current is not constant. It
depends strongly on the output voltage and the boost voltage. This relationship can be
complex. The TEA1716T contains a soft-start function to ensure that the resonant
converter starts or restarts with safe currents. This soft-start function forces a start at such
a high frequency that the currents are acceptable under all conditions. The soft-start then
slowly decreases the frequency. Normally, output voltage regulation takes over frequency
control before soft-start reaches its minimum frequency. Limiting the output current during
start-up also limits the rate at which the output voltage rises and prevents an overshoot.
Soft-start utilizes the voltage on the SSHBC/EN pin. The external capacitor Css(HBC) sets
the timing of the soft-start. The SSHBC/EN pin is also used as an enable input. Soft-start
voltage levels are above the enable voltage thresholds.
7.8.8.1 Soft-start voltage levels

Figure 13 shows the relationship between the soft-start voltage on pin SSHBC/EN and the
oscillator current.
At initial start-up, VSSHBC/EN < Vfmax(SSHBC) (3.2 V), which corresponds with the maximum
frequency. During start-up, CSSHBC is charged, VSSHBC/EN rises and the frequency
decreases. The contribution of the soft-start function is zero when
VSSHBC/EN > Vfmin(SSHBC) (8.0 V).
VSSHBC/EN is clamped at a maximum of Vclamp(SSHBC) (8.4 V) (frequency is at a minimum)

and at a minimum ( 3 V). Below Vfmax(SSHBC) (maximum frequency), the discharge
current is reduced to a maximum frequency soft-start current of 5 A. The voltage is
clamped at a minimum of Vpu(EN) (3 V). Both clamp levels are just outside the operating

area between Vfmax(SSHBC) and Vfmin(SSHBC). The margins avoid frequency disturbance
during normal output voltage regulation, but ensure that overcurrent regulation can
respond quickly.
7.8.8.2 Soft-start charge and discharge

At initial start-up, the soft-start capacitor Css(HBC) is charged to obtain a decreasing
frequency sweep from the maximum to the operating frequency. The soft-start
functionality is used to soft-start the resonant converter and for regulation purposes (such
as overcurrent regulation). Css(HBC) can therefore be charged or discharged. A continuous
alternation between charging and discharging occurs during overcurrent regulation. In this
way VSSHBC/EN can be regulated, overruling the signal from the feedback input.
The charge and discharge current can have a high value, Iss(hf)(SSHBC) (160 A), resulting
in fast charging and discharging. Or it can have a low value, Iss(lf)(SSHBC) (40 A), resulting
in a slow charging and discharging. This two-speed soft-start sweep allows a combination
of a short start-up time for the resonant converter and stable regulation loops (such as
overcurrent regulation).
The fast charge and discharge is used for the upper frequency range where
VSSHBC/EN < Vss(hf-lf)(SSHBC) (5.6 V). In the upper frequency range, the currents in the
converter do not react strongly to frequency variations.
The slow charge and discharge is used for the lower frequency range where
VSSHBC/EN > Vss(hf-lf)(SSHBC) (5.6 V). In the lower frequency range, the currents in the
converter react strongly to frequency variations.
Section 7.8.10.2 describes how the two-speed soft-start function is used for overcurrent
regulation.
The soft-start capacitor is not charged or discharged during non-operation time in Burst
mode. The soft-start voltage does not change during this time.
7.8.8.3 Soft-start reset

Some protection functions, such as overcurrent protection, require fast correction of the
operating frequency set point, but do not require switching to stop. See Section 7.9 for
details on which protection functions use this step to the maximum frequency. The
TEA1716T has a special fast soft-start reset feature for the HBC controller that forces an
immediate step to maximum frequency. Soft-start reset is also used when the HBC
controller is enabled using the SSHBC/EN pin or after a restart to ensure a safe start at
maximum frequency. Soft-start reset is not used when the operation was stopped in Burst
mode.
When a protection function is activated, the oscillator control input is disconnected from
the soft-start capacitor, Css(HBC), which is connected between the SSHBC/EN pin and
ground. The switching frequency is immediately set to a maximum. Setting the switching
frequency to a maximum restores safe switching operation in most cases. At the same
time, the capacitor is discharged to the maximum frequency level, Vfmax(SSHBC). Once
VSSHBC/EN has reached this level, the oscillator control input is connected to the pin again
and the normal soft-start sweep follows. Figure 14 shows the soft-start reset and the
two-speed frequency sweep downwards.

on
Protection
off
Vfmin(SSHBC)
VSSHBC/EN Vss(hf-lf)(SSHBC)
Vfmax(SSHBC)
fmax
fHB
fmin
0 t
regulation fmax fast slow sweep regulation
forced sweep
014aaa864
Fig 14. Soft-start reset and two-speed soft-start
7.8.9 HBC high-frequency protection, HFP-HBC

Normally the converter does not operate continuously at maximum frequency because it
sweeps down to much lower values. Certain error conditions, such as a disconnected
transformer, can cause the converter to operate continuously at maximum frequency. If
zero-voltage switching conditions are no longer present, the MOSFETs can overheat. The
TEA1716T features High-Frequency Protection (HFP) for the HBC controller to protect it
from being damaged in such circumstances.
HFP senses the voltage across the internal resistor Rfmax. This voltage indicates the
current frequency. When the frequency is higher than 75 % of the soft-start frequency
range, the protection timer is started. The 75 % level corresponds to an Rfmax voltage of
Vhfp(RFMAX) (4.31 V).
7.8.10 HBC overcurrent regulation and protection, OCR and OCP

(SNSCURHBC pin)
The HBC controller is protected against overcurrent in two ways:
• OverCurrent Regulation (OCR) which increases the frequency slowly; the protection
timer is also started.
• OverCurrent Protection (OCP) which steps to maximum frequency.
A boost voltage compensation function is used to reduce the variation in the output
current protection level.
7.8.10.1 Boost voltage compensation

The primary current, also known as the resonant current, is sensed using the
SNSCURHBC pin. It senses the momentary voltage across an external current sense
resistor Rcur(HBC). The use of the momentary current signal allows for fast overcurrent
protection and simplifies the stabilizing of overcurrent regulation. The OCR and OCP
comparators compare VSNSCURHBC with the maximum positive and negative values.

The primary current is higher when the boost voltage is low for the same output power.
Boost compensation is included to reduce the dependency of the protected output current
level on the boost voltage. The boost compensation sources and sinks a current from the
SNSCURHBC pin. This current creates a voltage drop across the series resistor Rcurcmp.
The amplitude of the current is linearly dependent on the boost voltage. At nominal boost
voltage, the current is zero and the voltage VCur(HBC) across the current sense resistor is
also present on the SNSCURHBC pin. At the UVP-boost start level Vuvp(SNSBOOST), the
current is at a maximum. The current sink or source direction depends on the active gate
signal. The voltage drop created across Rcurcmp reduces the amplitude at the pin. This
reduction in amplitude results in a higher effective current protection level. The Rcurcmp
value sets the amount of compensation. Figure 15 shows how the boost compensation
works for an artificial current signal. The sinking compensation current only flows when
VSNSCURHBC is positive because of the circuit implementation.
Vreg
Vboost
Vuvp
GATEHS
t
GATELS
t
sink
sink current only with positive VSNSCURHBC
ISNSCURHBC 0 t
source
VCur(HBC) = Rcur(HBC) × ICur(HBC)

Iocp(high)
Iocr(high)
Iocp(nom)
Iocr(nom)
ICur(HBC) 0 t
-Iocr(nom)
-Iocp(nom)
-Iocr(high)
-Iocp(high)
VSNSCURHBC
Vocp(HBC)
Vocr(HBC)
VSNSCURHBC
0 t
-Vocr(HBC)
-Vocp(HBC)
nominal Vboost nominal Vboost low Vboost low Vboost

no compensation no compensation strong compensation strong compensation
nominal OCR nominal OCP high OCR high OCP
014aaa865
Fig 15. Boost voltage compensation
7.8.10.2 OverCurrent Regulation (OCR-HBC)

The lowest comparator levels at the SNSCURHBC pin Vocr(HBC) (0.5 V and +0.5 V),
relate to the overcurrent regulation voltage. There are comparators for both the positive
and negative polarities. The positive comparator is active during the high-side on-time and

the following high-side to low-side non-overlap time. The negative comparator is active
during the remaining time. If either level is exceeded, the frequency is slowly increased.
Discharging the soft-start capacitor achieves this.
Each time the OCR level is exceeded, the event is latched until the next stroke and the
soft-start discharge current is enabled. When both the positive and negative OCR levels
are exceeded, the soft-start discharge current flows continuously.
Overcurrent regulation is very effective at limiting the output current during start-up. A
smaller soft-start capacitor is used to achieve a faster start-up. Using a smaller capacitor
can result in an output current that is too high at times. However, the OCR function slows
down the frequency sweep when required to keep the output current within the specified
limits. Figure 16 shows the operation of the OCR during output voltage start-up.
Iocr
ICur(HBC) 0 t
-Iocr
Iss(hf)(SSHBC)
ISSHBC/EN Iss(If)(SSHBC)
-Iss(If)(SSHBC) t
-Iss(hf)(SSHBC)
Vfmin(SSHBC)
VSSHBC/EN
Vss(hf-lf)(SSHBC)
Vfmax(SSHBC)
0 t
Vreg
VO
0 t
Fast soft start sweep (charge and discharge) Slow soft start sweep (charge and discharge)
014aaa866
Fig 16. Overcurrent regulation during start-up
The protection timer is also started. The Restart state is activated when the OCR-HBC
condition is still present after the protection time has elapsed.
7.8.10.3 OverCurrent Protection (OCP-HBC)

Under normal operating conditions, OCR is able to ensure the current remains below the
specified maximum values. However, in the event of certain error conditions occur,
however, it is not fast enough to limit the current. OCP is implemented to protect against
those error conditions. The OCP level Vocp(HBC) (1.75 V and +1.75 V), is higher than the
OCR level Vocr(HBC).

When the OCP level is reached, the frequency immediately jumps to the maximum value
using the soft-start reset, then a normal sweep down.
7.8.11 HBC capacitive mode regulation, CMR (HB pin)

The MOSFETs in the half-bridge drive the resonant circuit. Depending on the output load,
the output voltage and the switching frequency this resonant circuit can have an inductive
or a capacitive impedance. Inductive impedance is preferred because it facilitates efficient
zero-voltage switching.
Harmful switching in Capacitive mode is avoided using the adaptive non-overlap time
function (see Section 7.8.4.2). An extra action is performed which results in Capacitive
Mode Regulation (CMR). CMR causes the half-bridge circuit to return to Inductive mode
from Capacitive mode.
Capacitive mode is detected when the HB slope does not start within tto(cmr) after the
MOSFETs have switched off. Detection of Capacitive mode increases the switching
frequency. This increase is caused by discharging the soft-start capacitor with a relatively
high current Icmr(hf)(SSHBC) fimmediately after tto(cmr) expires until the half-bridge slope
starts. The frequency increase regulates the HBC to the border between capacitive and
inductive mode.
7.9 Protection functions overview

Table 4. Overview protections
Protected Symbol Protection Affected Action Description
part
IC UVP-SUPIC Undervoltage protection SUPIC IC disable Section 7.2.1
IC UVP-SUPREG Undervoltage protection SUPREG IC disable Section 7.2.2
IC UVP-supplies Undervoltage protection supplies IC disable and reset Section 7.3
IC SCP-SUPIC Short circuit protection SUPIC IC low HV start-up current Section 7.2.4
IC OVP-output Overvoltage protection output IC shut-down Section 7.5.4
IC FSP-output Failed start protection output IC restart after protection time Section 7.5.5
IC OTP Overtemperature protection IC disable Section 7.5.6
PFC OCR-PFC Overcurrent regulation PFC PFC switch off cycle-by-cycle Section 7.7.7
PFC UVP-mains Undervoltage protection mains PFC suspend switching Section 7.7.8
PFC OVP-boost Overvoltage protection boost PFC suspend switching Section 7.7.9
PFC SCP-boost Short circuit protection boost IC restart Section 7.7.10
PFC OLP-PFC Open-loop protection PFC IC restart Section 7.7.10
HBC UVP-boost Undervoltage protection boost HBC disable Section 7.8.2
HBC OLP-HBC Open-loop protection HBC IC restart after protection time Section 7.8.7
HBC HFP-HBC High-frequency protection HBC IC restart after protection time Section 7.8.9
HBC OCR-HBC Overcurrent regulation HBC HBC increase frequency Section 7.8.10.2
IC restart after protection time
HBC OCP-HBC Overcurrent protection HBC HBC step to maximum Section 7.8.10.3
frequency
HBC CMR Capacitive mode regulation HBC increase frequency Section 7.8.11
HBC ANO Adaptive non-overlap HBC prevent hazardous Section 7.8.4
switching

8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).; All voltages are measured with respect to theSGND
pin; Currents are positive when flowing into the IC; The voltage ratings are valid provided other ratings are not violated;
Current ratings are valid provided the maximum power rating is not violated.
Symbol Parameter Conditions Min Max Unit
Voltages
VSUPHV voltage on pin SUPHV continuous 0.4 +630 V
VSUPHS voltage on pin SUPHS DC 0.4 +570 V
t < 0.5 s 0.4 +630 V
referenced to the HB pin 0.4 +14 V
VSUPIC voltage on pin SUPIC 0.4 +38 V
VSNSAUXPFC voltage on pin SNSAUXPFC 25 +25 V
VSUPREG voltage on pin SUPREG 0.4 +12 V
VSNSOUT voltage on pin SNSOUT 0.4 +12 V
VRCPROT voltage on pin RCPROT 0.4 +12 V
VSNSFB voltage on pin SNSFB 0.4 +12 V
VSSHBC/EN voltage on pin SSHBC/EN 0.4 +12 V
VSNSBURST voltage on pin SNSBURST 0.4 +12 V
VGATEHS voltage on pin GATEHS [1] 0.4 VSUPHS + 0.4 V
VGATELS voltage on pin GATELS [1] 0.4 VSUPREG + 0.4 V
VGATEPFC voltage on pin GATEPFC [1] 0.4 VSUPREG + 0.4 V
VSNSCURHBC voltage on pin SNSCURHBC 5 +5 V
VSNSBOOST voltage on pin SNSBOOST 0.4 +12 V
VSNSMAINS voltage on pin SNSMAINS 0.4 +12 V
VSNSCURPFC voltage on pin SNSCURPFC current limited 0.4 +5 V
VCOMPPFC voltage on pin COMPPFC 0.4 +5 V
VCFMIN voltage on pin CFMIN 0.4 +5 V
VPGND voltage on pin PGND 1 +1 V
Currents
IGATEPFC current into pin GATEPFC duty cycle < 10 % 0.8 +2 A
ISNSCURPFC current into pin SNSCURPFC 1 +10 mA
General
Ptot total power dissipation Tamb < 75 C - 0.8 W
Tstg storage temperature 55 +150 C
Tj junction temperature 40 +150 C

Table 5. Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134).; All voltages are measured with respect to theSGND
pin; Currents are positive when flowing into the IC; The voltage ratings are valid provided other ratings are not violated;
Current ratings are valid provided the maximum power rating is not violated.
Symbol Parameter Conditions Min Max Unit
ESD
VESD electrostatic discharge voltage Human body model
Pin 12 (SUPHV) [2] - 1500 V
Pin 13,14,15 (HS driver) [2] - 1000 V
other pins [2] - 2000 V
Machine model
All pins [3] - 200 V
Charged device model
All pins - 500 V
[1] Exceeding this rating for short peak currents (t < 10 s) is allowed.
[2] Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[3] Equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10  resistor.
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient in free air; JEDEC single 90 K/W
layer test board
10. Characteristics
Table 7. Characteristics
Tamb = 25 C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
High-voltage start-up source (pin SUPHV)
Idism(SUPHV) disable mode current on Disabled IC state - 140 - A
pin SUPHV
Ired(SUPHV) reduced current on pin VSUPIC < Vscp(SUPIC) - 1.2 - mA
SUPHV
Inom(SUPHV) nominal current on pin VSUPIC < Vstart(hvd)(SUPIC) 4.3 5.1 - mA
SUPHV
Itko(SUPHV) takeover current on pin VSUPIC > Vstart(hvd)(SUPIC) - 7 - A
SUPHV
Vdet(SUPHV) detection voltage on pin - - 25 V
SUPHV
Vrst(SUPHV) reset voltage on pin VSUPIC < Vrst(SUPIC) - 7 - V
SUPHV

Table 7. Characteristics …continued

Low-voltage IC supply (pin SUPIC)
Vstart(hvd)(SUPIC) start voltage with high VSUPHV > Vdet(SUPHV) 19 20 21 V
voltage detected
Vstart(nohvd)(SUPIC) start voltage with no high VSUPHV < Vdet(SUPHV) or open 14.1 15 15.9 V
voltage detected
Vstart(hys)(SUPIC) hysteresis of start voltage - 0.3 - V
on pin SUPIC
Vuvp(SUPIC) undervoltage protection 12.3 13 13.7 V
voltage on pin SUPIC
Vrst(SUPIC) reset voltage on pin VSUPHV < Vrst(SUPHV) - 7 - V
SUPIC
Vscp(SUPIC) short-circuit protection 0.55 0.65 0.75 V
voltage on pin SUPIC
Ich(red)(SUPIC) reduced charge current VSUPIC < Vscp(SUPIC) - 0.95 - mA
on pin SUPIC
Ich(nom)(SUPIC) nominal charge current on - 4.8 4.0 mA
pin SUPIC
Idism(SUPIC) current on pin SUPIC in Disabled IC state - 0.22 0.29 mA
disabled mode
Iprotm(SUPIC) current on pin SUPIC in SUPIC charge, SUPREG charge; - 0.4 - mA
protection mode Restart or Shutdown state
Ioper(SUPIC) current on pin SUPIC in Operational supply state; Driver pins - 3.2 3.7 mA
operating mode open.
Iburstm(SUPIC) burst mode current on pin Burst stop state - 0.6 0.75 mA
SUPIC
Regulated supply (pin SUPREG)
Vreg(SUPREG) regulation voltage on pin ISUPREG = 1 mA to 40 mA [1] 11.0 11.3 11.6 V
SUPREG
Vstart(SUPREG) start voltage on pin [1] - 10.7 - V
SUPREG
Vuvp(SUPREG) undervoltage protection [1] - 10 10.4 V
voltage on pin SUPREG
Ich(SUPREG)max maximum charge current VSUPREG > Vuvp(SUPREG) 40 100 - mA
on pin SUPREG
Ich(red)(SUPREG) reduced charge current VSUPREG < Vuvp(SUPREG); T = 25 C. - 5.5 - mA
on pin SUPREG T = 140 C - - 2.5 mA
Enable input (pin SSHBC/EN)
Ven(PFC)(EN) PFC enable voltage on PFC only [2] 0.8 1.2 1.4 V
pin EN
Ven(IC)(EN) IC enable voltage on pin PFC + HBC [2] 1.8 2.2 2.4 V
EN
Ipu(EN) pull-up current on pin EN VSSHBC/EN = 2.5 V - 42 - A
Vpu(EN) pull-up voltage on pin EN - 3.0 - V


Fast shut-down reset (pin SNSMAINS)
Vrst(SNSMAINS) reset voltage on pin [2] - 0.8 - V
SNSMAINS
Protection and restart timer (pin RCPROT)
Vu(RCPROT) upper voltage on pin 3.8 4.0 4.2 V
RCPROT
Vl(RCPROT) lower voltage on pin 0.4 0.5 0.6 V
RCPROT
Ich(fast)(RCPROT) fast-charge current on pin - 2.2 - mA
RCPROT
Ich(slow)(RCPROT) slow-charge current on 120 100 80 A
pin RCPROT
Output voltage protection sensing, OVP/FSP output (pin SNSOUT)
Vovp(SNSOUT) overvoltage protection [2] 3.40 3.50 3.60 V
voltage on pin SNSOUT
Vfsp(SNSOUT) failed start protection [2] 2.35 2.5 2.65 V
voltage on pin SNSOUT
Ipu(SNSOUT) pull-up current on pin - 75 - nA
SNSOUT
Overtemperature protection
Totp overtemperature [2] 130 150 160 C
protection trip
Burst mode activation (pin SNSBURST)
Vburst(SNSBURST) burst mode voltage on pin Burst stop state activation 3.42 3.5 3.58 V
SNSBURST
Vburst(hys)SNSBURST burst mode hysteresis - 23 - mV
voltage on pin
SNSBURST
Iburst(hys)SNSBURST burst mode hysteresis VSNSBURST < Vburst(SNSBURST) 2.5 3 3.5 A
current on pin
SNSBURST
Rpd(SNSOUT) pull-down resistance on Burst stop state - 400 - 
pin SNSOUT
PFC driver (pin GATEPFC)
Isource(GATEPFC) source current on pin VGATEPFC = 2 V - 0.6 A
GATEPFC
Isink(GATEPFC) sink current on pin VGATEPFC = 2 V - 0.6 - A
GATEPFC VGATEPFC = 10 V - 1.4 - A
PFC on-timer (pin COMPPFC)
Vton(COMPPFC)zero zero on-time voltage on - 3.5 - V
pin COMPPFC
Vton(COMPPFC)max maximum on-time voltage - 1.25 - V
on pin COMPPFC
fmax(PFC) PFC maximum frequency 100 125 150 kHz


toff(PFC)min minimum PFC off-time - 1.4 - s
PFC error amplifier (pins SNSBOOST and COMPPFC)
Vreg(SNSBOOST) regulation voltage on pin ICOMPPFC = 0 2.475 2.500 2.525 V
SNSBOOST
gm transconductance VSNSBOOST to ICOMPPFC; - 80 - A/V
|VSNSBOOST  Vreg(SNSBOOST)| < 40 mV
Isink(COMPPFC) sink current on pin VSNSBOOST = 2.0 V - 90 - A
COMPPFC
Isource(COMPPFC) source current on pin VSNSBOOST = 3.3 V - 90 - A
COMPPFC
Voffset(gm)high high-transconductance pin SNSBOOST; ICOMPPFC = 40 A - 100 - mV
offset voltage ICOMPPFC = +40 A - 100 - mV
Vclamp(COMPPFC) clamp voltage on pin [3] - 4 - V
COMPPFC
PFC mains compensation (pin SNSMAINS)
ton(max) maximum on-time high mains; VSNSMAINS = 3.3 V 3.5 4.7 5.9 s
low mains; VSNSMAINS = 0.97 V 29 44 59 s
Vmvc(SNSMAINS)max maximum mains voltage 4.0 - - V
compensation voltage on
pin SNSMAINS
PFC demagnetization sensing (pin SNSAUXPFC)
Vdemag(SNSAUXPFC) demagnetization voltage 150 100 50 mV
on pin SNSAUXPFC
tto(mag) magnetization time-out 40 50 60 s
time
Iprot(SNSAUXPFC) protection current on pin VSNSAUXPFC = 50 mV 75 33 - nA
SNSAUXPFC
PFC valley sensing (pin SNSAUXPFC)
(dV/dt)vrec(min) minimum valley - - 1.7 V/s
recognition rate of voltage
change
tslope(vrec)min minimum valley VSNSAUXPFC = 1 V (p-p) [4] - - 300 ns
recognition slope time demagnetization to V/t = 0 [5] - - 50 ns
td(val-dem)max maximum - 200 - ns
valley-to-demagnetization
delay time
tto(vrec) valley recognition time-out 3 4 6 s
time
PFC soft-start (pin SNSCURPFC)
Ich(ss)(PFC) PFC soft-start charge - 60 - A
current
Vclamp(ss)(PFC) PFC soft-start clamp [1] 0.44 0.50 0.56 V
voltage


Vstop(ss)(PFC) PFC soft-start stop [1] - 0.45 - V
voltage
Rss(PFC) PFC soft-start resistor 12 - - k
PFC overcurrent sensing (pin SNSCURPFC)
Vocr(PFC) PFC overcurrent dV/dt = 50 mV/s 0.49 0.52 0.55 V
regulation voltage dV/dt = 200 mV/s 0.51 0.54 0.57 V
tleb(PFC) PFC leading edge 250 310 370 ns
blanking time
Iprot(SNSCURPFC) protection current on pin 50 33 - nA
SNSCURPFC
PFC mains voltage sensing and clamp (pin SNSMAINS)
Vstart(SNSMAINS) start voltage on pin [1] 1.11 1.15 1.19 V
SNSMAINS
Vuvp(SNSMAINS) undervoltage protection [1] 0.84 0.89 0.94 V
voltage on pin SNSMAINS
Vpu(SNSMAINS) pull-up voltage on pin UVP-mains active [1] - 1.05 - V
SNSMAINS
Ipu(SNSMAINS) maximum clamp current UVP-mains active - 42 35 A
Iprot(SNSMAINS) Protection current on pin VSNSMAINS > Vuvp(SNSMAINS) - 33 100 nA
SNSMAINS
PFC boost voltage protection sensing, SCP/UVP/OVP boost (pin SNSBOOST)
Vscp(SNSBOOST) short circuit protection 0.35 0.40 0.45 V
voltage on pin
SNSBOOST
Vstart(SNSBOOST) start voltage on pin - 2.30 2.40 V
SNSBOOST
Vuvp(SNSBOOST) undervoltage protection 1.50 1.60 - V
voltage on pin
SNSBOOST
Vovp(SNSBOOST) overvoltage protection 2.59 2.63 2.67 V
voltage on pin
SNSBOOST
Iprot(SNSBOOST) protection current on pin VSNSBOOST = 2.4 V - 45 100 nA
SNSBOOST
HBC high-side and low-side driver (pin GATEHS and GATELS)
Isource(GATEHS) source current on pin VGATEHS  VHB = 4 V - 310 - mA
GATEHS
Isource(GATELS) source current on pin VGATELS  VPGND = 4 V - 310 - mA
GATELS
Isink(GATEHS) sink current on pin VGATEHS  VHB = 2 V; - 560 - mA
GATEHS VGATEHS  VHB = 11 V - 1.9 - A
Isink(GATELS) sink current on pin VGATELS  VPGND = 2 V - 560 - mA
GATELS VGATELS  VPGND = 11 V - 1.9 - A


Vrst(SUPHS) reset voltage on pin - 4.5 - V
SUPHS
Iq(SUPHS) quiescent current on pin VSUPHS  VHB = 11 V - 37 - A
SUPHS
HBC adaptive non-overlap time (pin HB)
(dV/dt)ano(min) minimum adaptive - - 120 V/s
non-overlap time rate of
voltage change
tno(min) minimum non-overlap - - 160 ns
time
HBC current controlled oscillator (pin CFMIN)
fmin(HB) minimum frequency on Cfmin = 390 pF; 40 45 50 kHz
pin HB VSSHBC/EN > Vfmin(SSHBC)
VSNSFB > Vfmin(SNSFB)
Iosc(min) minimum oscillator current charge and discharge 138 153 168 A
Iosc(burst)/Imin burst oscillator current to VSNSFB = 5 V; Imin = Iosc(min) = 153 A 2.50 2.72 2.93 -
minimum current ratio
Iosc(fbck)/Imin feedback oscillator current VSNSFB < Vfmax(SNSFB); 3.53 3.92 4.31 -
to minimum current ratio Imin = Iosc(min) = 153 A; maximum
oscillator feedback current
Iosc(ss)/Imin soft-start oscillator current VSSHBC/EN < Vfmax(SSHBC); 4.54 5.65 6.77 -
to minimum current ratio Imin = Iosc(min) = 153 A; maximum
oscillator soft-start current
Iosc(red) reduced oscillator current Slowed-down oscillator - 30 - A
flimit(HB) limit frequency on pin HB Cfmin = 20 pF 500 670 - kHz
Vu(CFMIN) upper voltage on pin 2.85 3.0 3.15 V
CFMIN
Vl(CFMIN) lower voltage on pin 0.9 1.0 1.1 V
CFMIN
HBC feedback input (pin SNSFB)
Volp(SNSFB) open-loop protection [2] 7.7 8.2 8.5 V
voltage on pin SNSFB
Vfmin(SNSFB) minimum frequency 6.1 6.4 6.9 V
Vfmax(SNSFB) maximum frequency VSSHBC/EN > Vfmin(SSHBC) 3.9 4.1 4.3 V
HBC soft-start (pin SSHBC/EN)
Vfmax(SSHBC) maximum frequency - 3.2 - V
voltage on pin SSHBC
Vfmin(SSHBC) minimum frequency VSNSFB > Vfmin(SNSFB) 7.7 8.0 8.3 V
voltage on pin SSHBC
Vclamp(SSHBC) clamp voltage on pin - 8.4 - V
SSHBC


Vss(hf-lf)(SSHBC) high-low frequency [2] - 5.6 - V
soft-start voltage on pin
SSHBC
Iss(hf)(SSHBC) high-frequency soft start VSSHBC < Vss(lf-hf)(SSHBC)
current on pin SSHBC charge current - 160 - A
discharge current - +160 - A
Iss(lf)(SSHBC) low-frequency soft start VSSHBC > Vss(lf-hf)(SSHBC)
current on pin SSHBC charge current - 40 - A
discharge current - +40 - A
Icmr(hf)(SSHBC) high frequency CMR VSSHBC < Vss(lf-hf)(SSHBC) discharge - 1800 - A
current on pin SSHBC only
Icmr(lf)(SSHBC) low frequency CMR VSSHBC > Vss(lf-hf)(SSHBC) discharge - 440 - A
current on pin SSHBC only
HBC high frequency sensing, HFP-HBC (pin CFMIN)
Iosc(hfp)/Imin high-frequency protection Imin = Iosc(min) = 153 A 3.89 4.31 4.73
oscillator current to
minimum current ratio
HBC overcurrent sensing, OCR/OCP-HBC (pin SNSCURHBC)
Vocr(HBC) HBC overcurrent
regulation voltage positive level; HS on + HS-LS +0.45 +0.50 +0.55 V
non-overlap time
negative level; LS on + LS-HS 0.55 0.50 0.45 V
non-overlap time
Vocp(HBC) HBC overcurrent
protection voltage positive level; HS on + HS-LS +1.6 +1.75 +1.9 V
non-overlap time
negative level; LS on + LS-HS 1.9 1.75 1.6 V
non-overlap time
Ibstc(SNSCURHBC)max maximum boost VSNSBOOST = 1.8 V
compensation current on source current; VSNSCURHBC = 0.5 V - 175 - A
pin SNSCURHBC
sink current; VSNSCURHBC = 0.5 V - 175 - A
HBC Capacitive Mode Protection (CMP) (pin HB)
tto(cmr) time-out capacitive mode - 690 - ns
regulation
[1] The marked levels on this pin are correlated. The voltage difference between the levels has much less spread than the absolute value of
the levels themselves.
[2] Switching level has some hysteresis. The hysteresis falls within the limits.
[3] For a typical application with a compensation network on the COMPPFC pin, like the example in Figure 17.
[4] Minimum required voltage change time for valley recognition on the SNSAUXPFC pin.
[5] Minimum time required between demagnetization detection and V/t = 0 on the SNSAUXPFC pin.

11. Application information
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12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
D E A
X
y HE v M A
24 13
Q
A2 A
A1 (A 3)
pin 1 index
θ
Lp
L
1 12 detail X
e w M
bp
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z
(1)
θ
max.
0.3 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9
mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1
0.1 2.25 0.36 0.23 15.2 7.4 10.00 0.4 1.0 0.4 8o
o
0.012 0.096 0.019 0.013 0.61 0.30 0.419 0.043 0.043 0.035 0
inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004
0.004 0.089 0.014 0.009 0.60 0.29 0.394 0.016 0.039 0.016
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
99-12-27
SOT137-1 075E05 MS-013
03-02-19
Fig 18. Package outline SOT137 (SO24)


13. Abbreviations
Table 8. Abbreviations
Acronym Description
ANO Adaptive Non-Overlap
CMOS Complementary Metal-Oxide-Semiconductor'
CMR Capacitive Mode Regulation
DMOS Double-diffused Metal-Oxide-Semiconductor
EMI ElectroMagnetic Interference
FSP Failed Start Protection
HBC Half-Bridge Converter or Controller. Resonant converter which generates the
regulated output voltage.
HFP High-Frequency Protection
HV High-voltage
OCP OverCurrent Protection
OCR OverCurrent Regulation
OLP Open-Loop Protection
OTP OverTemperature Protection
OVP OverVoltage Protection
PFC Power Factor Converter or Controller. Converter which performs the power factor
correction.
UVP UnderVoltage Protection
SCP Short-Circuit Protection

14. Revision history

Table 9. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TEA1716T v.3 20121130 Product data sheet - TEA1716T v.2
Modifications: • Text and drawings updated throughout entire data sheet.
TEA1716T v.2 20120821 Product data sheet - TEA1716T v.1
TEA1716T v.1 20120127 Objective data sheet - -

15. Legal information
15.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Draft — The document is a draft version only. The content is still under
malfunction of an NXP Semiconductors product can reasonably be expected
internal review and subject to formal approval, which may result in
to result in personal injury, death or severe property or environmental
modifications or additions. NXP Semiconductors does not give any
damage. NXP Semiconductors and its suppliers accept no liability for
representations or warranties as to the accuracy or completeness of
inclusion and/or use of NXP Semiconductors products in such equipment or
information included herein and shall have no liability for the consequences of
applications and therefore such inclusion and/or use is at the customer’s own
use of such information.
risk.
Short data sheet — A short data sheet is an extract from a full data sheet
Applications — Applications that are described herein for any of these
with the same product type number(s) and title. A short data sheet is intended
products are for illustrative purposes only. NXP Semiconductors makes no
for quick reference only and should not be relied upon to contain detailed and
representation or warranty that such applications will be suitable for the
full information. For detailed and full information see the relevant full data
specified use without further testing or modification.
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications
full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP
data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and
NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of
customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate
shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their
deemed to offer functions and qualities beyond those described in the applications and products.
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
15.3 Disclaimers customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Limited warranty and liability — Information in this document is believed to
Semiconductors products in order to avoid a default of the applications and
be accurate and reliable. However, NXP Semiconductors does not give any
the products or of the application or use by customer’s third party
representations or warranties, expressed or implied, as to the accuracy or
customer(s). NXP does not accept any liability in this respect.
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in
responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC 60134) will cause permanent
source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
In no event shall NXP Semiconductors be liable for any indirect, incidental,
the Recommended operating conditions section (if present) or the
punitive, special or consequential damages (including - without limitation - lost
Characteristics sections of this document is not warranted. Constant or
profits, lost savings, business interruption, costs related to the removal or
repeated exposure to limiting values will permanently and irreversibly affect
replacement of any products or rework charges) whether or not such
the quality and reliability of the device.
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Terms and conditions of commercial sale — NXP Semiconductors
Notwithstanding any damages that customer might incur for any reason products are sold subject to the general terms and conditions of commercial
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at http://www.nxp.com/profile/terms, unless otherwise
customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual
with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the
changes to information published in this document, including without purchase of NXP Semiconductors products by customer.
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or
to the publication hereof. construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein product for such automotive applications, use and specifications, and (b)
may be subject to export control regulations. Export might require a prior whenever customer uses the product for automotive applications beyond
authorization from competent authorities. NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
Non-automotive qualified products — Unless this data sheet expressly
liability, damages or failed product claims resulting from customer design and
states that this specific NXP Semiconductors product is automotive qualified,
use of the product for automotive applications beyond NXP Semiconductors’
the product is not suitable for automotive use. It is neither qualified nor tested
standard warranty and NXP Semiconductors’ product specifications.
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
15.4 Trademarks
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer Notice: All referenced brands, product names, service names and trademarks
(a) shall use the product without NXP Semiconductors’ warranty of the are the property of their respective owners.
16. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 7.7.2.2 PFC mains compensation
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 (SNSMAINS pin) . . . . . . . . . . . . . . . . . . . . . . 17
2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . 2 7.7.3 PFC demagnetization sensing
2.2 PFC controller features. . . . . . . . . . . . . . . . . . . 2 (SNSAUXPFC pin). . . . . . . . . . . . . . . . . . . . . 18
2.3 HBC controller features . . . . . . . . . . . . . . . . . . 2 7.7.4 PFC valley sensing
2.4 Protection features . . . . . . . . . . . . . . . . . . . . . . 2 (SNSAUXPFC pin). . . . . . . . . . . . . . . . . . . . . 18
7.7.5 PFC frequency and off-time limiting . . . . . . . . 19
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
7.7.6 PFC soft-start and soft-stop
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 (SNSCURPFC pin) . . . . . . . . . . . . . . . . . . . . 19
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.7.7 PFC overcurrent regulation,
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 OCR-PFC (SNSCURPFC pin) . . . . . . . . . . . . 20
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.7.8 PFC mains undervoltage protection/brownout
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 protection, UVP-mains
7 Functional description . . . . . . . . . . . . . . . . . . . 6 (SNSMAINS pin) . . . . . . . . . . . . . . . . . . . . . . 20
7.1 Overview of IC modules . . . . . . . . . . . . . . . . . . 6 7.7.9 PFC boost overvoltage protection,
7.2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OVP-boost (SNSBOOST pin) . . . . . . . . . . . . 21
7.2.1 Low-voltage supply input 7.7.10 PFC short circuit/open-loop protection,
(SUPIC pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SCP/OLP-PFC (SNSBOOST pin) . . . . . . . . . 21
7.2.2 Regulated supply 7.8 HBC controller . . . . . . . . . . . . . . . . . . . . . . . . 21
(SUPREG pin) . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.8.1 HBC high-side and low-side driver
7.2.3 High-side driver floating supply (GATEHS and GATELS pins). . . . . . . . . . . . . 21
(SUPHS pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.8.2 HBC boost undervoltage protection,
7.2.4 High-voltage supply input UVP-boost (SNSBOOST pin) . . . . . . . . . . . . 21
(SUPHV pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.8.3 HBC switch control. . . . . . . . . . . . . . . . . . . . . 22
7.3 Flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.8.4 HBC Adaptive Non-Overlap
7.4 Enable input (ANO) time function (HB pin) . . . . . . . . . . . . . 22
(SSHBC/EN pin) . . . . . . . . . . . . . . . . . . . . . . . 11 7.8.4.1 Inductive mode (normal operation) . . . . . . . . 22
7.5 IC protection . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.8.4.2 Capacitive mode . . . . . . . . . . . . . . . . . . . . . . 24
7.5.1 IC restart and shutdown . . . . . . . . . . . . . . . . . 12 7.8.5 HBC slope controlled oscillator
7.5.2 Protection and restart timer . . . . . . . . . . . . . . 13 (pin CFMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5.2.1 Protection timer . . . . . . . . . . . . . . . . . . . . . . . 13 7.8.6 HBC feedback input (SNSFB pin) . . . . . . . . . 26
7.5.2.2 Restart timer . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.8.7 HBC open-loop protection, OLP-HBC
7.5.3 Fast shutdown reset (SNSFB pin). . . . . . . . . . . . . . . . . . . . . . . . . . 26
(SNSMAINS pin). . . . . . . . . . . . . . . . . . . . . . . 14 7.8.8 HBC soft-start (pin SSHBC/EN) . . . . . . . . . . . 26
7.5.4 Output overvoltage protection 7.8.8.1 Soft-start voltage levels . . . . . . . . . . . . . . . . . 26
(SNSOUT pin) . . . . . . . . . . . . . . . . . . . . . . . . 14 7.8.8.2 Soft-start charge and discharge . . . . . . . . . . . 27
7.5.5 Output failed start protection, FSP-output 7.8.8.3 Soft-start reset . . . . . . . . . . . . . . . . . . . . . . . . 27
(SNSOUT pin) . . . . . . . . . . . . . . . . . . . . . . . . 14 7.8.9 HBC high-frequency protection, HFP-HBC . . 28
7.5.6 OverTemperature Protection 7.8.10 HBC overcurrent regulation and protection, OCR
(OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 and OCP (SNSCURHBC pin) . . . . . . . . . . . . 28
7.6 Burst mode operation 7.8.10.1 Boost voltage compensation . . . . . . . . . . . . . 28
(SNSBURST pin) . . . . . . . . . . . . . . . . . . . . . . 15 7.8.10.2 OverCurrent Regulation
7.7 PFC controller. . . . . . . . . . . . . . . . . . . . . . . . . 15 (OCR-HBC) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.7.1 PFC gate driver 7.8.10.3 OverCurrent Protection
(GATEPFC pin). . . . . . . . . . . . . . . . . . . . . . . . 16 (OCP-HBC) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.7.2 PFC on-time control . . . . . . . . . . . . . . . . . . . . 16 7.8.11 HBC capacitive mode regulation,
7.7.2.1 PFC error amplifier CMR (HB pin). . . . . . . . . . . . . . . . . . . . . . . . . 31
(COMPPFC and SNSBOOST pins) . . . . . . . . 16 7.9 Protection functions overview . . . . . . . . . . . . 31
continued >>

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 32
9 Thermal characteristics . . . . . . . . . . . . . . . . . 33
10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 33
11 Application information. . . . . . . . . . . . . . . . . . 40
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 41
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 42
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 43
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 44
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 44
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 45
16 Contact information. . . . . . . . . . . . . . . . . . . . . 45
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 November 2012
Document identifier: TEA1716T

TEA1716T: 1. General Description

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TEA1716T

Resonant power supply control IC with PFC

Efficient PFC operation is achieved by implementing functions for Quasi-Resonant (QR)

The high-voltage chip is fabricated using a proprietary high-voltage Bipolar-CMOS-DMOS

Remark: Unless otherwise stated, all values are typical.

2. Features and benefits

2.1 General features

2.2 PFC controller features

2.3 HBC controller features

2.4 Protection features

Product data sheet Rev. 3 — 30 November 2012 2 of 47

Product data sheet Rev. 3 — 30 November 2012 3 of 47

616%2267 683+9 683,& 6835(*

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29(5 9 7:263((' 

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Fig 1. TEA1716T block diagram

Product data sheet Rev. 3 — 30 November 2012 4 of 47

Fig 2. TEA1716T pin configuration

6.2 Pin description

Product data sheet Rev. 3 — 30 November 2012 5 of 47

Table 2. Pin description …continued

7.1 Overview of IC modules

Product data sheet Rev. 3 — 30 November 2012 6 of 47

7.2 Power supply

7.2.1 Low-voltage supply input (SUPIC pin)

• from the internal high-voltage start-up source

• High voltage present on the SUPHV pin (VSUPHV > Vdet(SUPHV)).

Product data sheet Rev. 3 — 30 November 2012 7 of 47

• Boost charge state

7.2.2 Regulated supply (SUPREG pin)

• Supply the internal PFC driver

SUPREG is provided with undervoltage protection (UVP-SUPREG; see Section 7.9).

Product data sheet Rev. 3 — 30 November 2012 8 of 47

7.2.3 High-side driver floating supply (SUPHS pin)

7.2.4 High-voltage supply input (SUPHV pin)

7.3 Flow diagram

Product data sheet Rev. 3 — 30 November 2012 9 of 47

3URWHFWLRQWLPHU 893ERRVW \HV

8936835(* \HV 893683,& \HV 273 \HV %XUVWVWRS QR

Fig 3. Flow diagram of the TEA1716T

Product data sheet Rev. 3 — 30 November 2012 10 of 47

Table 3. Operating states

7.4 Enable input (SSHBC/EN pin)

Product data sheet Rev. 3 — 30 November 2012 11 of 47

'LVDEOHVXSSO\ 9HQ ,& (1

Fig 4. Circuit configuration around the SSHBC/EN pin

7.5.1 IC restart and shutdown

Product data sheet Rev. 3 — 30 November 2012 12 of 47

7.5.2 Protection and restart timer

7.5.2.1 Protection timer

short long repetative

Fig 5. Operation of the protection timer

7.5.2.2 Restart timer

Product data sheet Rev. 3 — 30 November 2012 13 of 47

Fig 6. Operation of the restart timer

7.5.3 Fast shutdown reset (SNSMAINS pin)

7.5.4 Output overvoltage protection (SNSOUT pin)

7.5.5 Output failed start protection, FSP-output (SNSOUT pin)

3*1' 9 29(5&855(17 9 29(5&855(17

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