Digital System Design 17EE35

MODULE 3

Flip Flops and Characteristic Equation

Structure
3.1 Objevtive
3.2 Introduction
3.3 Basic Bistable element
3.4 Latches, SR latch,
3.5 Application of SR latch,-A Switch debouncer.
3.6 The gated SR latch.
3.7 The gated D Latch,
3.8 The Master-Slave Flip-Flops (Pulse-Triggered Flip-Flops): The master-slave SR Flip-Flops,
The master-slave JK Flip-Flop,
3.9 Edge Triggered Flip-flop: The Positive Edge-Triggered D Flip-Flop, Negative-Edge
Triggered D Flip-Flop - Characteristic equations.
3.10 Registers,
3.11 Counters-Binary Ripple Counter, Synchronous Binary counters, Counters based on Shift
Registers,
3.12 Design of a Synchronous counters, Design of a Synchronous Mod-N counters using clocked
JK FlipFlops
3.13 Design of a Synchronous Mod-N counter using clocked D, T, or SR Flip-Flops.
3.14 Outcome
3.15 Future Readings

3.1 Objevtive
• To know different between latches and flip flops
• Data storage elements
• Designing of flip flops
• Design of synchronous Mod N for all the flip flops
3.2 Introduction
Logic circuit is divided into two types.

1. Combinational Logic Circuit

2. Sequential Logic Circuit
Definition :

1. Combinational Logic Circuit :

The circuit in which outputs depends on only present value of inputs. So it is possible to
describe each output as function of inputs by using Boolean expression. No memory
element involved. No clock input. Circuit is implemented by using logic gates. The
propagation delay depends on, delay of logic gates. Examples of combinational logic
circuits are : full adder, subtractor, decoder, codeconverter, multiplexers etc.

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inputs Combinational
outputs
Logic Circuit

2. Sequential Circuits :
Sequential Circuit is the logic circuit in which output depends on present value of inputs
at that instant and past history of circuit i.e. previous output. The past output is stored by
using memory device. The internal data stored in circuit is called as state. The clock is
required for synchronization. The delay depends on propagation delay of circuit and
clock frequency. The examples are flip-flops, registers, counters etc.

inputs outputs
Combinational
Logic Circuit

Memory Device

3.3 Basic Bistable element

o Flip-Flop is Bistable element.
o It consist of two cross coupled NOT Gates.
o It has two stable states.
o Q and Q are two outputs complement of each other.
o The data stored 1 or 0 in basic bistable element is state of flip-flop.
o 1 – State is set condition for flip-flop.
o 0 – State is reset / clear for flip-flop.
o It stores 1 or 0 state as long power is ON.

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Digital System Design 17EE35

3.4 Latches, SR latch

S-R Latch : Set-reset Flip-Flop

Flip
Latch is a storage device by using Flip-Flop.
Latch can be controlled by direct inputs.
Latch outputs can be controlled by clock or enable input.
Q and Q
Q are present state for output.
Q+ and Q+ are next states for output.
The function table / Truth table gives relation between inputs and outputs.
The S=R=1 condition
ition is not allowed in SR FF as output is unpredictable.

3.5 Application of SR latch- A Switch debouncer.

A switch debouncer

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Bouncing problem with Push button switch.

Debouncing action.
SR Flip-Flop
Flop as switch debouncer.

3.6 The gated SR latch. Characteristic equations,

Enable input C is clock input.

C=1, Output changes as per input condition.
C=0, No change of state.
Flip
S=1, R=0 is set condition for Flip-flop.
Flip
S=0, R=1 is reset condition for Flip-flop.
S=R=1 is ambiguous state, not allowed.

3.7 The gated D Latch Characteristic equations,

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D Flip-Flop is Data Flip-Flop.

D Flip-Flop
Flop stores 1 or 0.
R input is complement of S.
Only one D input is present.
D Flip-Flop
Flop is a storage device used in register.

3.8 The Master-Slave Flip-Flops (Pulse

Flops (Pulse-Triggered Flops): The master-slave SR Flip-
Flip-Flops):
Flops, The master-slave Flip
slave JK Flip-Flop Characteristic equations,

Two SR Flip-Flop, 1st is Master and 2nd is slave.

Master Flip-Flop
Flop is positive edge triggered.
Slave Flip-Flop
Flop is negative edge triggered.

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Digital System Design 17EE35

Slave follows master output.

The output is delayed.
Master slave JK Flip-Flop Characteristic equations,

In SR Flip-Flop
Flop the input combination S=R=1 is not allowed.
JK FF is modified version of SR FF.
Due to feedback from slave FF output to master, J=K=1 is allowed.
J=K=1, toggle, action in FF.
This finds application in counter.

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Digital System Design 17EE35

3.9 Edge Triggered Flip-flop: The Positive Edge-Triggered D Flip--Flop, Negative-Edge

Triggered D Flip-Flop. Characteristic equations,
Positive Edge Triggered D Flip
Flip-Flop

When C=0, the output of AND Gate 2 & 3 is equal to 1.

S = R = 1, No Change of State
If C=1, D=1, the output of AND Gate 2 is 0 and 3 is 1.

S = 0, R = 1, Q = 1 and Q = 0

3.10 Registers
Register is a group of Flip
Flip-Flops.
It stores binary information 0 or 1.
It is capable of moving data left or right with clock pulse.
Registers are classified as
• Serial-in
in Serial
Serial-Out
• Serial-in
in parallel Out
• Parallel-in
in Serial
Serial-Out

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• Parallel-in
in parallel Out

Parallel-in
in Unidirectional Shift Register

Parallel input data is applied at IAIBICID.

Parallel output QAQBQCQD.
Serial input data is applied to A FF.
Serial output data is at output of D FF.
L/Shift
L/Shift is common control input.
L/S
L/S = 0, Loads parallel data into register.
L/S
L/S = 1, shifts the data in one direction.

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Universal Shift Register

Bidirectional Shifting.
Parallel Input Loading.
Serial-Input Serial
Input and Serial-Output.
Parallel-Input Serial
Input and Serial-Output.
Common Reset Input.
4:1 Multiplexer is used to select register operation.

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Digital System Design 17EE35

3.11 Counters-Binary Ripple Counter, Synchronous Binary counters, Counters based on

Shift Registers
Counter is a register which counts the sequence in binary form.
The state of counter changes with application of clock pulse.
The counter is binary or non-binary.
The total no. of states in counter is called as modulus.
If counter is modulus-n, then it has n different states.
State diagram of counter is a pictorial representation of counter states directed by arrows
in graph.

000
111
001

110 010

101 011

100

Fig. State diagram of mod-8 counter

4-bit Binary Ripple Counter :

All Flip-Flops are in toggle mode.

The clock input is applied.
Count enable = 1.
Counter counts from 0000 to 1111.

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Synchronous Binary Counter :

The clock input is common to all Flip-Flops.

The T input is function of the output of previous flip-flop.
Extra combination circuit is required for flip-flop input.

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Counters Based on Shift Register

The output of LSB FF is connected as D input to MSB FF.

This is commonly called as Ring Counter or Circular Counter.
The data is shifted to right with each clock pulse.
This counter has four different states.

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This can be extended to any no. of bits.

Twisted Ring Counter or Johnson Counter

The complement output of LSB FF is connected as D input to MSB FF.

This is commonly called as Johnson Counter.
The data is shifted to right with each clock pulse.
This counter has eight different states.
This can be extended to any no. of bits.

Mod-7 Twisted Ring Counter

The D input to MSB FF is Q D .Q C

The counter follows seven different states with application of clock input.
By changing feedback different counters can be obtained.

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3.12 Design of a Synchronous counters, Design of a Synchronous Mod-N counters using

clocked JK Flip Flops
The clock input is common to all Flip-Flops.

Any Flip-Flop can be used.

For mod-n counter 0 to n-1 are counter states.

The excitation table is written considering the present state and next state of counter.

The flip-flop inputs are obtained from characteristic equation.

By using flip-flops and logic gate the implementation of synchronous counter is obtained.

Difference between Asynchronous and Synchronous Counter :

Asynchronous Counter Synchronous Counter

1. Clock input is applied to LSB FF. The output 1. Clock input is common to all FF.
of first FF is connected as clock to next FF.

2. All Flip-Flops are toggle FF. 2. Any FF can be used.

3. Speed depends on no. of FF used for n bit . 3. Speed is indepenSdent of no. of FF used.

4. No extra Logic Gates are required. 4. Logic Gates are required based on
design.

5. Cost is less. 5. Cost is more.

3.13 Design of a Synchronous Mod-N counter using clocked D, T, or SR Flip-Flops.

2Bit binary synchronous counter

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The flip-flop delay time and possibility of glitches are overcome by the use of a synchronous
ornparallel counter. Every flip-flop is triggered in synchronism with the clock

3.14 Outcome
• Student will knoe the necessity of flip flops and its importance
• Design flip flops based on the characteristic equations.
• Will be able to design N Mod Synchronous counter

3.15 Future Readings

http://nptel.ac.in/courses/117105080/

https://www.youtube.com/watch?v=VnZLRrJYa2I

“Logic Design” by RD Sudhaker Samuel

“Digital Logic Applications and Design” by John M Yarbrough, 2011 edition

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