D.V.R.K Raju et al. Int. Journal of Engineering Research and Applications www.ijera.

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ISSN : 2248-9622, Vol. 5, Issue 3, ( Part -5) March 2015, pp.01-04

RESEARCH ARTICLE OPEN ACCESS

UART Serial Communication Module Design and Simulation

Based on VHDL
D.V.R.K Raju1, B.Narsingarao2, K.Vikash3, D. Akshay Kumar4 , S.Rama
Krishna5
Department Of Ece, Lendi Institute Of Engineering And Technology, Vzm.

Abstract
UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol; mostly used
for short-distance, low speed, low-cost data exchange between computer and peripherals. During the actual
industrial production, sometimes we do not need the full functionality of UART, but simply integrate its core
part. UART includes three kernel modules which are the baud rate generator, receiver and transmitter. The
UART implemented with VHDL language and simulated using XILINX ISE12.1 to achieve compact, stable and
reliable data transmission. It’s significant for the design of SOC. The simulation results are completely
consistent.
Keywords- UART; asynchronous serial communication; VHDL; XILINX ISE12.1.

I. INTRODUCTION is used to alert the receiver that a word of data is

Asynchronous serial communication has about to be sent, and to force the clock in the receiver
advantages of less transmission line, high reliability, into synchronization with the clock in the transmitter.
and long transmission distance, therefore is widely These two clocks must be accurate enough to not
used in data exchange between computer and have the frequency drift by more than 10% during the
peripherals. Asynchronous serial communication is transmission of the remaining bits in the word [4].
usually implemented by Universal Asynchronous After the Start Bit, the individual data bits of the
Receiver Transmitter (UART) [1]. UART allows word are sent, with the Least Significant Bit (LSB)
full-duplex communication in serial link, thus has being sent first. Each bit in the transmission is
been widely used in the data communications and transmitted for exactly the same amount of time as all
control system. In actual applications, usually only a of the other bits, and the receiver “looks” at the wire
few key features of UART are needed. Specific at approximately halfway through the period assigned
interface chip will cause waste of resources and to each bit to determine if the bit is a 1 or a 0. For
increased cost. Particularly in the field of electronic example, if it takes two seconds to send each bit, the
design, SOC technology is recently becoming receiver will examine the signal to determine if it is a
increasingly mature. This situation results in the 1 or a 0 after one second has passed, then it will wait
requirement of realizing the whole system function two seconds and then examine the value of the next
in a single or a very few chips. Designers must bit, and so on.
integrate the similar function module into FPGA. When the entire data word has been sent, the
This paper uses VHDL to implement the UART transmitter may add a Parity Bit that the transmitter
core functions and integrate them into a FPGA chip generates. The Parity Bit may be used by the receiver
to achieve compact, stable and reliable data to perform simple error checking. Then at least one
transmission, which effectively solves the above Stop Bit is sent by the transmitter.
problem [2] [3]. When the receiver has received all of the bits in
Basic UART communication needs only two the data word, it may check for the Parity Bits (both
signal lines (RXD, TXD) to complete full-duplex sender and receiver must agree on whether a Parity
data communication. TXD is the transmit side, the Bit is to be used), and then the receiver looks for a
output of UART; RXD is the receiver, the input of Stop Bit. If the Stop Bit does not appear when it is
UART. UART’s basic features are: There are two supposed to, the UART considers the entire word to
states in the signal line, using logic 1 (high) and be garbled and will report a Framing Error to the host
logic 0 (low) to distinguish respectively. For processor when the data word is read. The usual
example, when the transmitter is idle, the data line cause of a Framing Error is that the sender and
is in the high logic state. Otherwise when a word is receiver clocks were not running at the same speed,
given to the UART for asynchronous transmissions, or that the signal was interrupted.
a bit called the "Start Bit" is added to the beginning Regardless of whether the data was received
of each word that is to be transmitted. The Start Bit correctly or not, the UART automatically discards the

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D.V.R.K Raju et al. Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 5, Issue 3, ( Part -5) March 2015, pp.01-04

Start, Parity and Stop bits. If the sender and receiver M =32MHz/16*9600Hz=208
are configured identically, these bits are not passed
to the host. When the UART receives serial data, it is very
If another word is ready for transmission, the critical to determine where to sample the data
Start Bit for the new word can be sent as soon as the information. The ideal time for sampling is at the
Stop Bit for the previous word has been sent. middle point of each serial data bit. In this design, the
Because asynchronous data are “self- receive clock frequency is designed to be 16 times
synchronizing”, if there are no data to transmit, the the baud rate, therefore, each data width received by
transmission line can be idle. The UART frame UART is 16 times the receive clock cycle.
format is shown in Fig. 1.
B. Receiver Module
During the UART reception, the serial data and
the receiving clock are asynchronous, so it is very
important to correctly determine the start bit of a
frame data. The receiver module receives data from
RXD pin. RXD jumps into logic 0 from logic 1 can
Figure 1. UART Frame Format be regarded as the beginning of a data frame. When
the UART receiver module is reset, it has been
II. IMPLEMENTATION OF UART waiting the RXD level to jump. The start bit is
In this paper, the top to bottom (Top to Down) identified by detecting RXD level changes from high
design method is used. The UART serial to low. In order to avoid the misjudgment of the start
communication module is divided into three sub- bit caused by noise, a start bit error detect function is
modules: the baud rate generator, receiver module added in this design, which requires the received low
and transmitter module, shown in Fig. 2. Therefore, level in RXD at least over 50% of the baud rate to be
the implementation of the UART communication able to determine the start bit arrives. Since the
module is actually the realization of the three sub- receive clock frequency is 16 times the baud rate in
modules. The baud rate generator is used to produce the design, the RXD low level lasts at least 8
a local clock signal which is much higher than the receiving clock cycles is considered start bit arrives.
baud rate to control the UART receive and transmit; Once the start bit been identified, from the next bit,
The UART receiver module is used to receive the begin to count the rising edge of the baud clock, and
serial signals at RXD, and convert them into parallel sample RXD when counting. Each sampled value of
data; The UART transmit module converts the bytes the logic level is deposited in the register rbuf [7, 0]
into serial bits according to the basic frame format by order. When the count equals 8, all the data bits
and transmits those bits through TXD. are surely received, also the 8 serial bits are
converted into a byte parallel data.
The serial receiver module includes receiving,
serial and parallel transform, and receive caching,
etc. In this paper we use finite state machine to
design, shown in Fig. 3.

Figure 2. UART Module

A. Baud Rate Generator

Baud Rate Generator is actually a frequency
divider. The baud rate frequency factor can be
calculated according to a given system clock
frequency (oscillator clock) and the requested baud
rate. The calculated baud rate frequency factor is
used as the divider factor. In this design, the
frequency clock produced by the baud rate
generator is not the baud rate clock, but 16 times the
baud rate clock. The purpose is to precisely sample
the asynchronous serial data at the receiver. Assume
that the system clock is 32MHz, baud rate is
9600bps, and then the output clock frequency of Figure 3. UART Receiver State Machine
baud rate generator should be 16 * 9600Hz.
Therefore the frequency coefficient (M) of the baud The state machine includes five states:
rate generator is: R_START (waiting for the start bit), R_CENTER
(find midpoint), R_WAIT (waiting for the sampling),
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ISSN : 2248-9622, Vol. 5, Issue 3, ( Part -5) March 2015, pp.01-04

R_SAMPLE (sampling), and R_STOP (receiving into the register txdbuf [7: 0]. The transmitter only
stop bit). needs to output 1 bit every 16 bclkt (the transmitting
R_START Status: When the UART receiver is clock frequency generated by the baud rate
reset, the receiver state machine will be in this state. generator) cycles. The order follows 1 start bit, 8 data
In this state, the state machine has been waiting for bits, 1 parity bit and 1 stop bit. The parity bit is
the RXD level to jump over from logic 1 to logic 0, determined according to the number of logic 1 in 8
i.e. the start bit. This alerts the beginning of a new data bits. Then the parity bit is output. Finally, logic
data frame. Once the start bit is identified, the state 1 is output as the stop bit. Fig. 4 shows the transmit
machine will be transferred to R_CENTER state. In module state diagram.
Fig. 3, RXD_SYNC is a synchronization signal of
RXD. Because when sampling logic 1 or logic 0, we
do not want the detected signal to be unstable. So
we do not directly detect RXD signal, but detect the
synchronization signal RXD_SYNC.
R_CENTER Status: For asynchronous serial
signal, in order to detect the correct signal each
time, and minimize the total error in the later data
bits detection. Obviously, it is the most ideal to
detect at the middle of each bit. In this state, the task
is to find the midpoint of each bit through the start
bit. The method is by counting the number of bclkr
(the receiving clock frequency generated by the
baud rate generator) (RCNT16 is the counter of
bclkr). In addition, the start bit detected in the
R_START may not be a really start bit, it may be an Figure 4. Transmit Module State Diagram
occasional interference sharp pulse (negative pulse).
This interference pulse cycle is very short. This state machine has 5 states: X_IDLE (free),
Therefore, the signal that maintains logic 0 over 1 / X_START (start bit), X_WAIT (shift to wait),
4 bit time must be a start bit. X_SHIFT (shift), X_STOP (stop bit).
R_WAIT Status: When the state machine is in X_IDLE Status: When the UART is reset, the
this state, waiting for counting bclkr to 15, then state machine will be in this state. In this state, the
entering into R_SAMPLE to sample the data bits at UART transmitter has been waiting a data frame
the 16th bclkr. At the same time determining sending command XMIT_CMD. XMIT_CMD_P is a
whether the collected data bit length has reached the processed signal of XMIT_CMD, which is a short
data frame length (FRAMELEN). If reaches, it pulse signal. Since XMIT_CMD is an external signal,
means the stop bits arrives. The FRAMELEN is outside FPGA, its pulse width is unable to be limited.
modifiable in the design (using the Generic). In this If XMIT_CMD is valid, it is still valid after sending
design it is 8, which corresponds to the 8-bit data one UART data frame. Then the UART transmitter
format of UART. will think by mistake that a new data transmit
R_SAMPLE Status: Data bit sampling. After command has arrived, and once again start the frame
sampling the state machine transfers to R_WAIT transmit. Obviously the frame transmit is wrong.
state unconditionally, waits for the arrival of the Here we limit the pulse width of XMIT_CMD.
next start bit. XMIT_ CMD_P is its processed signal. When
R_STOP Status: Stop bit is either 1 or 1.5, or 2. XMIT_CMD_P = '1 ', the state machine transferred
State machine doesn’t detect RXD in R_STOP, but to X_START, get ready to send a start bit.
output frame receiving done signal (REC_DONE X_START Status: In this state, sends a logic 0 signal
<= '1 '). After the stop bit, state machine turns back to the TXD for one bit time width, the start bit. Then
to R_START state, waiting for the next frame start the state machine transferred to X_WAIT state.
bit. XCNT16 is the counter of bclkt.
X_WAIT Status: Similar with the R_WAIT of
C. Transmit Module UART receive state machine.
The function of transmit module is to convert
the sending 8-bit parallel data into serial data, adds X_SHIFT Status: In this state, the state machine
start bit at the head of the data as well as the parity realizes the parallel to serial conversion of outgoing
and stop bits at the end of the data. When the UART data. Then immediately return to X_WAIT state.
transmit module is reset by the reset signal, the X_STOP Status: Stop bit transmit state. When
transmit module immediately enters the ready state the data frame transmit is completed, the state
to send. In this state, the 8-bit parallel data is read machine transferred to this state, and sends 16 bclkt

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D.V.R.K Raju et al. Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 5, Issue 3, ( Part -5) March 2015, pp.01-04

cycle logic 1 signal, that is, 1 stop bit. The state The simulation report shows that this module uses 78
machine turns back to X_IDLE state after sending logic elements（<1%, 13 pins (4%), and meets
the stop bit, and waits for another data frame timing requirement.
transmit command.

III. SIMULATION OF MODULES

The simulation software is XILINX ISE12.1.

A. Baud Rate Generator Simulation

During simulation, the system clock frequency
is set to 32MHz, and baud rate is set to 9600bps. Figure 7 Transmitter Simulation Diagram
Therefore the receiving sampling clock frequency
generated by the baud rate generator is 153600Hz, D. RTL of Top File
which is 16 times of the baud rate. Thus the Fig. 8 shows the RTL of UART Top File. It
frequency coefficient of baud rate generator can be includes the baud rate generator, receiver, and
calculated, which equals 208. Fig. 5 shows the transmitter modules.
simulation result of baud rate generator. The
simulation report shows that this module uses 42
logic elements （<1% ）, 33 registers (2%), and
meets timing requirement.

Figure 5. Simulation Result of Baud Rate Figure 8. RTL of Top File

Generator
IV. CONCLUSION
B. Receiver Simulation This design uses VHDL as design language to
During receiver simulation, the receiving achieve the modules of UART. Using Xilinx ise12.1
sampling clock frequency generated by the baud software to complete simulation and test. The results
rate generator is set to 153600 Hz, UART receiving are stable and reliable. The design has great
baud rate is set to 9600bps. The input sequence is: flexibility, high integration, with some reference
00110110001, including the start bit 0, parity bit 0 value. Especially in the field of electronic design,
and 1 stop bit. The received data is stored into the where SOC technology has recently become
register rbuf. Fig. 6 shows the receiver module increasingly mature, this design shows great
simulation diagram. The figure shows that the data significance.
in rbuf from high to low is 00110110, which is just
the part of data bits of UART frame. REFERENCES
[1] Zou,Jie Yang,Jianning。Design and
Realization of UART Controller Bas ed on
FPGA
[2] Liakot Ali ， Roslina Sidek， Ishak Aris，
Alauddin Mohd. Ali， Bambang Sunaryo
Suparjo. Design of a micro - UART for SoC
application [J].In: Computers and Electrical
Engineering 30 (2004) 257– 268.
Figure 6. Receiver Simulation Diagram [3] HU Hua, BAI Feng-e. Design and
Simulation of UART Serial Communication
C. Transmitter Simulation Module Based on Verilog -HDL[J]. J
During transmitter simulation, the sending ISUANJ I YU XIANDA IHUA 2008 Vol. 8
clock frequency generated by the baud rate [4] Frank Durda Serial and UART Tutorial.
generator is set to 153600 Hz, and UART uhclem@FreeBSD.org
transmitting baud rate is set to 9600bps. Fig. 7
shows the transmitter module simulation diagram.
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