M74HC76

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

■ HIGH SPEED :
fMAX = 67MHz (TYP.) at VCC = 6V
■ LOW POWER DISSIPATION:
ICC =2µA(MAX.) at TA=25°C
■ HIGH NOISE IMMUNITY:
VNIH = V NIL = 28 % VCC (MIN.)
( s )
■ SYMMETRICAL OUTPUT IMPEDANCE: DIP

c t SOP TSSOP

■
|IOH| = IOL = 4mA (MIN)
BALANCED PROPAGATION DELAYS:
d u
tPLH ≅ tPHL
r o
ORDER CODES
s )
■ WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
e P
PACKAGE

c t ( TUBE T&R

■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 76
l e t DIP
SOP
d u
M74HC76B1R
M74HC76M1R M74HC76RM13TR

s o r o
TSSOP M74HC76TTR
DESCRIPTION
b
The M74HC76 is an high speed CMOS DUAL J-K
O e P
and PRESET (PR) are independent of the clock
FLIP FLOP WITH CLEAR fabricated with silicon
gate C2MOS technology. - l e t and are accomplished by a logic low on the

s ) o
Depending on with the logic level at J and K
(
corresponding input.
All inputs are equipped with protection circuits

c t b s
inputs, this device changes state on the negative
going transition of clock pulse (CK). CLEAR (CLR)
against static discharge and transient excess
voltage.

d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
PIN CONNECTION AND IEC LOGIC SYMBOLS

s o
O b

August 2001 1/11

 M74HC76

INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION

Clock Input(HIGH to LOW
1, 6 1CK, 2CK
edge triggered)
2, 7 1PR, 2PR Set Inputs (Active LOW)
Asynchronous Reset
3, 8 1CLR, 2CLR
Inputs (Active LOW)
Data Inputs: Flip-Flop 1
4, 9 1J, 2J
and 2
Complement Flip-Flop
10, 14 1Q, 2Q
Outputs
11, 15 1Q, 2Q

( s )
True Flip-Flop Outputs
Data Inputs: Flip-Flop 1

t
16, 12 1K, 2K
and 2
13
u c
GND Ground (0V)
5

o d Vcc Positive Supply Voltage

)
P r ( s
TRUTH TABLE

t e c t
INPUTS

l e u
OUTPUTS

d FUNCTION
CLR PR J K CK

s o Q
r o Q
L
H
H
L
X
X
X
X
O b
X
X
e PL
H
H
L
CLEAR
PRESET
L L X X
- X

l e t H H ----
H H L

( s
L
) o
Qn Qn NO CHANGE
H H L

c t H
b s L H ----
H
H
H
H
d u H
H
L
H
- O H
Qn Qn
L ----
TOGGLE
H
rHo X
sX) Qn Qn NO CHANGE
X : Don’t Care

e P c t (
e t
LOGIC DIAGRAM
l d u
s o r o
O b e P
l e t
s o
O b

2/11
 M74HC76

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC Supply Voltage -0.5 to +7 V
VI DC Input Voltage -0.5 to VCC + 0.5 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Current ± 25 mA
ICC or IGND DC VCC or Ground Current ± 50 mA
PD Power Dissipation 500(*) mW
Tstg Storage Temperature -65 to +150
( s ) °C
TL Lead Temperature (10 sec) 300
c t °C

not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
d u
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is

r o s)
P t(
RECOMMENDED OPERATING CONDITIONS

Symbol Parameter
t e Value
u c Unit
VCC Supply Voltage
o l e o d
2 to 6 V
VI
VO
Input Voltage
Output Voltage
b s P r 0 to VCC
0 to VCC
V
V
Top Operating Temperature
- O te -55 to 125 °C
Input Rise and Fall Time
) VCC = 2.0V
le 0 to 1000 ns
tr, tf

c t ( s
b so
VCC = 4.5V
VCC = 6.0V
0 to 500
0 to 400
ns
ns

d u - O
r o s )
e P ct (
l e t d u
s o r o
O b e P
l et
s o
O b

3/11
 M74HC76

DC SPECIFICATIONS

Test Condition Value

Symbol Parameter TA = 25°C -40 to 85°C -55 to 125°C Unit

VCC
(V)
Min. Typ. Max. Min. Max. Min. Max.
VIH High Level Input 2.0 1.5 1.5 1.5
Voltage 4.5 3.15 3.15 3.15 V
6.0 4.2 4.2 4.2
VIL Low Level Input 2.0 0.5 0.5 0.5
Voltage 4.5 1.35 1.35 1.35 V
6.0 1.8 1.8 1.8
VOH High Level Output 2.0 IO=-20 µA 1.9

( s )
2.0 1.9 1.9
Voltage
4.5 IO=-20 µA
IO=-20 µA
4.4
c t 4.5 4.4 4.4
6.0
4.5 IO=-4.0 mA
d u
5.9
4.18
6.0
4.31
5.9
4.13
5.9
4.10
V

6.0 IO=-5.2 mA
r o 5.68
s )
5.8 5.63 5.60
VOL Low Level Output
Voltage
2.0 IO=20 µA

e P c t ( 0.0 0.1 0.1 0.1

4.5
6.0
l e t
IO=20 µA
IO=20 µA
d u
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1 V
4.5
s oIO=4.0 mA
r o 0.17 0.26 0.33 0.40

II Input Leakage
6.0

O b IO=5.2 mA

e P 0.18 0.26 0.33 0.40

Current
6.0
- t
VI = VCC or GND

l e
± 0.1 ±1 ±1 µA

ICC Quiescent Supply

( s )
6.0
o
VI = VCC or GND 2 20 40 µA
Current

c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b

4/11
 M74HC76

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)

Test Condition Value

Symbol Parameter TA = 25°C -40 to 85°C -55 to 125°C Unit

VCC
(V)
Min. Typ. Max. Min. Max. Min. Max.
tTLH tTHL Output Transition 2.0 30 75 95 110
Time 4.5 8 15 19 22 ns
6.0 7 13 16 19
tPLH tPHL Propagation Delay 2.0 60 125 155 190
Time (CK - Q, Q) 4.5 15 25 31 38 ns
6.0 13 21 26 32
tPLH tPHL Propagation Delay 2.0

( s ) 76 140 175 210

Time (CLR, PR -
Q, Q)
4.5
6.0
c t 18
16
28
24
35
30
42
36
ns

fMAX Maximum Clock 2.0

d u 6.2 21 5.0 4.2
Frequency 4.5
r o s ) 31 63 25 21 MHz

(
6.0 37 67 30 25
tW(H) Minimum Pulse 2.0

e P c t 18 75 95 110
tW(L) Width (CK) 4.5
6.0
l e t d u 6
6
15
13
19
16
22
19
ns

tW(L) Minimum Pulse

s o
2.0
r o 22 75 95 110
Width (CLR, PR)

O b 4.5
6.0
e P 6
6
15
13
19
16
22
19
ns

ts Minimum Set-up
- 2.0

l e t 25 75 95 110
Time

( s ) 4.5
o
7 15 19 22 ns

th
c
Minimum Holdt b s6.0
2.0
6 13
0
16
0
19
0
Time

d u - O 4.5
6.0
0
0
0
0
0
0
ns

tREM
r o
Minimum Removal
s ) 2.0 20 75 95 110

e P
Time (CLR, PR)

c t ( 4.5
6.0
6
5
15
13
19
16
22
19
ns

l e t d u
o o
CAPACITIVE CHARACTERISTICS

s r
O b e P Test Condition Value

Symbol

l e t Parameter VCC
(V)
TA = 25°C -40 to 85°C -55 to 125°C Unit

s o
CIN Input Capacitance 5.0
Min. Typ.
5
Max.
10
Min. Max.
10
Min. Max.
10 pF

O b CPD Power Dissipation

Capacitance (note 5.0 38 pF
1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + I CC/2 (per FLIP/
FLOP)

5/11
 M74HC76

TEST CIRCUIT

( s )
c t
d u
r o
CL = 50pF or equivalent (includes jig and probe capacitance)
s )
RT = ZOUT of pulse generator (typically 50Ω)

e P c t (
l e t
WAVEFORM 1 : MINIMUM REMOVAL TIME (f=1MHz; 50% duty cycle)

d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
WAVEFORM 2 : MINIMUM REMOVAL TIME (f=1MHz; 50% duty cycle)

s o r o
O b e P
l e t
s o
O b

6/11
 M74HC76

WAVEFORM 3 : PROPAGATION DELAY, MINIMUM PULSE WIDTH, SETUP AND HOLD TIME
(f=1MHz; 50% duty cycle)

( s )
c t
d u
r o s )
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s )
WAVEFORM 4 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b

7/11
 M74HC76

Plastic DIP-16 (0.25) MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.77 1.65 0.030 0.065

b 0.5 0.020

b1 0.25 0.010

( s )
D 20
c t 0.787

E 8.5
d u
0.335

e 2.54
r o
0.100
s )
e3 17.78
e P 0.700
c t (
F 7.1
l e t d u 0.280

I 5.1
s o r o 0.201

L 3.3
O b e P 0.130

- l e t
Z

( s ) 1.27

o
0.050

c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b

P001C

8/11
 M74HC76

SO-16 MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018

)
b1 0.19 0.25 0.007 0.010
C 0.5
(
0.019

t s
c1 45° (typ.)

u c
D 9.8 10
d
0.385

o )
0.393
E 5.8 6.2

P r0.228

( s
0.244
e
e3
1.27
8.89
t e c t
0.050
0.350
F 3.8 4.0
l e d
0.149u 0.157
G 4.6 5.3
s o r o
0.181 0.208
L 0.5
b
1.27

O e P 0.019 0.050
M
-
0.62

l e t 0.024
S

( s ) 8° (max.)
o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b

PO13H

9/11
 M74HC76

TSSOP16 MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.004 0.006

A2 0.8 1 1.05 0.031 0.039 0.041

b 0.19 0.30
(
0.007
s ) 0.012

c t
c 0.09 0.20

d u 0.004 0.0089

D 4.9 5 5.1
r o 0.193

s ) 0.197 0.201

E 6.2 6.4 6.6

e P c t (
0.244 0.252 0.260

E1 4.3 4.4
l e t
4.48
d u 0.169 0.173 0.176

e
s o
0.65 BSC
r o 0.0256 BSC

K 0°
O b 8°
e P 0° 8°

- l e t
L 0.45

( s ) 0.60

o
0.75 0.018 0.024 0.030

c t b s
d u - O
r o s )
e PA A2

c t (
l e t d u A1 b e
c
K L
E

s o r o
O b e P
l e t D

s o
O b
E1

PIN 1 IDENTIFICATION
1
0080338D

10/11
 M74HC76

( s )
c t
d u
r o s )
e P c t (
l e t d u
s o r o
O b e P
- l e t
( s ) o
c t b s
d u - O
r o s )
e P c t (
l e t d u
s o r o
O b e P
l e t
s o
O b
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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