Scribd
Upload
118 views

Objective:: To Design A 2X1 MUX Using Logic Gates

The document contains objectives, schematics, and Verilog code for three digital logic designs: 1) a 2x1 multiplexer using logic gates, 2) a 4x1 multiplexer using two 2x1 multiplexers, and 3) a 4-bit ripple carry adder.

Uploaded by

Rishabh Shukla
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
118 views

Objective:: To Design A 2X1 MUX Using Logic Gates

The document contains objectives, schematics, and Verilog code for three digital logic designs: 1) a 2x1 multiplexer using logic gates, 2) a 4x1 multiplexer using two 2x1 multiplexers, and 3) a 4-bit ripple carry adder.

Uploaded by

Rishabh Shukla
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 6

Objective:

To design a 2X1 MUX using logic gates

Schematic:

Verilog Code:
module mux_2(y,a,b,c);

input a,b,c;

output y;

wire w1,w2,w3;

not(w1,c);

and(w2,w1,a);

and(w3,b,c);

or(y,w2,w3);

endmodule
Output File:
Objective:
To design a 4X1 MUX using 2 X1 MUX

Schematic:

Verilog Code:
module mux_4(y,a,b,c,d,e,f);

input a,b,c,d,e,f;

output y;module

wire w1,w2;

mux_2 m1(w1,a,b,e);

mux_2 m2(w2,c,d,e);
mux_2 m3(y,w1,w2,f);

endmodule

Output File:
Objective: To design a ripple carry adder.

Schematic:

Verilog Code:

module ripple_adder(

input [3:0] a,

input [3:0] b,

input cin,

output [3:0] sum,

output carry

);

wire c1,c2,c3;

full_adder fa1(a[0],b[0],cin,sum[0],c1);

full_adder fa2(a[1],b[1],c1,sum[1],c2);
full_adder fa3(a[2],b[2],c2,sum[2],c3);

full_adder fa4(a[3],b[3],c3,sum[3],carry);

endmodule

Output File:

You might also like