State Transition Diagram

Lecture-18
HOLD State THOLD:

The 𝜇𝑝 enter in this state, if some external device wants direct
memory access (DMA) so that a string of data can be transferred to
or from the memory at a fast rate. The device requesting for DMA
makes the HOLD signal input high.
There are two possibilities-(i) the 𝜇𝑝 may be in the HALT state
and then the HOLD signal input becomes HIGH. In this situation, the
𝜇𝑝 first sets the HLDA flip-flop (HOLD acknowledge F/F) & then
enters the HOLD state (ii) the 𝜇𝑝 is executing some machine cycle.
While execution 𝜇𝑝 checks the HOLD signal at unique points during a
machine cycle. HOLD request signal to processor is asynchronous in
nature. The 𝜇𝑝 synchronizes this request and at proper time in a
machine cycle provides the HLDA signal by setting HLDA F/F to the
requesting device. The HOLD state is entered after a machine cycle
is completed.
The HOLD signal is checked during T2 state (after READY input
has been checked) and also during T4 state (provided the concerned
machine cycle requires T5 & T6 states also). If the HOLD signal is
found high, HLDA F/F is set and the processor enters the HOLD state
after the current machine cycle is over.
Upon entering the HOLD state, the HLDA output signal from the
𝜇𝑝 is set HIGH. During this state, the address & the data buses at the
RD, WR & IO/M control lines are floated (tri-stated). By floating its
address, data and control buses, the 𝜇𝑝 effectively disconnects itself
from the system. From this point on, it is up to the requesting device
to provide address, data & control signals to memory & I/O port to
implement the data transfer i.e., the requesting device then enables
its tri-state buffers. When DMA process is over it floats its address
data, and control buses and then bring the HOLD signal input LOW.
HOLD or VALID INT=1
T1 HALT(HLTA F/F=1)
THALT
HALT
(HLTA F/F=0)
HOLD=1 VALID INT=1
T2
SET
READY=1 HLDA F/F
Is Yes SET
HOLD=1 HLDA F/F
No
OFMC CC=6 Is Yes SET

T3 T4 HOLD=1 HLDA F/F
OFMC CC=4
No
T6 T5
HOLD=1
Is
Yes
HLDA F/F THOLD
SET
No
RESET
HLDA F/F
Is Yes
HALT=1
Go To T1 state No
Fig.4.19 Partial State Transition Diagram Indicating HOLD State

The 𝜇𝑝 exits the HOLD state and then continue its previous
operation from the point at which it was suspended by the HOLD
request. If resets, the HLDF F/F first. If the HALT F/F is found to be
set, it enters the HALT state else enters T1 state. The partial state
transition diagram showing HOLD state is shown in fig.4.19.
STATE TRANSITION DIAGRAM

Figure shows the complete state transition diagram of 8085A.
As discussed in previous lecture, the processor will be in one of the
10 different states namely T1, T2, T3, T4, T5, T6, TRESET, THALT, TWAIT
and THOLD. The next state of the state generator from the present
state is decided by many of the control signals input like READY,
HOLD, Interrupt control signals - TRAP, RST7.5, RST6.5, RST5.5
and INTR. State transition diagram is a compact way of showing
when during an instruction cycle the 8085A will enter a HALT state,
insert a WAIT state, respond to HOLD input or respond to an interrupt
input.
If RESET IN is asserted, the 𝜇𝑝 stays in a reset state with the
address bus floating. When RESET IN is not asserted or the previous
machine cycle is finished, the CPU enters T1 of a new machine cycle.
If the previous instruction executed was a HLT instruction state, the
CPU goes directly to a HALT state. The three ways to exit the halt
state are by a RESET, a valid interrupt and a HOLD request. Note
that the exit from HALT state is only temporary. As soon as HOLD is
not asserted, the CPU returns to the halt state.
If a halt state was not entered, then the CPU proceeds to T2 of
the machine cycle. Here it checks the READY input. If the READY
line is not asserted (LOW), the CPU inserts wait states until READY
goes high.
RESET IN=0
TRESET RESET IN=0
HOLD or VALID INT=1

RESET IN=1
T1 HALT(HLTA F/F=1)
THALT
HALT
(HLTA F/F=0)
HOLD=1
READY=0 READY=0 VALID INT=1
T2 TWAIT
SET RESET INTE F/F
READY=1 HLDA F/F
READY=1 SET INTA F/F
Is Yes SET
HOLD=1 HLDA F/F RESET
HLDA F/F
No
OFMC CC=6 Is Yes SET

T3 T4 HOLD=1 HLDA F/F
OFMC CC=4
No
T6 T5
HOLD =1
Is
Yes
HLDA F/F THOLD
SET
No
RESET
HLDA F/F
Is the
No current machine cycle Is
Yes Yes RESET INTE F/F Is
ended the last MC of instrctuion VALID INT=1 Yes
being exececuted SET INTA F/F HALT=1
No
No
Fig. State transaction diagram of 8085 A

The hold input is checked at several points. If a hold request is
present on it, the hold-acknowledge flip-flop is set. However the CPU
will not enter the HOLD state until the end of the current machine
cycle.
Note that the 𝜇𝑝 does not check whether a valid interrupt
request is present until the end of the instruction cycle. This is
necessary so that the address of the next instruction can be pushed
onto the stack. The processor checks valid interrupt after the
completion of instruction cycle because it has to execute the interrupt
service subroutine and for that internal registers, PC, SP are
required. However, it checks the HOLD signal after every machine
cycle and enters into HOLD state at the end of current machine cycle
if the signal is active. In HOLD state processor has nothing to do –
neither memory read/write nor I/O operation. Therefore, if both HOLD
and Interrupt becomes active together, processor first respond to
HOLD signal and after DMA operation only it responds to interrupt.
The complete state transition diagram is shown in fig.4.20.
To summarize, a halt state is entered during the T1, a wait state
is entered after T2, a hold state is entered after a machine cycle is
completed, and an interrupt is responded to after an instruction cycle
is completed.

State Transition Diagram

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Lecture-18

HOLD State THOLD:

OFMC CC=6 Is Yes SET

Fig.4.19 Partial State Transition Diagram Indicating HOLD State

STATE TRANSITION DIAGRAM

TRESET RESET IN=0

HOLD or VALID INT=1

OFMC CC=6 Is Yes SET

Fig. State transaction diagram of 8085 A

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