#STA #Constraint #Set Clock Groups #Static Timing Analysis

venerdì 11 ottobre 2019 16:46
The set_clock_groups command is useful to save us to write many many set_false_path commands.
The following command:

set_clock_groups -asynchronous -group CLKA -group CLKB
is equivalent to both the following commands:
set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB]]
set_false_path -from [get_clocks CLKB] -to [get_clocks CLKA]]
On the opposite side, set_false_path allows to remove specific constraints b/w clocks. For example I can remove setup checks and not the
hold ones, or only rise or fall edges.
There are 3 possible options to be specified and they are mutually exclusive, e.g. only one can be specified:
- asynchronous
- logically_exclusive
- phisically_exclusive
Asynchronous
When you say two(or more) clocks are asynchronous, that means there is no phase relationship between them at all.
Let's consider the following statements:

create_clock -period 10 -name ClkA [get_ports CLKA]
create_clock -period 1 -name ClkB [get_ports CLKB]
They are defined on primary ports and asynchronous to each other clock.
We should specify:
set_false_path -from [get_clocks ClkA] -to [get_clocks ClkB]]
set_false_path -from [get_clocks ClkB] -to [get_clocks ClkA]]
This is equivalent to
set_clock_groups -asynchronous -group {ClkA} -group {ClkB}
We can have the following constraint:

set_clock_groups -asynchronous -group {ClkA ClkC} -group {ClkB ClkD}
This means:
- ClkA and ClkC are synchronous to each other, and the same for ClkB and ClkD.
- ClkA and CLKC are asynchronous to ClkB and ClkD and viceversa.
We can conclude that the members of a group are synchronous to each other but they are asynchronous to the elements of the other
group.
set_clock_groups Page 1
ClkB and divClkB are synchronous to each other and they are asynchronous to ClkA.
set_clock_group on a master clock are NOT applied to generated clocks by default.
You need to explicitly include it as in the command below:
set_clock_groups -asynchronous -group [get_clocks ClkA] -group [get_clocks {ClkB divClkB}]
With the asynchronous switch U can also specify allow_paths switch to enable timing paths b/w specified async clocks.
Logically_exclusive
Two clocks are said to be logically exclusive when they are both active in the design but doesn’t have any paths between them.
An example would be a MUX selecting two or more of the clocks for a portion of the design using its select lines. Such clocks will not have
any timing path between them.
The clkOut clock is selected by the Sel of the Mux MX1. So, Clk1 and Clk2 cannot exist together logically in the downstream path of the
MX1. They are not interacting outside the MUX path:
set_clock_groups -logically_exclusive -group [get_clocks Clk1] -group [get_clocks Clk2]
Let's consider the following example:
There is a FF clocked by Clk2 outside the MUX which is interacting with flops clocked by ClkOut. So we cannot specify a logical exclusion
between Clk1 and Clk2. What we can do here is create generated clock statements for the output of the MX1 and put them as logically
exclusive:
create_generated_clock -name clkout1 -source [get_pins MX1/A] -master [get_clocks Clk1] [get_pins MX1/Z] -add
create_generated_clock -name clkout2 -source [get_pins MX1/B] -master [get_clocks Clk2] [get_pins MX1/Z] -add
set_clock_groups -logically_exclusive -group [get_clocks clkout1] -group [get_clocks clkout2]
Also when there is a clock divider U cannot put Clk1 and Clk2 as to be logically exclusive but instead U have to define generated clocks and
put the constraint:
create_generated_clock -name divClkOut1 -divide_by 1 -source [get_pins ClkDiv/A] -master [get_clocks Clk1] [get_pins ClkDiv/Z] -add
create_generated_clock -name divClkOut2 -divide_by 1 -source [get_pins ClkDiv/A] -master [get_clocks Clk2] [get_pins ClkDiv/Z] -add
set_clock_groups -logically_exclusive -group [get_clocks {Clk1 divClkOut1}] -group [get_clocks {Clk2 divClkOut2}]
Phisically_exclusive
These clocks do not exist in the design at the same time. e.g. clocks defined on the same primary port but working in two different modes
like the TestClk and Functional Clock (or RMII ang RGMII Ethernet clocks defined on the same primary port).
There will be no SI interaction between these clocks.
set_clock_groups -physically_exclusive -group [get_clocks SysClk] -group [get_clocks TestClk]
From a xtalk point of view, if there are more than 1 relationship between 2 clocks the precedence will be:
phisically_exclusive (highest)
asynchronous
logically_exclusive (lowest)

#STA #Constraint #Set Clock Groups #Static Timing Analysis

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venerdì 11 ottobre 2019 16:46

The following command:

Let's consider the following statements:

We can have the following constraint:

Let's consider the following example:

set_clock_groups -physically_exclusive -group [get_clocks SysClk] -group [get_clocks TestClk]

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