Effects of Control-FET Gate Resistance on False

Turn-on in GaN Based Point of Load Converter

Naga Babu Koganti, Shankar Dhakal, Roshan L. Kini, Michael R. Hontz, and Raghav Khanna
Electrical Engineering and Computer Science Department
University of Toledo
Toledo, OH, USA
nagababu.koganti@rockets.utoledo.edu

Abstract—This paper investigates the impact of an external levels by optimizing both power and gate loop parasitic
control-FET gate resistance on the spuriously induced inductance and adding external gate resistance.
synchronous-FET gate voltage in a 1 MHz point-of-load buck
converter. An analytical circuit model with intrinsic device Two other adverse anomalies that can appear in half bridge
components and external parasitic parameters has been converters are self-sustained oscillations and spurious turn-on
considered to resemble test bench conditions. A relationship (or false turn-on). In general, self-sustained oscillations are
between control-FET gate resistance and synchronous-FET different from underdamped natural ringing; the latter is a
false turn-on induced voltage is presented in agreement with consequence of the device’s transient response whereas the
modeled and experimental results. former is a parasitic induced forced oscillation that does not
extinguish itself unlike natural ringing. Spurious turn-on in
Keywords—control-FET, synchronous-FET, point-of-load half-bridge converters occurs when the rapid turn-on of the
buck converter control FET injects a high dv/dt current into the Miller
capacitance of the synchronous FET which is in its off-state.
I. INTRODUCTION This unintentional displacement current can induce a gate-
voltage on the device, thus unintentionally turning the device
Point-of-load (POL) converters are highly applicable in
on. Both self-sustained oscillations and spurious turn-on can
DC based distributed bus power topologies. With low output
be mitigated with proper design of parasitic gate and power
voltage and large current at the load-end, POL converters offer
inductance as well as additional externally applied gate
higher efficiencies and quick transient responses. Adding to
resistance [4], [5]. The use of two transistors in the half-bridge
that, considerably low weight ratio with tiny footprint makes
topology allows efficient power transfer by eliminating diode
them a preferred in miniature DC power system design such
conduction losses. Power losses in a converter are a
as voltage regulator module (VRM) in microprocessors,
combination of conduction and switching losses along with
mobile phones, and other portable electronics [1]. They are
residual leakage losses. In a POL half-bridge converter,
usually driven at higher frequencies for the reason to reduce
switching losses constitute a major proportion of total losses.
the size further and increase the converter’s power density.
In a half-bridge converter, the synchronous (low-side) FET
In general POL converters belong to the family of half can suffer from false turn-on due to the large voltage and
bridge converters. Traditionally, silicon (Si) power devices current swings on the control-FET which can lead to
have been the principle switching devices and contributed to additional transient power loss [6], [7]. To mitigate this false
major growth in switch mode power supplies. However, the triggering, the turn-on speed of the control FET can be
new generation of power switching devices such as gallium reduced by externally added gate resistance. This comes at the
nitride (GaN) exhibit several advantages over Si devices in expense of added switching loss.
terms of low conduction and switching loss, high power
This paper presents a detailed gate resistance-based
density, thermal conductivity and extremely low ON-
optimization scheme to control false turn-on of enhancement-
resistance [2]. In addition, GaN devices improve the
mode GaN HEMTs in a half-bridge converter that minimizes
performance of half-bridge converters through their high slew
switching loss. As a part of the proposed control scheme, an
rate, low internal capacitances and gate charge, and support
optimal gate resistance RG1 is calculated for the control-FET.
high-frequency operations on the order of MHz. This
This minimizes the risk of false turn-on of the synchronous-
significantly reduces the converter filter size which translates
FET while also enabling the fastest possible switching of the
into effective space saving. However, GaN devices are more
control-FET.
sensitive to undesirable transient effects. Among the transient
response generated anomalies, gate-to-source voltage The paper is organized as follows: Section II provides brief
overshoot poses as a significant challenge which can increase insights on false turn-on behavior and some of the mitigation
the risk of device breakdown, particularly in commercially methodologies available in literature. Then, an analytical
available lateral GaN HEMTs due to the narrow margin framework is developed with an objective to find a
between recommended and max gate bias rating. As reported relationship between control-FET gate resistance and false
in [3] it is possible to minimize voltage overshoot below safe turn-on magnitude in Section III. Section IV describes the

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experiment conducted to assess false turn-on and a device level parameters (both intrinsic and parasitic). Fig. 3 is
comparison study is drawn between the analytical model and derived with the intent of extracting information of all the
experimental analyses. Concluding remarks are presented in influential parameters related to false turn-on [13]. The
Section V. complete rise in voltage at switch node VSW takes place when
Q1 proceeds to the linear region of operation. At the same time
II. LITERATURE BACKGROUND the switch Q2 is in OFF state with input capacitance CISS (i.e.
CGD & CGS) completely discharged.
The false turn-on behavior in POL has been extensively
discussed in the literature along with some mitigation
methodologies. In [8] and [9], it was demonstrated that a
reduction in common source inductance can lead to negative
excursions in the spurious gate voltage, thereby potentially
suppressing the false turn-on. In [10], the potential benefits
of common source inductance for false turn-on were
discussed. A detailed analytical model is developed in [11] to
evaluate false switching behavior by considering the non-
linearities of intrinsic capacitances of GaN devices. Although
negative gate bias voltage clamping at synchronous-FET can
Fig. 1. Half bridge buck converter.
limit false triggering voltage below threshold, high reverse
conduction losses are observed if proper care is not taken.
Also, there is no standard metric available in the literature to
determine the limit of negative voltage clamping necessary to
avoid false turn-on. In [12] the effect of synchronous-FET
gate resistance on false triggering is analyzed with control-
FET gate resistance held at constant.
This paper adopts a similar approach to [12], however the
control-FET gate resistance is varied instead. As such, a
relationship between the control FET gate resistance and the
magnitude of spuriously induced voltage on the synchronous
FET is extracted. Here, the synchronous-FET gate resistance Fig. 2. Synchronous-FET spurious charging.
is kept at minimal value to enable high sinking capability and
quick turn-off. The control-FET gate resistance is varied, and
the corresponding false turn-on voltage magnitude is
recorded for both the analytical model and experimental test-
bed.

III. ANALYTICAL LINEAR CIRCUIT MODEL

False turn-on occurs due to a negative feedback charging
current that flows into gate resistance through reverse
transfer capacitance . To demonstrate the mechanism by
which false turn-on occurs, consider the synchronous buck
converter shown in Fig. 1, consisting of the control-FET, Q1,
and synchronous- FET, Q2. Fig. 2 shows the off-state
Fig. 3. POL analytical circuit model during false turn-on event.
equivalent circuit for Q2 during the instant in time when Q1
turns on. Due to the rapid switching of Q1, the change in drain
to source voltage of Q2, VDS2, can cause current to be injected
through the gate-drain capacitance of Q2, CGD2. This current
will then lead to a voltage drop, VGS2, across RG2. If VGS2
exceeds the threshold voltage of the device, Q2 can turn-on
during a time when it is nominally off, resulting in a large
current to flow through the device. This large current from the
input bus to ground will cause a short circuit condition, which
will lead to a large energy loss and can potentially cause Q2
to fail catastrophically. The fast switching capability of GaN
devices can make them more susceptible to false turn-on
events if proper care is not taken. To analyze the false turn-on
behavior in greater detail it is imperative to develop an Fig. 4. Simplified circuit model on high-side.
analytical model that takes into account all the circuit and

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 The investigation of effect of external gate resistance RG1 IV. COMPARISON OF MODEL AND EXPERIMENTAL
over false turn-on induced voltage is divided into parts. In the RESULTS
first half, the influence of external gate resistance RG1 over
A 40 V, 20 W synchronous buck converter was designed
switch node voltage is analyzed using the analytical circuit
to validate the results of modeling false turn-on and its
model shown in Fig. 4. The analytical model shown in Fig. 4
dependence on RG1. The converter, shown in Fig.6, was
is analyzed with a set of KCL based equations at each node
operated at a switching frequency of 1 MHz. The PCB layout
to derive a mathematical relationship between RG1 and switch
of synchronous converter was designed in a single layer
node VSW. These relations are shown in (1) – (4).
format to enable quick cooling and utmost care was taken to
Similarly, in the second part of investigation, the effect of minimize gate-loop parasitic inductance by positioning
change in voltage at VSW over false turn-on induced gate circuit components close to each other. Input capacitor filter
voltage VGS2 is analyzed using the analytical circuit model was designed and calibrated to reject any common mode
shown in Fig. 5. A mathematical relationship between switch noise emanated at the switching frequency. This helps to
node voltage and false turn-on induced voltage VGS2 is reduce the possibility of self-sustained oscillations and EMI
developed using nodal equations (5) – (8). In this way, it is issues, both of which are detrimental to device performance
possible to develop a final mathematical relationship between and carry the risk of catastrophic failure. The gate driver
external gate resistance RG1 and false turn-on induced voltage selected for both devices was the LM5113, which is
VGS2. With help of the nodal equations developed from the optimized specifically for commercially available GaN FETs.
analytical circuit model, a time-domain step response of false Both the FETs used in the experiment were 100-V, 2.7-A
turn-on induced voltage VGS2 is extracted by varying the devices with a typical threshold voltage of 1.47 V. The low
external gate resistance RG1. threshold voltage significantly increases the chance for false
triggering relative to Si FETs.
(1)
Figs. 7 and 8 illustrate the false turn-on response of VGS2
from both analytical model and experimental test bed driven
(2) at RG1 = 7 Ω. The experimental waveform exhibits higher
false turn-on magnitude compared to analytical model for the
reason of unaccounted parasitic gate loop inductance in PCB
(3) trace. However the magnitude of the induced voltage as well
as the general shape of the waveform is accurately captured.
(4) Shown in Fig. 9 is a comparison of the measured
maximum gate voltage and predicted maximum gate voltage
during false turn-on as a function of RG1. As can be seen in
(5) Fig. 9, the analytical model predicts the general trend seen in
the measured results with good accuracy. Furthermore, as the
value of RG1 is increased, the accuracy of the model improves.
(6) This can likely be attributed to the fact that the parasitics
(excluding RG1) of the testing/measurement system have less
(7) impact on the induced voltage when high values of RG1 are
employed. Conversely, at lower values of RG1, the parasitics
of the system have greater influence, and are not adequately
(8) accounted for in the analytical model. With further
refinement, the discrepancy at low values of RG1 can be
rectified to make the model more accurate across the entire
spectrum of gate resistances. However, it is clear from Fig. 9,
the analytical linear circuit model predicts false turn-on
induced voltage very close to experimental data, and thereby
the potential of using Q1’s gate resistance in mitigating false
turn-on is demonstrated. Furthermore, the trend in Fig. 9 can
be used to determine the optimal value of RG1, which keeps
switching losses in Q1 as low as possible, without forcing Q2
into spurious conduction.

Fig. 5. Simplified circuit model at low side.

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Fig. 6. Experimental response of VGS2 at RG1 = 9 Ω.

Fig. 9. False turn-on magnitude from the model and

experiment.

V. CONCLUSION
It is evident that an increase in resistance at the gate
terminal of control FET in a half bridge converter leads to
increase in switching loss. Conversely, it also reduces the risk
of false turn-on of the synchronous switch. Here, the selection
of appropriate equivalent sub-stages for both the FETs in the
analytical circuit model plays an important role in extracting
the relationship between gate resistance and false turn-
on induced voltage . Furthermore, the tuning of the
control FET’s gate resistance provides a mechanism to
control false turn-on in the synchronous FET. Also, the
analytical methodology does not involve any external non-
linear components (Zener diode, Snubber circuit etc.) to
Fig. 7. Modeled response of VGS2 at RG1 = 9 Ω. control spurious turn-on and thereby keeps the design simple
and comprehensive. This work presented an analytical model
capable of predicting false turn-on for any value of RG1. In
this way, users can select an RG1 that will lead to an induced
false turn-on voltage below the threshold voltage of Q2
thereby preventing shoot-through and keeping switching
losses minimal. In this way, the GaN device is employed in a
manner that allows its best possible performance with limited
risk of failure due to false turn-on.

ACKNOWLEDGMENT
This work was supported in part by a grant from the U.S.
Office of Naval Research under Grant N00014-16-1-3104.
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