SET A

BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE-PILANI, HYDERABAD CAMPUS

I SEM. 2013 – 2014 Comprehensive Examination Part- A (Solutions)
CS /EEE /ECE C391 CS /EEE /ECE /INSTR F215 December 6, 2013 (Friday) 2:00 to 5:00 PM
Max. Marks: 40 Digital Design/Digital Electronics and Computer Organization (Closed Book)
Note: (i) Q1 to Q20 are multiple choice questions, Mark your choice to the question in the space provided at
the back page with PEN and in Capital letters only.
(ii) Each correct answer carries 2 Marks,
(iii) Wrong Answer/Unattempted carries 0 Marks
(iv) Overwritten/ Striked off and rewritten answers/ Answers written with pencil carry -2 Marks.

Name: ID No.:

1. You have to design a display system for a 6. A network router connects multiple computers
thermometer .The minimum temperature that your together and allows them to send messages to each
display will have to output is 0 degrees and the other. If two or more computers send messages
maximum is 99 degrees. The minimum number of
simultaneously, they collide and the messages must
bits required to represent the temperature in
binary? be resent. Create a collision detection circuit for a
A) 10 B) 8 C) 12 D) 7 router that connects 3 computers .The circuit has 3
2. The gate required to produce a low output when a inputs labeled M0, M1 and M2 that are 1 when the
MOD-64 counter is at the count of 27 is (A is corresponding computer is sending a message and 0
MSB) otherwise. The circuit has one output labeled C that
A) 6 input NAND with inputs (A′,B′,C,D′,E′,F) is 1 when a collision is detected and 0 otherwise.
B) 6 input NAND with inputs (A,B′,C′,D,E′,F′) The expression for C is
C) 6 input NAND with inputs (A,B′,C′,D,E′,F′) A) M2M1M0′+ M2M1′ M0+ M2′ M1M0+ M2M1M0
D) 6 input NAND with inputs (A′,B′,C,D′,E′,F) B) M2′M1M0′+ M2M1′ M0+ M2′ M1M0+ M2M1′ M0
3. A 10 KHz clock signal having a duty cycle of C) M2M1M0′ + M2M1′ M0+ M2′ M1M0+ M2′ M1′ M0′
25% is used to clock a 3–bit binary ripple counter D) M2′ M1M0′+ M2M1′ M0′ + M2′ M1M0+ M2M1M0
which uses positive edge triggered D flip-flops.
The frequency and duty cycle of the output of the 7. The sequential circuit below yields an output
MSB flip-flop will be ---- and ------ respectively? sequence of Z = 11011111 when the input sequence
A) 1.25 KHz , 25% B) 1.25 KHz , 50% X = 01101010.What is the starting state of A?
C) 3.33 KHz , 25% D) 3.33 KHz, 50% X Z
4. The simplified Boolean expression for
F= (b c) + (a b)′ (a′+c′)′ is A Q
A) b c J

B) b c (a+b) Clk
K
C) b c (ab)′
D) b + c A) 0 B) 1 C) A′ D) J
5. The solutions to quadratic equation
are and , what is 8. The correct representation of 8 is
the base of the numbers? A) 001000 B) 101000
A) 5 B) 6 C) 110000 D) 1000000
C) 7 D) 8

Page (1/4)
 A) 100000111 B) 00000111
C) 11111001 D) 111111001
9. The simplified expression for the network shown
in fig. below is 14. Refer to the NAND and NOR latches shown in
D the figure. The inputs (P1, P2) for both the latches
A F
are first made (0,1) and then after a few seconds
B made (1,1). The corresponding stable outputs
(Q1, Q2) are
C
P1 Q1 P1 Q1
A) B+C
B) ( (D+(A′ B) ′ ) ( B+C′))′
C) ( (D+(A′ B) ′ ) ( B+C′ )) Q2 Q2
D) (D+(A′ B) ′ ) ′ + ( B+C))
P2 P2
10. Figure below shows a register made up of three D
flip-flops. If the value of B = `0` and P =`1` .The A) NAND:first (0,1) then (0,1) NOR: first (1,0) then (0,0)
value of Z is B) NAND:first (1,0) then (1,0) NOR: first (1,0) then (1,0)
C) NAND:first (1,0) then (1,0) NOR: first (1,0) then (0,0)
A B P D) NAND:first (1,0) then (1,1) NOR: first (0,1) then (0,1)
Z
15. Without any additional circuitry, an 8:1 MUX can
be used to obtain
A) Some but not all Boolean functions of 3 variables
A) B) 1 A C) A D) A′ B) All function of 3 variables but none of 4 variables
)0 C) All function of 3 variables and some but not all
11. The output Y in the circuit below is always logic functions of 4 variables
1 when D) All functions of 4 variables
P
16. When Mealy type outputs are logic 1, they are
Q Y represented in ASM chart by writing the
corresponding variable inside
R A) State box
B) Conditional output box
A) Two or more of the inputs are logic 0
B) Two or more of the inputs are logic 1 C) Decision box
C) Odd number of inputs are logic 0 D) Unconditional output box
D) Odd number of inputs are logic 1 17. For the 4:1 MUX based circuit shown in the
following figure, The output Z can be represented
12. What are the minimum number of 2:1 multiplexers as
required to generate a 2-input AND gate and a 2- P
input XOR gate respectively? (Only 2:1 Q 0
multiplexers should be used) P 1 Z
A) B) 1 and
A 3 C) 2 and 2 D) 2 and 2 P
Q 2
) 1 and 2
13. The two signed numbers (represented in 2’s P 3 S1 S0
complement format) are given as P = 11101101 and
R S
Q = 11100110. If Q is subtracted from P, the
resulting signed number (represented in 2’s A) P Q + P Q′ S + Q′ R′ S′
complement format) is B) P Q′ + P Q R′ + P ′ Q′ S′

Page (2/4)
 C) P Q′ R′ + P′ Q R + P Q R S + Q′ R′ S′
D) P Q R′ + P Q R S′ + P Q′ R′ S + Q′ R′ S′

Name:
18. The noise margin for a logic gate, with VOH =
2.5V, VIH = 2V, VOL = 0.3V, VIL = 0.7V, is equal ID No:
to
A) B) 0.4AV C) 1.7 V D) None
) 0.5 V
19. If the state QAQB of the circuit shown below is 10 Answer Sheet:
initially, then the state QAQB after 6 clock cycles Q No. Answer
(6 positive edges) will be
1. D
QA QB
J Q T Q 2.
Clock
Q’ Q’ 3. B
K
4. A
A) B) 01A C) 10 D) 11
) 00 5. C
20. T
6. A
he number of directed arcs terminating on any state of
a state diagram is 7. B
A) 2n where n is number of inputs
B) 2n where n is number of outputs 8. B
C) Independent of the number of inputs
D) Dependent on the number of outputs 9. A

10. C

11. B

12. A
Note:
1. Answer sheets without Name and ID No. 13. B
will not be evaluated
14. C

15. C

16. B

17. A

18. B

19. C

20. C

Page (3/4)
Evaluation: (For instructor use only)

Correct Answers

Wrong Answer

Total Marks

Page (4/4)