ISA Models

Assignment#1
Shakeel Abbas 2019F-mulmpl-cs-062@mul.edu.pk

Subject : Advance Computer Architecture
Submitted to: Sir Shahan Siddiqui
Instruction Set Architecture

1. RISC Architecture
RISC (Reduced Instruction Set Computer) is used in portable devices due to its power
efficiency. For Example, Apple iPod and Nintendo DS. RISC is a type of microprocessor
architecture that uses highly-optimized set of instructions. RISC does the opposite,
reducing the cycles per instruction at the cost of the number of instructions per program
Pipelining is one of the unique feature of RISC. It is performed by overlapping the
execution of several instructions in a pipeline fashion. It has a high performance
advantage over CISC. RISC processors take simple instructions and are executed within
a clock cycle.
2. CISC Architecture
The CISC approach attempts to minimize the number of instructions per program,
sacrificing the number of cycles per instruction. Computers based on the CISC
architecture are designed to decrease the memory cost. Because, the large programs
need more storage, thus increasing the memory cost and large memory becomes more
expensive. To solve these problems, the number of instructions per program can be
reduced by embedding the number of operations in a single instruction, thereby making
the instructions more complex.
Difference between CISC Vs RISC

3. MISC
Minimal instruction set computer (MISC) is a processor architecture with a very small number
of basic operations and corresponding opcodes. Such instruction sets are commonly stack-
based rather than register-based to reduce the size of operand specifiers.
Such a stack machine architecture is inherently simpler since all instructions operate on the top-
most stack entries.
As a result of the stack architecture is an overall smaller instruction set, a smaller and faster
instruction decode unit with overall faster operation of individual instructions.
Key points of MISC are:
• a minimal instruction set computer is viewed as having 32 or fewer instructions where NOP, RESET
and CPUID type instructions
• A MISC CPU cannot have zero instructions as that is a zero instruction set computer
• A MISC CPU cannot have one instruction as that is a one instruction set computer
• The only addressing mode considered acceptable for a MISC CPU to have is load/store, the same as for
RISC CPUs
• MISC CPUs can typically have between 64 KB to 4 GB of accessible addressable memory
• Features like Instruction pipelines, branch prediction, out-of-order execution, register renaming and
speculative execution do not form a part of MISC CPU
4. ZISC
ZISC is a general purpose computer architecture unique for its lack of a CPU or instruction set.
Computation is distributed to address mapped functional units which pair off and share data
under the direction of a simple sequencer. Customary traits of other general purpose
architectures; branching, interrupt handling (and multitasking), are present. In addition, ZISC
features on the fly configurability to the task at hand.
OISCs are a common choice for interpreter golf competitions, because only needing to
implement one instruction keeps the size of the interpreter low. However, they suffer somewhat
from needing to handle the code and data separately (even if they are in the same physical
memory array, you nonetheless tend to need separate registers for handling the instruction
pointer and for handling any data being manipulated). A ZISC arrangement simplifies the
problem still further, because there is no longer any need to keep track of command arguments.
(However, it can make programming more complex, as the data itself has to encode rules for
operating on that data.)
5. OISC
One instruction set computer (OISC) (also known as ultimate reduced instruction set
computer (URISC)) is a computer architecture based on two fundamental ideas:
• One instruction in instruction set
• memory-mapping registers
• self-modifying code
6. VLISW
Very long instruction word (VLIW) describes a computer processing architecture in which a
language compiler or pre-processor breaks program instruction down into basic operations
that can be performed by the processor in parallel (that is, at the same time). These
operations are put into a very long instruction word which the processor can then take apart
without further analysis, handing each operation to an appropriate functional unit.
VLIW is sometimes viewed as the next step beyond the reduced instruction set computing (
RISC ) architecture, which also works with a limited set of relatively basic instructions and
can usually execute more than one instruction at a time (a characteristic referred to as
superscalar ). The main advantage of VLIW processors is that complexity is moved from the
hardware to the software, which means that the hardware can be smaller, cheaper, and
require less power to operate. The challenge is to design a compiler or pre-processor that is
intelligent enough to decide how to build the very long instruction words. If dynamic pre-
processing is done as the program is run, performance may be a concern.
7. EPIC
Explicitly Parallel Instruction Computing (EPIC) refers to architectures in which features are
provided to facilitate compiler enhancements of instruction-level parallelism (ILP) in all
programs, while keeping hardware complexity relatively low. Using ILP-enhancement
techniques such as speculation and predication, the compiler identifies the operations that
can execute in parallel in each cycle and communicates a plan of execution to the hardware.
8. MIPS
MIPS is a simple, streamlined, highly scalable RISC architecture that is available for
licensing. Over time, the architecture has evolved, acquired new technologies and developed
a robust ecosystem and comprehensive industry support. Its fundamental characteristics –
such as the large number of registers, the number and the character of the instructions, and
the visible pipeline delay slots – enable the MIPS architecture to deliver the highest
performance per square millimeter for licensable IP cores, as well as high levels of power
efficiency for today’s SoC designs.
The MIPS architecture is one of the most widely supported of all processor architectures,
with a broad infrastructure of standard tools, software and services to help ensure rapid,
reliable, cost effective development. Microprocessor developers who want maximum
flexibility from processor IP have a solution in the MIPS architecture.
9. The x86 Instruction Set

The x86 instruction set refers to the set of instructions that x86-
compatible microprocessors support. The instructions are usually part of
an executable program, often stored as a computer file and executed on the processor.
The x86 instruction set has been extended several times, introducing wider registers and
datatypes as well as new functionality
10. SPARC
SPARC (Scalable Processor Architecture) is a 32- and 64-bit microprocessor architecture from
Sun Microsystems that is based on reduced instruction set computing (RISC). SPARC has become
a widely-used architecture for hardware used with UNIX-based operating systems, including
Sun's own Solaris systems. Sun has made SPARC an open architecture that is available for
licensing to microprocessor manufacturers. In its most recent brand name, UltraSPARC,
microprocessors can be built for PC boards (using either Peripheral Component
Interconnect or ATX) as well as for SPARC's original workstation market. As evidence of
SPARC's scalability, Sun says that its UltraSPARC III will be designed to allow up to 1,000
processors to work together.
11. ARM
The Arm architecture provides the foundations for the design of a processor or core, things we refer
to as a Processing Element (PE).
The Arm architecture is used in a range of technologies, integrated into System-on-Chip (SoC)
devices such as smartphones, microcomputers, embedded devices, and even servers.
The architecture exposes a common instruction set and workflow for software developers, also
referred to as the Programmer's model. This helps to ensure interoperability across different
implementations of the architecture, so that software can run on different Arm devices.
12. IBM
The IBM POWER ISA is a reduced instruction set computer (RISC) instruction set architecture (ISA)
developed by IBM. The ISA is used as base for high end microprocessors from IBM during the 1990s
and were used in many of IBM's servers, minicomputers, workstations, and supercomputers. These
processors are called POWER1 (RIOS-1, RIOS.9, RSC, RAD6000) and POWER2 (POWER2, POWER2+
and P2SC).

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Assignment#1

Shakeel Abbas 2019F-mulmpl-cs-062@mul.edu.pk

Instruction Set Architecture

Difference between CISC Vs RISC

• MISC CPUs can typically have between 64 KB to 4 GB of accessible addressable memory

9. The x86 Instruction Set

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