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    Neelima Pachori Design Engineer

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    Neelima Pachori
    This document summarizes the experience and skills of Neelima Pachori. She has over 5 years of experience as a design engineer working with 28nm and 14nm technologies. Her skills include physical design, placement and routing, timing analysis, and resolving issues like congestion and IR drops. She has a Master's degree in Electronics and Communications and has worked on projects involving wireless networks and antenna design.

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    Neelima Pachori Design Engineer

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    Neelima Pachori
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    This document summarizes the experience and skills of Neelima Pachori. She has over 5 years of experience as a design engineer working with 28nm and 14nm technologies. Her skills include physical design, placement and routing, timing analysis, and resolving issues like congestion and IR drops. She has a Master's degree in Electronics and Communications and has worked on projects involving wireless networks and antenna design.

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    This document summarizes the experience and skills of Neelima Pachori. She has over 5 years of experience as a design engineer working with 28nm and 14nm technologies. Her skills include physical design, placement and routing, timing analysis, and resolving issues like congestion and IR drops. She has a Master's degree in Electronics and Communications and has worked on projects involving wireless networks and antenna design.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    52 views3 pages

    Neelima Pachori Design Engineer

    Uploaded by

    Neelima Pachori
    This document summarizes the experience and skills of Neelima Pachori. She has over 5 years of experience as a design engineer working with 28nm and 14nm technologies. Her skills include physical design, placement and routing, timing analysis, and resolving issues like congestion and IR drops. She has a Master's degree in Electronics and Communications and has worked on projects involving wireless networks and antenna design.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 3

    Neelima Pachori

    ms.neelimapachori@gmail.com
    Professional Summary +91-9179500884

    I am an enthusiast design engineer experienced in latest technologies 14nm and 28nm.


    I have good knowledge of PnR flow and STA and have resolved various issues like congestion, routing, timing,
    Cross talk, IR drop and EM using tools like ICC and Innovus.I have good experience in APR flow (Floor
    Planning, Placement, CTS, Routing), STA, Physical Verification.

    I am cohesive team worker having strong analytical, problem solving and interpersonal skills.

    My colleagues describe me Approachable and Easy-going. I carry positive and proactive attitude towards
    learning new technologies.

    I am a friendly person and I love drawing, dancing and travelling in my free time.

    Education

    2013 2015 Master of Technology Electronics & Communications Eng., Nirma University (India)
    2009 2013 Bachelor of Engineering Electrical, Electronics & Communications Eng Bhopal (India)

    Technical skills

    PnR Flow RTL(Verilog,VHDL)


    Synthesis TCL
    STA
    Physical Verification
    IR/EM/Cross Talk issues
    MMMC/PVT
    Agile/Scrum

    Languages

    English Fluent in written and spoken


    Hindi Native speaker

    Tools Used

    ICC Aprisa
    Prime Time Innovus
    Work experience

    Design Engineer
    HCL Technology

    Assignment-1
    3/10/2017 to 30/05/2018

    Technology 28nm / 9 metal layers


    Gate count 731376
    Macros 20
    STD cell 200076
    No of clocks 3
    Frequency 172.4 MHz
    Tool used IC Compiler, IC Validator, Star RC, Prim Time

    Roles & Responsibility

    To perform Sanity Checks, Floorplan, Powerplan, Placement, CTS, Routing, Timing Analysis & Closure, LVS &
    DRC,
    Design Closure.

    Physical design knowledge, from netlist to GDS including physical verification.

    Assignment 2

    01/06/2018 to
    30/01/2019

    Technology 28nm / 9 metal layers


    Gate count 50K
    Macros 16
    STD cell 10K
    No of clocks 3
    Frequency 420 MHz
    Tool used IC Compiler, IC Validator, Star RC, Prim Time

    Roles & Responsibility

    To perform synthesis,Sanity Checks, Floorplan, Powerplan, Placement, CTS, Routing, Timing Analysis & Closure,
    LVS & DRC,Design Closure.

    Working knowledge of congestion and IR drop issues, Timing Closure and final sign off.

    Assignment 3 15/02/2019 to Till now


    Technology 28nm / 9 metal layers
    Gate count 200K
    Macros 24
    STD cell 38415
    No of clocks 5
    Frequency 350 MHz
    Tool used IC Compiler, IC Validator, Star RC, Prim Time

    Roles & Responsibility

    To perform Sanity Checks, Floorplan, Powerplan, Placement, CTS, Routing, Timing Analysis & Closure, LVS &
    DRC, Design Closure.
    I was responsible for all aspects of Physical Design for full chip covering Floor-planning, Budgeting, Clock tree,
    placement, Scan chain reordering, Optimization, Timing and SI analysis, ECO tasks, EM/IR, DRC, LVS, ERC
    analysis & fixes, Low power solution development & implementation
    Academic projects

    Improving energy efficiency & quality of services in an integrated green wireless optical
    broadband network using 4G technology. (16/08/2016 to 30/06/2017)

    Simulation & designing of micro strip patch antenna operating at 1.7GHz.(01/02/2015 to


    15/06/2015)

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