This document contains 30 multiple choice questions about electronics topics such as logic gates, time bases, and sampling circuits. The questions cover topics like the types of waveforms produced by sweep circuits, components of sampling gates, logic families with certain characteristics like low power dissipation, factors that affect phase delay, and definitions of terms like threshold voltage and fan out.
This document contains 30 multiple choice questions about electronics topics such as logic gates, time bases, and sampling circuits. The questions cover topics like the types of waveforms produced by sweep circuits, components of sampling gates, logic families with certain characteristics like low power dissipation, factors that affect phase delay, and definitions of terms like threshold voltage and fan out.
This document contains 30 multiple choice questions about electronics topics such as logic gates, time bases, and sampling circuits. The questions cover topics like the types of waveforms produced by sweep circuits, components of sampling gates, logic families with certain characteristics like low power dissipation, factors that affect phase delay, and definitions of terms like threshold voltage and fan out.
This document contains 30 multiple choice questions about electronics topics such as logic gates, time bases, and sampling circuits. The questions cover topics like the types of waveforms produced by sweep circuits, components of sampling gates, logic families with certain characteristics like low power dissipation, factors that affect phase delay, and definitions of terms like threshold voltage and fan out.
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PDC
SECTION-I: Multiple choice questions
1. Bootstrap’s sweep circuit produces _____ type of waveform. [ a] (a) positive going Ramp (b) negative going Ramp (c) either a or b (d) Both a and b 2. The gate signal is also called as ___________. [c ] (a) enabling pulse (b) control pulse (c) both a and b (d) either a or b 3. Sampling gates are used in _______. [d] (a)Multiplexers (b) D to A converters (c) Sample and Hold circuits (d) All the above 4. The variations in phase delay occur due to ____. [c ] (a) variations in loop gain (b) variations in supply voltage (c) both a and b (d) None 5. Among the logic families, low power dissipation is in _____. [ b] (a)DTL (b) CMOS (c) TTL (d) ECL 6. Synchronization is said to be with frequency division, if the generators operate at___ [b ] (a) same frequency (b) different frequency (c) both a and b (d) None 7. Synchronization with symmetrical signals is possible if_______. [c ] (a) Tp <= T0 (b) Tp >= T0 (c) both a and b (d) either a or b 8. Which of the following logic family has highest fan-out. [ d] (a) ECL (b) TTL (c) DTL (d) CMOS 9. Among the logic families, Slowest logic family is_____. [c ] (a)TTL (b)DTL (c)CMOS (d)ECL 10. In Miller circuit, the gain A of the inverting amplifier should be ____. [c ] (a) unity (b) zero (c) infinite (d) None of the above 11. The time during which the waveform returns to the initial value is called: [b ] (a) fall time (b) flyback time (c) rise time (d) delay time 12. The circuit which require an amplifier whose gain is nearly infinity [b] a) Boot strap ckt b) Miller ckt c) Phantastron ckt d) Inductor ckt 13. When generators with equal frequencies run in synchronism, the synchronization is said to be on a [ a] a) one-to-one basis b) one-to-two basis c) two-to-one basis d) one-to-four basis 14. A Transmission circuit which allows an input Signal to pass through it during a selected interval and blocks it passage outside this time interval is called: [ a] a) sampling gates b) conventional gates c) non-conventional gates d) logic gates 15. In unidirectional sampling gate the combination of RC forms a [ b] a)Differentiator b) Integrator c) Coupling elements d) Multivibrator 16. The ratio of maximum deviation to the sweep amplitude is called [ b] a) Slope error (b) displacement error (c) Transmission error (d) Linear error 17. A capacitor is charged linearly from a constant current source is used to generate [c ] a)sine wave form (b) pulse wave form (c) time base waveform (d) trapezoidal wave form 18. The several factors which affect phase delay given rise to [ a] a) Phase jitter b)amplitude jitter c)both amplitude and phase jitter d)frequency jitter 19. The interval of time is selected by means of an externally applied signal termed as: [b ] a) Transient signal b) gating signal c) output signal d)exponential signal 20. Logic gates are the basic elements that make a [ d] a) analog system b) gating system c) basic system d)digital system 21.The relation between the slope error, displacement error and transmission error is 22. To get a saw-tooth out put waveform, the restoration time is [ a] ( a ) zero ( b ) rise time ( c ) storage time ( d ) infinity 23. In Miller time base generator, which of the following is used [b ] (a) an inverting amplifier with a gain of unity (b) an inverting amplifier with a gain of infinity (c) non- inverting amplifier with a gain of unity (d) non-inverting amplifier with a gain of infinity 24. Synchronization with symmetrical signals is possible for [ d] ( a ) Tp = To only ( b ) Tp<To only ( c ) Tp >To only ( d ) both Tp<To and Tp> To 25. The time during which the output increases linearly is called [ a] ( a ) sweep time ( b ) flyback time ( c ) return time ( d ) restoration time 26. The interval of time of transmission of a signal in a sampling gate is selected by means of [ c] ( a ) time delay ( b ) off time of gate ( c ) gating signal ( d ) source signal 27. The following all are disadvantages of unidirectional gate, except [d ] ( a ) interaction between the signal source and control voltage source ( b ) limited used of gate ( c ) slow rise of the control voltage ( d ) little time delay though the gate 28. Which of the following logic gives the complementary outputs? [ d] ( a ) DTL ( b ) RTL ( c ) TTL ( d ) ECL 29. The voltage at the input of a gate which causes a change in the state of the ouput from one logic level to the other is [c ] ( a ) cut-in voltage ( b ) cut-off voltage ( c ) threshold voltage ( d ) peak voltage 30. The high state fan out of a gate is defined at when the [ c] ( a ) input is at logic ‘0’ ( b ) input is at logic ‘1’ ( c ) output is at logic ‘1’ ( d ) output is at logic ‘0’
