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VLSI Adders CLA

The document discusses different types of adders used in digital circuits. It explains that half adders and full adders can be used to add single bits, while ripple carry adders can add n-bit numbers by using a chain of full adders. Carry lookahead adders improve speed by calculating carry bits in parallel rather than serially. Other high-speed adder designs mentioned include carry-skip adders, carry-select adders, and carry-save adders which add numbers with minimal carry propagation.

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Neel Patel
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81 views38 pages

VLSI Adders CLA

The document discusses different types of adders used in digital circuits. It explains that half adders and full adders can be used to add single bits, while ripple carry adders can add n-bit numbers by using a chain of full adders. Carry lookahead adders improve speed by calculating carry bits in parallel rather than serially. Other high-speed adder designs mentioned include carry-skip adders, carry-select adders, and carry-save adders which add numbers with minimal carry propagation.

Uploaded by

Neel Patel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Darshana Sankhe, DJSCOE

 Half adder and Full adder can be used for


adding single bits.

 Ripple Carry Adder can be used to add n-bit


number.

 Generally, adding two n-bit words yields a


n-bit sum and a carry out bit.

Darshana Sankhe, DJSCOE


 A 4 bit Ripple Carry Adder is designed using
4 full adder.
B3 A3 B2 A2 B1 A1 B0 A0

Full C3 Full C2 Full C1 Full C0


Adder Adder Adder Adder

C4 S3 S2 S1 S0

Darshana Sankhe, DJSCOE


 A n-bit Ripple Carry adder can be designed using n full
adders.

 The output of any full adder is not valid until the


incoming carry bit is valid.

 Therefore, the left most circuit is the last to react.

 The word result is not valid until the left most circuit
reacts.

 The overall delay would depend on the characteristics


of full adder circuits.

Darshana Sankhe, DJSCOE


Equation for Carry Out:
Ci+1 = AiBi + Ci (Ai  Bi)

The I term of the equation:


If AiBi = 1, then Ci+1 =1,
Gi = AiBi Generate Term

The II term of the equation:


Ci = 1, may be propagated, if Ai  Bi = 1
 Pi = Ai  Bi Propagate Term

If Pi =1, Gi=0, since XOR produces 1, if inputs are not equal.

Darshana Sankhe, DJSCOE


 Lets analyze the 4-bit CLA equations:
 Ci+1 = A iBi+ Ci (Ai  Bi)

◦ C1 = G0 + P0.C0

◦ C2 = G1 + P1.C1 = G1 + P1.(G0 + P0.C0)


= G1 + P1.G0 + P1.P0.C0

◦ C3 = G2 + P2.C2 = G2 + P2.(G1 + P1.(G0 + P0.C0) )


= G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.C0

◦ C4 = G3 + P3.C3
= G3 + P3.(G2 + P2.(G1 + P1.(G0 + P0.C0) ))
= G3 + P3.G2 + P3.P2.G1 + P3.P2.P1.G0 + P3.P2.P1.P0.C0

Darshana Sankhe, DJSCOE


Darshana Sankhe, DJSCOE
Darshana Sankhe, DJSCOE
 Once carry is calculate using generate and propagate
term, the sum would be given by:
Si = Pi  Ci

 The main idea is to first calculate value of Pi and Gi for


every bit using partial full adder, then use them to find
Ci+1.

 Then using Pi and Ci, Si could be calculated for every bits.

 Thus, we use n Partial Full Adder to implement a n- Bit


Carry Look-Ahead Adder

 This avoids the need to ripple the carry bits serially down
the chain.

Darshana Sankhe, DJSCOE


C1 = g0 + p0.c0
 pFET pull-up not shown here

Darshana Sankhe, DJSCOE


C2 = g1 + p1.c1 = g1 + p1.(g0 + p0.c0)
g1 + p1.g0 + p1.p0.c0

Darshana Sankhe, DJSCOE


C3= g2 + p2.c2 = g2 + p2.(g1 + p1.(g0 + p0.c0) )
= g2 + p2.g1 + p2.p1.g0 + p2.p1.p0.c0

Darshana Sankhe, DJSCOE


C4 = g3 + p3.c3 = g3 + p3.(g2 + p2.(g1 + p1.(g0 + p0.c0) ) )
= g3 + p3.g2 + p3.p2.g1 + p3.p2.p1.g0 + p3.p2.p1.p0.c0

Darshana Sankhe, DJSCOE


 Static CMOS Logic
 Pseudo NMOS Logic
 Dynamic CMOS Logic
 MODL ( Multiple o/p Domino Logic )
 Manchester Carry adder

Darshana Sankhe, DJSCOE


Darshana Sankhe, DJSCOE
Darshana Sankhe, DJSCOE
Darshana Sankhe, DJSCOE
 Significantly fewer transistors
 Less chip area
 Output only valid during evaluate period
 Clocking is mandatory
 o/p has problem of charge leakage & sharing
 Series connected nFET chain gives long discharge time

Darshana Sankhe, DJSCOE


ai bi ci ci+1 gi Pi Ki
0 0 0 0 0 0 1
0 0 1 0 0 0 1
0 1 0 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 0 1 0
1 0 1 1 0 1 0
1 1 0 1 1 0 0
1 1 1 1 1 0 0

Darshana Sankhe, DJSCOE


ai bi ci ci+1 gi Pi Ki
0 0 0 0 0 0 1
0 0 1 0 0 0 1
0 1 0 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 0 1 0
1 0 1 1 0 1 0
1 1 0 1 1 0 0
1 1 1 1 1 0 0

Darshana Sankhe, DJSCOE


ai bi ci ci+1 gi Pi Ki
0 0 0 0 0 0 1
0 0 1 0 0 0 1
0 1 0 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 0 1 0
1 0 1 1 0 1 0
1 1 0 1 1 0 0
1 1 1 1 1 0 0

Darshana Sankhe, DJSCOE


Darshana Sankhe, DJSCOE
 Number of terms in the carry equation increases
with the width of the binary word to be added

 Gets overwhelming (and slow) with large binary


words•

 One method is to break wide adders into smaller


blocks

 e.g., use 4b blocks (4b is common, but could be


any number)

Darshana Sankhe, DJSCOE


 Alternative implementations for high-speed
adders

 Carry-Skip Adder

 Carry-Select Adder

 Carry-Save Adder

Darshana Sankhe, DJSCOE


 Carry Skip Adders is designed to speed up a
wide adder by aiding the propagation of carry
bit around a portion of the entire array.

 Depending on the position at which a carry


signal has been generated, the propagation
time can be variable.

 In the best case, when there is no carry


generation, the addition time will only take into
account the time to propagate the carry signal.

Darshana Sankhe, DJSCOE


 The AND gate accepts
the carry-in bit and
compares it to the group
propagation signal.

Group Propagation Signal:


P[i,i+3] = Pi+3 +Pi+2 +Pi+1 +Pi
Carry = Ci+4 + P[i,i+3] .Ci

 If P[i,i+3] is 1 and Ci is 1,
then the group carry is
automatically sent to the
next group of adders.

Darshana Sankhe, DJSCOE


 Carry Skip Adders take
advantage both of the
generation or the
propagation of the carry
signal.

 They are divided into


blocks, where a special
circuit detects quickly if
all the bits to be added
are different (Pi = 1 in all
the block).

 The signal produced by


this circuit will be called
block propagation signal.

Darshana Sankhe, DJSCOE


 Here, the size of carry-skip group is 4.

Darshana Sankhe, DJSCOE


Darshana Sankhe, DJSCOE
 The Carry Select principle requires two identical
parallel adders that are partitioned into four-bit
groups.

 The group generates a group carry.


 In the carry select adder, two sums are generated
simultaneously.

 One sum assumes that the carry in is equal to one


as the other assumes that the carry in is equal to
zero.

 The predicted group carry is used to select one of


the two sums.

Darshana Sankhe, DJSCOE


Darshana Sankhe, DJSCOE
Darshana Sankhe, DJSCOE
Darshana Sankhe, DJSCOE
 One of the major speed
enhancement techniques
used in modern digital
circuits is the ability to add
numbers with minimal carry
propagation.

 The basic idea is that three


numbers can be reduced to
2, in a 3:2 compressor, by
doing the addition while
keeping the carries and the
sum separate.

Darshana Sankhe, DJSCOE


 This means that all of the columns can be
added in parallel without relying on the
result of the previous column, creating a
two output "adder" with a time delay that is
independent of the size of its inputs.

 The sum and carry can then be recombined


in a normal addition to form the correct
result.

 This process may seem more complicated


and pointless in the above trivial example,
but the power of this technique is that any
amount of numbers can be added together
in this manner.

 It is only the final recombination of the


final carry and sum that requires a carry
propagating addition.

Darshana Sankhe, DJSCOE


Darshana Sankhe, DJSCOE
Thank You !

Darshana Sankhe, DJSCOE

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