LMS7002M Quick Starter Manual EVB7 2 2r0 PDF

LMS7002M Quick Starter Manual for EVB7 kit
Lime Microsystems
Surrey Tech Centre
Occam Road
The Surrey Research Park
Guildford
Surrey GU2 7YG
United Kingdom
Tel: +44 (0) 1483 685 063

Fax: +44 (0) 1428 656 662
e-mail: enquiries@limemicro.com
LMS7002M Quick Start Manual
The information contained in this document is subject to change without prior

notice. Lime Microsystems assumes no responsibility for its use, nor for
infringement of patents or other rights of third parties. Lime Microsystems' standard
terms and conditions apply at all times.
Version: 2.2 Last modified: 29/09/2014

REVISION HISTORY
The following table shows the revision history of this document:
Date Version Description of Revisions

05/06/2014 2.0 Initial version
2/07/2014 2.1 Updated GUI pictures and new control descriptions
8/08/2014 2.2 Updated GUI pictures and new control descriptions and 7.23 section added
25/08/2014 2.2 Released for distribution
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Contents
1. Introduction ............................................................................................................................... 7
2. Development System Content .................................................................................................. 8
3. Overview of the Development Board ...................................................................................... 9
4. Installing the LMS7002M Control Software ........................................................................ 11
4.1 Introduction to installing the software................................................................................ 11
4.2 Downloading the Software ................................................................................................... 12
4.3 Windows USB Setup ............................................................................................................. 12
4.4 Determining Serial Port ....................................................................................................... 15
4.5 Linux Setup............................................................................................................................ 16
4.6 Starting Control LMS7002M Software .............................................................................. 16
4.7 Connecting ............................................................................................................................. 16
5. Getting started with the EVB................................................................................................. 18
5.1 Introduction to using the EVB7 ........................................................................................... 18
5.2 Transmitter Setup and Basic Testing.................................................................................. 19
5.2.1. SXT/SXR tab setup ............................................................................................... 19
5.2.2. TRF tab setup ........................................................................................................ 20
5.2.3. TBB tab setup ....................................................................................................... 20
5.3 Testing the TX Output ......................................................................................................... 21
5.3.1. TX Basic Operation Checks.................................................................................. 22
5.4 Receiver Setup and Basic Testing........................................................................................ 23
5.4.1. SXT/SXR tab setup ............................................................................................... 23
5.4.2. RFE tab setup ........................................................................................................ 24
5.4.3. RBB tab setup ....................................................................................................... 25
5.5 Testing the RX Output ......................................................................................................... 27
5.5.1. RX Basic Operation Checks ................................................................................. 27
5.6 Testing With Minimal Equipment ...................................................................................... 28
6. EVB7 Connectors and Options .............................................................................................. 29
6.1 Introduction to the EVB7 Connectors and Options .......................................................... 29
6.2 Board Connections ................................................................................................................ 29
6.2.1. FMC connector pin description ............................................................................ 32
6.2.2. Digital I/O connector pin description ................................................................... 33
6.3 Hardware options.................................................................................................................. 34
6.3.1. TCXO’s Configuration ......................................................................................... 35
6.3.2. EVB7 synchronization .......................................................................................... 35
6.3.3. SPI Control Configuration .................................................................................... 36
6.3.4. Baseband Digital Interface Voltage ...................................................................... 36
6.3.5. EVB7 Matching networks..................................................................................... 37
7. Detailed Guide to LMS7002M Control Software ................................................................ 38
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7.1 Control LMS7002M – Software Description ...................................................................... 38

7.2 Control LMS7002M – Window Panels. .............................................................................. 38
7.2.1. GUI Control panel................................................................................................. 38
7.2.2. Configuration panel .............................................................................................. 38
7.2.3. Log panel .............................................................................................................. 40
7.3 The Menu Bar ....................................................................................................................... 40
7.3.1. The File Menu ....................................................................................................... 40
7.3.2. The Option Menu .................................................................................................. 41
7.3.3. The Tool Menu ..................................................................................................... 41
7.3.4. The Help Menu ..................................................................................................... 41
7.3.5. The Button Menu .................................................................................................. 41
7.3.6. The Configuring Channel Controls ....................................................................... 42
7.4 Board Setup (Si5351C and ADF4002)................................................................................. 43
7.5 RFE......................................................................................................................................... 44
7.6 RBB ........................................................................................................................................ 46
7.7 TRF......................................................................................................................................... 47
7.8 TBB......................................................................................................................................... 50
7.9 AFE......................................................................................................................................... 52
7.10 BIAS ..................................................................................................................................... 53
7.11 LDO ...................................................................................................................................... 54
7.12 XBUF.................................................................................................................................... 55
7.13 CLKGEN ............................................................................................................................. 56
7.14 SXT/SXR.............................................................................................................................. 59
7.15 Application Note on Tuning PLLs on LMS7002M .......................................................... 61
7.16 LimeLight & PAD ............................................................................................................... 62
7.17 TxTSP................................................................................................................................... 66
7.18 RxTSP .................................................................................................................................. 68
7.19 CDS....................................................................................................................................... 70
7.20 BIST ..................................................................................................................................... 71
7.21 SPI ........................................................................................................................................ 72
7.22 Buffers EVB7v2................................................................................................................... 74
8. Appendix A: Test Equipment Setup ..................................................................................... 75
8.1 Introduction ........................................................................................................................... 75
8.2 Recommended Test Equipment ........................................................................................... 75
8.3 Agilent MXG Setup............................................................................................................... 76
8.3.1. Setting Common Mode Voltage ........................................................................... 76
8.3.2. Enabling the Arbitrary Waveform Generator ....................................................... 77
8.3.3. Downloading *.wfm Files to the Signal Generator .............................................. 78
Table of Figures
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Figure 1 Development System Content ........................................................................................... 8

Figure 2 Board block diagram ....................................................................................................... 9
Figure 3 Device Manager content ................................................................................................ 12
Figure 4 Device properties ........................................................................................................... 13
Figure 5 Update Driver Wizard. ................................................................................................... 13
Figure 6 Hardware wizard. Install driver manually .................................................................... 14
Figure 7 Check for new communication port ............................................................................... 15
Figure 8 GUI communication settings.......................................................................................... 16
Figure 9 GUI detected device and firmware version.................................................................... 17
Figure 10 Tx Test Setup ................................................................................................................ 19
Figure 11 SXT register setup procedure ...................................................................................... 20
Figure 12 TBB register setup procedure ..................................................................................... 21
Figure 13 Basic TX testing using DC offset resulting in LO leakage .......................................... 21
Figure 14 Basic TX testing using WCDMA modulation .............................................................. 22
Figure 15 Rx Test Setup ............................................................................................................... 23
Figure 16 SXR register setup procedure ..................................................................................... 24
Figure 19 RX analog output on Spectrum Analyser. ................................................................... 27
Figure 20 Design kit connection descriptions, Top view. ............................................................ 29
Figure 21 Design connection descriptions, Bottom view. ............................................................ 30
Figure 22 GUI window diagram.................................................................................................. 39
Figure 23 GUI Control Panel window ........................................................................................ 39
Figure 24 GUI Configuration Board Setup window.................................................................... 39
Figure 25 GUI Log panel ............................................................................................................. 40
Figure 26 GUI Message Log tab .................................................................................................. 40
Figure 27 GUI Register Map window ......................................................................................... 41
Figure 28 GUI Board Setup tab.................................................................................................... 43
Figure 29 GUI RFE tab ................................................................................................................ 44
Figure 30 GUI RXBB tab ............................................................................................................. 46
Figure 31 GUI TRF page .............................................................................................................. 48
Figure 32 GUI TBB page .............................................................................................................. 50
Figure 33 GUI AFE tab ................................................................................................................ 52
Figure 34 GUI BIAS tab ............................................................................................................... 53
Figure 35 GUI LDO Power downs & Bias & Noise filter tab ..................................................... 54
Figure 36 GUI LDO Voltages tab ................................................................................................ 55
Figure 37 GUI XBUF tab ............................................................................................................ 55
Figure 38 GUI CLKGEN tab ........................................................................................................ 56
Figure 39 GUI SXT/SXR tab ........................................................................................................ 59
Figure 40 GUI Limelight&PAD Modes tab................................................................................. 62
Figure 41 GUI Limelight&PAD Sample position tab................................................................... 64
Figure 42 GUI TxTSP tab ............................................................................................................. 66
Figure 43 GUI RxTSP tab............................................................................................................. 68
Figure 44 GUI CDS tab ............................................................................................................... 70
Figure 46 GUI BIST tab ............................................................................................................... 71
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Figure 47 GUI SPI tab .................................................................................................................. 72

Figure 48 GUI Buffers EVBv2 tab ................................................................................................ 74
Figure 49 Agilent N5181A/82A MXG Front Panel ..................................................................... 76
Figure 50 CMD window showing successful ping........................................................................ 79
Figure 51 CMD window with ftp connection................................................................................ 79
Figure 52 CMD window ftp file transfer ...................................................................................... 80
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1
Introduction
The Lime Development System is a comprehensive hardware and software combination that
allows users to evolve and refine a wireless sub-system. It can be combined with a baseband
processor such as an FPGA or DSP processor to develop a comprehensive wireless solution.
The EVB7 module is a high-speed wireless communication module, based on the LMS7002M
fully programmable RF transceiver. It is designed to support 2G, 3G, 4G/LTE radio systems
with both time-division duplex (TDD) and frequency-division duplex (FDD) applications, M2M
and software defined radios. The wireless communication module covers the frequency range of
100 kHz to 3.8 GHz, including licensed and unlicensed bands. The channel bandwidth is
programmable from less than 100 kHz to 108 MHz through a combination of analog and digital
filtering via the easy-to-use GUI software.
The EVB7 provides system designers with the ability to connect the board to any type of
baseband, FPGA or CPU and allow them to implement their ideas for various wireless
communication applications.
This document describes how to make a quick start with the LMS7002M using the EVB7
module. Section 2 begins by listing the contents of the Quick Start kit. Section 3 gives a general
description of the evaluation board features. Section 4 describes the procedure for obtaining and
installing the LMS7002M control software “Control LMS7002M” for both Windows and Linux
platforms. Section 5 describes how to connect and use the EVB and LMS7002M control
software “Control LMS7002M” for the Quick Start example configurations. Section 6 describes
in detail the EVB connectors and hardware options. Section 7 describes in detail how to use the
LMS7002M control software “Control LMS7002M”. Section Error! Reference source not
ound. describes the calibration procedure. Appendix 1 details the recommended test and
measurement equipment, and how to set up the test equipment to work with EVB7 and the
LMS7002M.
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2
Development System Content
Figure 1 Development System Content
Complete development kit content consists of:

 Hardware
o 1 - EVB7 board
o 1 - Power supply cable that connects the EVB7 board to any lab power supply
unit
o 1 - USB-A to Micro-USB-B cable
 Software:
o LMS7002M GUI “Control_LMS7002M”
o Windows drivers
 Documentation:
o Quick Starter Manual
o LMS7002M datasheet
o Complete PCB database
o Generator waveforms
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3
Overview of the Development Board
Figure 2 Board block diagram
A photograph of the development board is shown in Figure 1. A block diagram of the board is
shown in Figure 2. The connections are shown in blue, the LMS7002M chip is shown in green,
and the other parts are shown in orange. The core of the board is the LMS7002M transceiver
chip, which has multiple RF, analogue and digital interfaces.
The evaluation board includes RF matching networks for the LMS7002M. These matching
networks include wideband transformers to allow operation over the entire frequency range.
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However, the matching networks have been optimized for operation over selected frequency
bands and offer the best performance in these bands. Connectors are provided for 4 RF
transmitter outputs and 6 RF receiver inputs. Further details of the matching networks are
provided in Section 6.3.5.
The evaluation board includes connectors for the baseband analogue differential receiver outputs
and differential transmitter inputs. Additionally, on board high speed differential to single ended
converters allow the EVB7 receivers to indirectly drive 50R test equipment such as spectrum
analysers for baseband testing.
The evaluation board includes a clock generation block, which by default, is a standalone
30.72 MHz low phase noise TXCO. TXCOs at other frequencies can also be fitted and three
different footprints are supported. The EVB7 can be easily modified to operate with external
clock sources. It can also be synchronized to the standard 10 MHz reference of measurement
equipment via an on board PLL. Details of the required changes on EVB7 are given in section
6.3.1 and 6.3.2.
EVB7 includes two kinds of digital I/O, one for control only, and two for data and control.
The USB interface is used to control the LMS7002M SPI via the LMS7002M control software.
The USB port is converted to SPI by an on board microcontroller.
The HSMC connector or the 44 pin header can be used for the buffered digital interface and can
be connected to compatible platforms such as the Lime “Stream” board. The Lime “Stream”
board also provides connections to general purpose lab equipment such as pattern generators and
logic analysers. A pin list for the digital interface can be found in Section 6.2. The logic level
for the digital interface can be set by modifying EVB7 and is described in section 6.3.4.
Additionally these connectors can be used to control the SPI but require the board modifications
described in 6.3.3.
A 7th order LC filter can be selected between the analogue output of the LMS7002M and its
digital inputs by using the LMS7002M control software. This allows additional filtering at
100 kHz (IF BW) for 2G applications.
The board includes memory to work with the LMS7002M internal microcontroller. This is
intended to provide calibration support for the LMS7002M and is currently under development.
The memory is programmed via the LMS7002M control software and the USB/SPI interface.
Test points are provided for various test signals including the LMS7002M internal peak and
RSSI detectors as well as various PLL test signals.
More detailed information on the connectors for the evaluation board can be found in Section
6.1. Information about PCB options supported is in Section 6.3.
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4
Installing the LMS7002M Control Software
4.1 Introduction to installing the software

To operate the EVB7 board, the LMS7002M Control Software, “LMS7002M Control” has to be
downloaded from http://www.limemicro.com and installed. The software consists of three parts.
 The main LMS7002M control Software, which provides a GUI to control the chip.
 The USB driver “USB to LMS7002M”, which provides an interface between the PC and
the EVB7 SPI microcontroller.
 The EVB7 microcontroller firmware, which is preinstalled on the board prior to shipping.
Section 4.1 describes the how to download the software from the Lime Microsystems web page.
Sections 4.2, 4.3 and 4.4 describe the set up for the Windows Operating System. Section 4.2
describes the installing of the “USB to LMS7002M” driver. Section 4.3 describes the Windows
OS set up. Section 4.4 describes how to identify which USB port is being used.
Section 4.5 describes installing the USB driver in a typical Linux distribution. Section 4.6
describes how to start the “LMS7002M Control Software”.
Section 4.7 describes how to connect the EVB7 with the “LMS7002M Control Software” via the
USB interface.
A simple demonstration of the “LMS7002M Control Software” is given in Section 5. A detailed

description of the “LMS7002M Control Software” is given in Section 7.
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4.2 Downloading the Software

To get started with the EVB7 board control software, download the latest version from
www.limemicro.com.
4.3 Windows USB Setup

The steps to setup “Control LMS7002M” software are as follows (please note that these steps
may vary based on the specific version of Windows software being used and you may need to be
logged in as Administrator to accomplish them):
1. Connect EVB7 board to your PC via the USB cable.
2. Go to Control Panel > System > Device Manager
3. Locate USB to LMS7002M under Other devices and press right click to select Properties
(Figure 3)
Figure 3 Device Manager content
4. When a new window pops-up press Update driver (Figure 4)
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Figure 4 Device properties
5. Select Browse my computer for driver software, locate the driver provided with EVB7
board and press Next (Figure 5)
Figure 5 Update Driver Wizard.
6. If the Windows Security window appears, select Install this driver software anyway
(Figure 6)
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Figure 6 Hardware wizard. Install driver manually
Windows should proceed to install drivers at this stage. Generally, once the above steps have
been taken for the EVB7, these steps do not need to be repeated.
IMPORTANT:
Before running the control software, unplug then plug your device back into your computer.
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4.4 Determining Serial Port

After driver installation, Windows will assign to your EVB7 board a serial port. To check your
board serial port number, please follow these steps:
1. Go to Control Panel > System > Device Manager
2. Locate USB Virtual Serial Port under Ports (COM & LPT)
Note that in this system example it has enumerated as COM2 (Figure 7).
Figure 7 Check for new communication port
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4.5 Linux Setup

For Linux users, there is no need to install USB drivers as the system will assign drivers
automatically once the EVB7 board is connected to PC.
To determine port number the easiest is via the command line and type command:
$ setserial -g /dev/ttyS[0123]
4.6 Starting Control LMS7002M Software

Apply +5V to the board and start “Control LMS7002M” software. The application must be run
under administrator privileges. To do that, right click on the “Control LMS7002M” icon and
select Run as an Administrator. This will provide administrator privileges, which are required
for EVB7 board communication via USB.
4.7 Connecting
Once the Windows driver is installed and the control software has been lunched, click on
Options>Connection Settings. The Connection Setting windows will pop-up (Figure 8).
Figure 8 GUI communication settings.
Select the dedicated USB port number of the EVB board. In this case, it is COM2, but the port
may be different, and press OK.
The GUI the device name and firmware version will appear in the bottom (Figure 9), once
connection with the board is established.
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Figure 9 GUI detected device and firmware version
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5
Getting started with the EVB
5.1 Introduction to using the EVB7

The EVB7 allows powerful demonstrations of the LMS7002M transceiver. In this quick start
guide, we demonstrate the board operating with analogue inputs and outputs. A future version is
planned to demonstrate the board operating with digital inputs and outputs and the Lime “Speed”
board.
Section 5.2 describes the set up of the transmitter, with Section 5.2.1 describing how to set up the
SXT (TX PLL) and Section 5.2.2 describing how to set up the TX analogue baseband and RF
tabs of the LMS7002M Control software. Section 5.4 describes the set up of the transceiver for
basic tests, with section 5.4.1 describing how to set up the SXR (RX PLL) and Section 5.4.2 and
5.4.3 describing how to set up the RX analogue baseband and RF tabs of the LMS7002M
Control software.
The analogue quick start demonstration assumes the user has all the equipment listed in
Appendix 8.2. Users with less equipment can use the set up of Section 5.6.
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5.2 Transmitter Setup and Basic Testing

To test the Tx path, the Agilent generator is used as an external baseband source. This is
connected to the Tx path via the analog inputs and generates a WCDMA modulation signal at
socket X1 (TX1_A) as shown in Figure 10. To generator settings are described in Section 8.3
(Appendix A).
Figure 10 Tx Test Setup
5.2.1. SXT/SXR tab setup
After power up, connect the GUI to the board and select the SXT/SXR tab. To configure the Tx
LO to 2140 MHz, do the following:
1. Select the B/SXT in the configuration channels window to control TxPLL

2. Enable Tx PLL VCO (Deselect).
3. Set Scales VCO bias current to 255.
4. Type the wanted frequency in Frequency, GHz box. In this case, 2140 MHz.
5. Press Calculate followed by Tune.
See Figure 11 below to check selections.
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Step 1
Step 2
Step 3 Step 4
Step 5
Figure 11 SXT register setup procedure
5.2.2. TRF tab setup
The TRF tab controls the TX RF gain and output path. By default the Tx RF gain is set to
maximum and TX1 is selected as the output path. For this test, we are not going to change these
settings.
5.2.3. TBB tab setup
In the TBB tab the baseband gain and filter bandwidth are controlled. Follow the instructions
below set up TBB:
1. Select the A/SXR to control channel A.

2. Set Frontend gain and reference bias current of IAMP.
3. Configure the base band filter settings.
4. Select the analog input path to current amplifier.
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Step 1
Step 2
Step 4
Step 3
Figure 12 TBB register setup procedure
5.3 Testing the TX Output

When the transmitter is configured as shown in section 5.2, the TX1_A output (socket X1) can
be connected to a spectrum analyzer (SA). The SA you can now observe the results of this basic
operational test (Figure 13). The test is looking at the DC offset from the un-programmed data
DAC as LO leakage and the example shown below is measuring a value of -26.8dBm.
Figure 13 Basic TX testing using DC offset resulting in LO leakage
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When the baseband is enabled, the WCDMA modulation can be tested and the results of Figure
14 can be obtained with the MXG Spectrum Analyser.
Figure 14 Basic TX testing using WCDMA modulation
5.3.1. TX Basic Operation Checks
To check the basic TX frequency and gain control, conduct some tests changing frequencies and
gain settings. The following four tests are recommended:
TRF – TXPAD gain change setting from 0 to 31 and observe results. LO should vary by approx.
1 dB steps, 31dB range.
Change frequency from 2.14 GHz to 2.11 GHz and press ‘Calculate’/’Tune’ (CAP value should
change), check the Spectrum Analyzer.
Change frequency from 2.11 GHz to 2.17 GHz and press ‘Calculate’/’Tune’ (CAP value should
change), check the Spectrum Analyzer.
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5.4 Receiver Setup and Basic Testing

The test bench for the receiver is shown in Figure 15. Basic functionality checks on the receiver
side are achieved by using the Analog output from connector X40.
Figure 15 Rx Test Setup
5.4.1. SXT/SXR tab setup
Select the SXT/SXR tab. To configure the Rx LO to 1950 MHz, do the following:
6. Select the A/SXR in the configuration channels window to control RxPLL

7. Enable Rx PLL VCO (Deselect).
9. Type the wanted frequency in Frequency, GHz box. In this case, 1950 MHz.
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Step 1
Step 2
Step 3 Step 4
Step 5
Figure 16 SXR register setup procedure
5.4.2. RFE tab setup
Select the RFE tab to configure the receiver RF front–end. Follow the configuration steps below:
1. Enable LNARFE, RXFE TIA and RFFE Quadrature LO generator.

2. Select active LNA. Select LNAW for this test.
3. Configure TIA reference current settings.
4. Configure LNA core current settings.
5. Configure Input switches. Deselect input of LNAW and select LNAL.
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Step 2
Step 1
Step 5
Step 3
Step 4
5.4.3. RBB tab setup
Select the TBB tab to configure the PGA gain and baseband filter bandwidths. Follow the
configuration steps below:
1. Set PGA gain to 19 dB.

2. Configure filter bandwidth.
3. Select PGA output to output pads. This selection enables receiver analog outputs.
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Step 2
Step 1
Step 3
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5.5 Testing the RX Output

Set the signal generator to 1955 MHz (i.e. 1 MHz offset from PLL frequency selected) and input
a sine wave at -60 dBm into the evaluation board antenna connector (LNAW_A, connector X5).
Configure the receiver as showed in Section 5.3. Connect an Analyser to X40 or X39. If
everything is correctly setup, you should see the 1 MHz peak. See Figure 19 below.
Figure 19 RX analog output on Spectrum Analyser.
5.5.1. RX Basic Operation Checks
To check the basic Rx frequency and gain control, conduct some tests changing frequencies and
gain settings. The following six tests are recommended:
a. RBB – change PGA gain setting from 19 to -12, observe results, gain should decrease.
b. RFE – change TIA gain settings from Gmax to Gmin, observe results, gain should
decrease.
c. RFE – LNA gain change from Gmax to Gmax -30, observe results, gain should decrease.
d. Change frequency from 1.95 GHz to 1.92 GHz and press ‘Calculate’/’Tune’. Change
Signal Generator to 1.925 GHz (1MHz offset from PLL). Observe results.
e. Change frequency from 1.92 GHz to 1.98 GHz and press ‘Calculate’/’Tune’. Change
Signal Generator to 1.985 GHz (1MHz offset from PLL). Observe results.
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5.6 Testing With Minimal Equipment

For users without all the equipment specified in Section 8.2 (Appendix A) it is possible to link
the TX1_A output (X1) to the receiver input LNAW_A input (X5) and rely on the LO leakage to
provide an input signal to the RX.
Using the methods of Section 5.2 and Section 5.4 set the SXT to 2140 MHz and SXR to
2145 MHz and measure a 5 MHz signal with an oscilloscope to observe the RXI output at X19.
The magnitude of the output signal can be controlled with the various gain controls in the RFE
and TRF.
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6
EVB7 Connectors and Options
6.1 Introduction to the EVB7 Connectors and Options

Section 6.2 describes the various connectors available on the EVB7. Section 6.3 describes the
hardware options available on the EVB7, including reference clocks and the SPI control. The
top and bottom of the board are shown in Figure 20 and Figure 21 respectively.
6.2 Board Connections
Figure 20 Design kit connection descriptions, Top view.
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Figure 21 Design connection descriptions, Bottom view.
Table 1 describes the high level pin assignment for each connector on the design kit.
Table 1 Design kit connectors and switches
Connector Schematic name Description
+3.3V Voltage This jumper is used to supply +3.3 V from the EVB to
J1
Supply Jumper the HSMC connector connected boards
This jumper enables the supply to the EVB7 board from
JP2 BB supply an FPGA development kit. U16 is a voltage regulator
that converts +12 V to +5 V
J5 USB USB Connector to PC
The FMC (HPC) is a standard connector used to
J6 FMC interface the Lime board directly to an FPGA design kit.
The signal pin description is shown in 6.2.1 section.
This connector provides access to externally buffered,
Digital I/O
J7 LMS70002M digital interface and SPI interface. Signal
Connector
pin description showed in 6.2.2 section.
J8 +5V Power Supply +5 V supply connector
J9 ATP Analog Test Point

Transmitter TX1 output, channel A. Wideband
X1 TX1_A
transmitter output
Transmitter TX2 output, channel A. Lower bands
X2 TX2_A
transmitter output
Receiver LNA_L input, channel A. Lower bands
X3 LNAL_A
receiver input
Receiver LNA_H input, channel A. Higher bands
X4 LNAH_A
receiver input
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Receiver LNA_W input, channel A. Wideband receiver

X5 LNAW_A
input
Transmitter TX1 output, channel B. Wideband
X8 TX1_B
transmitter output
Transmitter TX2 output, channel B. Lower bands
X9 TX2_B
transmitter output
Receiver LNA_L input, channel B. Lower bands
X10 LNAL_B
receiver input
Receiver LNA_H input, channel B. Higher bands
X11 LNAH_B
receiver input
Receiver LNA_W input, channel B. Wideband receiver
X12 LNAW_B
input
Reference clock input used to synchronize test
equipment with EVB7 board to calibrate frequency
X18 CLK I/O
error. A 10 MHz reference from the test equipment
connects to X18 connector
X19, X20,
RXBUFFI/Q Receiver analog single-ended outputs
X39, X40
X16, X17,
X25-X28, RXOUTI/Q Receiver analog differential outputs
X37, X38
X6, X7,
X21-X23, ADCINI/Q Receiver analog differential inputs
X13, X14
X29-X36 TXINI/Q Transmitter analog differential inputs
Switch to reset AT90USB162-16U and load new
SW1 U1 Reset
software. By default set to off
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6.2.1. FMC connector pin description
The digital baseband interface can be established via the FMC connector J6. The signal pin
description is shown in Table 2.
Note: FMC HPC connector has 400 pins, but not all pins are used. Some pins are not connected
and some are connected to GND. Please refer to EVB7 schematic for more details.
Table 2 FMC connector signal pin description

Pin number Schematic name Function
D8 SyntCLK1 Clock Out, CMOS
D9 SyntCLK2 Clock Out, CMOS
H7 IQSEL2_DIR IQSEL direction control for port 2. If ‘1’ – input, ‘0’ – output
H8 DIO_DIR_CTRL1 Data direction control for port 2. If ‘1’ – input, ‘0’ – output
G9 SDIO Serial port data in/out, CMOS
G10 DIG_RST
H10 INTR I2C port interrupt line, CMOS
H11 SCLK Serial port clock, positive edge sensitive, CMOS
H13 RXFCLK Clock from BBIC to RFIC during JESD207 mode, Port 2
H14 RXEN RX hard power off
G12 RXMCLK Clock from RFIC to BBIC during JESD207 mode, Port 2
G13 RXIQSEL IQ flag in RXTXIQ mode enable flag in JESD207 mode, Port 2
D14 RESET Hardware reset, active low, CMOS
D15 IQSEL1_DIR IQSEL direction control for port 1. If ‘1’ – input, ‘0’ – output.
C14 SDO Serial port data out, CMOS
C15 DIO_DIR_CTRL2 Data direction control for port 1. If ‘1’ – input, ‘0’ – output.
H16 RXD11 DIQ bus, bit 11, Port 2
G15 TXNRX1 LimeLight protocol control
G16 RXD10 DIQ bus, bit 10, Port 2
D17 SAEN Serial port A enable, active low, CMOS
G21 TXNRX2 LimeLight protocol control
H25 TXMCLK Clock from RFIC to BBIC during JESD207 mode, Port 1
H26 TXIQSEL IQ flag in RXTXIQ mode enable flag in JESD207 mode, Port 1
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D24 SBEN Serial port B enable, active low, CMOS

H28 TXFCLK Clock from BBIC to RFIC during JESD207 mode, Port 1
H29 TXD10 DIQ bus, bit 10, Port 1
G27 TXEN TX hard power off
G28 TXD11 DIQ bus, bit 11, Port 1
F10 G_PWR_DWN
F11 DIO_BUFF_OE DIO port buffer enable/disable. If ‘1’ – disable, ‘0’ – enable.
C31 SDA I2C port data line, CMOS
C30 SCL I2C port clock line, CMOS
D12 RSSI_ADC0 Analog test point
C10 RSSI_ADC1 Analog test point
6.2.2. Digital I/O connector pin description
The DIO card can be connected to EVB 7 via Digitail I/O connector J7. Connectr has 44 pins.
The pin description showed in the Table 3.
Table 3 Digital I/O connector pin description

Pin number Schematic name Function
1 TXD0 DIQ bus, bit 0, Port 1
13 TXFCLK Clock from BBIC to RFIC during JESD207 mode, Port 1
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14 SyntCLK2 Clock Out, CMOS.

15 VDIO +3.3V supply
16 TXIQSEL IQ flag in RXTXIQ mode enable flag in JESD207 mode, Port 1
17 TXMCLK Clock from RFIC to BBIC during JESD207 mode, Port 1
18 TXEN TX hard power off
19 GND GND
20 GND GND
21 RXD0 DIQ bus, bit 0, Port 2
33 TXNRX1 LimeLight protocol control
34 SynCLK1 Clock Out, CMOS
35 RXFCLK Clock from BBIC to RFIC during JESD207 mode, Port 2
36 RXIQSEL IQ flag in RXTXIQ mode enable flag in JESD207 mode, Port 2
37 RXMCLK Clock from RFIC to BBIC during JESD207 mode, Port 2
38 RXEN RX hard power off
39 TXNRX2 LimeLight protocol control
40 SAEN Serial port A enable, active low, CMOS
41 SCLK Serial port clock, positive edge sensitive, CMOS
42 SDIO Serial port data in/out, CMOS
43 SDO Serial port data out, CMOS
44 RESET Hardware reset, active low, CMOS
6.3 Hardware options

This section describes the configuration options and set up procedures for:
 TCXO’s and data clocks distribution

 EVB7 Synchronization
 SPI connection options
The board is shipped with the default mode which means a basic operation using an external
digital I/O source via the FMC connector. Various configurations are available depending on the
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system requirements for development work. The configurations are summarized and the
following sections describe the board modifications required to achieve these configurations.
6.3.1. TCXO’s Configuration
The LMS7002M device provides a flexible clocking scheme which allows the PLL reference
clock and digital interface clock to be independently clocked. In addition, the digital interface
clock can be generated internally in LMS7002M.
The EVB7 board is shipped with a 30.72MHz TCXO. In order to meet the demanding
specifications of the various standards, Lime Microsystems has worked with Rakon to develop a
new part, called E6245LF* that enables the board to meet the required specifications.
The board can accept three different types of TCXO’s as described in Table 4.
Table 4 TCXO Configurations
Reference Part
Size Description
number Number
61.44 MHz Crystal oscillator, used in combination with
14.7x9.2 XO2 E5405LF
divider /2 (U10) for performance improvements
7x5 (4pin) XO1 E5280LF 30.72 MHz crystal shipped with the board as a default
7x5 (6pin) XO3 E6245LF 30.72 MHz high performance crystal oscillator.
When E5280LF is fitted the resistor R144 must also be fitted.
*Please contact Rakon for E6245LF part: info@rakon.co.uk
6.3.2. EVB7 synchronization
The LMS7002M board provides options to synchronize the on-board TCXO with the base band
or test equipment systems. To do that, connect a 10 MHz reference clock generated by the test
equipment to EVB7 board X18 SMA connector. Program the on-board PLL via the GUI
ADF4002 page. When the board is synchronized the LED (LD2) will be lit.
A board that is synchronized with the test equipment or any other RF device will not have
frequency error.
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6.3.3. SPI Control Configuration
The LMS7002M SPI interface is controlled from a USB connection by default. The SPI interface
can also be controlled from baseband interface connectors J6 and J7. Please note only one SPI
master can be connected to the bus at the time.
If the SPI is controlled via the baseband connector J6 do not connect either a USB cable to J5
and do not use J7 connector. This removes any possible bus contention. Please note that NF
denotes component is Not Fitted.
Table 5 SPI Control Options

SPI control
DEFAULT MODE
SPI controlled via J6 baseband
Configuration USB connector or baseband
connector
connector J7
Description SPI controlled via USB or J7 SPI connected to BB via connector

Component connector J6 HSMC
R91 NF 0R
R92 NF 0R
R93 NF 0R
R94 NF 0R
R95 NF 0R
R96 NF 0R
All of these components are located on the underside of the board.
Note. The USB interface must be left disconnected when the external SPI control is being used
to prevent bus contention. Additionally the components R91-R96 should be fitted as listed in
Table 5.
6.3.4. Baseband Digital Interface Voltage
The default digital interface voltage is 3.3V. It can be adjusted by changing R183 to the values
listed in Table 6.
Table 6 Digital IO Voltage Control

R183 Interface Voltage
0.8k 1.8V
1.5k 2.5V
2.32k 3.3V
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6.3.5. EVB7 Matching networks
The matching networks that are fitted to EVB7 at manufacture are listed in Table 7.
Table 7 Default bands matched to EVB7

Connector Schematic name Matching network
X1, X42 TX1_A Broadband from 10 – 6000MHz, using TCM1-63AX+ Balun
X2, X43 TX2_A Broadband from 4.5 – 3000MHz, using TC1-1-13MA+ Balun
X3, X44 LNAL_A Broadband from 4.5 – 3000MHz, using TC1-1-13MA+ Balun
X4, X45 LNAH_A Broadband from 10 – 6000MHz, using TCM1-63AX+ Balun
X5, X46 LNAW_A Broadband from 10 – 6000MHz, using TCM1-63AX+ Balun
X8, X47 TX1_B Broadband from 10 – 6000MHz, using TCM1-63AX+ Balun
X9, X48 TX2_B Broadband from 4.5 – 3000MHz, using TC1-1-13MA+ Balun
X10, X49 LNAL_B Broadband from 4.5 – 3000MHz, using TC1-1-13MA+ Balun
X11, X50 LNAH_B Broadband from 10 – 6000MHz, using TCM1-63AX+ Balun
X12, X51 LNAW_B Broadband from 10 – 6000MHz, using TCM1-63AX+ Balun
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7
Detailed Guide to LMS7002M Control Software
7.1 Control LMS7002M – Software Description

This section describes the Control LMS7002M software GUI and each of the menus, buttons and
embedded controls. Most of the pages in the tool corresponds to the top level sections of the SPI
programming map, with the exception of the ‘Board Setup’ and the ‘SPI’ page.
7.2 Control LMS7002M – Window Panels.

The “LMS7002M Control” GUI is comprised in three main pieces: GUI control panel,
LMS7002M register and EVB7 board configuration panel, and LOG panel. These are shown in
Figure 22.
7.2.1. GUI Control panel
GUI Control panel includes menu bar and various control buttons for controlling the software.
These will be described in detail in Section 7.3. The GUI control panel is shown in Figure 23.
7.2.2. Configuration panel
Configuration panel controls the LMS7002M registers and some evaluation board setup and is
shown in Figure 24.
Each configuration panel has specific register control on internal LMS7002M blocks. There are
16 different configuration panels for controlling the LMS7002M chip and 2 for controlling other
devices on the EVB7. Every control of the panel is described in Sections 7.4 to 7.21.
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GUI Control Panel
LMS7002M Registers and EVB7 Board

Configuration Panel
LOG Panel
Figure 22 GUI window diagram
Figure 23 GUI Control Panel window
Figure 24 GUI Configuration Board Setup window
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7.2.3. Log panel
Log panel section logs all activity executed with the GUI and is shown in Figure 25.
Figure 25 GUI Log panel
The Clear button deletes previously registered activity.
When Log button pressed, the Message Log configuration pop-up, as shown in
Figure 26.
Figure 26 GUI Message Log tab

This allows you to select the type of the information you want to log. The logged messages can
be saved into *.txt file.
In the lower left corner of the log tab, the evaluation board version and firmware version is
displayed.
7.3 The Menu Bar

7.3.1. The File Menu
In the File menu, you can select to start new projects, save current GUI project (saved in *.ini or
*.txt format), or open previously saved project. Saved project file contains complete register
setup for LMS7002M. These files can be transferred to any other computer or used as a register
initialization setup for LMS7002M in baseband.
The .ini format is machine readable only.

The .txt format is human and machine readable.
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7.3.2. The Option Menu
In the Options menu, you can select the COM port to which evaluation board is attached.
7.3.3. The Tool Menu
Register Test and Register Map are accessible from Tools menu. Register Test is an
executable function. This function checks if all LMS7002M registers are working correctly.
When Register Map is selected, new window will pop-up showing current LMS7002M register
configuration per each channel, as shown in Figure 27.
Figure 27 GUI Register Map window
7.3.4. The Help Menu
The help menu contains one option giving the software version and build date. It also contains
the contact details for Lime Microsystems.
7.3.5. The Button Menu
The button menu contains 6 buttons controls and 3 other minor controls. The “new”, “open”,
“save” buttons are identical to those in the “File menu” of Section 7.3.1.
The RESET button performs a manual reset on the chip and updates the “LMS7002M Control”
software.
To write register configuration from the “LMS7002M Control” software to the chip, press
GUIChip button.
To read register configuration from the chip to the “LMS7002M Control” software, press
ChipGUI button.
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7.3.6. The Configuring Channel Controls
Configuring Channels window select which channel or PLL is currently controlled. The
activated channel is always displayed in a front panel:
If selected Both, front panel will display: Active Ch: SXR&SXT or Active Ch: A&B.
If selected A/SXR, front panel will display: Active Ch: SXR or Active Ch: A.
If selected B/SXT, front panel will display: Active Ch: SXT or Active Ch: B.
The display shows information depending which configuration tab you are currently and which
channel is selected.
The SXR option is used for setting the receive synthesizer parameters in the SXT/SXR tab (see
Section 7.14). The SXT option is used for setting the transmitter synthesizer parameters in the
SXT/SXR tab. The A and B channel to the A and B channels for the TX and RX MIMO
channels of the RFE, RBB, TRF,TBB and AFE tabs.
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7.4 Board Setup (Si5351C and ADF4002)

These tabs control two other devices on the EVB7 board.
The ADF4002 is a PLL to lock an external reference (usually 10MHz on X18 or X52) with the
on board TXCO (usually 30.72MHz or 52.00MHz). This 30.72MHz reference is supplied to the
LMS7002M synthesizers. This is normally used to synchronize the measurement equipment with
the EVB7 board remove very minor frequency differences typically a few kHz. To synchronize
board:
 Press ‘Synchronize’ button to program the ADF4002, if all is correct the green PLL
locked LED (LD2) on the interface board should illuminate. LD2 is located in the upper
left hand corner of the interface board.
Make sure that the Fvco value corresponds to the frequency of TCXO.
The Si5351C is a dual PLL for frequency conversion in the 10-100MHz range. It can be used to
provide programmable clock signals to external hardware through the external digital interfaces
and also to the LMS7002M RX and TX PLL Clocks. This allows the clock rates to be
independent of the TXCO frequency. The tab is shown in Figure 28.
Figure 28 GUI Board Setup tab
By default, the EVB7 is configured to supply LMS7002M RX and TX PLL reference clock pins
directly from TCXO. With a simple board modification TX and RX PLL clocks can be supplied
directly from the Si5351C clock generator.
Using this feature:
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 Type onboard TCXO frequency to CLKIN Frequency (MHz) window.

 Enable clock channel.
 Enter the desired output frequency.
 Press “Configure Clocks”.
7.5 RFE
RFE tab controls the RX Front End stages, including LNA selection, LNA gain, TIA gain and
RX LO cancellation. A picture of the tab is shown in Figure 29. A description of each function
available in this tab is shown below in Table 8.
Figure 29 GUI RFE tab
Table 8 GUI RFE control description

Parameter Description
Power down controls
LNARFE Power control for LNA. Must be deselected in normal operation.
RXFE loopback1 Power control signal for RXFE loopback to LNAL from TXRF. Used only for RF loopback.
RXFE loopback2 Power control signal for RXFE loopback to LNAW from TXRF. Used only for RF
loopback.
RXFE mixer buffer Power control signal for RXFE mixer lo buffer. Must be deselected in normal operation.
RXFE Quadrature Power control signal for RXFE quadrature LO generator. Must be deselected in normal
LO generator operation.
RXFE RSSI Power control signal for RXFE RSSI. Enables RSSI readings when powered on.
RXFE TIA Power control signal for RXFE TIA. Must be deselected in normal operation.
Enable RFE module Major power down for RXFE modules. All modules will be power down when deselected.
Direct control Enables direct control of PDs and ENs for RFE. Enabled when selected
Input shorting switches
Input of LNAH Enables the input shorting switch at the input of the LNA. Should be selected when LNAH
is NOT active or during very high signal conditions.
Input of loopback 1 Enables the input shorting switch at the input of the loopback with LNAL. Should be
selected when RXFE Loopback1 is NOT active.
Input of loopback 2 Enables the input shorting switch at the input of the loopback with LNAW. Should be
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selected when RXFE Loopback2 is NOT active.

Input of LNAL Enables the input shorting switch at the input of the LNAL. Should be selected when LNAH
is NOT active or during very high signal conditions.
Input of LNAW Enables the input shorting switch at the input of the LNAW. Should be selected when
LNAW is NOT active or during very high signal conditions.
Reference current
Loopback amplifier Controls reference current of the RXFE loopback amplifier. Recommended value is 1.8uA.
TIA 1st Stage Controls reference current of the RXFE TIA first stage. Recommended value is 4.
TIA 2nd Stage Controls reference current of the RXFE TIA second stage. Recommended value is 8.
Capacitor controls
Compensation TIA Compensation capacitor for TIA. Recommended value is 15.
Feedback TIA Feedback capacitor for TIA. Controls the 3dB BW of the TIA. Recommended value is 230.
Trim Duty Cycle
I channel Trims the duty cycle in I channel. Default value set to 8.
Q channel Trims the duty cycle in Q channel. Default value set to 8.
UNGROUPED
Active path to RXFE Selects the active LNA of the RXFE between LNAL, LNAH and LNAW. Default value is
no path active.
Decoupling cap at Control the decoupling cap at the output of the RX Mixer. The capacitor range is from 80fF
the output of RX to 2560fF, with step size of 80 fF (32 steps). Default value is 640fF.
mixer
Controls cap parallel Controls the Q of the input LNA matching circuit and provides tradeoff between gain/NF
with the LNA input and IIP2/3. The higher the frequency, the lower value should be. Also, the higher value
lower the Q. Default value is 6.
Compensation Controls the compensation resistors of the TIA operational amplifier. Recommended value
resistor of TIA is 5.
opamp
Sets feedback Sets the TIA feedback resistor value. Default vale is 13.
resistor value
Enable daisy chain Enable MIMO mode when MIMO is selected. If SISO is selected on Channel A is in
LO buffer operation.
DC
Offset I side Controls DC offset of the I channel at the output of the TIA by injecting current to the input
of the TIA. Control range from 0 to 127. Default value is 0.
Offset Q side Controls DC offset of the Q channel at the output of the TIA by injecting current to the
input of the TIA. Control range from 0 to 127. Default value is 0.
Mixer LO signal Controls DC voltage of the mixer LO signal. Control range from 0.44V to 0.621V. Default
value is 0.557V.
Enable DCOFFSET Enables the DC offset block for the RXFE. Select before calibrating DC offset of the Rx
block path
Current Control
LNA output common Controls the LNA output common mode voltage. Control range from 0 to 31. Default value
mode voltage is 2.
LNA Core Controls the current of the LNA core. Control range from 0uA to 1291.7uA. Default value
is 500uA.
Gain Controls
LNA Controls selected LNA gain. Control range from Gmax to Gmax-30. Default value is Gmax.
Loopback Controls RXFE loopback gain. Control range from Gmax to Gmax-40.Default value is
Gmax-40dB.
TIA Controls TIA Gain. Three gain stages: Gmax, Gmax-3dB and Gmax-12dB. Default value is
Gmax.
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7.6 RBB
RBB tab controls the receiver IF stage bandwidth, PGA gain and loopback.
Figure 30 GUI RXBB tab
A picture of the tab is shown in Figure 30. A description of each function available in this tab is
shown below in Table 9.
Table 9 GUI RXBB control description

UNGROUPED
EN_LB_LPFH_RBB Enables baseband loopback when to high band LPF. Enable loopback when selected.
Default value is disabled.
EN_LB_LPFL_RBB Enables baseband loopback when to low band LPF. Enable loopback when selected. Default
value is disabled.
PGA input Controls PGA input path. There are a total five different inputs to the PGA:
1. LPFL output connected to PGA
2. LPFH output connected to PGA
3. Bypass LPF blocks output connected to PGA
4. Tx baseband loopback connected to PGA
5. TXRF peak detector connected to PGA
Concurrently only one path can be selected as PGA input. Default path is LPFL output
connected to PGA.
PGA gain PGA gain control. Control range from -12dB to +19dB. Default value is -1 dB.
PGA Feedback PGA feedback capacitor value control. Control range from 0 to 511. Default value is 2.
capacitor
PGA connected to Control PGA output switch internally directly to ADC or indirectly via the Analog output
pads. Default value of PGA output is selected to ADC input.
Power down controls
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LPFH block Power down of the LPFH block. Default value block is powered down.
LPFL block Power down of the LPFL block. Default value block is powered on.
PGA block Power down of the PGA block. Default value block is powered on
Enable RBB module Powers down all RBB blocks when not selected. If selected enables power down of separate
RBB blocks. Default values set to enable.
Direct control Enable direct control of PDs and ENs. Enabled when selected.
RC time constant
Resistance Controls the absolute value of the resistance of the RC time constant in LPF. Control range
from 0 to 31. The higher value selected the wider LPF BW. Default values set to 16.
Capacitance of RC Controls the capacitance value of the RC time constant of high band LPF. Control range
time constant from 0 to 255. The lower value selected the wider LPF BW. Default values set to 0.
(rxMode from
37MHz to 108MHz)
Capacitance of RC Controls the capacitance value of the RC time constant of low band LPF. Control range
time constant from 0 to 255. The lower value selected the wider LPF BW. Default values set to 0.
(rxMode from Intended to be controlled together with the TIA to maintain Chebychev response.
1.4MHz to 20MHz)
Operational amplifier
Stability passive Controls the stability passive compensation of the LPFH operational amplifier. Control
compensation range from 0 to 7. Default values set to 0.
Stability passive Controls the stability passive compensation of the LPFL operational amplifier. Control
compensation range from 0 to 5. Default values set to 5.
Input stage reference Controls the reference bias current of the input stage of the operational amplifier used in
bias current LPF blocks (Low or High). Must increase up to 24 when a strong close blocker is detected
(RBB_LPF) to maintain the linearity performance. Control range from 0 to 31. Default values set to 12.
Output stage Controls the reference bias current of the output stage of the operational amplifier used in
reference bias current LPF blocks (Low or High). Must increase up to 24 when a strong close blocker is detected
(RBB_LPF) to maintain the linearity performance. Control range from 0 to 31. Default values set to 12.
Output stage Controls the output stage reference bias current of the operational amplifier used in the PGA
reference bias current circuit. Must increase up to 12 when a strong close blocker is detected or when operating at
(PGA) the high band frequencies to maintain the linearity performance. Control range from 0 to 31.
Default values set to 6.
Input stage reference Controls the input stage reference bias current of the operational amplifier used in the PGA
bias current (PGA) circuit. Must increase up to 12 when a strong close blocker is detected or when operating at
the high band frequencies to maintain the linearity performance. Control range from 0 to 31.
Default values set to 6.
Stability passive Controls the stability passive compensation of the PGA operational amplifier. Control range
compensation from 0 to 31. Default values set to 24.
7.7 TRF
The TRF page contains the Tx front end amplifier gain controls, Tx outputs paths selection
controls and all transmit block power down controls.
47 | P a g e
Figure 31 GUI TRF page
Table 10 GUI TRF control description

UNGROUPED
High pass pole Controls the high pass pole frequency of the mixer switches. Selection between low band
frequency and high band. Default is high band selection.
Enable daisy chain Enables MIMO mode. Default is set to SISO mode.
LO buffers
Enable TXPAD Controls TXPAD power detector gain. Default gain is set to 25dB.
power detector
preamplifier
Switched capacitor at Controls TXPAD output capacitor used for fine tuning. Control range from 0 to 7. Default is
TXPAD output set to 3.
Loss of loopback Controls Tx loopback path gain. Default gain is set to -24 dB.
path at TX side
TXPAD linearizing Controls TXPAD linearization gain. Control range from 0 to 31. Default is set to 0.
part gain
TXPAD gain and Controls the gain of TXPAD. Control range from 0 to 31. Default is set to 0 (Max gain).
output power
Bias voltage at gate Controls the bias voltage at the gate of TXPAD cascade. Control range from 0 to 31.
of TXPAD cascade Default is set to 0.
Bias at gate of mixer Controls the bias at the gate of the mixer NMOS switch. Control range from 0 to 31. Default
NMOS is set to 28.
Bias at gate of mixer Controls the bias at the gate of the mixer PMOS switch. Control range from 0 to 31. Default
PMOS is set to 16.
Enable signal for Enables TXFE, band 1 output. Enabled by default.
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TXFE, band 1
Enable signal for Enables TXFE, band 2 output. Disabled by default.
TXFE, band 2
Enable TXPAD Enables the TXPAD loopback path. Disabled by default.
loopback path
Power detector
Resistive load Controls power detector dynamic range by selecting resistive load. Default is set to
5K||1.25K.
Bias current
Linearization section Control the bias current of the linearization section of the TXPAD. Control range from 0 to
31. Default is set to 12.
Main gm section Control the bias current of the TXPAD. Control range from 0 to 31. Default is set to 12.
Power down controls
Power detector Enables power detector when deselected. By default power detector is powered down.
TX LO buffers Enables TX LO buffer. By default TX LO is enabled.
TXPAD Enables TXPAD block. By default TXPAD is enabled
Enable TRF modules Power down all TFE blocks when deselected. By default TRF blocks enabled.
Direct Control Enable direct control of PDs and ENs. Enabled if selected.
TXPAD cascade transistor gate bias
VDD TXPAD cascade transistor gate bias is referred to VDD – connect to VDD to operate.
GNDS TXPAD cascade transistor gate bias is referred to GND.
Trim duty cycle
I channel Trims the duty cycle in I channel. Default value set to 8.
Q channel Trims the duty cycle in Q channel. Default value set to 8.
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7.8 TBB
The TBB page controls TX IF gain settings, low-LPF and high-LPF filter bandwidths and
various loopback options.
Figure 32 GUI TBB page
Table 11 GUI TBB control description

UNGROUPED
Signal to loopback Controls the Tx BB loopback path. By default loopback is disconnected.
output
Frontend gain Tx baseband stage gain control. Control range from 0 to 63. Default is set to 24.
Reference bias This controls the reference bias current of the IAMP main bias current sources. Control
current of IAMP range from 0 to 31. Default is set to 12.
main bias current
source
Reference bias This controls the reference bias current of the IAMP's cascode transistors gate voltages that
current of IAMP set the IAMP's input voltage level. Control range from 0 to 31. Default is set to 12.
cascode transistors
gate voltage
TSTINTBB Controls Tx analog inputs path. By default disabled.
Bypass LPF ladder Controls TBB LPF ladder bypass mode.
of TBB
Operational amplifier
Output stage bias This controls the operational amplifier's output stage bias current. Control range from 0 to
current low band real 31. Default is set to 12.
pole filter
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Input stage bias This controls the operational amplifier's input stage bias current. Control range from 0 to 31.
current low band real Default is set to 12
pole filter
Input stage bias This controls the operational amplifiers input stage bias reference current of the high band
reference current of filter. Control range from 0 to 31. Default is set to 12.
high band low pass
filter
Output stage bias This controls the operational amplifiers output stage bias reference current of the high band
reference current of filter. Control range from 0 to 31. Default is set to 12.
high band low pass
filter
Output stage bias This controls the operational amplifiers' output stages bias reference current of the low band
reference for low filter. Control range from 0 to 31. Default is set to 12.
band ladder filter
Input stage bias This controls the operational amplifiers' input stages bias reference current of the low band
reference for low filter. Control range from 0 to 31. Default is set to 12.
band ladder filter
Power down controls
LPFHTBB biquad Enables LPFH filter when deselected. By default filter is powered down.
LPFIAMP front-end Enables LPF current amplifier when deselected. By default current amplifier is enabled.
current amp
LPFLADTBB low Enables LPF ladder when deselected. By default current amplifier is enabled.
pass ladder filter
LPFS5TBB low pass Enables LPF real-pole filter when deselected. By default real-pole filter is enabled.
real-pole filter
Turn off all of Enables TBB blocks once selected. By default TBB blocks are enabled.
TBBTOP
Enable direct control Enables direct control of PDs and ENs for TBB. Enabled when selected.
of PDs and ENs
Resistor banks
Equivalent resistance Control LPFH bandwidth. Control range from 0 to 255. The higher number the higher
of biquad filter stage bandwidth. Default setting is 0.
Equivalent resistance Control LPFL bandwidth. Control range from 0 to 255. The higher number the higher
of low pass filter bandwidth. Default setting is 193.
ladder
Common control A common control signal for all the capacitor banks of TBB filters. Control range from 0 to
signal for all 31. Default register value set to 8.
Equivalent resistance This controls the value of the equivalent resistance of the resistor banks of the real pole
of real pole filter filter stage. Control range from 0 to 255. Default register value set to 76.
stage
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7.9 AFE
The AFE page controls the TX and RX analog front-end interface to the digital section.
Figure 33 GUI AFE tab
Table 12 GUI AFE control description
AFE
Peak current of DAC Controls the peak current of the DAC output current. By default DAC peak current set to
325uA.
MUX input of ADC Controls the MUX at the input of the ADC channel 1. By default MUX set to PGA output.
ch 1.
MUX input of ADC Controls the MUX at the input of the ADC channel 2. By default MUX set to PGA output.
ch 2.
Time interleave two Default register set to Two ADC’s
analogue signals
into one ADC
Power down controls
AFE current mirror Enabled AFE current mirror in BIAS_TOP when deselected. Default current mirror is
in BIASTOP enabled.
ADC ch. 1 Enable control of ADC of channel 1. Enabled when not selected. Enabled by default.
ADC ch. 2 Enable control of ADC of channel 2. Enabled when not selected. Enabled by default.
DAC ch. 1 Enable control of DAC of channel 1. Enabled when not selected. Enabled by default.
DAC ch. 2 Enable control of DAC of channel 2. Enabled when not selected. Enabled by default.
Enable AFE module Enabled AFE blocks when selected. By default AFE is enabled.
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7.10 BIAS
The BIAS page controls the LMS7002M bias settings.
Figure 34 GUI BIAS tab
Table 13 GUI BIAS control description

Power down controls
Fix /RP block Enable signal for Fix/RP block when not selected. Default register setting is set to enabled.
Fix Enable signal for Fix block when not selected. Default register setting is set to enabled.
PTAT/RP block Enable signal for PTAT/RP block when not selected. Default register setting is set to
enabled.
PTAT Enable signal for PTAT block when not selected. Default register setting is set to enabled.
Enable central bias Enable signal for central bias block. Default register setting is set to enabled.
block
Power down all Enables BIAS block when selected. By default BIAS block is enabled.
block
BIAS
BIASTOP test mode Controls the test mode of the BIAS_TOP. No test mode selected by default.
RP_CALIB_bias Control bias current calibration code. Control range from 0 to 31. Default setting is 0. This
is used to set the voltage across current reference resistor R12 to 600mV – typically code 7.
The “calibrate” button automatically sets this.
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7.11 LDO
This tab controls the internal LDO modules. These LDO’s are used when the LMS7002M chip
analog blocks supplied by single 1.8V supply. Pictures of the tab is shown in Figure 35 and
Figure 36.
Figure 35 GUI LDO Power downs & Bias & Noise filter tab
Each 1.25V and 1.4V supply pins have internal regulators controlled via SPI interface. The LDO
’Power downs & Bias & Noise filter’ tab (figure above) divided in separate sections:
 Power control
 Short noise filter resistor
 Bias
In Power control section is the SPI controls are in groups related to their function. These
controls enable the LDO for the particular block.
Short noise filter resistor bypasses noise filtering resistor. By default enabled.
Bias section enables the load dependent bias to optimize the load regulation for each LDO. This
option reduces the LDO response, but increase total current consumption. Recommend to set to
constant bias (not selected).
In the ‘Voltage’ tab the voltage level of the each internal LDO can be adjusted (figure below).
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Figure 36 GUI LDO Voltages tab
7.12 XBUF
XBUF page controls the TX and RX PLL clock pin input configurations to provide a reference
frequency for SXT and SXR respectively. The CLKGEN PLL uses the SXR Clock.
Figure 37 GUI XBUF tab
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in Table 14.
Table 14 GUI XBUF control description
UNGRPUPED
Rx Enable biasing the Receiver clock input self-biasing digital control. By default disabled. For use with AC
input’s DC voltage coupled input.
Tx Enable biasing the Transmitter clock input self-biasing digital control. By default disabled. For use with
input’s DC voltage AC coupled input.
Shorts the input 3.3V Shorts the Input of 3.3V buffer in XBUF. By default disabled
buffer in XBUF RX
Shorts the input 3.3V Shorts the Input of 3.3V buffer in XBUF. By default disabled
buffer in XBUF TX
EN_OUT2_XBUF_TX Enables the 2nd output of TX XBUF. By default buffer is disabled. This control is
intended to internally rout TX PLL CLK to SXT and SXR by an internal path.
EN_TBUFIN_XBUF_RX Disables the input from the external XO. By default buffer is disabled. This control is
intended to internally rout TX PLL CLK to SXT and SXR by an internal path.
Power down controls
Power down Rx Power down control of the Rx XBUF. Not powered down by default.
Power down Tx Power down control of the Tx XBUF. Not powered down by default.
Enable XBUF module Power down complete XBUF block. Enabled by default.
7.13 CLKGEN
The block diagram of the CGEN module (internal clock generator) is shown. The table in this
chapter describes the control registers of the CGEN module.
Figure 38 GUI CLKGEN tab
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The internal LMS7002N CLKGEN generates clock for ADC’s, DAC’s and TSP modules. To
program the CLKGEN for wanted frequency follow the step below:
1. Enable ‘VCO’ in Power down controls

2. Type the wanted frequency in CLK_H (MHz) window
3. Press ‘Calculate’ followed by ‘Tune’
After this procedure the digital block core will be supplied by wanted frequency. All other
register are preset so no need to change.
Table 15 GUI CLKGEN control description

UNGROUPED
Bypass noise filter Bypasses the noise filter resistor for fast settling time. Disabled by default.
resistor
Enable coarse tuning Enable signal for coarse tuning block. Disabled by default.
block
Enable SDM clock Enables SDM clock. Used in INT-N mode or for noise testing. Enabled by default.
Reverse SDM clock Invert the SDM clock. By default not inverted.
Connection to Selects if F_CLKH or F_CLKL is connected to FCLK_ADC. By default FCLK_ADC
FCLK_ADC connected to F_CLKH and FCLK_DAC to F_CLKL.
Test mode of SX Controls the test mode of the SX. Available test modes:
0: TST disabled. By default test mode disabled.
1: tstdo[0]=CLKH1 & tstdo[1]=CLKH2
2: tstdo[0]=CLK_SDM & tstdo[1]=DIV_CLK
2: tstao=vco_vtune through a 50Kohm resistor
3: tstdo[0]=REFCLK & tstdo[1]=DIV_CLK
5: tstdo[0]=PFD UP & tstdo[1]=PFD DN
REV_CLKDAC_CGEN Inverts the clock F_CLKL for TX TSP. By default is not inverted.
REVPH_PFD_CGEN Inverts the pulses of PFD. It can be used to reverse the polarity of the PLL loop. By
default pulse is not inverted.
Pulse used in start-up to Enables pulse to reset the CLKGEN. By default set to normal operation.
reset
Enable INTEGER-N Enables INTEGER-N mode of the synthesizer. By default disabled.
mode
Enable SDM_TSTO Enables the buffer for SDM_TSTO test outputs. Is not enabled by default.
outputs
Enable dithering in SDM Enabled dithering. Disabled by default.
REV_CLKADC_CGEN Inverts the clock F_CLKL for RX TSP. By default is not inverted.
Signal coarse tuning Control signal for coarse tuning algorithm.
algorithm
Output for SDM Selects between the feedback divider output and Fref for SDM. By default feedback
divider is selected.
Power down controls
Charge pump Power down control for charge pump of the CGEN block. Enabled (deselected) by
default.
Frequency divider Power down control for forward frequency divider of the CGEN block. Enabled
(deselected) by default.
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VCO Power down control for VCO of the CGEN block. Disabled (selected) by default.
Enables CLKGEN Power down control of the CGEN block. Enabled (selected) by default.
module
Feedback frequency Power down control for feedback divider of the CGEN block. Enabled (deselected)
divider by default.
SDM Power down control for SDM of the CGEN block. Enabled (deselected) by default.
VCO comparator Power down control for VCO comparators of the CGEN block. Enabled (deselected)
by default.
VCO
CSW_VCO_CGEN Coarse control of VCO frequency, 0 for lowest frequency and 255 for highest, by 1
step. By default set to 128.
Scales VCO bias current Scales the VCO bias current from 0 to 2.5xInom. Control range from 0 to 31. Default
value 12.
PLL filter
CP2 Controls the value of CP2 (cap from CP output to GND) in the PLL loop filter.
Control range from 0 to 5688fF. Default value 2275.2 fF.
CP3 Controls the value of CP3 (cap from CP output to GND) in the PLL loop filter.
Control range from 0 to 3720fF. Default value 1736.00 fF.
CZ Controls the value of CP3 in the PLL loop filter. Control range from 0 to 43800fF.
Default value 321200.00 fF.
Charge pump
Scales offset current Scales the offset current of the charge pump, from 0 to 63. This current is used in
Fran-N mode to create an offset in the CP response and avoid the non-linear section.
Default value is set to 20.
Scales pulse current Scales the pulse current of the charge pump, from 0 to 63. Default value is set to 20.
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7.14 SXT/SXR
This tab controls the SXT and SXR modules. The table in this chapter describes the control registers of
SXT and SXR modules.
Figure 39 GUI SXT/SXR tab
Most of the SXT/SXR registers are preset to for normal (FDD) operation. To configure Tx/Rx
LO to wanted frequency, do the following:
1. Select the A/SXR (receiver PLL) or B/SXT (transmitter PLL) in configuration channels
window accordingly which PLL frequency you want to control.
2. Enable VCO (deselect).
4. Type the wanted frequency in Frequency, GHz box. In this case 1950MHz.
Table 16 GUI SXT/SXR control description

Division ration
Trim duty cycle of DIV2 Trims the duty cycle of DIV2 LOCH. Only works when forward divider is dividing
LOCH by at least 2 (excluding quadrature block division). If in bypass mode, this does not
work. By default set to 3.
Trim duty cycle of DIV4 Trims the duty cycle of DIV4 LOCH. Only works when forward divider is dividing
LOCH by at least 4 (excluding quadrature block division). If in bypass mode, this does not
work. By default set to 3.
LOCH_DIV division Controls the division ratio in the LOCH_DIV. By default set to 2.
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ration
Power down controls
Feedback divider block Enables PLL feedback divider. By default is enabled.
LO buffer from SXT to Power down control for LO buffer from SXT to SXR. Controlled for SXT only. To
SXR be activated only in the TDD mode. By default is disabled.
Charge pump Power down control for Charge Pump block. By default is enabled.
Froward frequency Power down control for feedback frequency divider and divider chain of the LO
divider and divider chain chain. By default is enabled.
of LO chain
SDM Power down control for SDM block. By default is enabled.
VCO comparator Power down control for VCO comparator block. By default is enabled.
VCO Power down control for VCO block. By default is disabled.
Enable SXR/SXT Power down control for SXT/SXR block. By default enabled.
module
Direct control Enabled control of PD and EN. Enabled if selected.
VCO
Active VCO Selects the active VCO. It is set by SX_SWC calibration. By default VCOH selected.
VCO LDO output Controls VCO LDO output voltage. Control range from 0 to 255. By default set to
voltage 185.
Scales VCO bias current Scales the VCO bias current from 0 to 2.5xInom. Control range from 0 to 255. By
default set to 185.
SXT/SXR controls
Reset SX Resets SX when enabled. A pulse should be used in the start-up to reset. By default
disabled.
Bypass SX LDO Controls the bypass signal for the SX LDO. By default LDO is bypassed.
Enable current limit Enables the output current limitation in the VCO regulator. By default enabled.
Enable INTEGR_N Enables INTEGER-N mode of the SX. By default SX is set to Frac-N mode.
mode
Enable Enables the SDM_TSTO outputs for SXR testing purposes. By default is disabled.
SDM_TSTO_SXR
outputs
Reverse SDM clock Inverts DSM clock. By default clock is not inverted.
Reverse pulses of PFD Inverts the pulses of PFD block. It can be used to reverse the polarity of the PLL
loop. By default the clock is not inverted.
Bypass noise filter Bypasses the noise filter resistor for fast settling time. By default the speed up is not
resistor enabled.
Enable coarse tuning Enable signal for coarse tuning block.
Enable additional DIV2 Enables additional DIV2 prescaler at the input of the programmable divider. The core
prescaler of programmable divider in the SX feedback divider works up to 5.5GHz. For
FVCO>5.5GHz, the prescaler is needed to lower the input frequency. BY default
prescaler is not enabled.
Enable SDM clock Enables SDM clock. In INT-N mode or for noise destining. Enabled by default.
Enable SDM_TSTO Enables the SDM_TSTO outputs for testing purposes. By default is disabled.
outputs
Enable dithering in SDM Enabled dithering in SDM. Disabled by default.
Test mode of SX Controls the test mode of the SX. Available test modes:
0: TST disabled. By default test mode disabled.
1: tstdo[0]=CLKH1 & tstdo[1]=CLKH2
2: tstdo[0]=CLK_SDM & tstdo[1]=DIV_CLK
3: tstdo[0]=REFCLK & tstdo[1]=DIV_CLK
5: tstdo[0]=PFD UP & tstdo[1]=PFD DN
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Feedback divider for Selects SDM clock input between the feedback divider output and Fref. By default
SDM feedback divider output is selected.
Reference voltage Sets the reference voltage for varactor. By default set to 0.675V.
Scales offset of charge Scales the offset current of the charge pump block. Control range from 0 to 63. This
pump current is used in Fran-N mode to create an offset in the CP response and avoid the
non-linear section. By default set to 20.
Scales pulse current of Scales the pulse current of the charge pump block. Control range from 0to 63. By
charge pump default set to 20.
CP2 Control for CP2 value (cap from CP output to GND) of the PLL loop filter. Control
range from 0fF to 34830fF. Default value 13932fF.
CP3 Control for CP3 value (cap from CP output to GND) of the PLL loop filter. Control
range from 0fF to 88200fF. Default value 41160fF.
CZ Control for CZ value of the PLL loop filter. Control range from 0fF to 705.6fF.
Default value 517.44fF.
CSW_VCO Coarse control of VCO frequency, 0 for lowest frequency and 255 for highest. This
control is set by SX_SWC calibration. Default value set to 128.
7.15 Application Note on Tuning PLLs on LMS7002M

The LMS7002M has three synthesisers: SXT, SXR and CLKGEN. The LMS7002M Control
Software uses a simple tuning algorithm to control these. The minimum and maximum
frequencies of each VCO are defined in the “VCO PARAMS” control for each VCO. This
allows linear interpolation of CSW_VCO control when using the “Tune” control. Further
frequencies could be added to the “VCO PARAMS” table to allow quadratic or cubic
interpolation.
The LMS7002M also provides two comparators to detect if the VCO tuning voltage is within the
recommended limits. These comparators are read with the “Read” or “Read CMP” buttons, after
the “Tune” process has been carried out. When the PLL is successfully locked, the low
comparator should be “1” and the high comparator “0”. If the comparators are both “0”, or both
“1”, then the tuning voltage is outside the recommended range.
For best phase noise and best protection against drift the following procedure is recommended.
The “Tune” button gives a nominal value for CSW_VCO. The value of CSW_VCO is manually
increased until the tuning comparators report the tune voltage is out of range. The last good
CSW_VCO value, CSW_VCOmax , is noted. Then CSW_VCO is manually decreased until the
tuning comparators report that the tune voltage is out of range. The last good CSW_VCO,
CSW_VCOmin, is also noted. The average of the two extreme CSW_VCO values is the optimum
CSW_VCOopt which will give good phase noise and protection against drift.
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7.16 LimeLight & PAD

This tab controls the LMS7002M digital interface configuration. The IO cell controls are
described in the chapter tables.
Figure 40 GUI Limelight&PAD Modes tab
The LimeLight tab has two sections:

 Modes
 Sample position & Clock
A picture of the tab is shown in Figure 40. A description of each function available in the
‘Modes’ tab is shown below in Table 17.
Table 17 GUI Limelight&PAD Modes control description

Pull up control
Engage pull up of TXCLK pad Controls Pull up resistor of TX_CLK pad. Pull-up enabled by default.
Engage pull up of SDA pad Controls Pull up resistor of SDA pad. Pull-up enabled by default.
Engage pull up of SDIO pad Controls Pull up resistor of SDIO pad. Pull-up enabled by default.
Engage pull up of SCLK pad Controls Pull up resistor of SCLK pad. Pull-up enabled by default.
Engage pull up of DIQ2 pad Controls Pull up resistor of DIQ2 pad. Pull-up enabled by default.
Engage pull up of TXNRX2 pad Controls Pull up resistor of TXNRX2 pad. Pull-up enabled by default.
Engage pull up of MCLK2 pad Controls Pull up resistor of MCLK2 pad. Pull-up enabled by default.
Engage pull up of IQSELEN1 pad Controls Pull up resistor of IQSELEN1 pad. Pull-up enabled by default.
Engage pull up of FCLK1 pad Controls Pull up resistor of FCLK1 pad. Pull-up enabled by default.
Engage pull up of RXCLK pad Controls Pull up resistor of RXCLK1 pad. Pull-up enabled by default.
Engage pull up of SCL pad Controls Pull up resistor of SCL pad. Pull-up enabled by default.
Engage pull up of SDO pad Controls Pull up resistor of SDO pad. Pull-up enabled by default.
Engage pull up of SEN pad Controls Pull up resistor of SEN pad. Pull-up enabled by default.
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Engage pull up of IQSELEN2 pad Controls Pull up resistor of IQSELEN2 pad. Pull-up enabled by default.
Engage pull up of FCLK2 pad Controls Pull up resistor of FCLK2 pad. Pull-up enabled by default.
Engage pull up of DIQ1 pad Controls Pull up resistor of DIQ1 pad. Pull-up enabled by default.
Engage pull up of TXNRX1 pad Controls Pull up resistor of TXNRX1 pad. Pull-up enabled by default.
Engage pull up of MCLK1 pad Controls Pull up resistor of MCLK1 pad. Pull-up enabled by default.
Reset Signals
Logic registers Tx MIMO ch. B Resets all registers to the default state for Tx MIMO channel B logic. By
default RESET inactive.
Logic registers Tx MIMO ch. A Resets all registers to the default state for Tx MIMO channel A logic. By
Logic registers Rx MIMO ch. B Resets all registers to the default state for Rx MIMO channel B logic. By
Logic registers Rx MIMO ch. A Resets all registers to the default state for Rx MIMO channel A logic. By
Rx FIFO soft reset Soft reset of LimeLight RX FIFO registers. By default RESET inactive.
Configuration memory Tx MIMO Resets configuration memory to the default state for Tx MIMO channel B
ch. B logic. By default RESET inactive.
Configuration memory Tx MIMO Resets configuration memory to the default state for Tx MIMO channel A
ch. A logic. By default RESET inactive.
Configuration memory Rx MIMO Resets configuration memory to the default state for Rx MIMO channel B
ch. B logic. By default RESET inactive.
Configuration memory Rx MIMO Resets configuration memory to the default state for Rx MIMO channel A
ch. A logic. By default RESET inactive.
Tx FIFO soft reset Soft reset of LimeLight TX FIFO registers. By default RESET inactive.
Driver strength
SDA pad Set SDA pad driver strength to 4mA or 8 mA. By default set to 4 mA.
SCL pad Set SCL pad driver strength to 4mA or 8 mA. By default set to 4 mA.
SDIO pad Set SDIO pad driver strength to 4mA or 8 mA. By default set to 4 mA.
DIQ2 pad Set DIQ2 pad driver strength to 4mA or 8 mA. By default set to 4 mA.
DIQ1 pad Set DIQ1 pad driver strength to 4mA or 8 mA. By default set to 4 mA.
Power Control
Enable Rx MIMO ch. B Enables Rx MIMO B channel. Enabled by default.
Enable Tx MIMO ch. B Enables Tx MIMO B channel. Enabled by default.
Enable Rx MIMO ch. A Enables Rx MIMO A channel. Enabled by default.
Enable Tx MIMO ch. A Enables Tx MIMO A channel. Enabled by default.
LimeLight modes
Enable LimeLight interface Enables LimeLight interface. By default enabled.
Frame start for Port1 Selects frame start ID for Port 1, can be set to ‘0’ or ‘1’. By default set to ‘0’.
Frame start for Port2 Selects frame start ID for Port 2, can be set to ‘0’ or ‘1’. By default set to ‘0’.
LimeLight port1 mode Select mode for Port 1: T TRXIQ or JESD207. By default set to JESD207.
LimeLight port2 mode Select mode for Port 2: T TRXIQ or JESD207. By default set to JESD207.
Port 1 mode selection IQSEL selection for Port 1: RXIQ or TXIQ. By default set to RXIQ.
Port 2 mode selection IQSEL selection for Port 2: RXIQ or TXIQ. By default set to TXIQ.
UNGROUPED
RxFIFO data source RxFIFO data source selection: RxTSP, TxFIFO, LFSR. By default set to
RxTSP.
Data transmit port to TSP Port selection for data transmit to TSP.
Disable MIMO channel B MIMO channel B enable control.
SPI mode SPI mode control.
MIMO access control MIMO access control.
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Figure 41 GUI Limelight&PAD Sample position tab
A picture of the tab is shown in Figure 41. Description of each function available from the
‘Sample position & Clock’ page is shown below in Table 18.
Table 18 GUI Limelight&PAD Sample position control description

Sample source when Port1 is Tx
Position 3 Select sample source of the position 3: BQ, BI, AQ or AI. By default BQ is selected.
Position 2 Select sample source of the position 2: BQ, BI, AQ or AI. By default BI is selected.
Position 1 Select sample source of the position 1: BQ, BI, AQ or AI. By default AQ is selected.
Position 0 Select sample source of the position 0: BQ, BI, AQ or AI. By default AI is selected.
Sample source when Port2 is Tx
Position 3 Select sample source of the position 3: BQ, BI, AQ or AI. By default BQ is selected.
Position 2 Select sample source of the position 2: BQ, BI, AQ or AI. By default BI is selected.
Position 1 Select sample source of the position 1: BQ, BI, AQ or AI. By default AQ is selected.
Position 0 Select sample source of the position 0: BQ, BI, AQ or AI. By default AI is selected.
Sample source when Port1 is Rx
BQ sample position Select BQ sample position in frame. Position: 3, 2, 1, or 0. By default position set to 3.
BI sample position Select BI sample position in frame. Position: 3, 2, 1, or 0. By default position set to 2.
AQ sample position Select AQ sample position in frame. Position: 3, 2, 1, or 0. By default position set to 1.
AI sample position Select AI sample position in frame. Position: 3, 2, 1, or 0. By default position set to 0.
Sample source when Port2 is Rx
BQ sample position Select BQ sample position in frame. Position: 3, 2, 1, or 0. By default position set to 3.
BI sample position Select BI sample position in frame. Position: 3, 2, 1, or 0. By default position set to 2.
AQ sample position Select AQ sample position in frame. Position: 3, 2, 1, or 0. By default position set to 1.
AI sample position Select AI sample position in frame. Position: 3, 2, 1, or 0. By default position set to 0.
Clock controls
TX FIFO read clock Select TX FIFO read clock source: TxTSPCLK, FCKL1 or FCKL2. By default
source TxTSPCLK is selected.
TX FIFO write clock Select TX FIFO write clock source: FCKL1, FCKL2 or RxTSPCLK. By default
source FCKL1 is selected.
RX FIFO read clock Select RX FIFO read clock source: MCKL1, MCKL2, FCKL1 or FCKL2. By default
source MCKL2 is selected.
RX FIFO write clock Select RX FIFO write clock source: FCKL1, FCKL2 or RxTSPCLK. By default
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source RxTSPCLK is selected.

MCLK2 clock source Select MCKL2 clock source from: RxTSPCLKA, TxTSPCLKA, RxTSPCLKA after
divider or TxTSPCLKA after divider. By default RxTSPCLK after divider is selected.
MCLK1 clock source Select MCKL1 clock source from: RxTSPCLKA, TxTSPCLKA, RxTSPCLKA after
divider or TxTSPCLKA after divider. By default TxTSPCLK after divider is selected.
TxTSPCLKA clock TxTSP clock divider, used to produce MCLK(1/2) clocks. Control range from 0 to
divider 255. By default set to 255.
RxTSPCLKA clock RxTSP clock divider, used to produce MCLK(1/2) clocks. Control range from 0 to
divider 255. By default set to 255.
Enable Tx clock divider Enables Tx clock divider. Set to enable by default.
FCLK1 invert Inverts FCLK1 clock. By default clock is not inverted.
Enable Rx clock divider Enables Rx clock divider. Set to enable by default.
FCLK2 invert Inverts FCLK1 clock. By default clock is not inverted.
MCLK1DLY Select MCLK1 clock delay. By default clock not delayed.
MCLK2DLY Select MCLK2 clock delay. By default clock not delayed.
Direction controls
DIQ2 mode DIQ2 direction control mode. By default set to Automatic.
DIQ1 mode DIQ1 direction control mode. By default set to Automatic.
DIQ2 direction DIQ2 direction. By default set to Input.
DIQ1 direction DIQ1 direction. By default set to Input.
ENABLE2 mode ENABLE2 direction control mode. By default set to Automatic.
ENABLE1 mode ENABLE1 direction control mode. By default set to Automatic.
ENABLE2 direction ENABLE2 direction. By default set to Input.
ENABLE1 direction ENABLE1 direction. By default set to Input.
LML1
Clock cycles to wait Controls the number of clock cycles to wait before data drive stop after burst stop is
before data drive stop detected in JESD207 mode on Port 1 and Port 1 is transmitter. By default set to 1.
Clock cycles to wait Controls the number of clock cycles to wait before data drive stop after burst start is
before data drive start detected in JESD207 mode on Port 1 and Port 1 is transmitter. By default set to 1.
Clock cycles to wait Controls the number of clock cycles to wait before data capture stop after burst stop is
before data capture stop detected in JESD207 mode on Port 1 and Port 1 is receiver. By default set to 1.
Clock cycles to wait Controls the number of clock cycles to wait before data capture stop after burst start is
LML2
Clock cycles to wait Controls the number of clock cycles to wait before data drive stop after burst stop is
before data drive stop detected in JESD207 mode on Port 1 and Port 1 is transmitter. By default set to 1.
Clock cycles to wait Controls the number of clock cycles to wait before data drive stop after burst start is
before data drive start detected in JESD207 mode on Port 1 and Port 1 is transmitter. By default set to 1.
Clock cycles to wait Controls the number of clock cycles to wait before data capture stop after burst stop is
Clock cycles to wait Controls the number of clock cycles to wait before data capture stop after burst start is
Direction controls
DIQ2 mode DIQ2 direction control mode for port 2. Set to Automatic by default.
DIQ1 mode DIQ1 direction control mode for port 1. Set to Automatic by default.
DIQ2 direction DIQ2 direction. Set to input by default.
DIQ1 direction DIQ1 direction. Set to input by default.
ENABLE2 mode ENABLE2 direction control mode. Set to Automatic by default.
ENABLE1 mode ENABLE1 direction control mode. Set to Automatic by default.
ENABLE2 direction ENABLE2 direction. Set to input by default.
ENABLE1 direction ENABLE1 direction. Set to input by default.
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7.17 TxTSP
The Tx_TSP tab controls the digital blocks of TxTSPA and TxTSPB modules.
Figure 42 GUI TxTSP tab
Table 19 GUI TxTSP control description
Enable TxTSP Enables TxTSP modules enable. Enabled by default.
CMIX gain control. Control range from -6 dB to +6d B. Step size 6 dB. Set to 0 dB by
CMIX_GAIN
default.
CMIX Spectrum control Spectrum control of CMIX. By default set to downconvert.
Start BIST Starts TxTSP built-in self-test. Keep it at 1 one at least three clock cycles.
Bypass
CMIX Bypass CMIX module when selected.
GFIR3 Bypass GFIR3 module when selected.
Gain correction Bypass Gain correction module when selected.
ISINC Bypass ISINC module when selected.
DC Correction Bypass DC correction module when selected.
Phase correction Bypass Phase correction module when selected.
GFIR1
Length Set GFIR parameter I. Control range from 0 to 7.
Clock Division Ration Sets GFIR filter clock division ration. Control range from 0 to 255.
Coefficients Sets/Load GFIR filters coefficients. By default all set to 0.
GFIR2
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GFIR3
DC Corrector
DC ch. I Sets DC corrector value to channel I. Control range from -128 to 128. By default 0.
DC ch. Q Sets DC corrector value to channel Q. Control range from -128 to 128. By default 0.
IQ Corrector
Gain ch. Q Sets Gain corrector value to channel Q. Control range from 0 to 2047. By default 2047.
Gain ch. I Sets Gain corrector value to channel I. Control range from 0 to 2047. By default 2047.
Phase corrector Sets Phase corrector value. Control range from 0 to 2047. By default 0.
Interpolation
HBI ratio Sets HBI interpolation ratio. Possible control values 2, 4, 8, 16, 32 and bypass. By
default bypassed.
TSG
Swap I and Q signal Swap IQ signals at test signal generator's output. By default not selected.
TSGFCW Select frequency generated by test NCO. By default TSG frequency set to the TSP clock
divided by 8.
TSGMODE Select test signal generator mode: NCO or DC. By default NCO is selected.
Input Source Select input source to TSP: LML output or TSG. By default LML output is selected.
TSGC TSG full scale control: 0 dB or -6 dB. By default set to -6 dB.
Load DC to I Load TSG DC I register with value from DC_REG (hex) box.
Load ED to Q Load TSG DC Q register with value from DC_REG (hex) box.
NCO
Mode Selects the CW or PHO (Phase offset) mode for NCO.
NCO bits to dither Selects number of bits for NCO dithering.
FCW(MHz) Type wanted NCO frequency.
Set reference frequency Set reference frequency for NCO. The frequency the same as TSP block.
Upload NCO Program NCO
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7.18 RxTSP
The Rx_TSP tab controls the digital blocks of RxTSPA and RxTSPB modules. A picture of the
tab is shown in Figure 43. A description of each function available in this tab is shown below in
Table 20.
Figure 43 GUI RxTSP tab
Table 20 GUI RxTSP control description

Enable RxTSP Enables TxRSP modules enable. Enabled by default.
CMIX gain control. Control range from -6 dB to +6 dB. Step size 6 dB. Set to 0 dB by
CMIX_GAIN
default.
CMIX Spectrum control Spectrum control of CMIX. By default set to downconvert.
Start BIST Starts RxTSP built-in self-test. Keep it at 1 one for at least three clock cycles
Bypass
CMIX Bypass CMIX module when selected.
Gain correction Bypass Gain correction module when selected.
AGC Bypass AGC module when selected.
DC Correction Bypass DC corrector module when selected.
Phase correction Bypass Phase corrector module when selected.
GFIR1
GFIR2
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GFIR3
DC Corrector
Numbers of samples Select the number of samples to average for Automatic DC corrector.
IQ Corrector
Gain ch. Q Sets Gain corrector value to channel Q. Control range from 0 to 2047. By default 2047.
Gain ch. I Sets Gain corrector value to channel I. Control range from 0 to 2047. By default 2047.
Phase corrector Sets Phase corrector value. Control range from 0 to 2047. By default 0.
Decimation
HBD ratio Sets HBD interpolation ratio. Possible control values 2, 4, 8, 16, 32 and bypass. By
default bypassed.
TSG
Swap I and Q signal Swap IQ signals at test signal generator's output. By default not selected.
TSGFCW Select frequency generated by test NCO. By default TSG frequency set to the TSP clock
divided by 8.
TSGMODE Select test signal generator mode: NCO or DC. By default NCO is selected.
Input Source Select input source to TSP: ADC input or TSG. By default LML output is selected.
TSGC TSG full scale control: 0 dB or -6 dB. By default set to -6 dB.
Load DC to I Load TSG DC I register with value from DC_REG (hex) box.
Load ED to Q Load TSG DC Q register with value from DC_REG (hex) box.
NCO
Mode Selects the CW or PHO (Phase offset) mode for NCO.
NCO bits to dither Selects number of bits for NCO dithering.
FCW(MHz) Type wanted NCO frequency.
PHO Type wanted PHO frequency.
Set reference frequency Set reference frequency for NCO. The frequency is the same as the TSP block.
Upload NCO Program NCO
AGC
AGC Mode Selects the AGC mode: Bypass, AGC, RSSI mode.
AGC loop gain Selects AGC loop gain.
AGC Average window AGC averaging window size is 2(AGC_AVG + 7).
size
Desired output level Selects desired output signal level
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7.19 CDS
The Clock Distribution System (CDS) controls are described in this this chapter.
Figure 44 GUI CDS tab
Table 21 GUI CDS control description

Clock inversion
TX TSPB TX TSP B channel clock inversion controls. By default clock is not inverted.
TX TSPA TX TSP A channel clock inversion controls. By default clock is not inverted.
RX TSPB RX TSP B channel clock inversion controls. By default clock is not inverted.
RX TSPA RX TSP A channel clock inversion controls. By default clock is not inverted.
TX LMLB TX LML interface B channel clock inversion control. By default clock is not inverted.
TX LMLA TX LML interface A channel clock inversion control. By default clock is not inverted.
RX LMLB RX LML interface B channel clock inversion control. By default clock is not inverted.
RX LMLA RX LML interface A channel clock inversion control. By default clock is not inverted.
MCKL2 MCLK2 clock inversion control. By default clock is not inverted.
MCKL1 MCLK1 clock inversion control. By default clock is not inverted.
Clock delay
MCLK2 clock delays. Clock can be delayed by 400 ps, 500 ps, 600 ps and 700 ps. By
MCLK2
default clock delayed 400 ps.
MCLK1 clock delays. Clock can be delayed by 400 ps, 500 ps, 600 ps and 700 ps. By
MCLK1
TX TSP B clock delays. Clock can be delayed by 400 ps, 500 ps, 600 ps and 700 ps. By
TX TSP B
TX TSP A clock delays. Clock can be delayed by 400 ps, 500 ps, 600 ps and 700 ps. By
TX TSP A
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RX TSP B clock delay. Clock can be delayed by 200 ps, 500 ps, 800 ps and 1100 ps. By
RX TSP B
RX TSP A clock delay. Clock can be delayed by 200 ps, 500 ps, 800 ps and 1100 ps. By
RX TSP A
TX LML B clock delay. Clock can be delayed by 400 ps, 500 ps, 600 ps and 700 ps. By
TX LML B
TX LML A clock delay. Clock can be delayed by 400 ps, 500 ps, 600 ps and 700 ps. By
TX LML A
RX LML B clock delay. Clock can be delayed by 200 ps, 500 ps, 800 ps and 1100 ps. By
RX LML B
RX LML A clock delay. Clock can be delayed by 200 ps, 500 ps, 800 ps and 1100 ps. By
RX LML A
7.20 BIST
The Build-In Self-Test (BIST) modules for SXT, SXR and CGEN controls are described in this
chapter.
Figure 45 GUI BIST tab
The BIST modules are used for the test proposes only. There is one test vector generator which
supplies the test vectors for CGEN, SXT and SXR modules. After pressing the ‘Read BIST’
button the test results (test vector signature) will be displayed for the selected block.
Table 22 GUI BIST control description

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BIST
Enable CGEN BIST Enables CGEN BIST. Disabled by default.
Enable receiver BIST Enables SXR BIST. Disabled by default.
Enable transmitter Enables SXT BIST. Disabled by default.
BIST
Start delta sigma Enables delta sigma BIST. Disabled by default.
BIST
7.21 SPI
This is used for test proposes only. Using this tab, every SPI register can be programmed using
the register map description. Every SPI register of the LMS7002M can be read back. A picture of
the tab is shown in Figure 46. A description of each function available in this tab is shown below
in Table 24.
Figure 46 GUI SPI tab
Table 23 GUI SPI control description

Write
Address (Hex) Register address in HEX format.
Value (Hex) Register value in HEX format.
Status Previously executed command status.
Read
Address (Hex) Register address in HEX format.
Read Values (Hex) Register value in HEX format.
Status Previously executed command status.
Batch Read Executes multiple reads from selected register. The read number selected by ReadCount.
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ReadCount Set read back function count number.

Write Tester Writes and read to selected register 100 times.
Triple check data When selected repeats function three times.
Save to file If selected save function results to txt file to selected location.
Switch channel Selects read/write channel.
Register Test
Test data (Hex) Register value in HEX format.
batch write and read Write/read registers to selected interval.
Save to file If selected save function results to txt file to selected location.
Start addr(hex) Start register read/write interval.
End addr(hex) End register read/write interval.
TOP
Lime Light LimeLight interval [0x0020 : 0x002e]
Bias BIAS interval [0x0083 : 0x0084]
CGEN CGEN interval [0x0086 : 0x008d]
BIST BIST interval [0x00a8 : 0x00ad]
AFE AFE interval [0x0082 : 0x0084]
XBUF XBUF interval [0x0085 : 0x0086]
LDO LDO interval [0x0092 : 0x00a7]
CDS CDS interval [0x00ad : 0x00b0]
TRX
TRF TRF interval [0x0100 : 0x0104]
RFE RFE interval [0x010c : 0x0114]
SXR/SXT SXR/SXT interval [0x011c : 0x0124]
TBB TBB interval [0x0105 : 0x010b]
RBB RBB interval [0x0115 : 0x011b]
Tx
TxTSP TxTSP interval [0x0200 : 0x023f]
TxNCO TxNCO interval [0x0240 : 0x027f]
Rx
RxTSP RxTSP interval [0x0400 : 0x043f]
RxNCO RxNCO interval [0x0440 : 0x047f]
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7.22 Buffers EVB7v2

This tab controls on board buffer directions for the LMS7002M digital interface. As well,
LOGIC_RESET pin and CORE_LDO _EN pin are controlled from this tab.
Figure 47 GUI Buffers EVBv2 tab
Table 24 GUI SPI control description

Buffers
DIO_DIR_CTRL1 On board buffers direction control for Port 1. If selected, Port 1 is receiver.
DIO_DIR_CTRL2 On board buffers direction control for Port 2. If selected, Port 2 is receiver.
DIO_BUFF_OE If selected, set onboard buffers to Hi-Impedance state.
IQSEL1_DIR On board buffers IQSEL pin direction control for Port 1. If selected, Port 1 is receiver.
IQSEL2_DIR On board buffers IQSEL pin direction control for Port 2. If selected, Port 2 is receiver.
G_PWR_DWN External enable control signal for the internal LDO’s.
DIG_RST Controls hardware pin logic reset.
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8
Appendix A: Test Equipment Setup
8.1 Introduction
This section lists the recommended test equipment to use with the EVB7. It also provides
detailed setup procedures for the Agilent MXG when used with EVB7. Note the set up procedure
is only required when using the analogue TX inputs of the LMS7002M. This procedure is not
required when the LMS7002M chip is driven digitally by a baseband processor.
8.2 Recommended Test Equipment

The following test equipment is recommended for the testing of EVB7. It is possible to use other
test equipment, but the alternatives may not provide all the necessary features.
 N5182A MXG
o Differential Arbitrary Waveform Generator Option 1EL
 N9020A MXA DC - 6 GHz
o NF personality
o Phase Noise personality
o WCDMA personality
o LTE personality
 Agilent Power Supply 5V
 Agilent 384C Noise Source
o 15 dB ENR
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8.3 Agilent MXG Setup

The front panel of the MXG is shown in Figure 48.
23. Modes
1
2
3
4
24. I/Q
5
Figure 48 Agilent N5181A/82A MXG Front Panel
8.3.1. Setting Common Mode Voltage
To apply 0.3 V common mode offset voltage to the IQ outputs:
1. Press ‘IQ’ button (24)

2. Press ‘IQ offsets (on/off)’ softkey (3. softkey 4)
3. Press ‘external output adjustments’ softkey (3. softkey 4)
4. Press ‘Common Mode I/Q offset’ softkey (3. softkey 2)
5. type 0.3 on number pad (4), press ‘V’ softkey (3. softkey 1)
6. 0.3 V should appear on the display next to the ‘Common Mode I/Q offset’ softkey
7. Press return
i. Check text next to ‘I/Q Adjustments’ softkey (3. softkey 1) highlights ‘off/on’
ii. If not press ‘I/Q Adjustments’ softkey (3. softkey 1), highlighted section should
alternate between on and off when pressed.
iii. press return
iv. Check text next to ‘I/Q’ softkey (3. softkey 1) highlights ‘off/on’
v. If not press ‘I/Q’ softkey (3. softkey 1), highlighted section should alternate
between on and off when pressed.
There should now be a 0.3 V common mode voltage on the differential IQ connections on the
signal generator. This can be verified by measuring the DC level of each of the 4 differential I/Q
lines with a multimeter.
Note: Very small DC offset levels in the transmit IQ path can result in LO breakthrough levels
changing in the transmit chain. To eliminate or minimize this effect the following practices
should be followed:
 The IQ cables should be of equal length.
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 Once I/Q gain and phase calibration is completed, connections should not be modified.
 Cables and connections should not be moved once the I/Q gain and phase calibration is
completed.
8.3.2. Enabling the Arbitrary Waveform Generator
The arbitrary waveform generator will run test vectors which are downloaded to it. These can be
generated either with Agilent’s “Signal Studio” program or can be generated independently via
“Matlab” or C.
Lime has a number of test vector files which are used for test and calibration of the LMS7002M
as follows:
 DC.wfm – Differential DC tone for TX CW testing (clock 52 MHz).

 onetone1.wfm - single tone at 1 MHz offset for sideband suppression calibration/test
(clock 52 MHz).
 twotone.wfm - two tone signal for linearity testing for MXG and LMS7002M use
MXG IQ scaling factor of 30% (clock 52 MHz).
 wcdma31.wfm - TM2 WCDMA signal - use MXG IQ scaling factor of 30%
(clock=15.36 MHz).
 EDGE3.wfm - GSM EDGE modulated test signal - (clock=13 MHz).
To download files to the signal generator follow the process described in section 9.3.3.
To apply the correct file
1. Press ‘Mode’ button (23)

2. Press ‘Dual Arb’ softkey (3. softkey 1)
3. Press ‘Select waveform’ softkey (3. softkey 2)
4. Use up/down arrows (5) or spin knob (18) to select the wanted waveform from list.
5. Press ‘Select waveform’ softkey (3. softkey 1)
6. The name of the selected waveform should now be present in the display window
7. The soft key list should have moved up one level back to ‘Arb’
8. Now change the Arb clock frequency
9. Press ‘Arb setup’ softkey (3. softkey 3)
10. Press ‘Arb sample clock’ softkey (3. softkey 1)
11. Type in the required frequency on the number pad eg for 13 MHz type ‘13’ and press
‘MHz’ softkey (3. softkey 2)
12. The sample clock frequency should now be displayed on the screen.
13. Now scale the waveform data if necessary
14. Go to the ‘Arb’ softkey menu
a. Either press the ‘return’ button from the ‘Arb setup’ menu or
b. Press the ‘Mode’ button then ‘Dual Arb softkey (3. softkey 1)
15. Press the ‘More’ button (21)
16. Press the ‘Waveform Utilities’ softkey (3. softkey 2)
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17. Use the up/down arrows (5) or spin wheel to highlight the wanted waveform from the list.
18. Press the ‘scale waveform data’ softkey (3. softkey 2)
19. Type in the required scaling factor e.g.25%, type ’25’ on number pad and press ‘%’
softkey (3. softkey 1).
Note – even if the text next to ‘scaling’ softkey already states 25% (for example) this
does not mean it has been applied to the waveform, still follow the process.
20. Press the ‘Apply to waveform’ softkey (3. softkey 4)
21. The progress bar will show on screen, soft menu will return to level up (Arb utilities).
22. Now return to the main ‘Arb’ Menu
a. Press the ‘return’ button twice or
b. Press the ‘Mode’ button then ‘Dual Arb softkey (3. softkey 1)
23. Check that Arb in enabled
a.‘Arb on/off’ softkey (3. softkey 1) the text should have on highlighted ‘Off / On’
b. If not, press the ‘Arb on/off’ softkey (3. softkey 1) to toggle between on and off.
24. The modulation can be also be toggled on and off by the ‘Mod on/off’ button (just above
the RF o/p connector). This must also be on – the green LED must be illuminated.
a. Press the ‘Mod on/off’ button to toggle the modulation on and off.
Note – The Mod on/off button turns the modulation on to the RF output and IQ output
simultaneously. The RF does not need to be on for the IQ outputs to work
8.3.3. Downloading *.wfm Files to the Signal Generator
The following process should allow you to download files to the Agilent signal generator. The
same process works for MXG and ESG.
This can be done via a network, however these instructions assume a direct connection between a
PC running Windows 7 and the signal generator.
 Connect a cable between the PC network port and the signal generator LAN port.
 Check that the LEDs are illuminated on both ends to indicate that the HW is connected.
 Find the IP address of the Signal generator
o Press the ‘Utility’ button
o Press the ‘I/O config’ softkey (3. softkey 1)
o Press the ‘LAN setup’ softkey (3. softkey 2)
o The IP address should now be displayed on the screen
o e.g.
IP Address : 192.168.2.92
Subnet Mask : 255.255.255.0
 Open a Command Prompt window on your PC
o Start
o In ‘Search programs and files’ window, type ‘cmd’
o The Command prompt window will pop-up
o Alternatively, it is located at C:\Windows\System32\
o Linux users can use a terminal session with the same commands.
 To check the connection to the signal generator attempt to ‘ping’ it
o Type ‘ping 192.168.2.92’ (or use your sig gen IP address)
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 A successful ping result should be returned as shown in

 Figure 49.
Figure 49 CMD window showing successful ping
To send wfm files to the signal generator the following procedure should be followed.
 Ensure that the wfm files are in a known directory e.g.
‘C:\Lime\Waveform’.
 In the ‘Command Prompt’ window set the directory to the one where the wfm files are
located using the “CD” command.
 Use FTP to send files to the signal generator.
 Type ‘ftp 192.168.2.92’ as shown in Figure 50.
Figure 50 CMD window with ftp connection
 If you are correctly connected, then the above should be returned.

 Press ‘return’ twice (for user name and password – none needed)
 Type ‘cd bbg1’
 Type ‘cd waveform’
 Type ‘bin’
 Type ‘put wcdma31.wfm’
 The applied command copies files to the sig gen – repeat ‘put’ command for all files
needed as shown in Figure 51.
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Figure 51 CMD window ftp file transfer
 To exit the ftp program type “bye”.

 To close the ‘Command Prompt’ window type exit.
 The wfm files should now be visible in the list of ARB files.
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NOTICE OF DISCLAMER
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection
and use of Lime Microsystems products. To the maximum extent permitted by applicable law:
(1) Materials are made available “AS IS” and with all faults, Lime Microsystems hereby
DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR
STATUTORY, INCLUDING BUT NOT LIMITED TO WARRRANTIES OF
MERCHANTABILITY, NON-INFRIGEMENT, OR FITNESS FOR ANY PARTICULAR
PURPOSE; and (2) Lime Microsystems shall not be liable (whether in contract or tort, including
negligence, or under any other theory of liability) for any loss or damage of any kind or nature
related to, arising under, or in connection with, the Materials (including your use of the
Materials), including for any direct, indirect, special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any
action brought by a third party) even if such damage or loss was reasonably foreseeable or Lime
Microsystems had been advised of the possibility of the same. Lime Microsystems assumes no
obligation to correct any errors contained in the Materials, or to advise you of any corrections or
update. You may not reproduce, modify, distribute, or publicly display the Materials without
prior written consent. Certain products are subject to the terms and conditions of the Limited
Warranties. Lime Microsystems products are not designed or intended to be fail-safe or for use in
any application requiring fail-safe performance; you assume sole risk and liability for use of
Lime Microsystems products in Critical Applications.
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LMS7002M Quick Starter Manual for EVB7 kit

Tel: +44 (0) 1483 685 063

LMS7002M Quick Start Manual

The information contained in this document is subject to change without prior

Version: 2.2 Last modified: 29/09/2014

Date Version Description of Revisions

7.1 Control LMS7002M – Software Description ...................................................................... 38

Figure 1 Development System Content ........................................................................................... 8

Figure 47 GUI SPI tab .................................................................................................................. 72

Figure 1 Development System Content

Complete development kit content consists of:

Figure 2 Board block diagram

4.1 Introduction to installing the software

A simple demonstration of the “LMS7002M Control Software” is given in Section 5. A detailed

4.2 Downloading the Software

4.3 Windows USB Setup

1. Connect EVB7 board to your PC via the USB cable.

2. Go to Control Panel > System > Device Manager

Figure 3 Device Manager content

4. When a new window pops-up press Update driver (Figure 4)

Figure 4 Device properties

Figure 5 Update Driver Wizard.

Figure 6 Hardware wizard. Install driver manually

4.4 Determining Serial Port

1. Go to Control Panel > System > Device Manager

Figure 7 Check for new communication port

4.5 Linux Setup

4.6 Starting Control LMS7002M Software

Figure 8 GUI communication settings.

Figure 9 GUI detected device and firmware version

5.1 Introduction to using the EVB7

5.2 Transmitter Setup and Basic Testing

Figure 10 Tx Test Setup

5.2.1. SXT/SXR tab setup

1. Select the B/SXT in the configuration channels window to control TxPLL

See Figure 11 below to check selections.

Figure 11 SXT register setup procedure

5.2.2. TRF tab setup

5.2.3. TBB tab setup

1. Select the A/SXR to control channel A.

See Figure 12 below to check selections.

Figure 12 TBB register setup procedure

5.3 Testing the TX Output

Figure 13 Basic TX testing using DC offset resulting in LO leakage

Figure 14 Basic TX testing using WCDMA modulation

5.3.1. TX Basic Operation Checks

5.4 Receiver Setup and Basic Testing

Figure 15 Rx Test Setup

5.4.1. SXT/SXR tab setup

6. Select the A/SXR in the configuration channels window to control RxPLL

See Figure 16 below to check selections.

Figure 16 SXR register setup procedure

5.4.2. RFE tab setup

1. Enable LNARFE, RXFE TIA and RFFE Quadrature LO generator.

See Figure 17 below to check selections.

Figure 17 SXR register setup procedure

5.4.3. RBB tab setup