HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611

DESCRIPTION
The 6N137, HCPL-2601/2611 single-channel and HCPL-2630/2631 dual-channel
optocouplers consist of a 850 nm AlGaAS LED, optically coupled to a very high
speed integrated photodetector logic gate with a strobable output. This output 8
features an open collector, thereby permitting wired OR outputs. The coupled
parameters are guaranteed over the temperature range of -40°C to +85°C. A 1
maximum input signal of 5 mA will provide a minimum output sink current of 13
mA (fan out of 8).
An internal noise shield provides superior common mode rejection of typically 10
kV/µs. The HCPL- 2601 and HCPL- 2631 has a minimum CMR of 5 kV/µs.
The HCPL-2611 has a minimum CMR of 10 kV/µs.
8
8
1
FEATURES 1
• Very high speed-10 MBit/s
• Superior CMR-10 kV/µs
• Double working voltage-480V
• Fan-out of 8 over -40°C to +85°C N/C 1 8 VCC + 1 8 VCC

• Logic gate output VF1

• Strobable output + 2 7 VE _ 2 7 V01
• Wired OR-open collector VF
• U.L. recognized (File # E90700) _ _
3 6 VO 3 6 V02

V
F2

N/C 4 5 GND + 4 5 GND

APPLICATIONS
• Ground loop elimination
• LSTTL to TTL, LSTTL or 5-volt CMOS
• Line receiver, data transmission 6N137 HCPL-2630
• Data multiplexing HCPL-2601 HCPL-2631
• Switching power supplies HCPL-2611
• Pulse transformer replacement
• Computer-peripheral interface

TRUTH TABLE
(Positive Logic)

Input Enable Output

H H L
L H H
H L H
L L H
H NC L
L NC H

A 0.1 µF bypass capacitor must be connected between pins 8 and 5.

(See note 1)

 2001 Fairchild Semiconductor Corporation

DS300202 7/9/01 1 OF 11 www.fairchildsemi.com
 HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS

SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611

ABSOLUTE MAXIMUM RATINGS (No derating required up to 85°C)

Parameter Symbol Value Units
Storage Temperature TSTG -55 to +125 °C
Operating Temperature TOPR -40 to +85 °C
Lead Solder Temperature TSOL 260 for 10 sec °C
EMITTER
50
DC/Average Forward Single channel IF mA
Input Current Dual channel (Each channel) 30
Enable Input Voltage Single channel
VE 5.5 V
Not to exceed VCC by more than 500 mV
Reverse Input Voltage Each channel VR 5.0 V
Power Dissipation Single channel 100
PI mW
Dual channel (Each channel) 45
DETECTOR
VCC
Supply Voltage 7.0 V
(1 minute max)

Output Current Single channel 50

IO mA
Dual channel (Each channel) 50
Output Voltage Each channel VO 7.0 V
Collector Output Single channel 85
PO mW
Power Dissipation Dual channel (Each channel) 60

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Max Units
Input Current, Low Level IFL 0 250 µA
Input Current, High Level IFH *6.3 15 mA
Supply Voltage, Output VCC 4.5 5.5 V
Enable Voltage, Low Level VEL 0 0.8 V
Enable Voltage, High Level VEH 2.0 VCC V
Low Level Supply Current TA -40 +85 °C
Fan Out (TTL load) N 8
* 6.3 mA is a guard banded value which allows for at least 20 % CTR degradation. Initial input current threshold value is 5.0 mA or less

www.fairchildsemi.com 2 OF 11 7/9/01 DS300202

 HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS

SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611

ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.)

INDIVIDUAL COMPONENT CHARACTERISTICS

Parameter Test Conditions Symbol Min Typ** Max Unit
EMITTER (IF = 10 mA) 1.8
VF V
Input Forward Voltage TA =25°C 1.4 1.75
Input Reverse Breakdown Voltage (IR = 10 µA) BVR 5.0 V
Input Capacitance (VF = 0, f = 1 MHz) CIN 60 pF
Input Diode Temperature Coefficient (IF = 10 mA) VF/TA -1.4 mV/°C
DETECTOR
7 10
High Level Supply Current Single Channel (VCC = 5.5 V, IF = 0 mA) ICCH mA
Dual Channel (VE = 0.5 V) 10 15
Low Level Supply Current Single Channel (VCC = 5.5 V, IF = 10 mA) 9 13
ICCL mA
Dual Channel (VE = 0.5 V) 14 21
Low Level Enable Current (VCC = 5.5 V, VE = 0.5 V) IEL -0.8 -1.6 mA
High Level Enable Current (VCC = 5.5 V, VE = 2.0 V) IEH -0.6 -1.6 mA
High Level Enable Voltage (VCC = 5.5 V, IF = 10 mA) VEH 2.0 V
Low Level Enable Voltage (VCC = 5.5 V, IF = 10 mA) (Note 3) VEL 0.8 V

SWITCHING CHARACTERISTICS (TA = -40°C to +85°C, VCC = 5 V, IF = 7.5 mA Unless otherwise specified.)
AC Characteristics Test Conditions Symbol Min Typ** Max Unit
Propagation Delay Time (Note 4) (TA =25°C) 20 45 75
TPLH ns
to Output High Level (RL = 350 1, CL = 15 pF) (Fig. 12) 100
Propagation Delay Time (Note 5) (TA =25°C) 25 45 75
TPHL ns
to Output Low Level (RL = 350 1, CL = 15 pF) (Fig. 12) 100
Pulse Width Distortion (RL = 350 1, CL = 15 pF) (Fig. 12) TPHL-TPLH 3 35 ns
(RL = 350 1, CL = 15 pF)
Output Rise Time (10-90%) tr 50 ns
(Note 6) (Fig. 12)
(RL = 350 1, CL = 15 pF)
Output Fall Time (90-10%) tf 12 ns
(Note 7) (Fig. 12)
Enable Propagation Delay Time (IF = 7.5 mA, VEH = 3.5 V)
to Output High Level (RL = 350 1, CL = 15 pF) (Note 8) (Fig. 13) tELH 20 ns
Enable Propagation Delay Time (IF = 7.5 mA, VEH = 3.5 V)
to Output Low Level (RL = 350 1, CL = 15 pF) (Note 9) (Fig. 13) tEHL 20 ns
Common Mode Transient Immunity (TA =25°C) VCM = 50 V, (Peak)
(at Output High Level) (IF = 0 mA, VOH (Min.) = 2.0 V)
6N137, HCPL-2630 (RL = 350 1) (Note 10) CMH 10,000 V/µs
HCPL-2601, HCPL-2631 (Fig. 14) 5000 10,000
HCPL-2611 VCM = 400 V 10,000 15,000
(RL = 350 1) (IF = 7.5 mA, VOL (Max.) = 0.8 V)
10,000
Common Mode 6N137, HCPL-2630 VCM = 50 V (Peak)
CML V/µs
Transient Immunity HCPL-2601, HCPL-2631 (TA =25°C)
5000 10,000
(at Output Low Level) (Note 11) (Fig. 14)
HCPL-2611 (TA =25°C) VCM = 400 V 10,000 15,000

DS300202 7/9/01 3 OF 11 www.fairchildsemi.com

 HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS

SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611

TRANSFER CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.)

DC Characteristics Test Conditions Symbol Min Typ** Max Unit
High Level Output Current (VCC = 5.5 V, VO = 5.5 V)
IOH 100 µA
(IF = 250 µA, VE = 2.0 V) (Note 2)
Low Level Output Current (VCC = 5.5 V, IF = 5 mA)
VOL .35 0.6 V
(VE = 2.0 V, ICL = 13 mA) (Note 2)
(VCC = 5.5 V, VO = 0.6 V,
Input Threshold Current IFT 3 5 mA
VE = 2.0 V, IOL = 13 mA)

ISOLATION CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.)

Characteristics Test Conditions Symbol Min Typ** Max Unit
Input-Output (Relative humidity = 45%)
Insulation Leakage Current (TA = 25°C, t = 5 s)
II-O 1.0* µA
(VI-O = 3000 VDC)
(Note 12)
Withstand Insulation Test Voltage (RH < 50%, TA = 25°C)
VISO 2500 VRMS
(Note 12) ( t = 1 min.)
Resistance (Input to Output) (VI-O = 500 V) (Note 12) RI-O 1012 1
Capacitance (Input to Output) (f = 1 MHz) (Note 12) CI-O 0.6 pF
** All typical values are at VCC = 5 V, TA = 25°C

NOTES

1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid tantalum
capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins
of each device.
2. Each channel.
3. Enable Input - No pull up resistor required as the device has an internal pull up resistor.
4. tPLH - Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5 V
level on the LOW to HIGH transition of the output voltage pulse.
5. tPHL - Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5 V
level on the HIGH to LOW transition of the output voltage pulse.
6. tr - Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. tf - Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. tELH - Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input voltage pulse
to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
9. tEHL - Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input voltage pulse
to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
10. CMH - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state
(i.e., VOUT > 2.0 V). Measured in volts per microsecond (V/µs).
11. CML - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low output state
(i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/µs).
12. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.

www.fairchildsemi.com 4 OF 11 7/9/01 DS300202

 HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS

SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611

TYPICAL PERFORMANCE CURVES

Fig.1 Low Level Output Voltage vs. Ambient Temperature Fig. 2 Input Diode Forward Voltage
vs. Forward Current
0.8
Conditions:
IF = 5 mA 30
0.7
VE = 2 V 16
IOL = 16 mA
VCC = 5.5V 10
VOL-Low Level Output Voltage (V)

0.6
IOL = 12.8 mA

IF = Forward Current (mA)

0.5 1

0.4
0.1
0.3

0.2 0.01
IOL = 9.6 mA
0.1
IOL = 6.4 mA
0.001
0.0
-40 -20 0 20 40 60 80 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6

TA - Ambient Temperature (˚C) VF - Forward Voltage (V)

Fig.3 Switching Time vs. Forward Current Fig. 4 Low Level Output Current
vs. Ambient Temperature
120 50
VCC = 5 V IF = 15 mA
IOL - Low Level Output Current (mA)

100 45
IF = 10 mA
TP - Propagation Delay (ns)

80 40

RL = 4 k1 (TPLH) IF = 5 mA
60 35

40 30
Conditions:
VCC = 5 V
VE = 2 V
20 RL = 1 k 1 (TPLH) 25 VOL = 0.6 V
RL = 1 k1
RL = 4 k1 (TPHL)
RL = 350 1 (TPLH) RL = 350 k1
0 20
5 7 9 11 13 15 -40 -20 0 20 40 60 80

IF - Forward Current (mA) TA - Ambient Temperature (˚C)

Fig. 5 Input Threshold Current Fig. 6 Output Voltage vs. Input Forward Current
vs. Ambient Temperature
4 6

Conditions:
VCC = 5.0 V
VO = 0.6 V RL = 350 1 5
RL = 350 1
IFT - Input Threshold Current (mA)

VO - Output Voltage (V)

3 4

RL =4k 1 RL = 1k 1
3

2 2

1
RL = 1k 1
RL = 4k 1
1 0
-40 -20 0 20 40 60 80 0 1 2 3 4 5 6

TA - Ambient Temperature (˚C) IF - Forward Current (mA)

DS300202 7/9/01 5 OF 11 www.fairchildsemi.com

 HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS

SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611

Fig. 7 Pulse Width Distortion vs. Temperature Fig. 8 Rise and Fall Time vs. Temperature

80 600

500
60

Tr/Tf - Rise and Fall Time (ns)

Conditions:
PWD - Pulse Width Distortion (ns)

Conditions:
IF = 7.5 mA IF = 7.5 mA
400
VCC = 5 V RL = 4 k 1 VCC = 5 V
RL = 4 k1(tr)
40
300
RL = 1 k1(tr)
RL = 1 k 1
RL = 350 1
200
20 RL = 350 1(tr)

100

0
0 RL = 1 k 1
]
RL = 4 k 1 (tf)
RL = 350 1
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100

TA - Temperature (˚C) TA - Temperature (˚C)

Fig. 9 Enable Propagation Delay vs. Temperature Fig. 10 Switching Time vs. Temperature

120 120
RL = 4 k 1(TELH)

100
100
TP-Propagation Delay (ns)
TE-Enable Propagation Delay (ns)

80
80
RL = 4 k 1TPLH
60 RL = 1 k 1TPLH
RL = 1 k 1(TELH)
RL = 350 1TPLH
RL = 350 1(TELH) 60
40

40
20

0
RL = 350 1
RL = 1 k 1
RL = 4 k 1 ] (TEHL)

20
RL = 1 k 1
RL = 4 k 1
RL = 350 1
] TPHL

-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100

TA-Temperature (˚C) TA-Temperature (˚C)

Fig. 11 High Level Output Current

vs. Temperature
20

Conditions:
VCC = 5.5 V
IOH-High Level Output Current (µA)

VO = 5.5 V
15 VE = 2.0 V
IF = 250 µA

10

0
-60 -40 -20 0 20 40 60 80 100

TA-Temperature (˚C)

www.fairchildsemi.com 6 OF 11 7/9/01 DS300202

 HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS

SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611

Pulse
Generator
tr = 5ns
Z O = 50 1 +5V

I F = 7.5 mA

VCC Input I F = 3.75 mA

1 8 (I F)
t PHL tPLH

.1 Ef Output
2 7 RL
(VO )
bypass
1.5 V
Input Output
Monitor
3 6 (VO ) 90%
Output
(I F) CL
(VO )
10%
471 4 GND 5
tf tr

Fig. 12 Test Circuit and Waveforms for tPLH, tPHL, tr and tf.

Pulse
Generator Input
tr = 5ns Monitor
Z O = 50 1 (V E)

+5V

3.0 V
VCC Input
(VE ) 1.5 V
1 8
t EHL tELH
7.5 mA
Output
2 7 .1 Ef
RL
(VO )
bypass 1.5 V
Output
3 6 (VO )
CL

4 5
GND

Fig. 13 Test Circuit tEHL and tELH.

DS300202 7/9/01 7 OF 11 www.fairchildsemi.com

 HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS

SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611

VCC
1 8 +5V

IF
A 2 7 .1 Ef 350 1
bypass
B
Output
VFF 3 6 (VO)

4 5
GND

VCM

Pulse Gen

Peak

VCM
0V

5V CM H
Switching Pos. (A), I F= 0
VO
VO (Min)

VO (Max)

Switching Pos. (B), I F= 7.5 mA

VO
0.5 V CM L

Fig. 14 Test Circuit Common Mode Transient Immunity

www.fairchildsemi.com 8 OF 11 7/9/01 DS300202

 HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS

SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611

Package Dimensions (Through Hole) Package Dimensions (Surface Mount)

0.390 (9.91)
0.370 (9.40)

PIN 1 PIN 1
4 3 2 1
ID. ID.
4 3 2 1

0.270 (6.86)
0.270 (6.86)
0.250 (6.35)
0.250 (6.35)

5 6 7 8

5 6 7 8
0.390 (9.91)
0.370 (9.40)
SEATING PLANE

0.070 (1.78) 0.070 (1.78) 0.300 (7.62)

0.045 (1.14) 0.045 (1.14) TYP

0.200 (5.08)
0.140 (3.55) 0.020 (0.51)
MIN 0.016 (0.41)
0.008 (0.20)
0.020 (0.51) MIN

0.154 (3.90 )
0.120 (3.05)
0.045 [1.14]
0.022 (0.56)
0.022 (0.56) 0.016 (0.41) 0.315 (8.00)
0.016 (0.41) 15° MAX
0.016 (0.40) MIN
0.008 (0.20) 0.100 (2.54)
0.405 (10.30)
0.100 (2.54) TYP 0.300 (7.62) TYP
MIN
TYP

Lead Coplanarity : 0.004 (0.10) MAX

Package Dimensions (0.4”Lead Spacing)

4 3 2 1 PIN 1
ID.

0.270 (6.86)
0.250 (6.35)

5 6 7 8

0.390 (9.91)
0.370 (9.40)
SEATING PLANE

0.070 (1.78)
0.045 (1.14)

0.200 (5.08)
0.140 (3.55)

0.004 (0.10) MIN

NOTE
0.154 (3.90) All dimensions are in inches (millimeters)
0.120 (3.05)

0.022 (0.56)
0° to15°
0.016 (0.41)
0.016 (0.40)
0.008 (0.20)
0.100 (2.54) TYP 0.400 (10.16)
TYP

DS300202 7/9/01 9 OF 11 www.fairchildsemi.com

 HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS

SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611

ORDERING INFORMATION
Order
Entry
Option Identifier Description
S .S Surface Mount Lead Bend
SD .SD Surface Mount; Tape and reel
W .W 0.4” Lead Spacing

QT Carrier Tape Specifications (“D” Taping Orientation)

12.0 ± 0.1
4.90 ± 0.20
4.0 ± 0.1 Ø1.55 ± 0.05
0.30 ± 0.05 4.0 ± 0.1
1.75 ± 0.10

7.5 ± 0.1

13.2 ± 0.2 16.0 ± 0.3

10.30 ± 0.20

0.1 MAX 10.30 ± 0.20 Ø1.6 ± 0.1

User Direction of Feed

www.fairchildsemi.com 10 OF 11 7/9/01 DS300202

 HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS

SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HERE-
IN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component in any component of a life support
systems which, (a) are intended for surgical device or system whose failure to perform can be
implant into the body,or (b) support or sustain life, reasonably expected to cause the failure of the life
and (c) whose failure to perform when properly support device or system, or to affect its safety or
used in accordance with instructions for use provided effectiveness.
in labeling, can be reasonably expected to result in a
significant injury of the user.

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