Customer Technology Union: Shenzhen Fly Young Technology Co.,LTD
Customer Technology Union: Shenzhen Fly Young Technology Co.,LTD
Customer Technology Union: Shenzhen Fly Young Technology Co.,LTD
样 品 规 格 承 认 书
公司料号:FY07024DI26A30-D
客户名称:
客户 料号 :
日 期: 2014-04-30
Note : The Product and specifications are subject to change without any notice.
Please ask for the latest Product Standards to guarantee the satisfaction of
our product requirements.
Please ask for the latest Product Standards to guarantee the satisfaction of
Contents
1 Revision Record------------------------------------------------ 2
2 Contents---------------------------------------------------------- 3
3 Product Information ---- -------------------- -------------- 4
3. PRODUCT INFORMATION
3.1. Description
FY07024DI26A30-D is a color active matrix LCD module incorporating amorphous
silicon TFT (Thin Film Transistor). It is composed of a color TFT-LCD panel, driver ICs,
FPC and a backlight unit. The 7.0′ display area contains 1024 (RGB) x 600 pixels
3.2. Applications
□UMPC
□Portable DVD
□GPS
□MID
3.3. Features
□High Resolution:1024(RGB) x 600 Dots
□adopting a high aperture ratio
□24 chip LED backlight
□Dot-Inversion
dots
3 Resolution 1024 × 3(RGB) × 600
-
4 Display mode FFS Normally black
mm
5 Dot pitch 0.1506(H) × 0.1432(V)
mm
6 Active area 154.21(H) × 85.92(V)
mm
7 Panel size 163.9 (H) ×97.1(V) ×2.6(T)
-
8 Color Pixel RGB vertical stripe
-
9 Surface treatment Glare type
o’clock
10 View Direction ALL
-
11 Interface MIPI
1 3. 08 ± 0 .5 0 1
27.43±0.50
1
168
15.50±0.10
P0.5*29=14.50±0.07
4 .0 0 ± 0 . 30
2 .1 0 ± 0 . 30
焊盘高度T=0.40MAX
Vf=9~10.6V If=160mA
7.ELECTRICAL CHARACTERISTICS
7.1 Typical operation conditions
ITEM SYMBOL MIN. TYP. MAX. UNIT NOTE
Digital supply voltage DVDD 1.79 1.8 1.89 V
Analog supply voltage AVDD 9.4 9.6 9.8 V
Gate on voltage VGH 17 18 19 V
Gate off voltage VGL -6.6 -6 -5.4 V
Common voltage VCOM 2.85 -- 3.45 V
VIH 0.7*DVDD - DVDD V NOTE1
Logic input voltage
VIL GND - 0.3*DVDD V
[note1] please adjust VCOM to make the flicker lever be minimum
Gate off Power Current IVGL VGL= -6V -- 0.7 1.5 mA Note1
+
TCLK-ZERO
Time to enable Clock Lane receiver line THS-TERM-E - - 38 ns
termination measured from when Dn N
crossVIL,MAX
Minimum time that the HS clock must be TCLK-PRE 8 - - UI
prior to any associated data lane beginning
the transmission from LP to HS mode
Time to drive HS differential state after last TCLK-TRAIL 60 - - ns
payload clock bit of a HS transmission burst
When Clock lane of DSI TX chip always keeps High speed mode, then Clock lane never go back to Low power
mode. If Date lane of TX chip
1 168
A
单层区域
Number of LED -- 24 --
Note 1: There are 1 Groups LED
Note 2: Ta = 25_
Note 3: Brightness to be decreased to 50% of the initial value
V f= 9 ~ 1 0 .6 V If= 1 6 0 m A
11.2 Storage
.Store in an ambient temperature of 5℃ to 45℃,and in a relative humidity
of 40% to 60%. Don’t expose to sunlight or intensive ultraviolet rays
. Storage in a clean environment, free from dust, active gas, and solvent.
. Store in anti-static electricity container.
. Store without any physical load.