A4 and A5)

WPC8765L / WPC8769L Mobile Embedded Controller with SPITM Flash Interface and MC-Compliant CIR Port (Revisions
Product Brief
June 2008
Revision 1.2

WPC8765L / WPC8769L Mobile Embedded Controller with

SPITM Flash Interface and MC-Compliant CIR Port
(Revisions A4 and A5)
General Description Outstanding Features
The Nuvoton WPC8765L and WPC8769L are highly inte- ■ Shared BIOS flash memory
grated embedded controllers (EC) with an embedded RISC ■ Support for SPI flash memories
core and integrated advanced functions. They are targeted
for a wide range of portable applications. ■ Flash page programing support
The WPC8765L/WPC8769L incorporate the CompactRISC® ■ MC-compliant Consumer Infrared (CIR) Port
CR16CPlus core (a high-performance 16-bit RISC proces- ■ High-accuracy, high-speed ADC
sor), on-chip ROM and RAM memories, system support func-
tions and a Flash Interface Unit (FIU) that interfaces directly ■ Up to 88 GPIO ports (including keyboard scanning)
with external SPI flash memory devices. with a variety of wake-up events

System support functions include: watchdog, PWM, timers, ■ 16-bit RISC core, with up to 4 Mbytes of external ad-
interrupt control, General-Purpose I/O (GPIO) with internal dress space, running at up to 25 MHz
keyboard matrix scanning, PS/2® interface, SMBus® inter- ■ 128-pin LQFP package
face, UART, SPI™, high-accuracy analog-to-digital (ADC)
and digital-to-analog (DAC) converters for battery charging,
system control, system health monitoring and analog con-
trols, and a SensorPath™ interface.
The WPC8765L/WPC8769L interface with the host via an
LPC interface.The WPC8765L/WPC8769L are PC01 and
ACPI compliant, and offer a single-chip solution for the most
commonly used notebook PC I/O peripherals.

System Block Diagram

Main Analog Standby Backup Battery
South Bridge VDD VCC VCC VBAT

SPI
Shared Flash 12 x 8 - 18 x 8
Keyboard Matrix

Battery 2 x SMBus 3 x PS2 Keyboard

Panel Touch Pad
Mouse
SPI
Temp Sensor WPC8765L/WPC8769L PWM
3 x Fan
Switch Pad
Tacho
and LEDs

Charger A/D and D/A

Brightness D/A
Contrast

CIR JTAG

© 2008 Nuvoton Technology Corporation www.nuvoton.com

WPC8765L / WPC8769L
Device-Specific Information
The following table shows the main differences between Revisions A4 and A5 of the WPC8765L and WPC8769L device.

Revision A4 Revision A5
Feature
WPC8765L WPC8769L WPC8769LA0
ADC Resolution 10 bit 8 bit 8 bit
PWM Outputs 3 8

Features Embedded Controller System Features

■ Host Interface
Embedded Controller Features — Comprises host interface channels, typically used
■ Processing Unit for KBC and ACPI Private or Shared EC channels
— CompactRISC CR16CPlus 16-bit embedded RISC — 8042 KBC-standard interface (legacy 60h, 64h)
processor core (the “core”) — Two PM interface ports (legacy 62h, 66h; 68h, 6Ch)
— Up to 4 Mbytes of external address space — ACPI EC with either Shared or Private interface
■ Internal Memory through the PM interface
— 1 Kbyte of ROM — Two Mailbox areas for host-core communication, up
to 4 Kbytes each; maximum 4 Kbytes total
— 4 Kbytes of on-chip RAM
— Generates IRQ, SMI and SCI
— All memory types can hold both code and data
— Provides IRQ1 and IRQ12 support
■ Flash Interface Unit (FIU)
— Provides Fast Gate A20 and Fast Host reset via firmware
— Up to 4 Mbytes of code and data
■ Interrupt Control Unit (ICU)
— Hardware-protected boot zone block protection
— 31 maskable vectored interrupts (of which eight are
— SPI External Memory external)
❏ Up to 32 Mbits — General-purpose external interrupt inputs through
❏ Fast Read mode MIWU
❏ Page programing support — Enable and pending indication for each interrupt
❏ Configurable clock rate — Non-maskable interrupt input
— Field upgradeable ■ Multi-Input Wake-Up (MIWU)
■ Shared Memory Controller (SHM) — Up to 40 wake-up or interrupt inputs
— Supports BIOS (flash) memory sharing with PC host — Generates wake-up event to PMC (Power Manage-
ment Controller)
— Supports host-controlled code download and update
— Generates interrupts to ICU
— Memory access protection
— User-selectable trigger conditions
LPC System Interface ■ Internal Keyboard Matrix Scanning
■ Based on Intel’s LPC Interface Specification Revision — Up to 18 open-collector outputs (at least 12)
1.1, August 2002 — Eight Schmitt inputs with internal pull-ups
■ Four optional 8-bit DMA channels
■ General-Purpose I/O (GPIO) Ports
■ I/O, Memory and 8-bit Firmware Memory read and write
— 64 port pins
cycles, Firmware Memory writes may insert wait cycles
— I/O pins individually configured as input or output
■ Bootable Memory Support
— Configurable internal pull-up / pull-down resistors
■ Base Address (BADDR1-0) straps to determine the
base address of the index-data register pair — Outputs individually configured as push-pull or
open-drain
— Alternate base address configurable by the core
— Two echo inputs with wake-enabled interrupts
■ LPCPD and CLKRUN support
— Additional 12 GPIOs with wake-enabled interrupts
— Four GPIOs capable of 20 mA sink current
— Seven GPIOs are accessible to the host
— Optional low-cost external GPIO expansion through
the SensorPath interface
■ PS/2 Interface
— Three external ports: can be used for keyboard,
mouse and an additional pointing device
— Byte-level handling via hardware accelerator

www.nuvoton.com 2 Revision 1.2

 WPC8765L / WPC8769L
Features (Continued)

■ Two SMBus (SMB) Interface Modules; each module: ■ Digital-to-Analog Converter (DAC)
2 ®
— Is Intel SMBus, Philips I C and ACCESS.bus — Four channels, 8-bit resolution
compatible — 1 µs conversion time for 50 pF load
— Is SMBus master and slave — Full output range from AGND to AVCC
— Supports up to two simultaneous slave addresses ■ Development Support
— Supports polling- and interrupt-controlled operations — Interface to debugger via Nexus 5001 interface
— Generates a wake-up signal on detection of a Start ❏ Physical connection using JTAG
condition while in Idle mode
❏ On-board Debug mode with eight hardware
— Supports an optional internal pull-up on SDA and
SCL pins breakpoints

■ Core Universal Asynchronous Receiver-Transmitter ❏ Embedded memory programing via JTAG with
(CR_UART) Module content read protection
— A full-duplex UART channel ■ Core Access to Host Modules
— Programmable baud rate — Enabled via lock mechanism
— Data transfer via interrupt or polling
Host Function Features
■ Two 16-bit Multi-Function Timer (MFT16) Modules;
each module has: ■ Mobile System Wake-Up Control (MSWC)
— Two 16-bit timers with a 5-bit prescaler — Software-controlled off events
— Pulse Width Modulation (PWM), Capture and — Event routing to IRQ, SMI or PWUREQ
Timer/Counter modes ■ Host- or Core-Controlled CEIR (Consumer Electronic
— Capture inputs with programmable edge detection IR) Receiver
— An interrupt on compare match — Supports RC-5, RC-6 and NEC protocols
■ Two Pulse Width Modulation (PWM) Modules — Wake-up on a pre-configured message
— Group A_PWM: two outputs in Rev. A4; four outputs in ■ Infrared Port
Rev. A5 — Supports IR learning and emitting
— Group B_PWM: one output in Rev. A4; four outputs in — Software compatible with the 16550A and the 16450
Rev. A5
— Shadow register support for write-only bit monitoring
■ Serial Peripheral Interface (SPI) Module — HP-SIR
— Bus master — ASK-IR option of SHARP-IR
— 8-bit interface — DASK-IR option of SHARP-IR
— Up to 10 MHz data clock rate — Consumer Remote Control supports RC-5, RC-6,
— Clock can be selected to be high or low in Idle mode NEC, RCA and RECS 80
— Clock polarity can be selected for normal (sample on ■ Serial Port (SP2)
rising edge) or alternate (sample on falling edge)
— Software compatible with the 16550A and the 16450
■ Timer and Watchdog (TWD) — Shadow register support for write-only bit monitoring
— 16-bit periodic interrupt timer with 30 µs resolution — UART data rates up to 1.5 Mbaud
and 5-bit prescaler for system tick and periodic
wake-up tasks ■ Supports Microsoft® Advanced Power Management
— 8-bit watchdog timer with enable/disable (APM) Specifications Revision 1.2, February 1996
— “Watchdog occurred” flag — Generates the System Management Interrupt (SMI)
— Two watchdog reset options: warm or cold ■ PC01 Rev 1.0 and ACPI 3.0 Compliant
™
■ SensorPath Bus Interface — PnP configuration register structure
— Single Wire bus master — Flexible resource allocation for all logical devices
— Supports up to seven slave devices ❏ Relocatable base address
— x1, x4 SensorPath clock rate support ❏ 15 IRQ routing options
■ Analog-to-Digital Converter (ADC) ❏ Four optional 8-bit DMA channels (where applicable)
— Six channels, with 8/10-bit resolution (10-bit resolu-
tion only in WPC8765L)
— 125 µs conversion time
— External voltage reference

Revision 1.2 3 www.nuvoton.com

WPC8765L / WPC8769L
Features (Continued)

Clocking, Supply and Package Information ■ Power Supply

■ Strap Input-Controlled Operating Modes: — 3.3V supply operation
— Shared BIOS memory mode — 5V tolerance and back-drive protection on all pins
(except crystal oscillator, A/D, D/A, LPC bus, and
— TRI-STATE® mode SPI flash pins)
— Development mode — Separate supply for host I/F (VDD) and EC functions
■ Clocks (VCC)
— Single 32.768 KHz crystal oscillator — Backup battery input for wake-up configuration
— On-chip high-frequency clock generators — Reduced power consumption capability
— Either 32.768 KHz or CR16CPlus clock out — Software- or hardware-switched power modes:
■ Testability ❏ Active mode
— XOR-tree structure includes all device pins (except ❏ Active mode executing WAIT
supply, A/D, D/A, and crystal oscillator pins), select-
❏ Idle
ed at power-up by strap inputs
— TRI-STATE device pins, selected at power-up by ❏ Deep Idle
strap input (TRIS) ❏ Suspend
❏ Power Off, for oscillator only, from the backup
battery
— Automatic wake-up on system events
■ Package Options
— 128-pin LQFP package

www.nuvoton.com 4 Revision 1.2

 A4 and A5)
WPC8765L / WPC8769L Mobile Embedded Controller with SPITM Flash Interface and MC-Compliant CIR Port (Revisions
Physical Dimensions
Control dimensions are in millimeters

128-Pin Low-Profile Plastic Quad Flatpack (LQFP)

Order Number: WPC8765LDG / WPC8769LDG for Rev. A4,
WPC8769LA0DG for Rev. A5

Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended
for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic
signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Nu-
voton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein
personal injury, death or severe property or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify
Nuvoton for any damages resulting from such improper use or sales.

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Please note that all data and specifications are subject to change without notice.
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