A Self-Tuned Class-E Power Oscillator: IEEE Transactions On Power Electronics July 2018

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A Self-Tuned Class-E Power Oscillator

Article  in  IEEE Transactions on Power Electronics · July 2018


DOI: 10.1109/TPEL.2018.2859387

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A Self-Tuned Class-E Power Oscillator


Mohammad Mahdi Ahmadi, Member, IEEE, Maryam Salehi-Sirzar
Department of Biomedical Engineering, Amirkabir University of Technology, Tehran, Iran

1
Abstract—The efficiency and output power of a high-Q Class-
E power amplifier are very sensitive to the values of the circuit
components. Any mismatch between the nominal Class-E
frequency and the input clock frequency could result in
considerable degradation in the efficiency and much change in
the output power. In this paper, we present a new self-oscillating
Class-E power amplifier (power oscillator) whose feedback
network is mainly constructed of a low-Q RC circuit. As a result,
the phase response of the feedback network is almost flat around
the operating frequency, and if the nominal Class-E frequency of
the load network changes due to variations in the component
values, the phase shift in the feedback network does not change Fig. 1. The basic structure of a Class-E PA
considerably, and therefore, the Class-E operation of the circuit
is substantially maintained. We also present a complete design
procedure for the proposed Class-E power oscillator. We have
built and tested a sample Class-E power oscillator based on the Class-E PAs, if tuned properly, can achieve efficiencies in
proposed circuit. At VDD = 4.5 V, the measured oscillation the range of 80%–100% [2]. In a nominally-tuned Class-E
frequency, output power and efficiency of the circuit are 800kHz, PA, the values of the load network components are chosen
0.96W, and 89%, respectively. Simulation and measurement such that the drain voltage of the transistor satisfies the zero-
results confirmed that the efficiency and output power of the voltage switching (ZVS) and zero-voltage-derivative
proposed Class-E power oscillator have small sensitivities to the
switching (ZVDS) conditions. There is only one switching
variations in the component values; therefore, we call the
proposed circuit a self-tuned Class-E power oscillator.
frequency that can maintain the Class-E at its nominal
operating conditions. This frequency, so-called Class-E
Index Terms— Power amplifier, power oscillator, self- frequency or f e , is between the series and parallel resonance
oscillating, self-tuned, circuit tuning, feedback, RC circuits. frequencies of the load network given by [3]:
1 (1)
f o1 =
2π L2 C 2
I. INTRODUCTION
f o2 =
1 (2)

C lass-E power amplifiers (PAs) are widely used in


numerous applications, including dc/ac inverters, dc/dc
converters, wireless communication and wireless power
CC
2π L 2 1 2
C1 + C 2
If a mismatch exists between the switching frequency and
transfer systems. Fig. 1 shows the basic topology of a Class-E
the Class-E frequency f e , the power loss in the transistor
PA, which was first introduced by the Sokals in 1975 [1]. This
circuit consists of a single transistor M1, an RF choke L1 , a could considerably increase and degrade the efficiency. If the
loaded q-factor of the PA, QL , is large, the power loss in the
load resistor RL , and a load network consisting of C 1 , C 2
transistor could be substantial, potentially damaging the
and L2 . An input clock signal periodically turns M1 on and
transistor. Even if the switching frequency is well-controlled
off at the clock frequency, which is also called the switching with a crystal oscillator, the mismatch between the switching
frequency. The inductance of L1 is usually very large at the frequency and f e can quite naturally arise from the changes in
switching frequency such that it behaves like a constant dc the component values. For example, the inductance of L2 can
current source. The load network filters out the second and
change due to the coil warping, or the proximity of L2 to
higher-order harmonics of the drain signal and delivers a near
sinusoidal waveform to RL . other strong electromagnetic fields or ferro-magnetic objects
[4]. Therefore, it is crucial to keep the PA in, or close to, its
optimal operating condition.
To resolve the aforementioned issue, a solution is to adjust
the switching frequency based on a feedback obtained from a
signal in the load network. Several circuits have been
proposed in the literature to implement this idea [4]–[16].
2

24 200
These circuits actually convert the Class-E PA to a self-
22 Magnitude 180
oscillating PA, or as is named in [16], a Class-E power Phase
20 160
oscillator (PO). Most of the proposed self-oscillating Class-E
18 140
PAs are for wireless power transfer applications and require
16 120
complicated frequency tuning circuits. The circuit proposed in
14 100
[16] is a general-purpose PO, for which several design 12 80
procedures have been proposed in the literature [17]–[21]. 10 60
In this paper, we propose a new general-purpose Class-E 8 40
PO which has a simpler feedback network than the 6 20
conventional Class-E PO proposed in [16]. The proposed 4 0
feedback network consists of only resistors and a capacitor, 2 -20
and since the feedback network does not have a self-resonance 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1

frequency, both the switching frequency and the Class-E Frequency (MHz)
frequency are defined by the inductor L2 and capacitors C1 and Fig. 2. The transfer function VX (s) VD (s) of the C2-L2-RL branch of the
C2 in the load network; therefore; these frequencies track each circuit shown in Fig. 1.
other better, and as a result, the output power and the
efficiency of the proposed PO show negligible sensitivities to Po = 1W , VDD = 4.5V and QL = 13 . If this value is different
the changes in the component values. This important feature
from the actual load resistance Ro , we can use well-known
allows for larger tolerances and variation windows for the load
network components. We also present a fully analytical design matching circuits [3], [22-23] to transform Ro to RL . As a
procedure for the proposed circuit. The procedure allows an result, for the sake of simplicity, we shall keep RL = 11.26 Ω
engineer to quickly calculate the component values using a in this section. In Sec. III, we briefly describe a couple of
hand-held calculator or computer software, such as MATLAB.
matching circuits that can convert Ro = 50 Ω to RL = 11.26 Ω .
II. WORKING PRINCIPLE It is shown in [3] and [24] that, if a Class-E PA is nominally
tuned, the phase shift between the fundamental components of
In this section, we explain the working principle of our
the gate signal VG and the drain signal VD equals +196.6°.
proposed Class-E PO using the same circuit specifications
described in [17]. In Sec. III, we present an analytical design Because VD lags VG , in this paper, we prefer to say that the
procedure for the proposed circuit. phase shift from the gate to the drain of M1 is -163.4°. The
The specifications of the Class-E PO described in this series C2 − L2 − RL branch is a narrow-band filter that filters
paper, taken from [17], are as follows: out the second and higher-order harmonics of VD , and
1) The output power delivered to the load Po = 1W .
delivers a near sinusoidal waveform to RL .
2) The supply voltage V DD = 4.5 V .
Fig. 2 shows an AC simulation on the C2 − L2 − RL branch
3) The operating frequency f e = 800kHz .
of the Class-E PA shown in Fig. 1. The phase shift from D to
4) The load resistance Ro = 50 Ω . the resonance node X , starts from +90° at dc (not shown in
5) The loaded q-factor QL = 13 . the figure) and moves toward +180° before reaching the
Assuming a large value for L1 and a duty ratio of D = 0.5 resonance frequency of the C2 − L2 − RL branch, which is
for the gate drive signal VG , we can use the following fo1 = 764kHz . As it is clear in Fig. 2, in the vicinity of fo1 ,
formulas, described by N. Sokal in [2], to find the values of the phase shift moves from around +180° to around 0°,
C1 , C2 , L 2 and RL for the circuit shown in Fig. 1: reaching to 0° at infinity. For the example that we are dealing
with, the phase shift is almost 83° at f o1 = 764 kHz and
V2  0.452 0.4 
RL = 0.5768 DD 1.001245− − 2 = 11.26Ω (3) +36.5° at the Class-E frequency of f e = 800 kHz . Since the
PO  QL QL 
phase shift from G to D is –163.4°, the phase shift from G to
QL RL
L2 = = 29 .21 µH (4) X is about -126.9°.
ωe
In order to convert the Class-E PA to a Class-E PO, we can
1  8  0.914 1.03  0.6 
C1 =   0.999 + − 2  +  = 3.45nF (5) add a feedback network that returns a portion of the signal at
ωe RL  π (π 2 + 4)  QL QL  QL (L1 L2 )  node X to node G with an appropriate phase shift and
1  1  1.015  0.2  amplitude. In order to satisfy the oscillation criteria, the phase
C2 =  1.001+ − = 1.49nF (6)
ωe RL  QL − 0.105 QL − 1.788 QL (L1 L2 )  shift in the entire oscillation loop should be –360°; therefore
the feedback network must provide a phase shift of –233.1° (=
where ωe = 2π f e is the nominal Class-E frequency in terms of
–360°+126.9°). A passive feedback network that can provide
radians per second. The calculated value for RL using (3) is such amount of phase shift is fairly complicated and needs at
the optimal value resulting in nominal Class-E operation for least three frequency poles in its transfer function.
3

VDD

L1
L2 C2
D X

G
M1 C1 RL

VF Feedback VX
Network Fig. 5. Three RC circuits that can be used as the feedback network of the
Class-E PO shown in Fig. 3: (a) a simple RC circuit that can only satisfy the
Fig. 3. The basic structure of a Class-E power oscillator. phase shift requirement on the feedback network; (b) an RC circuit that can
satisfy the phase shift and the voltage amplitude requirements; (c) an RC
24 20 circuit that can satisfy phase shift, voltage amplitude and dc level
22 Magnitude 0 requirements.
20 Phase -20
18 -40
16 -60
14 -80
12 -100
10 -120
8 -140
6 -160
4 -180
2 -200
0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
Frequency (MHz)
Fig. 4. The transfer function VX (s) VD (s) of the L2-C2-RL branch of the
circuit shown in Fig. 3.

If we put L2 at the left of C2 , as it is shown in Fig. 3, the


requirement for the feedback network is facilitated. Fig. 4
shows an AC simulation on the L2 − C2 − RL branch of the
circuit shown in Fig. 3. In Fig. 3, the phase shift from D to X,
starts from +0° at dc and around the resonance frequency of
fo1 = 764kHz , it sharply drops to about -180°. It then goes Fig. 6. Circuit implementation of our proposed Class-E PO.

back up to -90° at infinity (not shown in Fig. 4). For our


example, the phase shift is almost –83° at fo1 = 764kHz and – M1. Adjusting the dc level of VF helps defining the duty cycle
of the gate drive signal.
134° at f e = 800 kHz . In other words, since the phase shift Fig. 6 shows a complete circuit implementation of the
from G to D is –163.4°, the phase shift from G to X is about proposed Class-E PO. The gate driver is not necessarily part of
–297.4°, which means that the feedback network must only the circuit and can be removed for many designs. In order for
provide a phase shift of about –62.6° to satisfy the oscillation the Class-E PO to work properly, a couple of issues should be
criteria. Fortunately, this amount of phase shift can be easily taken care of: first, the loading effect of M1 (or the gate driver)
obtained using a simple series RC circuit. on the feedback network, and second, the loading effect of the
A simple RC network, as shown in Fig. 5(a), is sufficient to feedback network on the load network.
convert the Class-E PA to a Class-E PO. However, the signal If the gate capacitance of M1 is less than the calculated
amplitude at node X is often large and could damage M1. capacitance for the feedback network, i.e. CF in Fig. 5(a), or
Therefore, the feedback network, in addition to providing
sufficient phase shift, should attenuate the signal. This can be C F' in Fig. 5(b,c), we can easily account for that by
achieved with the RC network shown in Fig. 5(b). Adding subtracting the value of the gate capacitance from the
another resistor to the feedback network of Fig. 5(b), as is calculated value for C F (or C F' ). However, if the gate
shown in Fig. 5(c), can provide enough flexibility to adjust the capacitance of M1 is larger than the calculated CF , we can use
phase shift, the dc level and the amplitude of the signal driving
a gate driver to minimize the loading effect, and then, account
4

for the input capacitance and delay of the gate driver while TABLE I
THE REQUIRED PHASE SHIFT, ϕ F , IN THE FEEDBACK NETWORK FOR DIFFERENT
calculating the phase shift of the feedback network. In either
case, using a gate driver is beneficial because, first it buffers QL VALUES AND L1/L2 RATIOS
the nonlinear gate capacitance of M1, which is difficult to

model and account for in the calculations, and secondly, it 100 20 10 5 3 1
converts the sinusoidal waveform outputted from the feedback 
network to a pulsatile waveform and minimizes the transistor 5 -69.6 -70.1 -70.6 -71.0 -72.1 -77.4
loss during the switching times.
10 -60.2 -62.9 -63.1 -63.5 -65.8 -66.4
To account for the loading effect of the feedback network
on the load network, we can model the feedback network with 20 -59.8 -60.3 -60.3 -60.5 -60.6 -62.9
a parallel RC section placed between the node X and ground. 50 -57.8 -57.9 -58.1 -58.4 -58.7 -60.3
At the same time, we can convert the series C2 − RL branch to 100 -55.9 -56.6 -56.6 -56.6 -57.9 -58.3
its equivalent parallel circuit. We can then account for the
loading effect of the feedback network on the load network therefore ϕ X can be obtained by:
while choosing the values of RL and C 2 . This procedure is  1   1 
more clearly explained in Sec. III. ϕ X = tan −1   + tan −1   − 180 ° (9)
Q
 C2  Q
 L − Q C2 

We know that the phase shift in the whole network should


III. DESIGN PROCEDURE. be zero or –n360°. We also know that, in a tuned Class-E PA
A. Design procedure with ideal circuit components with D=0.5, the phase shift from node G to node D is -163.4°
In this sub-section, we present the design procedure of the [3], [24]. Therefore, after calculating ϕ X using (9), we can
circuit shown in Fig. 6 for the case that all the circuit obtain the phase shift that the feedback network has to
components are ideal, i.e. we assume that the transistor is an provide, defined here by ϕ F , using
ϕ F = −360 − ϕ X − (− 163.4 )
ideal switch and the rest of circuit components do not have
(10)
any parasitic element. In Sec. III.E, we incorporate the effects
of component imperfections in the design procedure. Since (3) to (6) are not 100% accurate [2], if the values of
In order to find the phase shift that the feedback network RL, L2 and C2 that are directly resulted from (3), (4) and (6) are
has to provide, first we need to find the phase shift in the load used in (8) to (10), we could see large errors in the calculated
network from node D to node X . Consider the Class-E PO ϕ F . Therefore, we suggest simulating the Class-E PA using
shown in Fig. 3. The voltage transfer function from node D to the values calculated from (3) to (6) and fine-tuning the PA to
node X is given by: find the optimum values for C1, C2, L2 and RL, and then using
1 (8) to (10) to find ϕ F . Table I provides ϕ F for some typical
+ RL
VX (s) C2 s RL C 2 s + 1 values of QL and L1 L2 .
H (s) = = = 2
(7)
1
VD ( s ) + RL + L2 s L2C2 s + RLC2 s + 1 As shown in Table I, the phase shift that the feedback
C2 s network has to provide, i.e. ϕ F , ranges from -55.9° to -77.4°.
Therefore, a single-pole RC network can easily satisfy the
Let us define the phase of H (s) at the Class-E frequency f e phase shift requirement. Now we can develop a design
by ϕ X . We can calculate ϕ X by substituting jω for s in (7) procedure for the feedback network.
and then using: Before moving forward with the design procedure, we
review the series-to-parallel conversion of an RC circuit as we
 RL C 2ω e 
ϕ X = tan −1 (R L C 2ω e ) − tan −1  
2 
use it multiple times in the design procedure. The theory of
 1 − L C ω
2 2 e 
impedance transformation states that the series Rs-Cs branch
shown in Fig. 7(a) is equivalent to the parallel Rp-Cp section
 
  shown in Fig. 7(b) around the operating frequency of ω , if the
−1  1 
= tan (R L C 2 ω e ) − tan 
−1 (8) following relationships hold [15]:
1 L2 ω e 
 −  Q2
 RL C 2ω e R L  C p = Cs ×
1 + Q2
(11)

We define QC 2 = 1 RL C 2ω e . Since fe is larger than the


resonance frequency of the series C2 − L2 branch, i.e. fo1 , the
(
R p = Rs × 1 + Q2 ) (12)
where Q represents the q-factor of the parallel and series
series C2 − L2 branch is inductive at fe and QC 2 is smaller circuits at the operating frequency of ω :
than QL . Hence, QC 2 − QL is negative. From the circuit 1
Q= = R p C pω (13)
example that we described in Sec. II, we know that we should RsCsω
end up having ϕ X in the third quadrant of the unit circle;
5

Fig. 7. (a) A series RC network, (b) A parallel RC network.

Using this technique, we can simplify the feedback networks


shown in Fig. 5 and convert them to a parallel RC section,
R Fp − C Fp , as is shown in Fig. 8. The series C 2 − R L branch
in Fig. 3 can also be converted to the parallel C 2 p − RLp
section , as is shown in Fig. 8. We can subtract the admittance
of the RFp − C Fp section from the admittance of the
Fig. 8. Equivalent parallel RC circuit of the feedback network and  − 
C 2 p − RLp section and from the remaining R Lp
'
− C 2' p section branch seen by the Class-E power oscillator.

construct the load and matching networks.


'
In Fig. 8, we can see that R Fp is in parallel with R Lp . tuned.
Therefore, a portion of the power, that was supposed to be Using (9) and (10), or using Table I, we find ϕ F to be -
delivered to the output load, is now wasted in R Fp , i.e. the 61.6°. Using series-to-parallel conversion, we then convert the
series C 2 − R L branch to the parallel RC branch consisting of
feedback network. Therefore, we should account for this
power loss at the onset of our design procedure. To minimize R Lp = 1 .51 k Ω and C 2 p = 1 .558 nF . Looking at Fig. 8, we
the power loss in the feedback network, we should choose '
realize that R Lp = RLp
'
|| R Fp and C2 p = C2 p || CFp . We choose to
'
R Fp considerably larger than R Lp . Let us define K R with: have only 5% power loss in the feedback network; therefore,
RFp we divide RLp into two parallel resistors such that R Fp is 20
KR = '
(14)
RLp '
times of R Lp . This results in RFp = (K R +1)RLp = 31.71kΩ and
If, for example, we choose KR = 10, almost 10% , or to be '
RLp = ((KR +1) / KR )RLp = 1.59kΩ .
precise, 100 (K R + 1)= 9.1% , of the drawn power from VDD will In order to construct the feedback network, we should
be dissipated in the feedback network. Obviously, the larger convert the parallel R Fp − C Fp section to its equivalent series
'
that we choose the ratio of R Fp over R Lp , the larger branch R F − C F , which in fact, would construct the feedback
efficiency we can obtain; however, as we will see later in this network shown in Fig. 5(a).
section, increasing the value of R Fp will reduce the We know that, in order for the Class-E PO to be nominally
tuned, the phase shift in the series RF − CF branch should be
calculated value for the feedback network capacitor ( CF or
equal to ϕ F . The transfer function of the series RF − CF
C F' shown in Fig. 5). Therefore, we should choose a value for
branch shown in Fig. 5(a) can be expressed by:
R Fp that will not result in a prohibitively small values for V ( jω ) 1
H F ( jω ) = F = (15)
CF or C F' . V X ( jω ) 1 + R F C F j ω
Assuming that we are acquiesced with 5% power loss in the The phase of H F ( jω ) at ω = ωe is:
feedback network (or K R = 20 ), we start the design of the −1
ϕ F = − tan (R F C F ω e ) . (16)
basic Class-E PA with 5% more output power, i.e.
Let us define the q-factor of the series RF − C F circuit by
Po = 1.05 W . We also assume that D = 0.5 . Since we do not
know the value of L1 a priori, we assume a reasonably large QF . QF is also the q-factor of the parallel RFp − CFp section;
value for the ratio of L1 L2 , e.g. 40. Using (3) to (6), we therefore we have:
1
obtain the values of RL , C1 , C2 and L2 as 10.73 Ω , 3.65nF , QF = = RFpC Fpωe . (17)
RF C F ω e
1.56nF and 27.74 µH , respectively. Then, we choose L1 to
Combining (16) and (17), we can calculate QF using:
be 900 µH to make the ratio of L1 over L2 fairly large. We
1 1
then construct a Class-E PA and fine-tune the values of C1 and QF = =− = 0.527 (18)
C2 using the procedure explained in [2]. During the fine- RF C F ω e tan (ϕ F )
tuning process, we realized that the value of C 2 should be Substituting (18) in (17), we can calculate the value of
adjusted from 1.56nF to 1.57nF for the circuit to be nominally
6

C Fp as follows: 2
2PO  1 
−1 VX = × RL2 +   = 56.51V (25)
C Fp = = 3.3 pF (19) RL  C2ωe 
tan (ϕ F )RFpωe
Let us assume that:
'
We can then calculate the value of C2 p , shown in Fig. 8, R F' = α R F" (26)
using: where α is the ratio of R F' over R F" in Fig. 5(b). From (46),
C 2' p = C 2 p − C Fp = 1558 − 3.3 ≅ 1555 pF (20) proved in Appendix A, we can calculate the value of α using:
To construct the simplest feedback network which is the V
one shown in Fig. 5(a), we can simply convert the parallel α = X cos (ϕ F ) − 1 = 7.78 (27)
VF
R Fp − C Fp section to its equivalent series circuit. R Fp can be
The input impedance, Z F , of the feedback network of Fig.
calculated using:
5(b) can be calculated using:
RFp
RF = = 24.8 kΩ (21) RF" RF' + RF" + RF' RF" C F' ωj
Z F = RF' + = (28)
1 + QF2 1 + RF" C F' ωj 1 + RF" C F' ωj
2 2
Using (18) and considering that 1 + tan (ϕF ) = 1 sin (ϕF ) , and the input admittance YF can be expressed by:
we can simplify (21) to: 1 1 + RF" CF' ωj
YF = = ' (29)
RF = RFp sin (ϕF ) .
2
(22) Z F RF + RF" + RF' RF" CF' ωj

Considering (18) the value of CF can now be using: Substituting R F' from (26) in (29), we can calculate the real
− tan(ϕ F ) part of YF as:
CF = = 15.2 pF (23)
ωe RF 1 α + sin 2 (ϕ F )
Re{YF } = × . (30)
Combining (22) and (23), CF can also be directly calculated RF" α (α + 1)
from R Fp using: The real part of YF represents a conductance which
−2
CF = = 15.2 pF (24) actually should be equal to the inverse of RFp . In other
ωe RFp sin (2ϕ F )
words, we have:
Looking at (24), we realize that if we increase the value of
1 1 α + sin 2 (ϕ F )
R Fp , the value of CF will decrease. This means that, if we = " × (31)
RFp RF α (α + 1)
'
increase the ratio of R Fp over RLp to minimize the power
Therefore, we can calculate the value of R"F from:
α + sin2 (ϕ F )
loss in the feedback network, CF decreases and we might end
RF" = RFp × = 3.97kΩ (32)
up to a situation that CF becomes smaller than the gate α (α + 1)
capacitance of M1 in which case, the feedback network of Fig.
5(a) is not realizable, unless we use a gate driver to buffer the Using (26), we can calculate the value of R F' to be 30.9kΩ.
gate capacitance. To calculate the value of C F' , we consider that both
If one wants to use the feedback network shown in Fig. 5(a) feedback networks of Fig. 5(a) and 5(b) should provide the
to implement a Class-E PO, the design of the feedback same amount of phase shift. Hence, the RC time-constant of
network is now complete. However, as explained in Sec. II, both networks should be the same, or:
the feedback network of Fig. 5(a) does not provide any
flexibility to adjust the amplitude or the dc level of the gate ( )
RF C F = RF' || RF" C F' → RF C F ωe = 
 α  " '
 RF C F ωe (33)
drive signal. Therefore, we can resort to the networks shown α +1
in Fig. 5(b) or 5(c). We first explain the design procedure for Therefore, we can find the value of C F' as:
the feedback network shown in Fig. 5(b); from there, we R C ω − tan(ϕ F )
explain the procedure for the network shown in Fig. 5(c). C F' = ' F F" e = ' = 107 pF (34)
( RF || RF )ωe ( RF || RF" )ωe
The feedback network of Fig. 5(b) allows us to adjust either
the amplitude, or the dc level of the gate drive signal, but not The design of the feedback network of Fig. 5(b) is now
both. We design it for the case that we want to adjust the complete. We should only calculate the equivalent parallel
amplitude of the gate drive signal. capacitance of this feedback network, i.e. CFp , shown in Fig.
Let VX and VF be signal amplitudes at input and output 8, from which, we can take into account the capacitive loading
nodes of the feedback network, respectively. We usually of the feedback network on the load network. It is proved in
choose VF to be, at least, half the supply voltage, however to Appendix B that CFp can be calculated using:
achieve very small MOSFET on-resistance, larger values are QF2 2 α 2 + (α + 1) 2 tan 2 (ϕ F ) ' (35)
C Fp = × CF
preferred. Let us choose VF = 3.0 V . As it is proved in 1 + QF2 2 (α + 1) 2 tan 2 (ϕ F )
Appendix A, VX can be calculated using:
7

where Q F 2 is defined in Appendix B and is proved that can be


calculated using:
tan(ϕ F ) . (36)
QF 2 = −
α + (1 + α ) tan 2 (ϕ F )
Using (35), CFp is calculated to be 6pF, and using (20),
C 2' p is calculated to be 1552pF.
If we want to define both the amplitude and the dc level of
the gate drive signal, we should choose the feedback network
shown in Fig. 5(c). We can find the values of R F" 1 and R "F 2
in Fig. 5(c) using the following equations:
R F" 1 || R F" 2 = R F" (37)
R"F 2 (38)
VF ,dc =
(
R"F 2 + R"F1 || RF' ) ×V DD

where VF ,dc is the dc level of the gate drive signal.


We usually set VF ,dc slightly larger than the threshold Fig. 9. The impedance transformation procedures. (a) The parallel
C2' p − RLp
' section. (b) The series equivalent circuit of the parallel
voltage of M1 to achieve a duty cycle of 50% and also initiate
the oscillation after the supply is turned on. As it will be C2' p − RLp
' section shown in (a). (c) Using capacitive transformation to
explained in the Sec. IV, because the gate capacitance of M1 is convert R o = 50 Ω to RL' = 10.3 Ω . (d) Using an L-match circuit to
nonlinear and voltage dependent, it is almost impossible to '
convert R o = 50 Ω to RLp = 1.59kΩ .
achieve a duty cycle of 50% without using a gate driver.
Therefore, we recommend using a gate driver for M1 and TABLE II
setting VF ,dc larger than the switching threshold voltage of the THE VALUES CALCULATED AND SIMULATED FOR THE PROPOSED CLASS-
E PO WITH IDEAL CIRCUIT COMPONENTS
gate drive. If we assume that VF ,dc should be 2.25V, or half       
 
 
Component
the supply voltage, the values of R F" 1 and R "F 2 are calculated () () () () (Ω) (Ω) (Ω) (Ω) ( )
Calculated 0.9 27.74 3.65 1.56 10.3 30.9 9.1 7 107
to be 9.1kΩ and 7.0kΩ, respectively.
Simulated 0.9 27.74 3.56 1.565 10.3 30.9 9.1 7 106

B. Load Impedance Matching of the transistor (or the gate driver) to obtain a duty cycle of
Most often, the calculated value for RL for nominal Class- 50%; but because the q-factor of the load network is not
E operation is different from the actual load resistance Ro . In infinity, the voltage signal at the resonance node X and at the
these cases, we can use impedance matching techniques to output node of the feedback network are not ideal sinusoids
make the actual resistance seen by the Class-E load network and have harmonics; therefore, the positive and negative half-
equal to RL . For example, if Ro > RL , or in other words, cycles of the gate drive signal does not have exactly the same
duration. As a consequence, the values of the components
'
Ro < RLp , we can use the capacitive transformer circuit should be slightly adjusted to bring the drain waveform to its
shown in Fig. 9(c), or the L-match circuit shown in Fig. 9(d) nominal Class-E condition.
to arrive to the actual load resistance Ro = 50 Ω . To provide insight on how the drain waveform of the PO
changes with the variation in the component values, we have
For now, we just convert the parallel C2' p − RLp
'
section to its first simulated the Class-E PO designed in Sec. III(A) and
equivalent series C2' − RL' branch to make our designed Class- fine-tuned the values of the components. The final values,
E PO similar to a standard Class-E PA. The final calculated resulted from simulation, are given in Table II. As it is clear,
values for the Class-E PO with feedback circuit shown in Fig. the value of C 1 has to change about 2.5% and the values of
5(c) are given in Table II. C 2 and C F' have to change by less than 1%. Then we
simulated the designed PO with ±10% changes in each of the
C. Fine-tuning the Class-E PO major components affecting the circuit performance, and
In Sec. III.A, even though we assumed that all the components plotted the drain waveforms. For example, Fig. 10(a) shows
are ideal, the values calculated by the formulas provided in the drain waveforms for the cases that C1 is nominal ( ∆C1 = 0 )
that section might result in slightly sub-optimal waveforms. A ,10% larger ( ∆C 1 = +0.1C 1 ), and 10% smaller ( ∆C1 = −0.1C1 ).
couple of issues contribute to this issue. First of all, equations
We have increased and decreased R"F 1 and R"F 2 together and
(3) to (6) are not completely accurate. Secondly and more
importantly, equations (3) to (6) are for the duty ratio of with the same proportion in order not to change the duty cycle
D=0.5. We set VF ,dc slightly larger than the threshold voltage of the gate drive signal.
8

Fig. 10. The drain waveforms for ±10% variations in (a) C 1 , (b) C 2 , (c) L2 , (d) R L , (e) C F' and (f) RF" 1, F 2 .

Looking at the waveforms shown in Fig. 10, we can make 10(f), moves the trough of the waveform upwards and to the
the following conclusions: left.
1. L2 has the largest effect on the frequency of operation Since we do not usually want to change the oscillation
(Shown in Fig. 10(c)), and in fact, f e ∝ L−20.5 . In addition, frequency or the output power, we recommend fine-tuning the
increasing L2 moves the trough, i.e. the zero-slope point, of the Class-E PO by adjusting the values C1 and C F' .
waveform downwards and to the right.
D. Comparison with a standard Class-E PA
2. The effect of C2, shown in Fig. 10(b), on the frequency is
almost as large as the effect of L2. Increasing C2 moves the To compare the effects of component variations on the
trough of the waveform downwards and to the right. output power, efficiency and drain waveform of the proposed
3. Increasing C1, as is shown in Fig. 10(a), moves the trough Class-E PO with those of a standard Class-E PA designed for
of the waveform upwards and to the right. Increasing C1 the same specifications, we designed a Class-E PA for the
slightly reduces fe. same specifications listed in Sec. II. The values of C1, C2, L2,
4. Increasing RL, as is shown in Fig. 10(d), moves the trough and RL obtained from (3) to (6) for the standard Class-E PA
of the waveform upwards. are 3.65nF, 1.57nF, 27.74µH and 10.73Ω, respectively.
5. Increasing C F' , as is shown in Fig. 10(e), slightly moves the We simulated the proposed Class-E PO and the Class-E PA
and measured the output power and efficiency of the circuits
trough of the waveform downwards and to the right (similar to for nominal, 10% increased and 10% decreased values of each
the effect of C2). component. Fig. 11 illustrates the drain waveforms for each
6. Similarly to increasing C F' , increasing R"F 1 and R"F 2 comparison. For instance, Fig. 11(a) shows the comparison
together and with the same proportion, as is shown in Fig. when C1 changes. Five drain waveforms are plotted in Fig.
9

Fig. 11. Comparing the variations in the output power, efficiency and drain waveform of the proposed Class-E PO with those of a Class-E PA designed for the
same specifications. The values of (a) C 1 , (b) C 2 , (c) L2 and (d) R L , have changed by ±10%.

11(a): the black curve is for the nominal case which is the decreases by 10%, the efficiency of the PA decreases by about
same for both PA and PO; one waveform is for the case that 23%, while it changes by less than 1% in the PO.
C1 of the PA increases by 10%, one is for the case that C1 of We should clarify that, the percent variations that we have
PO increases by 10%, one is for the case that C1 of the PA reported in this section are for the Class-E PO and PA
decreases by 10%, and finally one is for the case that C1 of PO designed with the specifications listed in Sec. II, and as the Q
decreases by 10%. The percent changes of the output power of the circuit increases, the PA becomes more sensitive the
and the efficiency of both PA and PO are written on each plot. component values and the advantages of the proposed Class-E
Looking at Fig. 11(a), we can observe that 10% variation in PO becomes more pronounced.
C1 would cause almost 5% change in the output power in both
E. Design procedure considering the imperfections in the
PA and PO. The variation in the output power of the PO is
components
about 1% larger than that of the PA. The percent changes in
efficiency are less than 0.3% in all cases for both PO and PO. In Sec. III.A, we assumed that all the circuit components
Therefore, we can conclude that the output power of the PA is are ideal, and accordingly, we developed a design procedure
slightly more robust against the variations in C1. for the proposed Class-E PA. In reality, no ideal circuit
Similar statements can be made for the variation in RL. As is component exists and we should modify our design procedure
illustrated in Fig. 11(d), the output power of the PA has to incorporate the effects of circuit imperfections that
changed slightly less than that of the PO. The percent changes considerably degrade the efficiency and the signal phase shift
in efficiency are less than 1% for both PO and PA. as it travels through the feedback loop.
The merits of the proposed Class-E PO become clear when The main components of power loss include the transistor
we compare the effects of variations in C2 and L2. The output on-resistance, R on , the power loss for charging and
power and the efficiency are most sensitive to the values of discharging the transistor gate capacitance, the power
these two components. As is illustrated in Fig. 11(c), when L2 consumption of the gate driver, the power loss in the ESR of
increases by 10%, the output power of the PA decreases by L 1 , L 2 , and the capacitors, and finally the losses associated
70% (or more than three times), while it decreases by only with the nonzero fall time of the drain current when the
6.3% in the PO. Also when L2 decreases by 10%, the output transistor is turning off. Another component of the power loss
power of the PA increases by 46%, while it increases by only is the one dissipated in the feedback network; however, the ac
6.8% in the PO. Efficiency of the Class PA is also very power loss in the feedback network is already taken into
sensitive to the values of C2 and L2, while the efficiency of the account in the design procedure, and the dc power loss in the
PO shows little sensitivity to the changes in all component resistive divider of the feedback network is fairly small due to
values. For example, as illustrated in Fig. 11(b) when C2 the large values of RF' , R "F 1 and R "F 2 .
The aforementioned losses are not known at the start of the
10

design procedure. Therefore, we have to assume a realistic constructed L2 using litz wire, and measured its inductance
value for the efficiency η in the first round of calculations and and resistance at 800kHz using a GW 8101G LCR meter. We
then, we can choose the components, which considerably measured the inductance and resistance to be 25.6 µH and
degrade the power efficiency, i.e. the transistor, the gate driver RL 2 = 0.5 Ω , respectively. The degradation in the efficiency
and the inductors L 1 and L 2 . In the second round of due to R L 2 is about R L 2 R L × 100 , or 4.7% which is very
calculations, we know the approximate power loss in these
large compared to other losses. R L 2 also introduces a
components using either, calculation, simulation or
measurement and we can reiterate the design procedure and negligible change in the calculated ϕ X which can be
fine-tune the component values. neglected.
The transistor should be chosen based on the following The gate driver should be chosen based on the following
criteria [2]: criteria:
1) Its typical threshold voltage must be much less than VDD 1) It should have a small propagation delay compared to the
so that the gate driver can easily turn it on. delay of the feedback network. Usually an inverting gate
driver has a smaller delay compared to a non-inverting
2) Its drain-source breakdown voltage, BVDSS , should be
one; but due to the phase shift requirement on the
higher than 3.56VDD . feedback network, a non-inverting gate drive should be
3) Its Ron should be much smaller than RL . Ron degrades used in the proposed circuit.
the efficiency by about (1.365 Ron R L ) ×100 percent [2]. 2) Its input capacitance should be smaller than the calculated
4) The turn-on transition time of the transistor should be less capacitance for the feedback network, i.e. C F' .
than 30% of the period and the turn-off should be less than An important parameter of the gate driver is its propagation
20% of the period [2]. delay. Let us represent the propagation delay of the gate driver
5) The drain capacitance of the transistor should be less than by td . The phase shift ϕ d caused by the gate driver can then be
the calculated C1 . expressed by:
6) Its maximum allowed power dissipation should be more ϕ d = −ω × t d (39)
than the desired output power. When the Class-E operation
To take ϕ d into account, the passive part of the feedback
of the circuit is established the power dissipated in the
transistor is much less than the output power; but, during network should provide a phase shift of ϕ F − ϕ d .
the start-up, the circuit is not yet tuned and the power loss We used a 74AC244 digital buffer as the gate driver. The
in the transistor can be high enough to damage the power consumption of this buffer is 200 µW which is fairly
transistor. negligible compared to other losses. This buffer has a
Based on the criteria for the transistor, we chose FQT13n06 switching threshold voltage of 2.25 V, an input capacitance of
MOSFET manufactured by ON Semiconductor for our design 4.5 pF and a typical delay of 5ns. According to (39), this delay
example. FQT13n06 has a maximum drain capacitance of amounts to a phase shift -1.44° at 800 kHz. Therefore, after
120pF, and a typical Ron of 0.1Ω . Therefore, we expect to finding the required phase shift in the feedback network, we
have a degradation of about 1.3% (= 1.365 Ron R L ×100)
should subtract 1.44° from that and design the feedback
network for the remaining amount.
due to Ron . Another component of the power loss is the one dissipated
ESRs of L1 and L2 are other sources of power loss in the due to the charging and discharging of the transistor gate
circuit. Since we have chosen the value of L1 much larger capacitance. The gate capacitance of FQT13n06, based on its
datasheet, is typically about 270pF. However, the input
than the value of L2 , the current in L1 is fairly constant and capacitance of a MOSFET is very nonlinear (voltage-
its ac component is very small. Therefore, we can ignore the dependent). Relatively speaking, the input capacitance is small
magnetic loss in L1 and only consider the power loss due to when the MOSFET is OFF. It increases considerably when the
the dc resistance of L1 . We have chosen an RF choke with an transistor becomes ON and is in saturation. It drops again,
when the transistor is fully ON and is in the triode region [25].
inductance of 900µH and a dc resistance of 0.01Ω. The dc
Consequently, when the amplitude of the gate signal is so
resistance of L1 introduces a power loss of about 0.5 mW and
large that the transistor periodically switches ON and OFF, it
an efficiency degradation of about 0.05%, which is negligible. is not possible to simply model the input capacitance with a
In contrast to the current of L1 , the current in L2 is a high- linear (ideal) capacitor. Even if we want to have a rough value
frequency ac current. At high frequencies, the effective ESR of the input capacitance, we should simulate the transistor
of L2 , i.e. R L 2 , increases by a large extent due to skin effect with real large signals and in a circuit similar to the actual one.
and magnetic loss in the inductor’s core. Therefore, choosing Therefore, to measure the power loss due to the charging and
discharging the gate capacitance, we designed a very simple
L2 needs considerable attention. A good strategy to minimize
Class-E PA for the specifications stated in Sec. II and drove
R L 2 is to use air core inductor with litz wire to increase the the transistor with an 800-kHz 4.5V pulse signal. We
effective wire cross-section at high frequencies. We measured the power required to charge and discharge the input
11

TABLE IIIIV TABLE IV III


MAJOR SOURCES OF POWER LOSS IN THE PROPOSED CLASS-E PO AND THEIR VALUES OF CIRCUIT COMPONENTS IN FIG. 6 RESULTED FROM
SHARE IN DEGRADING EFFICIENCY CALCULATION, SIMULATION AND EXPERIMENTAL TUNING. INSTEAD OF THE
Source of power loss Degradation in η (%) R2-CL BRANCH IN FIG. 6, THE MATCHING NETWORK, SHOWN IN FIG. 9(C) IS
USED.
AC Power Loss in Feedback 5
ESR of L2 4.7 Parameter Calculation Simulation Experiment
RON of transistor 1.3  () 3.6 3.3 3.4
Gate charge and discharge 0.8 " () 1.85 1.85 2.02
" () 8.0 8.0 8.6
 ( ) 104 98 62
 (Ω) 50 50 50

capacitance to be about 8mW. Therefore, we expect an  (Ω) 31 31 30

efficiency degradation of about 0.8% due to the gate  (Ω) 8.38 8.38 8.02

capacitance.  (Ω) 6.59 6.59 6.32
The major components of power loss are summarized in () 0.9 0.9 0.9
Table III. Overall, we estimate to have about 12% degradation () 28 28 25.6
in efficiency due to the feedback network, the ESRs of L1 #$ (%) 800 800 800
&' (() 1 0.99 0.96
and L 2 , Ron of the transistor and charging and discharging of
)(%) 88 89 89
the gate capacitance. It should be noted that the dc power loss
in the feedback network and the power dissipated in the gate
capacitance and the gate driver are not supplied through L1,
Therefore, the design procedure, i.e. calculating RL using (3),
should be started with a Po that includes the output power and
the power loss in Ron and L2, as well as the ac power loss in the
feedback network. In other words, we should start the design
procedure with Po = 1.11 W .
We started the aforementioned design procedure with
Po = 1.11 W . Then we simulated the PO using LT-SPICE
XVII [26] and realized that the circuit is not nominally tuned.
The source of the issue was that the duty cycle of the gate
drive signal was slightly larger than 50%. The reason, as
explained in Sec. III.C, was the limited q-factor of the load
network. We fine-tuned the values of C1 and C F' to achieve the Fig.12. Simulation result of the proposed Class-E PO with actual
ZVS and ZVDS conditions, but we ended up having about 7% components
more output power than the expected value. The cause of the
issue was again the larger than expected duty cycle of the gate efficiency of the circuit. But, it is not our aim to develop a
drive signal. Therefore we re-iterated the design procedure, Class-E PO that outperforms all previous Class-E POs in
but this time, with 7% less power, or Po = 1.04 W . After efficiency; here, we only want to prove the concept, describe
the design procedure of the new circuit and verify it through
simulating the PO and fine-tuning the values of C1 and C F' ,
simulation and experimental results. Therefore, we kept
the output power was 0.99W and the efficiency was 89%. KR=20.
After designing the basic structure of Class-E PO shown in In summary, we suggest that the designer start the design
Fig. 6, we designed the impedance matching network shown with a reasonable estimate of the power loss in the circuit (for
in Fig. 9(c) to arrive to RL=50Ω. The finally calculated values example 10%). Then, he should calculate the values of C1, C2
of the circuit components are shown in the “Calculation”
, L 2 and RL using (3)-(6), and based on those values, choose
column of Table IV. The values of the components, after fine-
tuning in simulation, are given in the “Simulation” column of an appropriate transistor, gate driver and RF choke. He should
Table IV. It is clear that our design procedure results in a simulate the resulting Class-E PA with the selected
circuit that is very close to being fully tuned. The simulated components and their parasitic elements, and fine-tune the PA
waveforms of the drain voltage, drain current and output in simulation. This step is required because the values of C1
voltage are depicted in Fig. 12. and C2 should be adjusted based on the chosen transistor, gate
It is worth mentioning that the calculated C F'
in (34) is driver and RF choke. The designer should then continue the
much larger than the input capacitance of the gate driver that rest of the described design procedure to convert the Class-E
we have chosen in this work. Therefore, we could go back to PA to a Class-E PO. Fig. 13 shows a flowchart summarizing
(14) and choose a larger value for KR. This would minimize the design procedure.
the ac power loss in the feedback network and increase the
12

Fig. 14. The schematic of the conventional Class-E power oscillator [17].

shift changes from -40° to -140°, while the phase shift of the
proposed circuit is almost fixed at -60° with less than 0.5°
change. This is an important advantage of the proposed circuit
because, for example, if L2 increases by only 2%, the Class-E
frequency of the load network decreases by about 1%, or it
goes from 800 kHz to 792 kHz. So now, the phase shift
provided by the proposed feedback circuit is still about -60°
and the proposed PO stays close to its nominal Class-E
operation; while the phase shift provided by the conventional
feedback circuit changes from -90° to -45° and greatly
disturbs the Class-E operation of the circuit. Moreover the
exact values of Lf and Cg play important roles in the proper
operation of the conventional Class-E PO. If either Lf or Cg
slightly changes, the phase shift of the conventional feedback
network changes considerably and the PO either becomes
mistuned or stops oscillating. This fact is also indicated in [17]
Fig. 13. Flow chart of the design procedure. where it is mentioned that Lf and Cg are the most influential
elements on the operating frequency. We see several issues
with this feature of the circuit:
IV. COMPARISON WITH CONVENTIONAL CLASS-E POWER
1) An important reason for using a Class-E PO, instead of a
OSCILLATOR
Class-E PA, is that in a Class-E PA the frequency of the gate
Fig. 14 illustrates the schematic of the conventional Class-E drive signal is defined by an external oscillator and is
PO [16], [17]. Similar structures to the one proposed in [16] independently-controlled from the Class-E frequency of the
and [17] have been used to convert other classes of PAs to load network. These two frequencies should ideally be equal.
POs [27]–[28]. In this section, we compare our proposed In fact, the purpose of tuning a Class-E PA is to make these
Class-E PO with the conventional one proposed in [16], [17]. two frequencies exactly equal. If, for a reason, any of these
In the circuit shown in Fig. 14, the feedback network frequencies deviates from its desired value, we will see large
mainly consists of Cn1, Cn2, Lf and the transistor’s gate degradations in the efficiency or the output power as
capacitance, Cg. In this circuit, the feedback signal is obtained illustrated in Sec. III.D. Therefore, we resort to feedback
from the voltage across RL which is an attenuated version of theory to convert a Class-E PA to a Class-E PO to minimize
the signal at node X. This signal is further attenuated by the this problem. In the conventional Class-E PO shown in Fig.
capacitive voltage divider consisting of Cn1and Cn2. Therefore, 14, both the load network and the feedback network are high-
in the feedback network, Lf is added to generate a high-Q RLC Q resonant RLC circuits which have steep slopes in their
circuit that can amplify the attenuated feedback signal so that input-to-output phase responses. The transfer function of these
it can drive the transistor. The high-Q RLC circuit consisting RLC circuits should be well-matched in order to sustain a
of Cn1, Cn2, Lf and Cg, has a steep slope in its phase response. phase shift of 360° around the power oscillator loop. Any
Fig. 15(a) depicts the feedback network of the Class-E change in the values of the components of either the feedback
oscillator designed in [17] and Fig. 15(b) shows the phase or the load network can cause large degradation in the output
shifts provided by the this circuit (dotted line) and the phase power or the efficiency, albeit, these degradations are less than
shift of the proposed PO in this paper (solid line). As it is clear those for a conventional Class-E PA.
in Fig. 15(b) when the input frequency of the conventional 2) Since the gate capacitance, Cg, plays a crucial role in the
feedback network changes from 790kHz to 810kHz, its phase proper operation of the conventional Class-E PO, it is
13

20
VDD
16
Vin 12
Rd1 100kΩ
Cn1 8.8nF 8
LF 4
VG 0
H / 2.5Ω
-4
Rg 2.5Ω
Cn2 293nF Rd2 170kΩ -8
-12
Cg 0.81nF
-16
Equivalent impedance -20 Drain Voltage
of the transistor gate -24 Gate Voltage

(a) -28
0 0.5 1 1.5 2 2.5
-20
Time ( s)
Conventional Class-E PO
-40 Proposed Class-E PO Fig.16. Drain waveform of conventional Class-E power oscillator [17]
designed with a FQT13N06L MOSFET.
-60
In our calculations and simulations, we chose an ESR of
-80
2.5Ω for LF (as in [17]) and an ESR of 0.5Ω for L2. We
-100 simulated the designed PO with the calculated values, but the
PO was far from being nominally tuned and satisfying the
-120
ZVS and ZVDS conditions. After much effort, the best drain
-140 waveform that we could achieve is shown in Fig. 16. The
values resulted from calculation and the ones achieved after
-160 fine-tuning in simulation are given in Table V. The drain
790 792.5 795 797.5 800 802.5 805 807.5 810
waveform shown in Fig. 16 fulfills the ZVS condition, but not
Frequency (kHz) the ZVDS condition. In addition, even though we designed the
(b)
PO for the duty cycle of 50 percent, the actual duty cycle of
Fig. 15. (a) Feedback network of the conventional Class-E PO presented in the gate signal is about 60 percent. We believe this is the main
[17], and (b) the phase response of the conventional and proposed feedback
networks.
cause of the circuit not satisfying ZVDS condition and that is
due to the large nonlinearity in the gate capacitance.
important to know its precise value before starting the design As it is clear, in Fig. 16, when the gate signal goes over the
procedure. Cg consists of two portions; a portion due to the Vth of the transistor, it slows down because when the transistor
gate-source capacitance Cgs, and a portion due to the gate- turns on, its gate capacitance considerably increases.
drain capacitance Cgd. Cgs is a very nonlinear voltage- Therefore, even though we set the dc level of the gate drive
dependent capacitor. Also, Cgd experiences different Miller signal slightly larger than Vth to have a duty cycle of 50%, the
multiplication factors as the transistor turns on and off. duty cycle is much larger than 50%. To adjust the duty cycle
Therefore, we cannot simply model the gate capacitance with back to 50%, we should reduce the dc level of the gate signal
a simple linear capacitor [29], [30]. by decreasing the ratio of Rd2/Rd1. However, this causes that
3) Even if we assume Cg is a linear capacitor, its value the dc level become smaller than Vth, which itself causes that
greatly changes from transistor to transistor. This means that the power oscillator does not autonomously start oscillation
for each design and each product, the input impedance of the and if we kick-start the oscillation by an external circuit, the
transistor should be measured and then, based on that, the oscillation could easily die out. Therefore, conflicting
feedback network should be designed and tuned. This is requirements exist on the dc level of the gate signal. As such,
difficult and time-consuming. to minimize the issues regarding the nonlinearity and
To compare the performance of the proposed Class-E PO modeling of the gate capacitance, we suggest using a gate
with that of the conventional one, we designed the driver for the conventional PO as well.
conventional Class-E PO for the same specification mentioned We should clarify that using a gate driver for the
in Sec. II and with the same transistor that we used in our own conventional circuit only removes the nonlinearity issues due
circuit, i.e. FQT13n06. Using simulation, we measured the to the gate capacitance and also simplifies the design
gate impedance of FQT13n06 to be 1.4-j379Ω, which means a procedure; but the main problem of the circuit, which is the
1.4Ω resistor in series with an 525 pF capacitor and then large sensitivity of the feedback phase shift to the values of the
followed the rest of the design procedure as described in [17] components, still exists.
to design the circuit shown in Fig. 14 for the specifications To evaluate the influence of component tolerances on the
listed in Sec II. performance of the proposed and the conventional circuits, we
increased the values of the components that have major effects
14

TABLE V TABLE VII


THE VALUES RESULTED FROM CALCULATION AND SIMULATION FOR THE PERFORMANCE COMPARISON OF PUBLISHED CLASS-E POS.
CIRCUIT OF FIG. 14 This
   " " 1 2 2 Parameter [17] [18] [21] [21] [28]
Component work
() () () () (Ω) () () () (Ω) (Ω) fe (MHz) 0.8 0.8 1.95 2.02 1.97 0.8
Calculated 0.9 3.29 28.7 1.79 50 7.87 320 75.4 100 65 Po (W) 0.96 0.95 4.82 6.8 2.8 0.91
Simulated 0.9 2.5 28.7 1.79 50 7.87 320 70 100 65 η (%) 89 82 89 90.7 89.7 86.2
RL (Ω) 50 50 10 10 9.9 49.4
TABLE VI VDD(V) 4.5 4.5 12 12 12 6
COMPARING THE INFLUENCE OF THE COMPONENT VALUES ON THE QL 13 13 10 10 3 12
PERFORMANCE OF THE CONVENTIONAL AND THE PROPOSED CLASS-E POS FQT MTP IRF IRF IRF IRFR
Δ&' Δ) Δ#$ Transistor
13n06 3055E 530 530 530 120Z
3 5 × 100 3 5 × 100 3 5 × 100
&' ) #$ Class E E E E E E/F3
Circuit Type Conv. Prop. Conv. Prop. Conv. Prop.
Δ = /5% -21.5 +0. 1 -1.0 In fact, if a component value changes, the oscillation
frequency of the PO moves towards the new nominal Class-E
Δ = /5% -26.3 -4.71 +0.26 +0.22 -1.26 -2.25
frequency of the load network; therefore, we call this circuit a
Δ" = /5% -11.0 -3.77 -0.55 +0.56 +0.26 -1.75 self-tuned Class-E PO.
Δ = /5% or
Δ8 = /4.2%
+38.5 +3.77 0.0 0.0 -1.3 -1.25
V. EXPERIMENTAL RESULT
Δ 1 = /3.7% +35.0 0.0 -1.28
To confirm the circuit operation, the designed and simulated
Δ = /5% 0.0 +0.22 0.0 Class-E PO in Sec III.E was built and tested. The calculated
values of the components and their corresponding values in
on the operation of the circuits and simulated both circuits. simulation and in measurement are given in Table IV.
Table VI shows the percent changes in the oscillation Experimental parameters are also shown in Table IV,
frequency, output power and the efficiency of both circuits alongside the simulation results. Experimental waveforms of
when the value of some components increases by five percent. the drain voltage VD, the load voltage VO, the input voltage to
One major issue that we observed with the conventional the gate driver VF, and the gate drive signal VG are shown in
circuit is that, in some cases, if the change in the component Fig. 17, which shows that the drain voltage VD has satisfied
value is large, the oscillator does not oscillate, even if we try ZVS and ZVDS conditions at the turn-on time.
to kick-start it. For example, if the value of LF increases by The frequency and the amplitude of the output signal were
more than 3.7% or if the gate capacitance increases by more measured to be 800kHz. and 9.8V, respectively. This
than 4.2%, the oscillator does not oscillate or does not have corresponds to an output power of 0.960 W (RL=50 Ω). The
sustainable oscillation. Therefore, in Table VI, we increased measured efficiency of the PO was 89%.
Cg by only 4.2% and LF by 3.7% and then compared the result We increased the value of Cn1 by 10% to evaluate the self-
with those with five percent increase in C F' or RF' of the tuning capability of the PO. Fig. 18 shows VD, VO, VF, and VG
after 10% increase in Cn1. Clearly, the VD still achieves the
proposed circuit. ZVS and ZVDS conditions at the turn-on time. The new
Putting the problem of sustainable oscillation aside, e frequency, output power and efficiency are 773 kHz, 940 mW
efficiencies of both circuits are fairly insensitive to the and 89% respectively, indicating that the PO has adjusted its
changes in the component values. However, the variations in frequency of operation to maintain its Class-E operation and
the output power of the conventional circuit could be as high its high efficiency.
as 38.5%, while it is less than 5% in the proposed circuit. Table VII compares the performance of the proposed
We believe that the advantages of the proposed circuit is Class-E PO with other published Class-E POs designed for
due to the fact that the feedback network in the proposed similar specifications and in almost the same frequency range.
circuit is a low-Q RC circuit, whose the phase response, as The measured efficiency of the proposed PO is on par or better
shown in Fig. 15(b), is almost flat around the Class-E than the previously published works. As mentioned in Sec.
frequency and if the Class-E frequency changes for whatever III.E, we could easily increase the efficiency of the proposed
reason, the change in the phase shift provided by the feedback PO by at least 2%, had we chosen a larger KR to dissipate less
network would be very small and the proposed PO stays close ac power in the feedback network; but, our aim in this paper is
to its nominal Class-E operation. In addition, because our to only prove the concept of a Class-E PO with a low-Q RC
feedback network is not a resonant circuit, it does not have a feedback network. It is worth mentioning that the main
specific resonance frequency interfering with the Class-E advantage of the proposed Class-E PO over the existing ones
frequency of the load network. is that its output power has much smaller sensitivities to the
As shown in this section and also in Sec. III.D, the output component variations, a fact that cannot be seen in Table VII.
power and the efficiency of the proposed Class-E PO have
negligible sensitivities to the variations in component values.
15

In Fig. 5, the transfer function of the feedback network can


be expressed by:
RF"
H F' ( jω ) = (42)
RF" + RF' + RF" RF' C F' ( jω )
The phase shift in H F' ( j ω ) can be calculated by:
 RF" RF' C F' ω 
ϕ F = − tan −1  " ' 
. (43)
 FR + R F 
If we define the magnitude of the sinusoidal waveform at
the output of the feedback network as VF , we can write:

Fig. 17. Experimental waveforms of the Class-E PO. VF RF"


= (44)
VX
(RF" + RF'
2
) (
+ RF" RF' C F' ω
2
)
Considering that R F' = α R F" , we can simplify (43) and
(44) to:
 αR" C ' ω 
ϕ F = − tan −1  F F  (45)
 1+ α 
 
and
VF R F"
=
VX (R "
F + α R F" )
2
( (
+ R F" α R F" C F' ω) ) 2

1 cos (ϕ F ) , (46)
= =
(1 + α ) × 1 + tan 2
(ϕ F ) (1 + α )
respectively.
Fig. 18. Experimental waveforms of the Class-E PO when the value of
Cn1 increases by 10%.
B. Analytical Proof of Equations (35) and (36)
' "
The q-factor of the parallel CF − RF section in Fig. 5(b) can
VI. CONCLUSION be expressed by:
In this paper, we presented a new Class-E PO whose QF 1 = ωC F' RF" (47)
feedback network is constructed of a low-Q RC network. As a Therefore, the values of the resistor and capacitor in the series
result, the phase shift of the feedback network does not change ' "
much if the Class-E frequency of the power oscillator changes equivalent circuit of the parallel CF − RF can be calculated
due to the variations in the circuit components. Simulation and using:
experimental evaluations verified that the performance of the ' 1 + Q F2 1 1 + (ωC F' R"F )2
C Fs = C F' = C F' (48)
proposed circuit is much less sensitive to the component Q F2 1 (ωC F' RF" )2
tolerances. We also presented a design procedure for the new
and
Class-E PO and then verified the design procedure with
simulation and experimental measurements. " RF" RF"
RFs = = . (49)
1 + Q 2f 1 1 + (ωCF' RF" ) 2
VII. APPENDIX
respectively. Using (26) and (45), equations (48) and (49) can
A. Analytical Proof of Equations (25) and (27). be simplified to
Consider the Class-E PA shown in Fig. 1. The output power α 2 + (α + 1) 2 tan 2 (ϕ F ) '
'
Po delivered to RL is an input parameter and is equal to: CFs = CF (50)
(α + 1) 2 tan 2 (ϕ F )
1
Po = RL I 2p (40) α2
"
2 RFs = RF" . (51)
where I p is the magnitude of the sinusoidal current flowing α 2 + (α + 1) 2 tan 2 (ϕ F )
into RL . From there, we can find the magnitude of the Now, we calculate the parallel equivalent RC circuit of the
"
sinusoidal voltage at node X as: series connection of RFs + RF' and CFs
'
. The q-factor of this
2 connection can be calculated using:
2 Po  1  (41)
VX = × R L2 +   1
RL  C 2ω  QF 2 = , (52)
' "
ωC Fs ( R Fs + R F' )
16

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[12] Guoxing Wang et al., "A closed loop transcutaneous power transfer for hearing aids. From 2010 to 2014, he was with Synopsys Inc.,
system for implantable devices with enhanced stability," in Toronto, Canada, where he designed high-speed circuits for multi-
proceedings of the IEEE International Symposium on Circuits and standard multi- Gb/s wireline applications. In the summers of 2015
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Self-Tuning Inductive Powering System for Biomedical Implants, electrical links. Since 2014, he has been an assistant professor with
Proc. Eurosensors, vol. 25, pp. 1585-1588, 2011. the Department of Biomedical Engineering, Amirkabir University of
[14] A. Trigui, S. Hached, F. Mounaim, A. C. Ammari, and M. Sawan,
Technology, Tehran, Iran. His current research interests include
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energy transmission with a variable load parameter", ETRI J., vol. 32, which received the 2010 EDN Innovation award for developing the
no. 4, pp. 548-554, 2010. world’s first full SoC for hearing aids.
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oscillator,” IEEE J. Solid-State Circuits, vol. 16, no. 2. pp. 62–66, Maryam Salehi-Sirzar received the B.Sc. degree in biomedical
1981.
engineering from Amirkabir University of Technology, Tehran, Iran,
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Chernov, “Class-E MOSFET tuned power oscillator design procedure,” in 2015 (with honors).
IEEE Trans. Circuits Syst. I Regul. Pap., vol. 52, no. 6, pp. 1138–1147, Her research interests include medical instrumentation and circuit
2005. design for biomedical applications.

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