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    DSD Notes Unit 2 PDF

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    VAISHAKA N RAJ
    The document describes binding in HDL code. Binding (linking) one module to another makes all information in the second module visible to the first. This allows modules to be reused by instantiating them in other modules and connecting their ports.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    DSD Notes Unit 2 PDF

    Uploaded by

    VAISHAKA N RAJ
    67 views18 pages
    The document describes binding in HDL code. Binding (linking) one module to another makes all information in the second module visible to the first. This allows modules to be reused by instantiating them in other modules and connecting their ports.

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    DSD notes Unit 2.pdf

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    The document describes binding in HDL code. Binding (linking) one module to another makes all information in the second module visible to the first. This allows modules to be reused by instantiating them in other modules and connecting their ports.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    67 views18 pages

    DSD Notes Unit 2 PDF

    Uploaded by

    VAISHAKA N RAJ
    The document describes binding in HDL code. Binding (linking) one module to another makes all information in the second module visible to the first. This allows modules to be reused by instantiating them in other modules and connecting their ports.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 18

    Binding

    Binding in HDL is common practice. Binding (linking) segment1 in HDL code


    to segment2 makes all information in segment2 visible to segment1.
    FULL ADDER

    Verilog Description
    module FULL_ADDER (x, y, cin, sum, carry);
    input x, y, cin;
    output sum, carry;
    HA H1 (y, cin, s0, c0);
    HA H2 (x, s0, sum, c1);
    //The above two statements bind module HA
    //to the present module FULL_ADDER
    or (carry, c0, c1);
    endmodule
    module HA (a, b, s, c);
    input a, b; output s, c;
    xor (s, a, b);
    and (c, a, b);
    endmodule
    module dec24_str(
    output [3:0] y;
    input [1:0] a;
    input en);
    and (y[0], ~a[1], ~a[0], en); /* 3-input AND gates */
    and (y[1], ~a[1], a[0], en);
    and (y[2], a[1], ~a[0], en);
    and (y[3], a[1], a[0], en);
    endmodule
    module dec4x16_str(output [15:0] y, input [3:0] a, input en);
    wire [3:0] w;
    dec2x4_str u0(w, a[3:2], en);
    dec2x4_str u1(y[3:0], a[1:0], w[0]);
    dec2x4_str u2(y[7:4], a[1:0], w[1]);
    dec2x4_str u3(y[11:8], a[1:0], w[2]);
    dec2x4_str u4(y[15:12], a[1:0], w[3]);
    endmodule
    STRUCTURAL DESCRIPTION OF A THREE-BIT RIPPLE-CARRY
    ADDER

    module three_bit_adder (x, y, cin, sum, cout);


    input [2:0] x, y;
    input cin;
    output [2:0] sum;
    output cout;
    wire [1:0] carry;
    FULL_ADDER M0 (x[0], y[0], cin, sum[0], carry[0]);
    FULL_ADDER M1 (x[1], y[1], carry[0], sum[1], carry[1]);
    FULL_ADDER M2 (x[2], y[2], carry[1], sum[2], cout);
    endmodule

    module FULL_ADDER (x, y, cin, sum, carry);


    input x, y, cin;
    output sum, carry;
    HA H1 (y, cin, s0, c0);
    HA H2 (x, s0, sum, c1);
    //The above two statements bind module HA
    //to the present module FULL_ADDER
    or (carry, c0, c1);
    endmodule

    module HA (a, b, s, c);


    input a, b; output s, c;
    xor (s, a, b);
    and (c, a, b);
    endmodule

    DATAFLOW DESCRIPTION
    module adr_rcla (x, y, cin, sum, cout);
    input [2:0] x, y;
    input cin;
    output [2:0] sum;
    output cout;
    // I. RIPPLE CARRY ADDER
    wire c0, c1;
    time delay_gt = 4; //Assume 4.0-ns propagation delay for all gates.
    assign #(2*delay_gt) sum[0] = (x[0] ^ y[0]) ^ cin;
    //Treat the above statement as two 2-input XOR.
    assign #(*2delay_gt) sum[1] = (x[1] ^ y[1]) ^ c0;
    assign #(2*delay_gt) sum[2] = (x[2] ^ y[2]) ^ c1;
    assign #(2*delay_gt) c0 = (x[0] & y[0]) | (x[0] & cin) | (y[0] & cin);
    assign #(2*delay_gt) c1 = (x[1] & y[1]) | (x[1] & c0) | (y[1] & c0);
    assign #(2*delay_gt) cout = (x[2] & y[2]) | (x[2] & c1) | (y[2] & c1);
    endmodule

    STRUCTURAL DESCRIPTION OF AN SET-RESET LATCH

    module SR_Latch (R, S, Q, Qbar);


    input R, S;
    output Q, Qbar;
    nor (Qbar, S,Q);
    nor (Q, R, Qbar);
    endmodule
    STRUCTURAL DESCRIPTION OF A D-LATCH WITH ACTIVE LOW
    CLEAR

    Verilog Description
    module D_latchWclr(D, E,clrbar, Q, Qbar);
    input D, E, clrbar;
    output Q, Qbar;
    /* assume 4 ns delay for and gate and nor gate, and 1 ns for inverter */
    //The clear is active low; if clrbar = 0, Q=0
    and #4 gate1 (s1, D, E, clrbar);
    /* the name “gate1” is optional; we could have written and #4 (s1, D, E) */
    and #4 gate2 (s2, Eb, Q, clrbar);
    not #1 (Eb, E);
    nor #4 (Qbar, s1, s2);
    not #1 (Q, Qbar);
    endmodule

    STRUCTURAL DESCRIPTION OF A PULSE-TRIGGERED, MASTER-


    SLAVE D FLIP-FLOP WITH ACTIVE LOW CLEAR

    Verilog Description
    module D_FFMasterWclr(D, clk,clrbar, Q, Qbar);
    input D, clk, clrbar;
    output Q, Qbar;
    not #1 (clkb, clk);
    not #1 (clk2, clkb);
    D_latchWclr D0 (D, clkb, clrbar, Q0, Qb0);
    D_latchWclr D1 (Q0, clk2, clrbar, Q, Qbar);
    endmodule

    TWO-BIT MAGNITUDE COMPARATOR


    Verilog Description
    module compr_2(x, y, xgty, xlty, xeqy);
    input [1:0] x, y;
    output xgty, xlty, xeqy;
    assign xgty = (x[1] & ~ y[1]) | (x[0] & ~ y[1] & ~ y[0]) | (x[0] & x[1] & ~ y[0]);
    assign xlty = (y[1] & ~ x[1] ) | (~ x[0] & y[0] & y[1]) |(~ x[0] & ~ x[1] & y[0]);
    assign xeqy = ~ (xgty | xlty);
    endmodule

    Tristate Buffer
    module decoder2x4 (I, Enable, D);
    input [1:0] I; input Enable;
    output [3:0] D; wire [1:0] Ibar;
    bufif1 (D[0], s0, Enable);
    bufif1 (D[1], s1, Enable);
    bufif1 (D[2], s2, Enable);
    bufif1 (D[3], s3, Enable);
    not (Ibar[0], I[0]);
    not (Ibar[1], I[1]);
    and (s0, Ibar[0], Ibar[1]);
    and (s1, I[0], Ibar[1]);
    and (s2, Ibar[0], I[1]);
    and (s3,I[0],I[1]);
    endmodule
    ARRAY OF INSTANCES OF PRIMITIVES

    and gate [7 : 4 ] (a, b, c);

    and gate [7] (a[3], b[3], c[3]),


    gate [6] (a[2], b[2], c[2]),
    gate [5] (a[1], b[1], c[1]),
    gate [4] (a[0], b[0], c[0]);
    Syntax: and gate[mm : nn](a, b, c);

    Byte Comparator
    CLOCKED RS FLIP FLOP

    Verilog Description
    module JK_FF (J, K, clk,clrbar, Q, Qbar);
    input J, K, clk, clrbar;
    output Q, Qbar;
    wire s1, s2;
    and #4 (s1, J, Qbar);
    and #4 (s2, Kb, Q);
    not #1 (Kb, K);
    or #4 (DD, s1, s2);
    D_FFMasterWclr D0 (DD, clk,clrbar, Q, Qbar);
    endmodule

    module D_FFMasterWclr(D, clk,clrbar, Q, Qbar); /* no need to rewrite this module here if it has been
    already attached to the above module (JK_FF). */
    input D, clk, clrbar;
    output Q, Qbar;
    not #1 (clkb, clk);
    not #1 (clk2, clkb);
    D_latchWclr D0 (D, clkb,clrbar, Q0, Qb0);
    D_latchWclr D1 (Q0, clk2,clrbar, Q, Qbar);
    endmodule

    module D_latchWclr(D, E,clrbar, Q, Qbar); /* no need to rewrite this module here if it has been
    already attached to the above module (JK_FF). */
    input D, E, clrbar;
    output Q, Qbar; /* assume 4 ns delay for and gate and nor gate, and 1 ns for inverter */ //The clear is
    active low; if clrbar = 0, Q=0 and #4 gate1 (s1, D, E, clrbar); /* the name “gate1” is optional; we
    could have written and #4 (s1, D, E) */
    and #4 gate2 (s2, Eb, Q, clrbar);
    not #1 (Eb, E);
    nor #4 (Qbar, s1, s2);
    not #1 (Q, Qbar);
    endmodule

    Delays with Tri state gates

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