Foxconn 848M02 Rev A

5 4 3 2 1
Foxconn Precision Co. Inc.

D
848M02 Schematic Fab A
Date: 2004/6/25
D
PAGE INDEX
01. Index Page 20. ICH5-3
02. Topology 21. LAN RTL8101L & USB
03. Rest Map 22. LAN_POWER
C 04. Clock Distribution 23. LAN Connector C
05. Power Delivery Map 24. FWH

06. ClockGen ICS952603 25. USB Connectors
07. Voltage Regulator Down 10 26. AC'97 Codec
08. 2.5V Power and 5V_DUAL 27. Power/MISC Connectors
09. 1.5V Power 28. PCI Slots 1,2
10. VTT_DDR Power 29. PCI Slot 3
11. LGA775 -1 30. Super IO ITE8712
12. LGA775 -2 31. Keyboard/Mouse/FAN
B
13. Springdale-GMCH-1 32. Serial/Print Ports B
14. Springdale-GMCH-2 33. GPIO Summary

15. Springdale-GMCH-3 34. Jumper Setting Summary
16. DDR Channel A 35. Modify list
17. AGP Connector
18. ICH5-1
19. ICH5-2 & IDE Connecter
A A
FOXCONN PCEG
Title
Index Page
Size Doc ument Number Rev
C 848M02 F
Dat e: Friday , A ugus t 27, 2004 S heet 1 of 34

5 4 3 2 1
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5 4 3 2 1
Intel
VRD 9/10
Prescott processor
3 Phase PWM LGA775 ZIP Socket
D D
400/533/800 FSB CK-409 Clock
AGP 4X / 8X 4x/8x AGP DDR 400/333/266 Channel A DDR

AGP Solt DIMM1
GMCH
848P
DDR 400/333/266
Channel B DDR
932 Pin FC-BGA DIMM1
C C
Back Panel
USB2.0 Port 1
USB2.0 Port 2
USB2.0 Port 3
uATX Form Factor
USB2.0 Port 4 PCI Interface
PCI Slot 1
Front Panel ICH5 PCI Slot 2
USB2.0 Port 5 PCI Slot 3
USB2.0 Port 6
USB2.0 Port 7 460 Pin mBGA 10/100 BT LAN
USB2.0 Port 8 RTL8100C
B B
IDE CONN 1
IDE CONN 2
S-ATA0
S-ATA1
Super I/O
ITE8712F
PS2 Parallel Floppy Firmware HUB AC 97 Code 2.3

Keyboard / Mouse Serial Drive Connector 2MB ALC 655
A A
FOXCONN PCEG
Title
Size Doc ument Number

Topology Rev
Cus t om 848M02 F
5 4 3 2 1

5 4 3 2 1
CPU
CPU_PWRGD
CPURSTJ
D D
ATX
Power
PSON GMCH
PWRGD_ATX PWRGD_3V CPURSTJ
PS_On
C C
PCIRSTJ
ICH5
AGP 4X / 8X
ICH_PWRGD
AGP Solt
PCIRSTJ Buffer
uATX Form Factor
KBRST
PWRGD_3V PCI Slot 1
PCI Slot 2
Front Panel
SLP_S3# PCI Slot 3
B B
FR_RST System_RST
RSMRST#
PWRBTN#
Buffer
IDE CONN 1
SW_ON SW_ON#
IDE CONN 2
PANSWH#
POWBTN FWH
Super IO
PSIN
KBRST
PWR_ON# PSON
RSMRST#
A A
FOXCONN PCEG
Title
Reset Map
C 848M02 F

5 4 3 2 1

5 4 3 2 1
14.318MHz
CPU
100/133/200 MHz Diff Pair

D D
100/133/200 MHz Diff Pair
66 MHz Channel A DDR

AGP 4x/8x
SpringDale DIMM1
48 MHz
48 MHz Channel B DDR

DIMM1
66 MHz
C C
CK409-ICS952603
14.318Mhz
66 MHz
33 MHz
48 MHz
33 MHz FWH
ICH5
33 MHz
PCI LAN
RTL8101L
B B
33 MHz
PCI Slot 1
32.768KHz
33 MHz
PCI Slot 2
33 MHz
PCI Slot 3
AC'97
Super I/O
33 MHz
100 MHz Diff Pair SRC
A A
FOXCONN PCEG
Title
Clock Distribution
C 848M02 F

5 4 3 2 1

5 4 3 2 1
SPD
D D
5V_SYS 1.5V VCCQ

> REGULATOR > VCC, CORE LOG,
1.5V 2.46A
ATX
ATX SPS
12V
P/S
SPD
> VCCAGP, AGP I/O
1.5V 1.5A
5
V 5
3
.
+
1
-
1 + > V TTFSB
0.8375V~1.6V
5V _D UAL
DDR 2 DIMMS:
S
B
V 3
V
2
V
2
V
1
2
V
2.4A
> 2.6V >
VCCDAC, DAC I/O
1.5V 65mA
6.00A
M PG A 478
2.6V 2D 6V _STR VCCSM, DDR I/O
12V _VRM C O R E _C PU_SYS C O R E _C PU_SYS

> REGULATOR > 2.6V 2.8A
> VRD 10 > 0.8375V~1.6V 60A

VCCGPIO
V CC_VID D D R _V TT_STR DDR VTT
> M IC5258 VCCVID
> 1.2V 30mA 2D 6V _STR
> 1.3V
REGULATOR > 1.3V
3D 3V_SYS
>
3.3V
30mA
ICH 5 2.1A
5V _D UAL
P W R G _A TX
C V CC3_3: V _C PU _IO C
3D 3V_SYS 1.1V~1.85V
> 3.3V
610mA
45mA > 3D 3V_SYS
CLK_GEN
> 3.3V
250mA
5V _SB 3D 3V_SB
A M S1086
> V C C SUS3_3
R E SUME:
V CC1_5:
C ORE LOGIC: 5V _SB
3.3V 70mA 1.5V 970mA
> 5V_SYS > SUPER I/O
3D 3V_SYS > 5V
> 3.3V
> OR V C C _RTC
3 VOLTS
B A TTERY > > V CCRTC
3D 3V_SYS FWH CORE
> 3.3V
24mA
3D 3V_SYS PCI PER SLOT:
5V_SYS > 5V_SYS 5V _D UAL
>
USB POWER
12V_SYS > 3.3V

5V
7.6A
5.0A PWRG_ATX 5V
-12V_SYS > 12V
-12V
0.5A
0.1A 5V _SB 5V _D UAL
3D 3V_SB > 3.3Vaux
0.375A > PS2 KB/MS POWER
B
> 5V
B
12V_SYS 5V _A U DIO
AUDIO
VREG > AC' 97 AUDIO CODEC
A5V 70mA
3D 3V_SYS
> 3.3V 10mA
5V _SB 3D 3V_SB
A M S1086
A A
FOXCONN PCEG
Title
Power Delivery Map

C 848M02 F

5 4 3 2 1

5 4 3 2 1
D D
3D3V_SYS 3D3V_SYS 3D3V_SYS
1
FB1 FB2 FB3
FB L0805 300 Ohm FB L0805 300 Ohm FB L0805 300 Ohm
2
3D3V_CLK
U1
3 48
VDD_REF VDD_A
10
VDD_PCI0
16
VDD_PCI1
40 24
VDD_CPU VDD_48
27
VDD_3V66
10nF
BC1
1uF
BC2
10nF
BC3
10nF
BC5
10nF
BC7
10nF
BC9
0.1uF
BC10
34
VDD_SRC
4.7uF
BC11
0.1uF
BC12
4.7uF
BC13
0.1uF
BC14
DUMMY DUMMY
3D3V_CLK 166_P _GMCH

39 R1 1 2 33
CPU0 CK _166M_P _GMCH 13
38 166_N_GMCH R2 1 2 33
CPU0# CK _166M_N_GMCH 13
42 166_P _CPU R3 1 2 33 CK _200M_P _CPU 11
1
CPU1 41 1 66_N_CP U R4 1 2 33
CPU1# CK _200M_N_CPU 11
1K
R5
45 166_P _ITP
CPU_ITP 166_N_ITP
44
C CPU_ITP# C
36 100_P _ICH R8 1 2 33
2
SRC CK _100M_P _ICH 18
35 1 0 0_N_ICH R9 1 2 33
SRC# CK _100M_N_ICH 18
20
1
RST#/PD#
49.9
R10
49.9
R11
49.9
R12
49.9
R13
R14
R15
49.9
R16
49.9
R17
VCCP 3D3V_CLK
DUMMY DUMMY
2
1
1
220
R18
10K
R19
7 33M_LAN R 20 1 2 33
*FS_C/PCIIF0 CK _33M_LAN 21
32 8 DISCONNECT THE 1394CLK FS_D
16, 31 S MB _DA TA _MAIN SDATA *FS_D/PCIIF1
31 9 33M_P CI1 RN1
2
16, 31 S MB _CLK _MAIN SCLK *FS_E/PCIIF2

12 7 8 CK _33M_P CI1 28
PCI0 13 33M_P CI2 5 6 CK _33M_P CI2 28
PCI1 33M_P CI3
14 3 4
PCI2 CK _33M_P CI3 29
15 33M_FWH 1 * 2
PCI3 CK _33M_FWH 24
33 18 33_4 R 21 1 2 33
VTT_PWRGD# PCI4 CK _33M_ICH 20
19 33_5 33 R 22 1 2 33
PCI5 CK _33M_SIO 30
4
Q1 XTAL_IN 66_0 R 23 33
5 30 1 2 CK _66M_GMCH 13
XTAL_OUT 3V66_0 29 66_1 R 24 33
1 2 CK _66M_AGP 17
3V66_1 66_2 R 25 33
46 26 1 2
IREF *3V66_2/MODE CK _66M_ICH 18
MMB T3904 25 3V 66_3-V CH R 26 1 2 33
3V66_3/VCH CK _48M_SIO 30
X1 6
XTA L-14.318MHz VSS_REF
11
VSS_PCI0 48_DOT R 27
17 21 1 2 33 CK _48M_GMCH 13
VSS_PCI1 DOT48 48_USB R 28
1 2 23 22 1 2 33 CK _48M_ICH 18
VSS_48 USB48
28
VSS_3V66
37
VSS_SRC
1
43 1 FS_A R 29 1 2 33
VSS_CPU **FS_A/REF_1 CK _14M_ICH 18
475
R30
47 2 FS_B R 31 1 2 33
VSS_A **FS_B/REF_0 A DU14MCLK 26
0.1uF
BC943
2
* 150K Internal Pull-up

B B
BC15
27pF
BC16
27pF
**150K Internal Pull-down

D UMMY
ICS 952603
SM Bus Address :1101-0010
3D3V_CLK
2
4
6
8
R N712
10K
R35
1K
8P 4R0603
+/-5%
*
1
3
5
7
R 36 1 2 10K FS_A
12, 13 FS B SEL0
R 37 1 2 10K FS_B
12, 13 FS B SEL1
12 FS B SEL2
1
1K
R38
2
3V 66_3-V CH
A A
FOXCONN PCEG
Title
Clock Generator CK-409
C 848M02 F

5 4 3 2 1

5 4 3 2 1
5V _SYS
* R 501
4.7
+/-5%
R 0603
D D
B C501 12V _S YS V IN
4. 7uF
* 10V , X7R, +/-10%
C1206 B C503
U 51 4. 7uF
*
7
IS L6566CR 16V , X5R, +/-10%
D
38 33 B C504 C 1206
VCC
D
11, 30 V ID4 VID4 PVCC1 30 R503 2.2 B C505 1 uF Q101 Q102
11, 30 V ID3 39
*
*
VID3 BOOT1 R0603 +/-1% 0. 1uF 16V , X7R, +/-10%
11, 30 V ID2
11, 30 V ID1
40
1
VID2
VID1
* C 0805 G D UMMY
2 C0603 A OD412 G V CCP
11, 30 V ID0 VID0
3 31 25V , X7R, +/-10% R504 1
S
11, 30 V I D5
*
DACSEL/VID5 UGATE1
1
35 +/-1% R 0603 A OD412
S
PGOOD
10K
R719
B C670 37 L31 Chok e Coil 1. 0uH
*
V RM_EN ENLL
0. 1uF P HA SE1
* 16V , X7R, +/-10% PHASE1
29
+/-1%
D
C0603
* R0603
2
32 R 506 1K Q103
D
*
ISEN1 R 0603 +/-5% Q104 2.2 E C101 E C102 E C103 E C104 E C105 TC3 TC4 E C119 E C120
B C508 34 R508 0 G R 507
* 100uF
* 100uF
* *
*
note: 7/6-chang PWRGD_VRM pullup VCCP to 12V R509 1K 5. 6nF LGATE1 +/-5% R0603 A OD412
8
* 3300uF
** 3300uF
** 3300uF
** 3300uF
** 3300uF
*
*
* *
+/-5% C0603 50V , X7R, +/-10% COMP DUMMY B C510 C TD C TD 560uF 560uF
add R601 to 330 G
S
R0603 B C509 1nF D UMMY DUMMY
7/7 del Power Good VRM for timing
10pF DUMMY 12V _S YS A OD412 * 50V , X7R, +/-10%
S
50V , NP O, +/-5% C0603
C0603 9
FB V IN DUMMY D UMMY
DUMMY D UMMY
R 510 1K 10 24
*
R 0603 +/-5% VDIFF PVCC2/EN_PH3 B C512 B C514
D
560pF 26 R511 2.2 B C515 1 uF 4. 7uF
* *
D
*
B C511 R512 BOOT2/NC R0603 +/-1% 0. 1uF 16V , X7R, +/-10% Q105 16V , X5R, +/-10%
*
*
C0603 C 0805 DUMMY Q106 C1206

50V , X7R, +/-10% +/-5% R0603 D UMMY C0603 G
V CCP 750 25V , X7R, +/-10% R514 1 A OD412
27 G
*
UGATE2/PWM3
1
12 +/-1% R 0603
S
VSEN
10K
R717
A OD412 L32 Chok e Coil 1. 0uH
*
S
C 28 P HA SE2 C
PHASE2/NC
11 +/-1%
D
RGND
5V _S YS
* E C106 E C107 E C108 TC5
D
R0603
2
25 R 516 1K Q107 Q108 TC6
*
ISEN2/ISEN3 2.2
R 518 200K 6 R 0603 +/-5%
* ** ** * * * 100uF
*
OFST R 517
* R 520 23 R519 0 G DUMMY
*
R0603 +/-5% 0 LGATE2/NC +/-5% R0603 A OD412 3300uF 3300uF 3300uF C TD C TD
G
R0603 B C518 D UMMY
S
+/-5% A OD412 1nF 100uF D UMMY
*
S
DUMMY 12V _SYS 50V , X7R, +/-10%
C0603
V IN D UMMY
36
FS
* R 521
150K B C519 5
+/-5% 10nF REF
R 0603 * 25V , X7R, +/-10% PVCC3
18
B C520 B C522
D
5V _S YS C0603 21 R522 2.2 B C523 1uF 4. 7uF
* *
D
*
BOOT3 R 0603 +/-1% 0. 1uF 16V , X7R, +/-10% Q109 Q110 16V , X5R, +/-10%
R 523 1K 4 * C0805 C 1206
*
R 0603 +/-5% VRM10 C0603 D UMMY

G
R 524 2.2K 13 20 25V , X7R, +/-10% R525 1 A OD412 G
*
1
R 0603 +/-5% OCSET UGATE3 +/-1% R0603
S
10K
R718
A OD412
S
14 22 L33 Chok e Coil 1. 0uH
*
ICOMP PHASE3 P HA SE3
+/-1%
D
* R0603 TC1 TC2
D
2
R526 0 R 527 33K 15 19 R528 1K Q111 E C115 * * E C116 * 100uF * 100uF E C109 E C100
*
ISUM ISEN3 2.2

+/-5% R0603 R0603 +/-5% R0603 +/-5% Q112 560uF 560uF
* * * * * *
GND
16 17 R 530 0 G DUMMY R529 C TD C TD E C118
*
B C524 IREF LGATE3 +/-5% R0603 A OD412 D UMMY DUMMY 3300uF 3300uF E C117
G
R T1 10K R 531 0 10nF A OD412 B C525 560uF 560uF
*
*
S
41
*
R0603 +/-5% +/-5% R0603 25V , X7R, +/-10% 1nF DUMMY

DUMMY
*
S
T
DUMMY DUMMY C 0603 50V , X7R, +/-10%

C0603 DUMMY D UMMY
D UMMY
B B
B C526 22nF R 532 39K P HA SE1

*
* * *
C0603 25V , X7R, +/-10% R0603 +/-5%
R 533 39K P HA SE2

R0603 +/-5%
R534 39K P HA SE3

R0603 +/-5%
V IN
B C921 0. 1uF
12V _SYS B C925 0. 1uF

12V _VRM
V TT_OUT_RIGHT
R 39 680 5V _S B _SYS
V TT_P W RGD
V TT_P W RGD 12
* R515
2
5
C N 100
A TX12V _P1_2X2
+/-5% R 0603
* R 43
1K
10.7K
+/-1%
P W R4NW P 1 +/-5% R0603
R 0603 For EMI
1
L4 Chok e Coil 1. 2uH V RM_EN

*
V RM_EN
B C527 R 52
D
V IN
0. 1uF Q2
* B
*
25V , X7R, +/-10% * E C111 E C114 * E C112 * E C113 B C528 2. 74K MMBT3904 Q3
C0603
* * R 0603 S OT23_BEC * R535
E
1500uF 1500uF 1500uF 1500uF 3. 3uF

+/-1%
* R 58
22. 1K
G
2N7002
1.4K
+/-1%
change bc527 from 10u to 0.1u 0704 +/-1% R0603
S
R0603
A A
FOXCONN PCEG
Title
VRD10.1
C 848M02 F
Dat e: Saturday, August 28, 2004 S heet 7 of 34

5 4 3 2 1

5 4 3 2 1
2D5V_STR Regulator
3D3V _S YS 12V _SYS 5V _S B_SYS

D D
* E C20 R 93
2
5V _S B_SYS 470uF
12V _S YS R 92
10V , +/-20% 47K
10K +/-5%
1
CE 35D80H200 R0402
*
S
D5 R 0402
1
+/-5%
B A T54C G
3D3V _SB
D
Q18
1
N TD40N03R Q19
D
D6
B120 G
* R 94
220
* R 95
220
2N7002
C
S
2
R 96
5V _S B _SYS +/-5% +/-5%
*
R0603 R0603 Q20 B
D
MMB T3904 P W RG_ATX 27
R 97 Q21
E
2
1K
47K G R 0402
+/-5% N TD40N03R (2.64V) +/-5%
D
5V _DUAL
S
R0603 Q22
1
2D5V _S TR
3
G U6
LM431A CZ 1 R 98
*
C
R 99
2N7002 B C922
B Q23 560 E C21 E C22 0. 1uF
*
18 S LP _S4J MMB T3904 R 100

10K
* 1000uF
10V , +/-20%
* 1000uF
10V , +/-20%
E
1K * CE 35D80H200 CE 35D80H200
C R0603 C
+/-5%
3D3V _S YS 5V _SYS
B C923 0. 1uF
B C924 0. 1uF
For EMI
5V_DUAL Circuit 3D3V_SV Regulator

SB3.3V
B
5V _DUAL Vref=1.25V 3D3V _SB B
5V _DUA L
U7
12V _SYS 3
5V _S B _SYS Vin
5V _S YS 5V _S B_SYS 4 2
4 Vout
R101 1
Q24 ADJ
IF USE 1086 DUMMY R103〞CHANGE THE R104 TO 0
8 1 1.5K R 102
A IC1086 OHM
D1
S1
7 2 PWOK+ 1K
D1
G1
D UMMY
6 3 Q25
D2
S2
5 4 P W OKJ U8 A ME 1085
3 2
D2
G2
ADJ/GND
VIN VOUT
BC57
2N7002 Q26
Vout=Vref(1+R2/R1)+IadjR2
EC24
A O4600
P W RG_A TX R1 is Up Resister.
1
P W RG_ATX 27 R 103
Q27
Iadj=50uA
1uF
2N7002
1
301
220uF
Vref=1.25V
2
5 4
D4 G
6 3
7 D3 S3 2
D2 S2
8 1
D1 S1 R 104
499
S i4410DY
FDS8958A
A + E C25
7A,30V. 28mohm @Vgs=10V for N-Channel A
-5A,-30V. 80mohm @Vgs=-4.5 for P-Channel
1000uF
0.1uF
BC58
FOXCONN PCEG
Title
Power 2.5V-5VDUAL-3.3SB
C 848M02 F

5 4 3 2 1

5 4 3 2 1
3D3V _S YS
12V _S YS
1D5V_CORE Regulator
1
3D3V _SB
220uF
EC26
0.1uF
BC59
2
B C60
0. 1uF
1
D D
12V _SYS
R 105
910
D
2
U 9A
8
LM358M Q28
3 +
note: 7/6-chang del D7 reg 1 G
2 N TD40N03R
-
S
4
1 2
change R105&R108 to 910 ohm 080204
R 107
B C61 1K
0. 1uF
B C62 B C63
2.2uF
BC64
10nF 0. 1uF
1
DUMMY
R 108
DUMMY
DUMMY
910
2
DUMMY
1uF
BC65
12V _SYS
D
U 9B
8
LM358M Q29
5 +
7 G
6 N TD40N03R 1D5V _CORE
-
S
4
C 1 2 C
2
R 110 R 109
1
1. 54K B C66 1K
0.1uF
BC67
0. 1uF
1000uF
EC27
1000uF
EC28
BC68
D UMMY B C69 B C70
2
10nF 0. 1uF
D UMMY
D UMMY DUMMY
PROCHOTJ Signal
B B
A A
FOXCONN PCEG
Title
Power 1.5V
C 848M02 F

5 4 3 2 1

5 4 3 2 1
PSC=1.2V
D D
FSB_VTT Regulator
GMCH VTT Source 1.6A and Sink 600mA
change Q30 2N3904 to MMBT3904 FOR FOOTPRINT 0705
del Q30 0707

1 D5V _CORE
FS B _VTT V CCP
12V _SYS
3D3V _SB
2
4
6
8
RN2
0.1uF
BC71
D UMMY
0.1uF
BC72
Y 5V + 20%~-80% D UMMY -12V _SYS
R 111
*
1uF
BC73
C change R111 from 1k ohm to 910 ohm 0707 910 C
1
3
5
7
+/-1% 0
D
R 0603 +/-5%
Q31 8P 4R0603
U 10A
8
LM358M U10B R 112 G
8
3 LM358M N TD40N03R
+
0.1uF
BC920
1 5 1K
S
+
2 - 7 1 2
6
E
-
R 113 R 114 220
4
523 1 2 B Q32
1
change R113from 562 ohm to 523ohm 0707 +/-1%
R 0603 2N2907A
220uF
EC29
4.7uF
BC75
2
-12V _SYS
-12V _SYS
DUMMY
Y 5V + 20%~-80%
0.1uF
BC76
B B
VTT_DDR Regulator
2D5V _S TR 3D3V _S YS V TT_DDR
DEL THE BOOTSELECT CIRCUIT FOR ADAPTING TO THE 775CPU DESIGNGUIDE 0705
7/7:DEl CAP
C1 + E C30
1
U 11 DUMMY
1 5
2
0. 1uF VIN VCNTL1

6
A VCNTL2 A
7
R115 VCNTL3
8
VCNTL4
10K 4
VOUT
3 2 7/7:change EC33 1000uf to 470uf
1
REFEN GND C2
1
R116 RT9173 E C32 E C33

10K 0. 1uF
2
D UMMY 470uF 470uF

FOXCONN PCEG
2
B C78
Title
7/7:DEl 1uf CAP
Power 1.25V-GMCH VTT
C 848M02 F

5 4 3 2 1

5 4 3 2 1
HDJ[ 63. . 0] HA J[ 31. . 3]

HDJ[ 63. . 0] 13 13 HA J[ 31. . 3]
2 OF 7 U 12A
U12B H A J3 L5 D2
H A J4 A03# ADS# H A DS J 13
P6 C2
HDJ0 H D J32 H A J5 A04# BNR# H B N RJ 13
B4 G16 M5 D4
HDJ1 D00# D32# H D J33 H A J6 A05# HIT# TP _RS PJ H I TJ 13
C5 E15 L4 H4 TP1
HDJ2 D01# D33# H D J34 H A J7 A06# RSP#
A4 E16 M4 G8
HDJ3 D02# D34# H D J35 H A J8 A07# BPRI# H B P RIJ 13
C6 G18 R4 B2
HDJ4 D03# D35# H D J36 H A J9 A08# DBSY# HDB SYJ 13
D A5 G17 T5 C1 D
HDJ5 D04# D36# H D J37 H A J10 A09# DRDY# H DRDY J 13
B6 F17 U6 E4
HDJ6 B7 D05# D37# F18 H D J38 H A J11 T4 A10# HITM# AB2 H I E R RJ H I TMJ 13
HDJ7 D06# D38# H D J39 H A J12 A11# IERR#
A7 E18 U5 P3
HDJ8 D07# D39# H D J40 H A J13 A12# INIT# I N I TJ 18, 24
A10 E19 U4 C3
HDJ9 A11 D08# D40# F20 H D J41 H A J14 V5 A13# LOCK# E3 H L OCK J 13
H D J10 D09# D41# H D J42 H A J15 A14# TRDY# T P _B INITJ H TR
TP2 DY J 13
B10 E21 V4 AD3
H D J11 D10# D42# H D J43 H A J16 A15# BINIT#
C11 F21 W5 G7
H D J12 D8 D11# D43# G21 H D J44 N4 A16# DEFER# F2 TP _E DRDY J H D E FE RJ 13
TP3
H D J13 D12# D44# H D J45 RSVD1 EDRDY# TP _MCE RRJ TP4
B12 E22 P5 AB3
H D J14 D13# D45# H D J46 13 HRE QJ[ 4. . 0] H R E QJ0 RSVD2 MCERR#
C12 D22 K4
H D J15 D14# D46# H D J47 H R E QJ1 REQ0# TP _A PJ0 TP5
D11 G22 J5 U2
H D B IJ0 A8 D15# D47# D19 H D B IJ2 H R E QJ2 M6 REQ1# AP0# U3 TP _A PJ1 TP6
13 H D B IJ0 DBI0# DBI2# H D B IJ2 13 REQ2# AP1#
C8 G20 H R E QJ3 K6
13 H D S TB NJ0 DSTBN0# DSTBN2# H D S TB NJ2 13 REQ3#
B9 G19 H R E QJ4 J6 F3 H B R0J
13 HDS TB P J0 DSTBP0# DSTBP2# HDS TB P J2 13 HA J[ 31. . 3] REQ4# BR0# H B R0J 13
R6 G3 TE S THI_8
13 HA J[ 31. . 3] 13 HA DS TB J0 ADSTB0# TESTHI08
H D J16 G9 D20 H D J48 G5 G4 TE S THI_9
H D J17 F8 D16# D48# D17 H D J49 PCREQ# TESTHI09 H5 TE S THI_10
H D J18 D17# D49# H D J50 H A J17 TESTHI10
F9 A14 AB6
H D J19 D18# D50# H D J51 H A J18 A17# TP _DP J0 TP7
E9 C15 W6 J16
H D J20 D19# D51# H D J52 H A J19 A18# DP0# TP _DP J1 TP8
D7 C14 Y6 H15
H D J21 D20# D52# H D J53 H A J20 A19# DP1# TP _DP J2 TP9
E10 B15 Y4 H16
H D J22 D21# D53# H D J54 H A J21 A20# DP2# TP _DP J3 TP 10
D10 C18 AA4 J17
H D J23 D22# D54# H D J55 H A J22 A21# DP3#
F11 B16 AD6
H D J24 D23# D55# H D J56 H A J23 A22# H GTLRE F
F12 A17 AA5 H1
H D J25 D24# D56# H D J57 H A J24 A23# GTLREF
D13 B18 AB5
H D J26 D25# D57# H D J58 H A J25 A24#
E13 C21 AC5 G23
H D J27 D26# D58# H D J59 H A J26 A25# RESET# H C P URS TJ 13
G13 B21 AB4
H D J28 F14 D27# D59# B19 H D J60 H A J27 AF5 A26# B3
H D J29 D28# D60# H D J61 H A J28 A27# RS0# H R S J0 13
G14 A19 AF4 F5
H D J30 D29# D61# H D J62 H A J29 A28# RS1# H R S J1 13
F15 A22 AG6 A3
H D J31 G15 D30# D62# B22 H D J63 H A J30 AG4 A29# RS2# H R S J2 13
H D B IJ1 G11 D31# D63# H D B IJ3 H A J31 A30#
C20 AG5
13 H D B IJ1 DBI1# DBI3# H D B IJ3 13 A31#
G12 A16 TP _LA G775_P IN_AH4 AH4
13 H D S TB NJ1 DSTBN1# DSTBN3# H D S TB NJ3 13 TP11 A32#
E12 C17 TP _LA G775_P IN_AH5 AH5
13 HDS TB P J1 DSTBP1# DSTBP3# HDS TB P J3 13 TP12 A33#
TP _LA G775_P IN_AJ5 AJ5
TP13 A34#
TP _LA G775_P IN_AJ6 AJ6 HBR0J
TP14
AC4
A35# TBD CRB 0.7: 220 ohm, 5%
C TBD CP U_S oc ket V TT_OUT_RIGHT FS B _VTT AE4 RSVD3 DG 0.51: 62 ohm, 5% C
Pin D23 TBD AD5
RSVD4
CRB 0.7: test point TP_VCCPLL Pin AL2 PROCHOT# 13 HA DS TB J1 ADSTB1#
Pin AM5 CRB 0.7: pull up to VTT_OUT_RIGHT
CRB 0.7: test point TP_VID6 DG/611A: example VR thermal monitor circuit R118 GTLREF voltage should be 0.67*FSB_VTT R 117 1 OF 7
100 12 mils width, 15 mils spacing 100 GTLREF voltage should be 0.67*FSB_VTT CP U_S oc ket
+/-1% divider should be within 1.5" of the GTLREF pin +/-1% 12 mils width, 15 mils space
R0603 caps should be placed near CPU pin R0603 caps should be placed near MCH pin
H GTLRE F H GTLRE F_MCH

H GTLRE F_MCH 12, 13
10V, X5R, +/-10%

* R120
210 B C79 B C80
* R 121 B C711 B C712
+/-1% * 1uF * 220pF 210 * 1uF * 220pF
R0603 10V , Y 5V , + 80%/-20% 50V , X7R, +/-10% +/-1% 50V , X7R, +/-10%
C0603 C0603 R0603 C0603 C0603
Place at CPU end of route
FS B _VTT
R 122 62 TE S THI_0
TE S THI_0 12
**
R 0603 +/-5%
R 123 62 TE S THI_2_7
3 OF 7 R 0603 +/-5%
U 12C
P2 F26 TE S THI_0
18 S MIJ SMI# TESTHI00
K3 W3 TE S THI_1
18 A 20MJ A20M# TESTHI01
R3 P1 TE S THI_11
18 F E R RJ FERR#/PBE# TESTHI11 V TT_OUT_RIGHT
K1 W2 TE S THI_12
18 I N TR
L1
LINT0 TESTHI12
F25
TBD V TT_OUT_LEFT
18 N MI LINT1 TESTHI02
N2 G25 Pin AK6, G6 Place at CPU end of route
18 I G N NE J IGNNE# TESTHI03
M3 G27 refer to CRB 0.7 R125 62 H B R0J
B 18 S TP CLKJ B
* *
STPCLK# TESTHI04 R0603 +/-5%
G26
TESTHI05 R 124 62 H I E R RJ Place at CPU end of route
12 H V CCA A23 G24
*
VCCA TESTHI06 TE S THI_2_7 R0603 +/-5% R128 100 +/-1% C P U_P W RG

12 HV S SA B23 F24
TP 15 TP _V CCP LL VSSA TESTHI07 RS V D_AK6 R0603
D23 AK6
RSVD5 RSVD10 R N601
C23 G6 RS V D_G6
12 H V CCIOP LL VCCIOPLL RSVD11 R 129 DUMMY RS V D_AK6
*
1 2 TE S THI_9
* *
L2 +/-5% 3 4 TE S THI_8
SLP# CP US LP J 18
V ID0 AM2 AH2 R 722 5 6 TE S THI_10
7,30 V ID0 VID0 RSVD12
V ID1 AL5 N1 130 P R OCHOTJ 7 8 TE S THI_1
7,30 V ID1 VID1 PWRGOOD C P U_P W RG 18
V ID2 AM3 AL2 +/-1%
7,30 V ID2 VID2 PROCHOT# P R OCHOTJ 13 FS B _VTT
V ID3 AL6 M2 R0603 8P 4R0603
7,30 V ID3 VID3 THERMTRIP# THE RMTRIP J 18 62
V ID4 AK4 R134 62 TE S THI_11
7,30 V ID4
***
V ID5 VID4 R 225 1 2 62 T HE RMTRIP J R0603 +/-5%
7,30 V ID5 AL4
TP 16 TP _V ID6 AM5 VID5 A13 HCOMP 0 R 226 1 2 62 F E RRJ R135 +/-5% 62 TE S THI_12
RSVD6 COMP0 HCOMP 1 R0603 +/-5%
T1
COMP1 HCOMP 2 R136 DUMMY RS V D_G6
G2
COMP2 HCOMP 3 +/-5%
F28 R1
6 CK _200M_P _CPU BCLK0 COMP3 V TT_OUT_LEFT
6 CK _200M_N_CPU G28
BCLK1 10 mils width R 126 62 H C P URS TJ
B C81
N5
*
S K TOCCJ RSVD13 R0603 +/-5% 2 2pF
30 S K TOCCJ
AE8
SKTOCC# RSVD14
AE6
C9
TBD R137
7 mils spacing
100 HCOMP 2 * 50V , NP O,+/-5%
**
RSVD15 G10 Pin N5 ~ Pin J3 R0603 +/-1% C 0603

RSVD16 R138 100 HCOMP 3
30 THE RMDA AL1 D16 CRB 0.7: connections ok?
THERMDA RSVD17 R0603 +/-1%
30 THE RMDC
AK1 A20
THERMDC RSVD18
TP 17 TP _V CCS E NSE AN3 V TT_OUT_RIGHT
TP 18 TP _V SSSENSE AN4 VCCSENSE E23 TP _RS V D_CP U_N5 TP19
VSSSENSE RSVD19
*
AN5 E24 TP _RS V D_CP U_AE6 TP20 R139 680 V ID0
V CC_S E NSE VCC_MB_REG RSVD20
AN6 F23 TP _RS V D_CP U_C9 TP21 +/-5%
V S S _SENSE VSS_MB_REG RSVD21
H2 TP _RS V D_CP U_G10 TP22 RN3
Changed pin name RSVD22 TP _RS V D_CP U_D16 TP23 V ID3
J2 8 7
RSVD23 TP _RS V D_CP U_A20 TP24 V ID2
F29 from RSV J3 6 5
RSVD9 RSVD24 V ID4
4 3
2 * 1 V ID1
Y1
BOOTSELECT V2 L L_ID0 680
LL_ID0 L L_ID0
AA2 TP _LL_ID1 HCOMP 0 R140 60. 4 R 141
+/-5%
*680 V ID5
**
A LL_ID1 TP25 R0603 +/-1% +/-5% A

HCOMP 1 R142 60. 4
R0603 +/-1%
CP U_S oc k et
10 mils width
7 mils spacing
FOXCONN PCEG
Title
LGA775 -1
848M02 A

5 4 3 2 1

5 4 3 2 1
V CCP V CCP
U12E 5 OF 7 V CCP U 12G 7 OF 7

AG22 AK12
K29 VCCP1 VCCP93 AH22 U 12F 6 OF 7 H22 D5
VCCP2 VCCP94 VSS126 VSS211
AM26 T29 AF9 AL23 H21 A9
VCCP3 VCCP95 VCCP185 VSS41 VSS127 VSS212
AL8 AM14 AF22 A12 H20 D3
VCCP4 VCCP96 VCCP186 VSS42 VSS128 VSS213 V CCP
AE12 AM25 AH11 L25 H19 B1
VCCP5 VCCP97 VCCP187 VSS43 VSS129 VSS214 Place these caps. inside CPU socket
AE11 AE9 AJ14 J7 H18 B5
VCCP6 VCCP98 VCCP188 VSS44 VSS130 VSS215 10uF/SDK caps. co-layout
W23 Y29 AH19 AE28 AB7 B8
W24 AK25 AH29 AE29 H17 AJ4
W25 AK19 AH27 K5 AJ24 AE26
C1206
BC82
C1206
BC83
C1206
BC84
C1206
BC85
C1206
BC86
C1206
BC87
C1206
BC88
C1206
BC89
C1206
BC90
C1206
BC91
C1206
BC92
C1206
BC93
C1206
BC94
C1206
BC95
C1206
BC96
C1206
BC97
C1206
BC98
C1206
BC99
T25 AG15 AG28 J4 AM17 AH1
D Y28 J22 AL26 AE30 AC3 E29 D
AL18
AC25 VCCP12
VCCP13
VCCP104
VCCP105
T24
AG21
AM12
J24 VCCP194
VCCP195
VSS50
VSS51
AN20
AF10
H14
P28 VSS136
VSS137
VSS221
VSS222
V7
C13 * * * * * * * * * * * * * * * * * *
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
6.3V,X5R,+/-10%
10uF
W30 AM21 J13 AE24 V6 AK24
Y30 J25 T28 AM24 AK2 AB30
AN14 VCCP15 VCCP107 U30 W28 VCCP197 VSS53 AN23 P27 VSS139 VSS224 L6
AD28 AL21 J12 H9 P26 L7
Y26 AG25 J27 H8 AM28 AB29
AC29 VCCP18 VCCP110 AJ18 AG19 VCCP200 VSS56 H13 AJ13 VSS142 VSS227 M1
M29 J19 AL9 AC6 W4 AB28
U24 AH30 AD30 AC7 P25 E8
J23 J15 AF21 AH6 AJ20 AG20
AC27 VCCP22 VCCP114 AG12 Y24 VCCP204 VSS60 C16 W7 VSS146 VSS231 AN17
AM18 AJ22 AK14 AM16 P23 AB27
AM19 J20 J9 AE25 AG13 AB26
AB8 VCCP25 VCCP117 AH18 M27 VCCP207 VSS63 AE27 AG16 VSS149 VSS234 AN16
AC26 AH26 AF14 AJ28 AG17 M7
J8 VCCP27 VCCP119 W27 J30 VCCP209 VSS65 AJ7 C7 VSS151 VSS236 AB25
J28 AL25 AG18 F19 Y2 AB24
T30 AN8 AA8 AH13 L30 AB23
AM9 AH14 AG8 AD7 L29 N3
AF15 U27 AL29 AH16 D15 AA30
VCCP32 VCCP124 VCCP214 VSS70 VSS156 VSS241 VTT_OUT_RIGHT note: 7/6-change termination 49.9 to RN702 47
AC8 T23 AD29 AK17 AL27 F4
AE14 R8 W8 E17 Y7 AG10
VCCP34 VCCP126 VCCP216 VSS72 VSS158 VSS243 51 Place BPM termination near CPU
N23 AK22 AH8 AH17 L27 AE13 R N 702
VCCP35 VCCP127 VCCP217 VSS73 VSS159 VSS244 8P 4R0603
W29 AN29 N24 AH20 AA29 AF30
VCCP36 VCCP128 VCCP218 VSS74 VSS160 VSS245 +/-5% H T DO
U29 AG11 AN22 AE5 N6 H28 8 7
VCCP37 VCCP129 VCCP219 VSS75 VSS161 VSS246 HB P M4J
AC24 AK26 J14 AH23 N7 F7 6 5
AC23 VCCP38 VCCP130 J10 K26 VCCP220 VSS76 AE7 AA28 VSS162 VSS247 AF29 HB P M3J
4 3
VCCP39 VCCP131 VCCP221 VSS77 VSS163 VSS248 HB P M5J
Y23 AJ15 AF19 AM13 AN13 AF28 2 * 1
AN26 AG26 N8 AH24 AA27 G1
AN25 VCCP41 VCCP133 AN9 AF12 VCCP223 VSS79 AJ30 AA26 VSS165 VSS250 AF27 R147 49. 9 +/-1% HB P M1J
**
AN11 AH15 M28 AJ10 P4 AF26
VCCP43 VCCP135 VCCP225 VSS81 VSS167 VSS252 R148 49. 9 +/-1% HB P M0J
AN18 AF18 AK9 AF3 AA25 AF25
Y27 AL15 AK5 AA24 AN28
Y25 VCCP45 VCCP137 J26 VSS83 AJ16 P7 VSS169 VSS254 AN27
VCCP46 VCCP138 VSS84 VSS170 VSS255
AD24 J18 C10 AF6 E26 AF24
VCCP47 VCCP139 VSS1 VSS85 VSS171 VSS256
AE23 J21 D12 AK29 V30 AF23
C AE22 VCCP48 VCCP140 AG27 AM7 VSS2 VSS86 AJ17 R2 VSS172 VSS257 AG24 C
AN19 AK15 C24 F22 V29 AF17
V8 AF11 K2 AH3 V28 AN24
K8 VCCP51 VCCP143 AD23 C22 VSS5 VSS89 AK10 R5 VSS175 VSS260 H3
AE21 AM15 AN1 AM10 V27 AN7
AM30 AF8 B14 F16 R7 P24
AE19 AK21 K7 AJ23 E20 AE20
AC30 AG30 AE16 F13 AN10 AE17
VCCP56 VCCP148 VSS10 VSS94 VSS180 VSS265 VTT_OUT_RIGHT
AE15 AJ21 B11 AG7 V25 E27
M30 AM11 AL10 F10 T3 T7
K27 AL11 AK23 L26 V24 R30
M24 VCCP59 VCCP151 AJ11 H12 VSS13 VSS97 AD4 V23 VSS183 VSS268 AJ27 B C100 B C101
AN21 K30 AF7 H11 T6 AB1
7
5
3
1
*
T8 AL14 AK7 L24 AL7 AM4 0. 1uF 0. 1uF
AC28
N25
VCCP63 VCCP155
AN30
AH25
H7
E14
VSS17 VSS101
L23
AM23
E25
U1
VSS187 VSS272
V26
AA23
* R 149
49. 9
R N 711
51
AE18 VCCP64 VCCP156 AL12 L28 VSS18 VSS102 A15 R29 VSS188 VSS273 AL28 +/-1%
VCCP65 VCCP157 VSS19 VSS103 VSS189 VSS274 8P 4R0603
W26 AJ9 Y5 AH10 R28 AF20 R 0603
VCCP66 VCCP158 VSS20 VSS104 GTLRE F_SEL VSS190 VSS275 +/-5%
AD25 AK11 E11 H29 R27 AG23
8
6
4
2
M8 VCCP67 VCCP159 AG14 AL16 VSS21 VSS105 B24 R26 VSS191 VSS276
VCCP68 VCCP160 VSS22 VSS106 VSS192 HTMS
N30 N29 AL24 L3 R25 place TDO termination near XDP connector
AD26 VCCP69 VCCP161 AL30 AK13 VSS23 VSS107 H27 U7 VSS193
VCCP70 VCCP162 VSS24 VSS108 VSS194 H TD I
AJ26 AJ25 AL3 A21 R24
AM29 VCCP71 VCCP163 AH9 D21 VSS25 VSS109 AE2 R23 VSS195 HB P M2J
VCCP72 VCCP164 VSS26 VSS110 VSS196 H TCK
M25 J29 AL20 AJ29 P30
VCCP73 VCCP165 VSS27 VSS111 VSS197
M26 J11 D18 A24 V3
L8 VCCP74 VCCP166 K25 AN2 VSS28 VSS112 AK27 P29 VSS198 V1 place TCK/TDI/TMS terminations near CPU within 1.5 inch
VCCP75 VCCP167 VSS29 VSS113 VSS199 RSVD25 H T RS TJ
U25 P8 AK16 AK28 AF16 F6 place TRSTJ termination anywhere on route
VCCP76 VCCP168 VSS30 VSS114 VSS200 RSVD26
Y8 K23 AK20 B20 AE10 T2
AJ12 AL19 AM27 AM20 AF13 Y3
AD27 AM8 AM1 H26 H6 AE3
U23 T26 AL13 B17 A18 W1
M23 N28 AL17 H25 A2 E7
AG29 VCCP81 VCCP173 AH12 C19 VSS35 VSS119 H24 E2 VSS205 RSVD31 B13
N27 AL22 E28 AA3 D9 D14
AM22 AN15 AH7 AA7 C4 E6
U28 AJ8 AK30 H23 A6 D1
K28 VCCP85 VCCP177 U26 D24 VSS39 VSS123 AA6 D6 VSS209 RSVD35 E5
B VCCP86 VCCP178 VSS40 VSS124 VSS210 RSVD36 B
U8 AJ19 H10
VCCP87 VCCP179 VSS125 CP U_S oc ket
AK18 T27
VCCP88 VCCP180 CP U_S oc k et
AD8 AK8
VCCP89 VCCP181 FS B _VTT
K24 AN12
VCCP90 VCCP182 PLL Supply Filter
AH28 AG9
VCCP91 VCCP183
AH21 N26
VCCP92 VCCP184
For supporting to LGA775 P4EE CPU
1
CP U_S oc k et 125mA 125mA
L8 L9
12V _SYS V CCP L0805 10uH L0805 10uH
0805 0805
+/-10% +/-10%
* R 746 Notes:
2
FS B _VTT R745 619 H V CCIOP LL 1. Cap. should be within 600 mils of the VCCA and VSSA pins
11 H V CCIOP LL
10K +/-1% B C102 2. VCCA route should be parallel and next to VSSA route
R 0603 1uF
U 1 2D 4 OF 7
* R0603 *
10V , X5R, +/-10%
* R 154
3. Min. 12 mils trace from the filter to the processor pins
4. The inductors should be close to the cap.
D
H TCK +/-5% C0603 0
AE1 A29
H TD I TCK VTT1 Q120 +/-1%
AD1 B25
H T DO TDI VTT2 R0603 E C34
AF1 B29
TDO VTT3
HTMS
H T RS TJ
AC1
AG1 TMS VTT4
B30
C29
G
2N7002 H V CCA
*
33uF
25V , +/-20%
TRST# VTT5 11 H V CCA
A26 HVSSA CE 20D50H110
S
VTT6 11 HV S SA
B27 ESL <= 5 nH, ESR < 0.3 ohm
VTT7 H GTLRE F_MCH 11, 13
HB P M0J AJ2 C28
HB P M1J BPM0# VTT8
AJ1 A25
HB P M2J AD2 BPM1# VTT9 A28 3D3V _S YS
HB P M3J BPM2# VTT10
AG2 A27
AF2 C30
AG3 A30
BPM5# VTT13
6, 18, 27 I C H_S Y S _RS TJ

I C H_S Y S _RS TJ AC2 VTT14
C25
C26
* R 751
249
DBR# VTT15 +/-1%
C27
VTT16
AK3
AJ3
ITPCLKOUT0 VTT17
B26
D27
GTLRE F_SEL R0603
* R 752
110
D
ITPCLKOUT1 VTT18 D28 +/-1%

FS B SEL0 VTT19 Q121 R 0603
G29 D25
A 6,13 FS B SEL0 FS B SEL1 BSEL0 VTT20 A
6,13 FS B SEL1
H30 D26
FS B SEL2 BSEL1 VTT21
G30 B28 G
6 FS B SEL2 BSEL2 VTT22 D29 2N7002
VTT23
D30
S
VTT24 TE S THI_0
AM6 V TT_P W RGD 7 11 TE S THI_0
VTTPWRGD
VTT_OUT1
AA1
J1
V TT_OUT_RIGHT
V TT_OUT_LEFT
V TT_OUT_RIGHT
V TT_OUT_LEFT
* R 753
VTT_OUT2
0.1uF
BC440
F27 R 155 1 2 3D3V _S YS 62

VTT_SEL
CP U_S oc ket DUMMY
Place at CPU end of route
+/-5%
R 0603
FOXCONN PCEG
Title
LGA775 -2
848M02 A

5 4 3 2 1

5 4 3 2 1
U 1 3D
GCB E J0 Y7 AC6 A D_S TB0

D 17 G CB E J0 GCBE0 GADSTBF0 A D_S TB0 17 D
GCB E J1 W5 AC5 A D_S TB 0J
17 G CB E J1 GCBE1 GADSTBS0 A D_S TB 0J 17
GCB E J2 AA3
17 G CB E J2 GCBE2 GA D[ 31. .0] 17
GCB E J3 U2 AE6 GA D0
17 G CB E J3 GCBE3 GAD0 GA D1
AC11
U13A HDJ[ 63. . 0] GFRA MEJ U6 GAD1 AD5 GA D2
11 HA J[ 31. . 3] HDJ[ 63. . 0] 11 17 GFRA MEJ GFRAME GAD2
GS W ING_GMCH H4 AE5 GA D3
H A J3 HDJ0 A GP RE F_GMCH 6 CK _66M_GMCH GDE V S ELJ GCLKIN GAD3 GA D4
D26 B23 AB4 AA10
H A J4 D30 HA3# HD0# E22 HDJ1 17 GDE V S ELJ G IRD YJ V11 GDEVSEL GAD4 AC9 GA D5
H A J5 HA4# HD1# HDJ2 17 G IRDYJ G TR DY J GIRDY GAD5 GA D6
L23 B21 AB5 AGP AB11
H A J6 HA5# HD2# HDJ3 17 G TR DY J GS TOPJ GTRDY GAD6 GA D7
E29 D20 W11 AB7
H A J7 HA6# HD3# HDJ4 17 GS TOPJ GP A R GSTOP GAD7 GA D8
B32 B22 AB2 AA9
H A J8 K23 HA7# HD4# D22 HDJ5 17 GP A R G RE QJ N6 GPAR/ADD_DETECT GAD8 AA6 GA D9
HA8# HD5# 17 G RE QJ GREQ GAD9
0.1uF
BC103
10nF
BC104
0.1uF
BC105
10nF
BC106
H A J9 C30 B20 HDJ6 G GNTJ M7 AA5 GA D10
H A J10 HA9# HD6# HDJ7 17 G GNTJ GGNT GAD10 GA D11
C31 C21 W10
H A J11 J25 HA10# HD7# E18 HDJ8 GRCOMP AC2 GAD11 AA11 GA D12
H A J12 HA11# HD8# HDJ9 GRCOMP GAD12 GA D13
B31
HA12# HD9#
E20 1D5V_CORE 17 GS W ING_GMCH
AC3
GVSWING GAD13
W6
H A J13 E30 B16 H D J10 AD2 W9 GA D14
H A J14 HA13# HD10# H D J11 17 A GP RE F_GMCH GVREF GAD14 GA D15
B33 D16 V7
H A J15 HA14# HD11# H D J12 GAD15
J24 B18 R10
H A J16 HA15# HD12# H D J13 17 R B FJ GRBF A D_S TB1
F25 B17 R9 V4 A D_S TB1 17
1
H A J17 HA16# HD13# H D J14 17 W B FJ GWBF GADSTBF1 A D_S TB 1J
D34 E16 M4 V5 A D_S TB 1J 17
H A J18 HA17# HD14# H D J15 R 156 17 P IP E J DBI_HI GADSTBS1
C32 D18 M5
HA18# HD15# 17 DB I_LO DBI_LO GA D[ 31. .0] 17
H A J19 F28 G20 H D J16 226 AA2 GA D16
H A J20 HA19# HD16# H D J17 ST0 GAD16 GA D17
C34 F17 N3 Y4
H A J21 HA20# HD17# H D J18 17 ST0 ST1 GST0 GAD17 GA D18
J27 E19 N5 Y2
2
H A J22 HA21# HD18# H D J19 W IS W ING_S P D 17 ST1 ST2 GST1 GAD18 GA D19
H A J23
G27
F29
HA22# HD19#
F19
J17 H D J20
0.8V 17 ST2
N2
GST2 GAD19
W2
Y5 GA D20
1
H A J24 E28 HA23# HD20# L18 H D J21 18 HI[ 10. . 0] HI0 AF5 GAD20 V2 GA D21
H A J25 HA24# HD21# H D J22 R 157 HI1 HI0 GAD21 GA D22
H27 G16 AG3 W3
H A J26 HA25# HD22# H D J23 147 HI2 HI1 GAD22 GA D23
K24 G18 AK2 U3
HA26# HD23# HI2 GAD23
0.1uF
BC107
H A J27 E32 F21 H D J24 HI3 AG5 T2 GA D24
HA27# HD24# HI3 GAD24
10nF
BC108
HUB
H A J28 F31 F15 H D J25 HI4 AK5 T4 GA D25
2
H A J29 HA28# HD25# H D J26 H I_V S W ING HI5 HI4 GAD25 GA D26
G30 E15 AL3 T5
H A J30 HA29# HD26# H D J27 H I_V RE F HI6 HI5 GAD26 GA D27
J26 E21 AL2 R2
H A J31 G26 HA30# HD27# J19 H D J28 HI7 AL4 HI6 GAD27 P2 GA D28
HA31# HD28# D UMMY HI7 GAD28
G14 H D J29 D UMMY HI8 AJ2 P5 GA D29
HD29# H D J30 HI9 HI8 GAD29 GA D30
E17 AH2 P4
C 11 HRE QJ[ 4. . 0] H R E QJ0 B29 HD30# K17 H D J31 H I 10 AJ3 HI9 GAD30 M2 GA D31 C
HREQ0# HD31# HI10 GAD31
10nF
BC109
10nF
BC110
H R E QJ1 J23 J15 H D J32 HI_S TB F AH5
H R E QJ2 HREQ1# HD32# H D J33 W IV RE F_S PD 18 HI_S TB F HI_S TBS HISTRF SB_STB
H R E QJ3
L22
C29 HREQ2# HD33#
L16
J13 H D J34
0.35V 18 HI_S TBS
AH4
HISTRS GSBSTBF
U11
T11 S B _S TBJ
SB_STB 17
S B _STBJ 17
1
H R E QJ4 HREQ3# HD34# H D J35 H I_RCOMP _MCH GSBSTBS
J21 F13 AD4
HREQ4# HD35# HI_RCOMP S B A [ 7..0] 17
B30 F11 H D J36 R 158 H I_V S W ING AE3 R6 SBA0
11 HA DS TB J0 HADSTB0# HD36# H D J37 H I_V RE F HI_SWING GSBA0# SBA1
D28 E13 113 AE2 P7
11 HA DS TB J1 HADSTB1# HD37# HI_VREF GSBA1#
0.1uF
BC111
10nF
BC112
K15 H D J38 R3 SBA2
HD38# H D J39 GSBA2# SBA3
B7 G12 AK7 R5
2
6 CK _166M_P _GMCH HCLKP HD39# CI0 GSBA3#
FSB
C7 G10 H D J40 AH7 U9 SBA4

6 CK _166M_N_GMCH HCLKN HD40# H D J41 CI1 GSBA4# SBA5
L15 AD11 U10
B19 HD41# E11 H D J42 AF7 CI2 GSBA5# U5 SBA6
11 HDS TB P J0 HDSTBP0# HD42# D UMMY D UMMY CI3 GSBA6#
C19 K13 H D J43 AD7 T7 SBA7
11 H DS TB NJ0 HDSTBN0# HD43# CI4 GSBA7#
H D B IJ0 C17 J11 H D J44 AC10
11 H D B IJ0 DINV0# HD44# CI5
CSA
L19 H10 H D J45 AF8 H3
11 HDS TB P J1 HDSTBP1# HD45# CI6 DDCA_DATA
K19 G8 H D J46 AG7 F2
11 H DS TB NJ1 H D B IJ1 HDSTBN1# HD46# H D J47 CI7 DDCA_CLK
11 H D B IJ1 L17 E9 AE9 pull low the VGA signal pin according to the 848p demo sch 0703
DINV1# HD47# H D J48 CI8
G9 B13 AH9 F4
11 HDS TB P J2 HDSTBP2# HD48# H D J49 CI9 RED
11 H DS TB NJ2 F9 E14 AG6 E4
H D B IJ2 L14 HDSTBN2# HD49# B14 H D J50 AJ6 CI10 RED# H6
11 H D B IJ2 DINV2# HD50# CISTRF GREEN
D12 B12 H D J51 AJ5 G5
VGA
11 HDS TB P J3
E12 HDSTBP3# HD51# B15 H D J52 CISTRS GREEN# H7
11 H DS TB NJ3 H D B IJ3 HDSTBN3# HD52# H D J53 R 159 1 BLUE
11 H D B IJ3 C15 D14 1D5V_CORE 2 52.3 AG2 G6
DINV3# HD53# C13 H D J54 W IS W ING_S P D AF2 CI_RCOMP BLUE#
HD54# H D J55 W IV RE F_S PD CI_SWING
F27 B11 AF4 G3
11 H A DS J ADS# HD55# H D J56 CI_VREF HSYNC
D24 D10 E2
11 H TR D Y J HTRDY# HD56# H D J57 VSYNC
G24 C11 G4
11 HDRDY J DRDY# HD57# H D J58 6 CK _48M_GMCH DREFCLK
L21 E10 AP8 D2
11 H D E FE RJ DEFER# HD58# H D J59 EXTTS# REFSET
E23 B10 TP 26 AJ8
11 H ITMJ HITM# HD59# H D J60 ICH_SYNC#
K21 C9 FS B SEL0 6,12 AK4 A3
11 H I TJ HIT# HD60# H D J61 20, 24,30 I C H _P CIRS TJ RSTIN# NC_1
E25 B9 FS B SEL1 6,12 A33
11 H L OCK J HLOCK# HD61# H D J62 NC_2
B24 D8 AG10 A35
11 H B R0J
B28
BREQ0# HD62#
B8 H D J63 1D5V_CORE AG9
RESERVED_1 NC_3
AF13
1
11 H B N RJ
B26 BNR# HD63# B C113 AN35 RESERVED_2 NC_4 AF23
11 H B P RIJ BPRI# R 160 R 161 12pF RESERVED_3 NC_5
E27 AP34 AJ12
11 HDBSYJ DBSY# 2K 2K RESERVED_4 NC_6
11 H R S J0
G22 L20 P R OCHOTJ 11 AR1 AN1
RS0# PROCHOT# R 162 1 2 51. 1 H I_RCOMP _MCH RESERVED_5 NC_7
C27 AP2
11 H R S J1
B27 RS1# NC_8 AR3
B B
2
11 H R S J2 RS2# NC_9
E8 L13 AR33
11 H C P URS TJ P W RGD_3VG CPURST# BSEL0 GRCOMP NC_10
AE14 L12 R 163 1 2 43. 2 AR35
PWROK# BSEL1 NC_11
1 B2
1
H D_RCOMP POST1 NC_12

E24 2 B25
H D _S W ING HDRCOMP R 164 R 165 POST2 NC_13
C25 3 B34
HDSWING 2. 49K 2. 49K POST3 NC_14
F23 4 C1
11, 12 HGTLRE F_MCH HDVREF POST4 NC_15
5 C23
POST5 NC_16
6 C35
2
2
2
GMCH 848P 7 POST6 NC_17 E26

R 166 POST7 NC_18
8 M31
POST8 NC_19
20
R25
NC_20
0.1uF
BC114
GMCH 848P
U13_1
V CCP
1D5V_CORE
P W RGD_3VG
Ver A to Ver B HD_SWING 18, 24,27 P W RGD_3V
update GMCH_VTT replace note: 7/6-del u17 and gate ;R169 0
with VCCP
1
1 U13_A U 13_C
R 168
226
R 167
301
2
Clip_2P Clip_2P
H I_V S W ING 18
H D _S W ING
Pin Name Pin # Decouping cap N/A N/A
1
Heat s ink
VTTFSB A15 0.22uF R 170 grant s dale1210
1
147
VTTFSB A21 0.47uF
0.1uF
B C116 BC115
R 171 0. 1uF R e s erved
VCC_DDR E35 0.47uF
2
100
A A
VCC_DDR R35 0.22uF
2
VCCA_DDR AL35 0.1uF

VCCA_DDR AA35 0.1uF
VCC_DDR AR31 0.1uf H I_V RE F 18
VCC_DDR AR21 0.22uF
1
VCC_DDR AR15 0.1uF R 172

113 FOXCONN PCEG
VCC_AGP AG1 0.1uF
0.1uF
BC117
Title
VCC_AGP Y1 0.1uF GMCH-1
2
BaseOn Intel WW29 Update Size Doc ument Number Rev

C 848M02 F

5 4 3 2 1

5 4 3 2 1
U 13C
U13B
M_DQS _A [ 7..0] 16 AG31 AF15
16 M_MA A _A[12..0] M_MAA_A0 M_DQS_A0 SMAA_B0 SDQS_B0
AJ34 AN11 M_DQM_A [7..0] 16 AJ31 AG11
M_MAA_A1 SMAA_A0 SDQS_A0 M_DQM_A0 SMAA_B1 SDM_B0
AL33 AP12 M_DA TA _A [63..0] 16 AD27 AJ10
M_MAA_A2 SMAA_A1 SDM_A0 M_DA TA_A0 SMAA_B2 SDQ_B0
AK29 AP10 AE24 AE15
M_MAA_A3 SMAA_A2 SDQ_A0 M_DA TA_A1 SMAA_B3 SDQ_B1
D AN31 AP11 AK27 AL11 D
AL30 AM12 AG25 AE16
M_MAA_A5 AL26 SMAA_A4 SDQ_A2 AN13 M_DA TA_A3 AL25 SMAA_B5 SDQ_B3 AL8
AL28 AM10 AF21 AF12
AN25 AL10 AL23 AK11
M_MAA_A8 AP26 SMAA_A7 SDQ_A5 AL12 M_DA TA_A6 AJ22 SMAA_B8 SDQ_B6 AG12
AP24 AP13 AF29
M_MAA_A10 SMAA_A9 SDQ_A7 SMAA_B10
AJ33 M_DQS _A [ 7..0] 16 AL21 AG13
M_MAA_A11 AN23 SMAA_A10 AP15 M_DQS_A1 AJ20 SMAA_B11 SDQS_B1 AG15
SMAA_A11 SDQS_A1 M_DQM_A [7..0] 16 SMAA_B12 SDM_B1
M_MAA_A12 AN21 AP16 M_DQM_A1
SMAA_A12 SDM_A1
M_DA TA _A [63..0] 16 AE27 AE17
16 M_MA B _A[5..1] M_MAB_A1 M_DA TA_A8 SMAB_B1 SDQ_B8
AL34 AP14 AD26 AL13
M_MAB_A2 AM34 SMAB_A1 SDQ_A8 AM14 M_DA TA_A9 AL29 SMAB_B2 SDQ_B9 AK17
M_MAB_A3 SMAB_A2 SDQ_A9 M_DA TA_A10 SMAB_B3 SDQ_B10
AP32 AL18 AL27 AL17
M_MAB_A4 SMAB_A3 SDQ_A10 M_DA TA_A11 SMAB_B4 SDQ_B11
AP31 AP19 AE23 AK13
SMAB_A4 SDQ_A11 SMAB_B5 SDQ_B12
DDR Channel B
M_MAB_A5 AM26 AL14 M_DA TA_A12 AJ14
SMAB_A5 SDQ_A12 M_DA TA_A13 SDQ_B13
AN15 W27 AJ16
SDQ_A13 SWE_B# SDQ_B14
DDR Channel A
AB34 AP18 M_DA TA_A14 W31 AJ18
16 M_W E_AJ SWE_A# SDQ_A14 M_DA TA_A15 SCAS_B# SDQ_B15
Y34 AM18 W26
16 M_CA S _AJ SCAS_A# SDQ_A15 SRAS_B#
AC33 AG21
16 M_RA S _AJ SRAS_A# M_DQS _A [ 7..0] 16 SDQS_B2
AP23 M_DQS_A2 AE21
16 M_B S _A[1..0] SDQS_A2 M_DQM_A [7..0] 16 SDM_B2
M_BS_A0 AE33 AM24 M_DQM_A2 Y25
M_BS_A1 SBA_A0 SDM_A2 SBA_B0
AH34 AA25 AE19
SBA_A1 M_DA TA _A [63..0] 16 SBA_B1 SDQ_B16
AP22 M_DA TA_A16 AE20
SDQ_A16 M_DA TA_A17 SDQ_B17
AA34 AM22 U26 AG23
16 M_S CS _A0J SCS_A0# SDQ_A17 M_DA TA_A18 SCS_B0# SDQ_B18
Y31 AL24 T29 AK23
Y32 AN27 V25 AL19
W34 AP21 W25 AK21
16 M_S CS _A3J SCS_A3# SDQ_A20 AL22 M_DA TA_A21 SCS_B3# SDQ_B21 AJ24
16 M_S CK E _A[3..0] M_S CKE_A0 SDQ_A21 M_DA TA_A22 SDQ_B22
AL20 AP25 AK19 AE22
M_S CKE_A1 SCKE_A0 SDQ_A22 M_DA TA_A23 SCKE_B0 SDQ_B23
AN19 AP27 AF19
M_S CKE_A2 AM20 SCKE_A1 SDQ_A23 AG19 SCKE_B1 AH27
SCKE_A2 M_DQS _A [ 7..0] 16 SCKE_B2 SDQS_B3
M_S CKE_A3 AP20 AM30 M_DQS_A3 AE18 AJ28
SCKE_A3 SDQS_A3 M_DQM_A [7..0] 16 SCKE_B3 SDM_B3
AP30 M_DQM_A3
SDM_A3
AK32 M_DA TA _A [63..0] 16 AG29 AK25
16 CK _M_133M_P _DDR0_A
AK31 SCMDCLK_A0 AP28 M_DA TA_A24 AG30 SCMDCLK_B0 SDQ_B24 AH26
16 CK _M_133M_N_DDR0_A SCMDCLK_A0# SDQ_A24 M_DA TA_A25 SCMDCLK_B0# SDQ_B25
AP17 AP29 AF17 AG27
16 CK _M_133M_P _DDR1_A SCMDCLK_A1 SDQ_A25 M_DA TA_A26 SCMDCLK_B1 SDQ_B26
AN17 AP33 AG17 AF27
C 16 CK _M_133M_N_DDR1_A
N33 SCMDCLK_A1# SDQ_A26 AM33 M_DA TA_A27 N27 SCMDCLK_B1# SDQ_B27 AJ26 C
16 CK _M_133M_P _DDR2_A SCMDCLK_A2 SDQ_A27 M_DA TA_A28 SCMDCLK_B2 SDQ_B28
N34 AM28 N26 AJ27
AK33 AN29 AJ30 AD25
16 CK _M_133M_P _DDR3_A
AK34 SCMDCLK_A3 SDQ_A29 AM31 M_DA TA_A30 AH29 SCMDCLK_B3 SDQ_B30 AF28
AM16 AN34 AK15
16 CK _M_133M_P _DDR4_A SCMDCLK_A4 SDQ_A31 SCMDCLK_B4
AL16 M_DQS _A [ 7..0] 16 AL15 AD29
16 CK _M_133M_N_DDR4_A SCMDCLK_A4# M_DQS_A4 SCMDCLK_B4# SDQS_B4
P31 AF34 M_DQM_A [7..0] 16 N31 AC31
16 CK _M_133M_P _DDR5_A SCMDCLK_A5 SDQS_A4 M_DQM_A4 SCMDCLK_B5 SDM_B4
P32 AF31 N30
16 CK _M_133M_N_DDR5_A SCMDCLK_A5# SDM_A4 SCMDCLK_B5#
M_DA TA _A [63..0] 16 AE30
GMCH_V RE F_A M_DA TA_A32 GMCH_V RE F_B SDQ_B32
E34 AH32 AP9 AC27
SMVREF_A SDQ_A32 M_DA TA_A33 SMVREF_B SDQ_B33
AG34 AC30
S MXRCOMP AK9 SDQ_A33 AF32 M_DA TA_A34 S MY RCOMP AA33 SDQ_B34 Y29
SMXRCOMP SDQ_A34 M_DA TA_A35 SMYRCOMP SDQ_B35
AD32 AE31
S MXRCOMPVOH AN9 SDQ_A35 AH31 M_DA TA_A36 S MY RCOMP VOH R34 SDQ_B36 AB29
SMXRCOMPVOH SDQ_A36 M_DA TA_A37 SMYRCOMPVOH SDQ_B37
AG33 AA26
S MXRCOMPVOL SDQ_A37 M_DA TA_A38 S MY RCOMPVOL SDQ_B38
AL9 AE34 R33 AA27
SMXRCOMPVOL SDQ_A38 AD34 M_DA TA_A39 SMYRCOMPVOL SDQ_B39
SDQ_A39
U30
M_DQS _A [ 7..0] 16 SDQS_B5
V34 M_DQS_A5 U31
SDQS_A5 M_DQM_A [7..0] 16 SDM_B5
W33 M_DQM_A5
SDM_A5
M_DA TA _A [63..0] 16 AA30
AC34 M_DA TA_A40 SDQ_B40 W30
AB31 U27
SDQ_A41 V32 M_DA TA_A42 SDQ_B42 T25
V31 Subject: New DDR Tuning Requirement AA31
AD31 V29
SDQ_A44 SDQ_B45
SDQ_A45
AB32 M_DA TA_A45
M_DA TA_A46
> The following are the updated DDR SDQ_B46
U25
U34 R27
SDQ_A46 M_DA TA_A47 tuning guidelines for DQ/DQM to DQS. DQ SDQ_B47
U33
SDQ_A47
L27
M32 M_DQS_A6
M_DQS _A [ 7..0] 16
M_DQM_A [7..0] 16
> & DQM is matched to DQS in EACH byte SDQS_B6
M29
SDQS_A6 M_DQM_A6 SDM_B6
M34
SDM_A6 lane: P29
M_DA TA _A [63..0] 16 SDQ_B48
SDQ_A48
T34
T32
M_DA TA_A48
M_DA TA_A49
> From GMCH pad to DIMM-0 pin +/-25mils. SDQ_B49
R30
K28
SDQ_A49 SDQ_B50
SDQ_A50
K34 M_DA TA_A50 > From GMCH pad to DIMM-1 pin +/-25mils. GMCH 848P
SDQ_B51
L30
GMCH 848P K32 M_DA TA_A51 R31
B
SDQ_A51
SDQ_A52
T31 M_DA TA_A52 > From DIMM-1 pin to Rtt no tuning SDQ_B52
SDQ_B53
R26 B
P34 M_DA TA_A53 P25
SDQ_A53
L34 M_DA TA_A54 required. SDQ_B54
L32
SDQ_A55
L33 Form Intel WW32 update J30
M_DQS _A [ 7..0] 16 SDQS_B7
H31 M_DQS_A7 J31
SDQS_A7 M_DQM_A [7..0] 16 SDM_B7
H32 M_DQM_A7
SDM_A7
M_DA TA _A [63..0] 16
K30
M_DA TA_A56 SDQ_B56
J33 H29
SDQ_A56 H34 M_DA TA_A57 SDQ_B57 F32
E33 G33
F33 N25
K31 M25
J34 J29
SDQ_A61 G34 M_DA TA_A62 SDQ_B62 G32
F34
SDQ_A63
2D5V _S TR 2D5V _S TR 2D5V _S TR

V _S MY RCOMP V _S MY RCOMPVO V _S MY RCOMPVO 2D5V _S TR
1
1
1
R173 R174 R175 R 176

42.2
10K
30.1K
150
R 177 R178 R 179
42.2
30.1K
10K
2
A A
2
S MY RCOMP S MY RCOMP VOH S MY RCOMPVOL GMCH_V RE F_B

S MXRCOMP S MXRCOMPVOL S MXRCOMPVOH GMCH_V RE F_A
1
1
1
R180 R181 R182 R 183

42.2
30.1K
10K
150
R 184 R185 R 186
42.2
10K
30.1K
1uF
BC118
1uF
BC119
2.2uF
BC120
0.1uF
BC121
1uF
BC122
1uF
BC123
2.2uF
BC124
0.1uF
BC125
D UMMY DUMMY
2
2 FOXCONN PCEG
2
D UMMY Title
GMCH-2
note: 7/6-change BC118 and BC119 to Dummy Size Doc ument Number Rev
C 848M02 F

5 4 3 2 1

5 4 3 2 1
FS B _VTT 1D5V _CORE
U13E U 13F U13G
V CCP _DCA P 1 A15 J6 AR32 AE11 L31 F16

V CCP _DCA P 2 VTT VCC VSS VSS VSS VSS
A21 J7 AR29 AE10 L26 F14
VTT VCC VSS VSS VSS VSS
A4 J8 AR27 AE4 L25 F12
A5 J9 AR25 AE1 L24 F10
A6 K6 AR23 AD33 K33 F8
B5 K7 AR20 AD30 K29 F5
B6 K8 AR16 AD28 K27 F3
D C5 K9 AR13 AD10 K25 F1 D
C6 L6 AR11 AD9 K22 E3
D5 VTT VCC L7 AR9 VSS VSS AD8 K20 VSS VSS E1
D6 L9 AN32 AD6 K18 D35
V _S MY RCOMPVO V _S MY RCOMP VTT VCC VSS VSS VSS VSS
D7 L10 AN30 AD3 K16 D33
E6 VTT VCC L11 AN28 VSS VSS AC35 K14 VSS VSS D31
V _S MY RCOMP 2D5V _S TR VTT VCC VSS VSS VSS VSS
E7 M8 AN26 AC32 K12 D29
F7 M9 AN24 AC4 K11 D27
VTT VCC M10 AN22 VSS VSS AC1 J35 VSS VSS D25
VCC VSS VSS VSS VSS
AA35 M11 AN20 AB33 J32 D23
VCC_DDR VCC VSS VSS VSS VSS
C3
C4
AL6 N9 AN18 AB30 J28 D21
AL7 N10 AN16 AB28 J22 D19
AM1 VCC_DDR VCC N11 AN14 VSS VSS AB27 J20 VSS VSS D17
0.22uF
0.1uF
AM2 P10 AN12 AB26 J18 D15
AM3 P11 AN10 AB10 J16 D13
AM5 VCC_DDR VCC R11 AM35 VSS VSS AB9 J14 VSS VSS D11
GND
AM6 T16 AM29 AB8 J12 D9
AM7 VCC_DDR VCC T17 AM27 VSS VSS AB6 J10 VSS VSS D1
AM8 T18 AM25 AB3 H33 C28
AN2 T19 AM23 AA32 H30 C26
AN4 T20 AM21 AA4 H26 C24
AN5 U16 AM19 AA1 H24 C22
POWER
AN6 U17 AM17 Y35 H22 C20
AN7 U20 AM15 Y33 H20 C18
AN8 V16 AM13 Y30 H18 C16
AP3 V18 AM11 Y28 H16 C14
AP4 V20 AM9 Y27 H14 C12
AP5 W16 AL32 Y26 H12 C10
AP6 VCC_DDR VCC W19 AL1 VSS VSS Y10 H9 VSS VSS C8
AP7 W20 AK28 Y9 H8 C4
V 2P 5_DCAP5 VCC_DDR VCC VSS VSS VSS VSS
AR15 Y16 AK26 Y8 H5 A32
V 2P 5_DCAP4 AR21 VCC_DDR VCC Y17 AK24 VSS VSS Y6 H2 VSS VSS A29
V _S MY RCOMPVO VCC_DDR VCC VSS VSS VSS VSS
AR31 Y18 AK22 Y3 G35 A27
AR4 Y19 AK20 W32 G31 A25
AR5 Y20 AK18 W18 G28 A23
GND
AR7 VCC_DDR VCC AK16 VSS VSS W17 F26 VSS VSS A20
V 2P 5_DCAP1 VCC_DDR VSS VSS VSS VSS
E35 AK14 W4 F24 A16
VCC_DDR VSS VSS VSS VSS
R35 J1 AK12 V33 F22 A13
C VCC_DDR VCC_AGP J2 AK10 VSS VSS V30 F20 VSS VSS A11 C
VCC_AGP VSS VSS VSS VSS
3D3V _S YS G1 J3 AK8 V28 F18 A9
VCC_DAC VCC_AGP VSS VSS VSS VSS
G2 J4 AK3 V27 A7
1D5V _CORE VCC_DAC VCC_AGP J5 AJ35 VSS VSS V26 VSS
V CORE _DCA P 1 VCC_AGP VSS VSS
AG1 K2 AJ32 V19
VCCA_AGP VCC_AGP VSS VSS
Y11 K3 AJ9 V17
VCCA_AGP VCC_AGP VSS VSS GMCH 848P
K4 AJ4 V10
V CCP _DCA P 3 VCC_AGP VSS VSS
A31 K5 AJ1 V9
V _1P 5_V CCA_FSB VCCA_FSB VCC_AGP VSS VSS
B4 L1 AH33 V8
V CCA _DP LL VCCA_FSB VCC_AGP VSS VSS
B3 L2 AH30 V6
V _1P 7_DAC VCCA_DPLL VCC_AGP VSS VSS
C2 L3 AH24 V3
VCCA_DAC VCC_AGP L4 AH22 VSS VSS U32
V 2P 5_DCAP2 VCC_AGP VSS VSS
AL35 L5 AH20 U19
AB25 VCCA_DDR VCC_AGP Y1 V CORE _DCA P 2 AH18 VSS VSS U18
VCCA_DDR VCC_AGP VSS VSS
AC25 AH16 U4
V _1P 5_V CCA_SM VCCA_DDR VSS VSS
AC26 D3 AH14 T35
VCCA_DDR VSSA_DAC AH12 VSS VSS T33
VSS VSS
AH10 T30
GMCH 848P VSS VSS
AH6 T28
AH3 VSS VSS T27
VSS VSS
AG35 T26
AG32 VSS VSS T10
VSS VSS
AG28 T9
AG26 VSS VSS T8
VSS VSS
AG24 T6
1D5V _CORE 2D5V _S TR VSS VSS
AG22 T3
FS B _VTT AG20 VSS VSS T1
VSS VSS
AG18 R32
VSS VSS
AG16 R4
VSS VSS
AG14 R1
VSS VSS
EC36
AG8 P33
VSS VSS
EC35
AG4 P30
7/7:DEl 1psc CAP VSS VSS
AF33 P28
AF30 VSS VSS P27
+ +
VSS VSS
BC129
BC130
BC131
AF25 P26
D UMMY VSS VSS
AF24 P9
VSS VSS
1000uF
AF22 P8
AF20 VSS VSS P6
B VSS VSS B
10uF
BC126
BC127
BC128
D UMMY AF18 P3
3D3V _S YS VSS VSS
0.1uF
1uF
D UMMY AF16 N35

VSS VSS
AF14 N32
DUMMY VSS VSS
DUMMY AF11 N4
VSS VSS
AF9 N1
VSS VSS
AF6 M33
VSS VSS
AF3 M30
B C133 VSS VSS
AE35 M28
0. 1uF AE32 VSS VSS M27
VSS VSS
AE26 M26
VSS VSS
AE25 M6
VSS VSS
AE13 M3
VSS VSS
AE12 L35
VSS VSS
GMCH 848P
Subject: GMCH Vtt VR Clarification

The GMCH VTT regulator is required to be capable of sinking 600mA of current in addition to
sourcing 1.6A of current in normal operation.
1D5V _CORE 1D5V _CORE 1D5V _CORE 1D5V _CORE V CORE _DCA P 1
V CORE _DCA P 2
Sinking 600mA of current is a new requirement for the Springdale platform regardless if a
V CCP _DCA P 1 Northwood or Prescott processor is installed. The reason
V CCP _DCA P 2
V CCP _DCA P 3
why the GMCH VTT VR must be able to sink 600mA is because there will be times when the GMCH
V 2P 5_DCAP2 VTT VR's output will be set to a voltage lower than
V 2P 5_DCAP5 the VRD 10's output. The difference in voltage will cause current to be driven from the VRD
* R187
0
V 2P 5_DCAP4
V 2P 5_DCAP1 to the GMCH VTT regulator. If the GMCH VTT VR doesn't
+/-1% have the capability to sink the current, damage to the GMCH can occur. In order to meet
R0603
L10 L0603 0. 1uH L11 L12 L0603 0. 1uH this requirement, Intel is using a P-FET in an SOT-23
C5
C6
C7
C8
C9
C10
C11
C12
C13
L0603 0. 82uH footprint on the GMCH VTT voltage regulator. The back driven current will be sunk into the
D UMMY
A
ground plane through this P-FET A
without causing damage to the Springdale GMCH.
0.47uF
0.22uF
0.1uF
0.1uF
0.1uF
0.47uF
0.47uF
0.47uF
0.47uF
V _1P 7_DAC V _1P 5_V CCA_FSB V _1P 5_V CCA_SM V CCA _DP LL Update from Intel WW34 MOV
1
DUMMY
1
DUMMY
100uF
EC37
D UMMY
2
10nF
BC134
0.1uF
BC135
470uF
EC38
100uF
EC39
0.1uF
BC136
0.1uF
BC137
100uF
EC40
0.1uF
BC138
2
FOXCONN PCEG
Title
GMCH-3
C 848M02 F

5 4 3 2 1

5 4 3 2 1
VTT_DDR
RN4
M_ D ATA_ A[63..0] 14
*
1
3
2
4
M_ D ATA_A0
M_ D ATA_A4
5 6 M_ D ATA_A5
7 8 M_ D ATA_A1
56
RN5
*
1
3
2
4
M_ D QS_A0
M_ D QM_A0
5 6 M_ D ATA_A2
M_ D ATA_A6 14 M_ MAB_ A[5..1]
7 8
56
RN6
D
*
1
3
2
4 M_ D ATA_A7
D
5 6 M_ D ATA_A3
M_ D ATA_A8 DIMM1
7 8 DIMM2
56
Updated DDR Termination Resistor CN2
RN7 (Rtt) Values 14 M_ MAA_ A[1 2..0]
CN3 M_ MAA_A0 48
A0 /CS0
157 M_ SC S_A2J 14
*
1
3
2
4
M_ D ATA_A9
M_ D ATA_A12 The recommended termination resistor
M_ MAA_A0
M_ MAA_A1
48
43
A0 /CS0
157
158
M_ SC S_A0J 14
M_ MAB_A1
M_ MAB_A2
43
41
A1 /CS1
158
21 M_ SCKE_A2 M_ SC S_A3J 14
A1 /CS1 M_ SC S_A1J 14 A2 CKE0
5 6 M_ D QS_A1 M_ MAA_A2 41 21 M_ SCKE_A0 M_ MAB_A3 130 111 M_ SCKE_A3
7 8 M_ D ATA_A13 (Rtt) value for DQ/DQM/DQS is M_ MAA_A3 130
A2
A3
CKE0
CKE1
111 M_ SCKE_A1 M_ MAB_A4 37
A3
A4
CKE1
DQS0
5 M_ D QS_A0
M_ SC KE_ A[3..0] 14
M_ MAA_A4 37 5 M_ D QS_A0 M_ MAB_A5 32 14 M_ D QS_A1
56 changed to 56 ohms.The previous M_ MAA_A5 32 A4 DQS0 14 M_ D QS_A1 M_ SC KE_ A[3..0] 14 M_ MAA_A6 125 A5 DQS1 25 M_ D QS_A2
RN8 M_ MAA_A6 A5 DQS1 M_ D QS_A2 M_ MAA_A7 A6 DQS2 M_ D QS_A3
recommendation was 110 ohms. 125 25 29 36
A6 DQS2 A7 DQS3
*
1
3
2
4
M_ D QM_A1
M_ D ATA_A14 Form Intel FAE WW32
M_ MAA_A7
M_ MAA_A8
29
122
A7 DQS3
36
56
M_ D QS_A3
M_ D QS_A4
M_ MAA_A8
M_ MAA_A9
122
27
A8 DQS4
56
67
M_ D QS_A4
M_ D QS_A5
M_ D ATA_A15 M_ MAA_A9 A8 DQS4 M_ D QS_A5 M_ MAA_A10 A9 DQS5 M_ D QS_A6
5 6 27 67 141 78
7 8 M_ D ATA_A10 M_ MAA_A10 141 A9 DQS5 78 M_ D QS_A6 103 A10 DQS6 86 M_ D QS_A7
A10 DQS6 M_ D QS_A7 M_BS_A0 A13 DQS7
103 86 59 47
56 14 M_ BS_ A[1..0] M_BS_A0 A13 DQS7 M_BS_A1 BA0 DQS8 M_ D QM_A0
59 47 M_ D QS_ A[7..0] 14 52 97
RN9 M_BS_A1 BA0 DQS8 M_ D QM_A0 BA1 DM0 M_ D QM_A1
52 97 113 107
BA1 DM0 BA2 DM1
*
1
3
2
4
M_ D ATA_A20
M_ D ATA_A16 14 M_ MAA_ A[1 2..0] M_ MAA_A11
113
118 BA2 DM1
107
119
M_ D QM_A1
M_ D QM_A2
M_ MAA_A11
M_ MAA_A12
118
115 A11 DM2
119
129
M_ D QM_A2
M_ D QM_A3
M_ D ATA_A17 M_ MAA_A12 A11 DM2 M_ D QM_A3 M_ D ATA_A0 A12 DM3 M_ D QM_A4
5 6 115 129 2 149
14 M_ D ATA_ A[63..0] M_ D ATA_A0 A12 DM3 M_ D QM_A4 M_ D ATA_A1 DQ0 DM4 M_ D QM_A5
7 8 2 149 4 159
M_ D ATA_A1 DQ0 DM4 M_ D QM_A5 M_ D ATA_A2 DQ1 DM5 M_ D QM_A6
4 159 6 169
M_ D ATA_A2 DQ1 DM5 M_ D QM_A6 M_ D ATA_A3 DQ2 DM6 M_ D QM_A7
56 6 169 8 177
RN10 M_ D ATA_A3 DQ2 DM6 M_ D QM_A7 M_ D ATA_A4 DQ3 DM7
8 177 94 140
M_ MAA_ A[1 2..0] 14 DQ3 DM7 DQ4 DM8
*
1
3
2
4
M_ D QS_A2
M_ D QM_A2
M_ D ATA_A4
M_ D ATA_A5
94
95
DQ4 DM8
140
82
M_ D QM_ A[7..0] 14
M_ D ATA_A5
M_ D ATA_A6
95
98
DQ5 VDDID
82
137
M_ D ATA_A18 M_ BS_ A[1..0] 14 M_ D ATA_A6 DQ5 VDDID M_ D ATA_A7 DQ6 CK0 C K_ M_ 133M_P_DDR3_A 14
5 6 M_ SC KE_ A[3..0] 14 98 137 C K_ M_ 133M_P_DDR0_A 14 99 138 C K_ M_ 133M_N_DDR3_A 14
M_ D ATA_A22 M_ D ATA_A7 DQ6 CK0 M_ D ATA_A8 DQ7 /CK0
7 8 M_ D QM_ A[7..0] 14 99 138 C K_ M_ 1 33M_N_DDR0_A 14 12 16 C K_ M_ 133M_P_DDR4_A 14
M_ D ATA_A8 12 DQ7 /CK0 16 M_ D ATA_A9 13 DQ8 CK1 17
56 M_ D QS_ A[7..0] 14 M_ D ATA_A9 DQ8 CK1 C K_ M_ 133M_P_DDR1_A 14 M_ D ATA_A10 DQ9 /CK1 C K_ M_ 133M_N_DDR4_A 14
13 17 C K_ M_ 1 33M_N_DDR1_A 14 19 76 C K_ M_ 133M_P_DDR5_A 14
M_ D ATA_A10 DQ9 /CK1 M_ D ATA_A11 DQ10 CK2
19 76 C K_ M_ 133M_P_DDR2_A 14 20 75 C K_ M_ 133M_N_DDR5_A 14
M_ D ATA_A11 DQ10 CK2 M_ D ATA_A12 DQ11 /CK2 SMB_ C L K_MAIN
20 75 C K_ M_ 1 33M_N_DDR2_A 14 105 92
M_ D ATA_A12 DQ11 /CK2 M_ D ATA_A13 DQ12 SCL SMB_ D ATA_MAIN
105 92 SMB_ C L K_MAIN 6,31 106 91
R851 56 M_ D ATA_A24 M_ D ATA_A13 106 DQ12 SCL 91 M_ D ATA_A14 109 DQ13 SDA 181
*
VTT_DDR M_ D ATA_A14 DQ13 SDA SMB_ D ATA_MAIN 6,31 M_ D ATA_A15 DQ14 SA0
109 181 110 182
M_ D ATA_A15 DQ14 SA0 M_ D ATA_A16 DQ15 SA1
110 182 23 183
C M_ D ATA_A16 DQ15 SA1 M_ D ATA_A17 DQ16 SA2 C
23 183 24 90
RN12 M_ D ATA_A17 DQ16 SA2 M_ D ATA_A18 DQ17 WP
24 90 28 108
DQ17 WP DQ18 VDD
*
1 2 M_ D ATA_A25 R188 47 M_ D ATA_A18 28 108 M_ D ATA_A19 31 120
**** * **** *
M_ D ATA_A29 M_ SC S_A0J 14 M_ D ATA_A19 DQ18 VDD M_ D ATA_A20 DQ19 VDD

3 4 31 120 114 148
M_ D QM_A3 R189 56.2 M_ D QM_A5 M_ D ATA_A20 DQ19 VDD M_ D ATA_A21 DQ20 VDD
5 6 114 148 117 70
M_ D QS_A3 R854 56 M_ D QS_A5 M_ D ATA_A21 DQ20 VDD M_ D ATA_A22 DQ21 VDD
7 8 117 70 121 85
R190 56 M_ D ATA_A22 DQ21 VDD M_ D ATA_A23 DQ22 VDD
M_ R AS_AJ 14 121 85 123 168
56 R191 47 M_ D ATA_A23 123 DQ22 VDD 168 M_ D ATA_A24 33 DQ23 VDD 38
RN13 M_ WE_AJ 14 M_ D ATA_A24 DQ23 VDD M_ D ATA_A25 DQ24 VDD
33 38 35 7
DQ24 VDD DQ25 VDD
*
1
3
2
4
M_ D ATA_A30
M_ D ATA_A26
R192 47 M_BS_A0 M_ D ATA_A25
M_ D ATA_A26
35
39
DQ25 VDD
7
46
M_ D ATA_A26
M_ D ATA_A27
39
40
DQ26 VDD
46
54
M_ D ATA_A31 47 M_ MAA_A6 M_ D ATA_A27 DQ26 VDD M_ D ATA_A28 DQ27 VDDQ
5 6 40 54 126 96
M_ D ATA_A27 M_ MAA_A9 M_ D ATA_A28 DQ27 VDDQ M_ D ATA_A29 DQ28 VDDQ
7 8 R193 47 126 96 127 62
R194 47 M_ MAA_A11 M_ D ATA_A29 DQ28 VDDQ M_ D ATA_A30 DQ29 VSDQ
127 62 131 128
56 M_ MAA_A12 M_ D ATA_A30 DQ29 VSDQ M_ D ATA_A31 DQ30 VDDQ 2D5V_STR
R195 47 131 128 133 104
RN14 R196 M_ D ATA_A31 DQ30 VDDQ 2D5V_STR M_ D ATA_A32 DQ31 VDDQ
133 104 53 136
DQ31 VDDQ DQ32 VDDQ
*
1
3
2
4
M_ D ATA_A32
M_ D ATA_A36 RN15
M_ D ATA_A32
M_ D ATA_A33
53
55 DQ32 VDDQ
136
30
M_ D ATA_A33
M_ D ATA_A34
55
57 DQ33 VDDQ
30
143
DQ33 VDDQ DQ34 VDDQ
5
7
6
8
M_ D ATA_A33
M_ D ATA_A37
*
1
3
2
4
M_ C AS_AJ 14
M_ D ATA_A34
M_ D ATA_A35
57
60
DQ34 VDDQ
143
77
M_ D ATA_A35
M_ D ATA_A36
60
146
DQ35 VDDQ
77
112
M_ SC S_A2J 14 M_ D ATA_A36 DQ35 VDDQ M_ D ATA_A37 DQ36 VDDQ
5 6 M_ SC S_A1J 14 146 112 147 156
56 M_ D ATA_A37 DQ36 VDDQ M_ D ATA_A38 DQ37 VDDQ
7 8 M_ SC S_A3J 14 147 156 150 164
RN16 M_ D ATA_A38 150 DQ37 VDDQ 164 M_ D ATA_A39 151 DQ38 VDDQ 172
DQ38 VDDQ DQ39 VDDQ
*
1
3
2
4
M_ D QS_A4
M_ D ATA_A34
56
RN17
M_ D ATA_A39
M_ D ATA_A40
151
61
DQ39 VDDQ
172
180
M_ D ATA_A40
M_ D ATA_A41
61
64
DQ40 VDDQ
180
15
DQ40 VDDQ DQ41 VDDQ
5
7
6
8
M_ D QM_A4
M_ D ATA_A38
*
1
3
2
4 M_ MAA_A0
M_ D ATA_A41
M_ D ATA_A42
64
68
DQ41 VDDQ
15
22
M_ D ATA_A42
M_ D ATA_A43
68
69
DQ42 VDDQ
22
1 SMVR EF_A
M_ MAA_A10 M_ D ATA_A43 DQ42 VDDQ SMVR EF_A M_ D ATA_A44 DQ43 VREF
5 6 69 1 153 3
M_BS_A1 M_ D ATA_A44 DQ43 VREF M_ D ATA_A45 DQ44 VSS
56 7 8 153 3 155 145
RN18 M_ D ATA_A45 DQ44 VSS M_ D ATA_A46 DQ45 VSS
155 145 161 18
DQ45 VSS DQ46 VSS
*
1
3
2
4
M_ D ATA_A39
M_ D ATA_A35
47
RN19
M_ D ATA_A46
M_ D ATA_A47
161
162
DQ46 VSS
18
58
M_ D ATA_A47
M_ D ATA_A48
162
72
DQ47 VSS
58
50
DQ47 VSS DQ48 VSS
5
7
6
8
M_ D ATA_A44
M_ D ATA_A40
*
1
3
2
4
M_ MAA_A7
M_ MAA_A8
M_ D ATA_A48
M_ D ATA_A49
72
73
DQ48 VSS
50
100
M_ D ATA_A49
M_ D ATA_A50
73
79
DQ49 VSS
100
160
M_ D ATA_A50 DQ49 VSS M_ D ATA_A51 DQ50 VSS
5 6 79 160 80 139
56 M_ D ATA_A51 DQ50 VSS M_ D ATA_A52 DQ51 VSS
7 8 80 139 165 132
M_ D ATA_A52 DQ51 VSS M_ D ATA_A53 DQ52 VSS
165 132 166 152
47 M_ D ATA_A53 166 DQ52 VSS 152 M_ D ATA_A54 170 DQ53 VSS 116
R852 56 M_ D ATA_A45 RN21 M_ D ATA_A54 DQ53 VSS M_ D ATA_A55 DQ54 VSS
170 116 171 11
**
DQ54 VSS DQ55 VSS

B
R853 56 M_ D ATA_A41
*
1
3
2
4 M_ SCKE_A3
M_ D ATA_A55
M_ D ATA_A56
171
83
DQ55 VSS
11
34
M_ D ATA_A56
M_ D ATA_A57
83
84
DQ56 VSS
34
26 B
M_ SCKE_A0 M_ D ATA_A57 DQ56 VSS M_ D ATA_A58 DQ57 VSS
5 6 84 26 87 66
M_ SCKE_A2 M_ D ATA_A58 DQ57 VSS M_ D ATA_A59 DQ58 VSS
7 8 87 66 88 93
RN22 M_ D ATA_A59 DQ58 VSS M_ D ATA_A60 DQ59 VSS
88 93 174 124
DQ59 VSS DQ60 VSS
*
1 2 M_ D ATA_A42 R855 47 56 M_ D ATA_A21 M_ D ATA_A60 174 124 M_ D ATA_A61 175 74
******* *
M_ D ATA_A43 M_ D ATA_A61 DQ60 VSS M_ D ATA_A62 DQ61 VSS 2D5V_STR

3 4 175 74 178 176
M_ D ATA_A46 R857 47 M_ SCKE_A1 M_ D ATA_A62 DQ61 VSS 2D5V_STR M_ D ATA_A63 DQ62 VSS
5 6 178 176 179 42
7 8 M_ D ATA_A47 R858 56 M_ D ATA_A23 M_ D ATA_A63 179 DQ62 VSS 42 44 DQ63 VSS 81
R859 56 M_ D ATA_A11 DQ63 VSS CB0 VSS
44 81 45 89
56 R860 56 M_ D ATA_A19 CB0 VSS CB1 VSS
45 89 49 184
M_ MAA_A5 CB1 VSS CB2 VDDSPD
RN23 R861 47 49 184 51 167
CB2 VDDSPD CB3 NC/FETEN
*
1
3
2
4
M_ D ATA_A48
M_ D ATA_A49
R862
R863
47
56
M_ MAB_A5
M_ D ATA_A28
51
134 CB3 NC/FETEN
167
71
134
135 CB4 NC/CS2
71
163
M_ D ATA_A52 RN24 CB4 NC/CS2 CB5 NC/CS3
5 6 135 163 142 10
CB5 NC/CS3 CB6 NC
7 8 M_ D ATA_A53
*
1
3
2
4
M_ MAA_A2
M_ MAB_A2
142
144
CB6 NC
10
9 M_ R AS_AJ
144
154
CB7 NC
9
101
56 M_ MAA_A1 CB7 NC M_ C AS_AJ /RAS NC
5 6 154 101 65 102
RN25 7 8 M_ MAB_A1 14 M_ R AS_AJ 65 /RAS NC 102 M_ WE_AJ 63 /CAS NC 173
14 M_ C AS_AJ /CAS NC /WE NC
*
1
3
2
4
M_ D QM_A6
M_ D QS_A6 47 RN26 14 M_ WE_AJ
63
/WE NC
173
D D R 3 33_DIMM
5
7
6
8
M_ D ATA_A54
M_ D ATA_A55
*
1
3
2
4
M_ MAA_A4
M_ MAB_A4
D D R 3 33_DIMM
5 6 M_ MAB_A3
56 7 8 M_ MAA_A3
RN27 2 D 5 V_STR
*
1
3
2
4
M_ D ATA_A50
M_ D ATA_A51
47
5 6 M_ D ATA_A60
7 8 M_ D ATA_A61
56
* R197
75
RN28 +/-1%
*
1
3
2
4
M_ D ATA_A56
M_ D ATA_A57
R0603
5 6 M_ D QM_A7 2D5V_STR VTT_DDR

7 8 M_ D QS_A7 SMVR EF_A
56 BC139
RN29 * R198
* 0.1uF
A *
1
3
2
4
M_ D ATA_A62
M_ D ATA_A63
75
+/-1%
2 5 V, X7 R, +/-10% BC140
C0603 0.1uF A
5 6 M_ D ATA_A59 R0603
BC141
BC151
BC152
BC153
BC154
BC155
BC156
BC157
BC170
BC172
7 8 M_ D ATA_A58
B C143
B C144
B C145
B C146
B C147
B C148
B C149
B C150
B C158
B C159
B C160
B C161
B C162
B C163
B C164
B C165
B C166
B C167
B C168
B C169
B C171
B C173
B C174
B C175
B C176
B C177
B C178
B C179
B C180
B C181
B C182
B C183
B C184
B C185
B C186
56 D U MMY
* *** ***** **** ** * * * *** **** *** * ****** ** * ** *****

0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
0 . 1uF
1 uF
1 uF
1 uF
1 uF
1 uF
0 .1uF
0 .1uF
0 .1uF
0 .1uF
0 .1uF
0 .1uF
D U MMY
FOXCONN PCEG
Title
D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY DDR Channel A Termination
D U MMY D U MMY D U MMY Size D o cu ment Number R ev
D U MMY D U MMY D U MMY D U MMY D U MMY D U MMY Custom 848M02 C
D a te: Fri d a y, Au g ust 27, 2004 Sheet 16 of 34
5 4 3 2 1

5 4 3 2 1
AGP CONN. 1D5V _CORE 1D5V _CORE
12V _SYS
3D3V _SB
D D
5V _SYS CN4
3D3V _S YS
B9
1.5 AGP 8X A65 GA D0
GA D[ 31. .0] 13
B16 VCC3.3 AD0 B65 GA D1

VCC3.3 AD1 GA D2
B25 A63
VCC3.3 AD2 GA D3
B28 B63
VCC3.3 AD3 A62 GA D4
AD4 GA D5
A9 B62
VCC3.3 AD5 GA D6
A16 A60
VCC3.3 AD6 GA D7
A25 B60
A28 VCC3.3 AD7 B57 GA D8
VCC3.3 AD8 GA D9
A56
AD9 GA D10
A34 B56
B34 VDDQ AD10 A54 GA D11
VDDQ AD11 GA D12
B40 B54
B47 VDDQ AD12 A53 GA D13
VDDQ AD13 GA D14
B52 B53
2
R 199 VDDQ AD14 GA D15
B58 A51
VDDQ AD15 GA D16
B64 A39
VDDQ AD16 GA D17
A40 B38
VDDQ AD17 GA D18
A52 A38
6.8K VDDQ AD18 GA D19
A58 B36
1
VDDQ AD19 GA D20
A64 A36
VDDQ AD20 GA D21
B2 B35
5.0V AD21 GA D22
B3 A35
5.0V AD22 GA D23
A1 B33
A2 12V AD23 A30 GA D24
TYPEDET# AD24 GA D25
B1 B30
OVRCNT# AD25 GA D26
A4 A29
B4 USB- AD26 B29 GA D27
I N TA J USB+ AD27 GA D28
A6 A27
20, 28 I N TA J I N TB J INTA# AD28 GA D29
B6 B27
20, 28 I N TB J I CH_P _P CIRE S TJ INTB# AD29 GA D30
A7 A26
19, 20, 21, 28,29 I CH_P _P CIRE S TJ G GNTJ A8 RST# AD30 B26 GA D31
13 G GNTJ CK _66M_AGP GNT# AD31 SB_STB
B7 B18 SB_STB 13
6 CK _66M_AGP G RE QJ CLK SB_STB S B _S TBJ
B8 A18 S B _S TBJ 13
C 13 G RE QJ P IP E J A12 REQ# SB_STB# A59 A D_S TB 0J C
13 P IP E J PIPE#/DBI_HI AD_STB0# A D_S TB 0J 13
W B FJ A14 A32 A D_S TB 1J
13 W B FJ WBF# AD_STB1# A D_S TB 1J 13
R B FJ B12 B59 A D_S TB0
13 R B FJ RBF# AD_STB0 A D_S TB0 13
PMEJ A48 B32 A D_S TB1
20, 21, 28,29 PMEJ PME# AD_STB1 A D_S TB1 13
GP A R A50 A57 GCB E J0
13 GP A R PAR C/BE0# GCB E J0 13
G IRD YJ B41 B51 GCB E J1
13 G IRDYJ IRDY# C/BE1# GCB E J1 13
GDE V S ELJ B46 B39 GCB E J2
13 GDE V S ELJ DEVSEL# C/BE2# GCB E J2 13
G P E RRJ B48 A33 GCB E J3
PERR# C/BE3# GCB E J3 13
G S E RRJ B50 B10
SERR# ST0 ST0 13
GFRA MEJ A41 A10
13 GFRA MEJ FRAME# ST1 ST1 13
G TR DY J A46 B11
13 G TR DY J TRDY# ST2 ST2 13
GS TOPJ A47 B15 SBA0
13 GS TOPJ STOP# SBA0 SBA1
B5 A15
B13 GND SBA1 B17 SBA2
GND SBA2 SBA3
B19 A17
GND SBA3 SBA4
B23 B20
B31 GND SBA4 A20 SBA5
GND SBA5 SBA6
B37 B21
GND SBA6 SBA7
A21
B49 SBA7 B14
GND DBI_LO S B A [ 7..0] 13
B55 B22 DB I_LO
GND RESERVED D B I_LO 13
B61 B24
GND 3.3V_AUX
A5
A13 GND
GND A GP RE F_GMCH
A19 B66
GND VREFCG G C_DE TJ
A23 A3
A31 GND GC_DET A11
GND MB_DET
A37 A22
GND RESERVED
A24
RESERVED
A49
GND
A55
NC1
NC2
NC3
GND
A61 A66
GND RESERVED
1
2
3
B B
R e s erved
DECUBLE CAP.
AGPREF & AGPSWING CIRCUIT
5V _S YS 3D3V _S YS 12V _SYS 1D5V _CORE 3D3V _SB
1D5V _CORE
1
R 200
1D5V _CORE 12V _SYS 1D5V _CORE 60. 4
BC187
BC188
BC189
BC190
BC191
7/6 Update from
2
1
B C192 PBSS4320T to
GS W ING_GMCH 13
1
R 201 3904
1
R e s erved R e s erved R e s ervedR e s erved R e s erved 0. 1uF
R e s erved R202 R 203 8.2K add R702 2.2K
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
8.2K 8.2K R 204

39. 2
2
G P E RRJ
2
A A
C
2
R 702 R 205 39. 2
B Q33
A GP RE F_GMCH 13
*
R 0603 MMB T3904 +/-1%

C
R0603
E
G C_DE TJ B 2.2K B Q35 1

Q34 MMB T3904
1
MMB T3904 +/-1% R 206

E
R 207 100
100
FOXCONN PCEG
2
2
Title
AGP Connector
C 848M02 F

5 4 3 2 1

5 4 3 2 1
U15B
U 1 5D
13 HI[ 10. . 0] HI0 US B P0P
H20 C23
HI1 HI0 USBP0P US B P 0N US B P0P 25 I CH_GP IO6_P U
H21 D23 T22 R5
HI1 USBP0N US B P 0N 25 30 A 20GATE A20GATE AGPBUSY#/GPI6 L_S MIJ
HI2 J20 A22 US B P1P V23 U3 B OA RD0
HI3 HI2 USBP1P US B P 1N US B P1P 25 11 A 20MJ A20M# GPI7 GP I8_P U
H23 B22 P22 Y2
HI4 HI3 USBP1N US B P2P US B P 1N 25 11 C P US LP J CPUSLP# GPI8 S MB _A LE RT_UP
M23 C21 U24 AC3
HI5 HI4 USBP2P US B P 2N US B P2P 23 11 F E R RJ FERR# SMBALERT#/GPI11
M21 D21 R21 W4 L_P MEJ 30
HI6 HI5 USBP2N US B P3P US B P 2N 23 11 I G N NE J IGNNE# GPI12 S LE EPJ
N21 A20 R23 W5
HI7 HI6 USBP3P US B P 3N US B P3P 23 11, 24 I N I TJ INIT# GPI13 I CH_GP IO_18 TP27
M20 B20 U23 U21
HI8 HI7 USBP3N US B P4P US B P 3N 23 11 I N TR INTR STP_PCI#/GPO18 I CH_GP IO_19 TP28
L22 C19 R22 T20
HI9 HI8 USBP4P US B P 4N US B P4P 25 11 NM I NMI SLP_S1#/GPO19 I CH_GP IO_20 TP29
D J22 D19 P23 U22 D
H I 10 HI9 USBP4N US B P5P US B P 4N 25 30 K B RS TJ RCIN# STP_CPU#/GPO20 I CH_GP IO_21 TP30
K21 A18 F23 R1
R208 1 2 61. 9 G22 HI10 USBP5P B18 US B P 5N US B P5P 25 30 S E RIRQ
V24 SERIRQ C3_STAT#/GPO21 U20 ICH_GP O22_UP
HI11 USBP5N US B P 5N 25 11 S MIJ SMI# CPUPERF#/GPO22 ICH_GP O22_UP 24
C17 US B P6P T24 F22 I CH_GP IO_23 TP31
HI_S TB F USBP6P US B P 6N US B P6P 25 11 S TP CLK J STPCLK# SSMUXSEL/GPO23
K23 D17 AC1
13 HI_S TB F HI_S TBS J24 HI_STBF USBP6N A16 US B P7P US B P 6N 25
P20 CLKRUN#/GPIO24 W3
13 HI_S TBS H I _ RCOMP _ICH HI_STBS USBP7P US B P 7N US B P7P 25 CN5 DPRSLPVR GPIO25
N24 B16 1 TP32 R24 V3
H I _ V S W ING_ICH HIRCOMP USBP7N US B P 7N 25 DPSLP# GPIO27 S 1LED
L20 SATA 8 2 W2
13 H I_V S W ING HI_VSWING GPIO28 S 1LED 27
H I _ V RE F_ICH L24 R N30 3 S A TA _TXP0 AA8 T1
13 H I_V RE F HIREF SATA0TXP GPIO32 I CH_GP IO_32 21
6 CK _66M_ICH
N22
CLK66 OC0#
C15
D15
*
1
3
2
4
4
5
S A TA _TXN0
S A TA _RXN0
AB8
AD7
SATA0TXN GPIO33
G23
F21
S A TA _LED
B OA RD1
S A TA _LED 19
OC1# US B _OC3 25 S A TA _RXP0 SATA0RXN GPIO34
C10 D14 5 6 9 6 AC7
C9 LAN_RXD0 OC2# C14 US B _OC 23 SATA0RXP
7 8 7 AD2
LAN_RXD1 OC3# SMBCLK S MB _CLK _RESUME 21, 28, 29,31
C11 B14 AD1 S MB _DA TA _RESUME 21, 28, 29,31
LAN_RXD2 OC4#/GPI9 0 CN6 S A TA _TXP1 SMBDATA S MLINK0
D9 A14 1 AA10 AD3
E9 LAN_TXD0 OC5#/GPI10 D13 +/-5% SATA 8 2 S A TA _TXN1 AB10 SATA1TXP SMLINK0 AA2 S MLINK1 3D3V _SB
add LAN_RST pull low 4.7k resistor 0627 B12
LAN_TXD1 OC6#/GPI14
C13 8P 4R0603 3 S A TA _RXN1 AD9
SATA1TXN SMLINK1
V5 R 211 1 2 10K
D10 LAN_TXD2 OC7#/GPI15 4 S A TA _RXP1 AC9 SATA1RXN LINKALERT#
R 213 LAN_RSTSYNC SATA1RXP
E10 A24 R212 1 2 22. 6 5 E24
LAN_CLK USBRBIAS SPKR SPKR 26, 27 V C CRTC
AA1 B24 9 6 R214 1 2 24. 9 Y11 AB3
LAN_RST# USBRBIAS# SATARBIASP RI# I C H _ RIJ 32
7 Y9 Y4 S IOP W RB TNJ 30
SATARBIASN PWRBTN#
B11 F24 Y1 S US CLK
4.7K EE_DIN CLK48 C K _48M_ICH 6 SUSCLK ICH_B A TLOW _PU
B10 AC5 AB2
EE_CS 6 CK _100M_P _ICH CLK100P BATLOW#
R215
A12 AD5 AB1 L P CP DJ 30
2
EE_SHCLK 6 C K _100M_N_ICH CLK100N SUS_STAT#
B9 R N31 W1
EE_DOUT Clear CMOS SLP_S3# S LP _S3J 30
R216 33 B8 H I_V S W ING 24, 30 L_A D0
2
4
* 13 T5
R4
LAD0 SLP_S4#
U2
AA3
S LP _S4J 8
26 I C H _ S Y NC AC_SYNC H I_V RE F 24, 30 L_A D1 LAD1 SLP_S5#
C12 JP1 CMOS 6 5 R3 U1 I CH_S Y S _RS TJ 6, 12,27
26 I C H _RS TJ AC_RST# 24, 30 L_A D2 LAD2 SYS_RESET#
390K
R217 33 A9 8 7 U4 R20 I CH_V RMP W RGD_UP
1
26 I C H _S DOUT AC_SDOUT 24, 30 L_A D3 LAD3 VGATE/VRMPWRGD
E12 T4 P24
AC_SDIN0 24, 30 L_FRA MEJ LFRAME# CPUPWRGD/GPO49 CP U_P W RG 11
D12 Clear (1-2) 33 U5 T21
AC_SDIN1 30 L _ DRQ0J LDRQ0# THRMTRIP# THE RMTRIP J 11
A13 +/-5% R2 T2 I C H_THRM_UP
26 I C H _S DIN2 AC_SDIN2 LDRQ1#/GPI41 THRM# I C H_THRM_UP 30
10nF
BC193
10nF
BC194
D8 Normal (2-3) D efault AD10 INTV RME N
26 I CH_B CLK AC_BIT_CLK I C H _RTCX1 INTVRMEN
AC11 F20 CK _14M_ICH 6
I C H _RTCX2 RTCX1 CLK14 I N TR U DE RJ
AB12 Y12 I N TR UDE RJ 27
ICH5 3D3V _S YS R T CRS TJ AA12 RTCX2 INTRUDER#
RS MRS TJ RTCRST#
AB13 A11
RSMRST# NC
AC12
C PWROK Difference C
2
D8 I C H5 between
DemoSch and
S D103AW
DG1.0
prevent clearing CMOS when power-on
1
JP1
3D3V _S YS
3
3
ICH_SID0/1/2 internal pull-down 9k-50k. 2
R T CRS TJ 2
1
1
R219
R220
Header_1X3
2
2
DUMMY
DUMMY
1
1
V C C RTC
JP 1(P in2-3) P W RGD_3V 13, 24,27
B OA RD0
R 221 1 2 1M I N TR U DE RJ
B OA RD1
1D5V _CORE Jumper_2P -Black note: 7/6-del pull down GND

N/A
R224 1 2 52. 3 H I _ RCOMP _ICH
3D3V _SB
R N713
8 7 ICH_B A TLOW _PU
B B
6 5 I C H _ R IJ
4 3 S MLINK0
2 *1 S MB _A LE RT_UP
10K
R N714
+/-5%
8 7 GP I8_P U X2(Ret ainer) B A T1_1
6 5 L_P MEJ
4 3 S LE EPJ
2 *1 S MLINK1 LITHIUM BATT
C R 2 032
10K Cry s t al Ret ainer 3D3V _SB 3D3V _SB 3D3V _SB
+/-5% N/A B at t ery
N/A
1
R 234
14
14
51K
U 16A U16B
74LV C14A 74LV C14A
2
3D3V _SB V C C RTC 1 2 3 4 RS MRS TJ RS MRS TJ
RS MRS TJ 30
I C H _RTCX1
I C H _RTCX2
3D3V _S YS
7
D9
B A T54C R 235
R 236 1 2 10K I CH_GP IO6_P U 2 B C197
R 237 1 2 10K ICH_GP O22_UP 1uF 10K
R 238 1 2 10K I CH_V RMP W RGD_UP R228 1 2 10M 3
1
1
R 239 1 2 8.2K I C H_THRM_UP

R 240
20K
1
X2 XTA L-32. 768kHz

2
A 2 1 R 241 A
1K R T CRS TJ
1uF
BC198
4
2
6.8pF
BC195
6.8pF
BC196
BAT1
1uF
BC199
B at t ery Holder
FOXCONN PCEG
2
Title
ICH5-1
C 848M02 F
Dat e: Fridayplace
Note , A ugus
att 27,
ICH2004 S heet
end of roulte 18 of 34
5 4 3 2 1

5 4 3 2 1
ICH5 IDE INTERFACE 3 D 3V_SYS PRIMARY IDE CONN.
R242
R243
1
1
U 15C
D D
P IDE_D15 AB17 AA23 S IDE_D15
P IDE_D14 PDD15 SDD15 S IDE_D14
AA16 AB24
Y16 AC24
2
PDD13 SDD13
8.2K
4.7K
P IDE_D12 AC16 AB22 S IDE_D12
AA15 AA20
AD16 AC22 C N7
P I DE_D9 PDD10 SDD10 S I DE_D9 P_IDERST J
Y15 AD22 1 2
P I DE_D8 PDD9 SDD9 S I DE_D8 P I DE_D7 P I DE_D8
AD15 Y19 3 4
P I DE_D7 PDD8 SDD8 S I DE_D7 P I DE_D6 P I DE_D9
AB14 AC20 5 6
P I DE_D6 PDD7 SDD7 S I DE_D6 P I DE_D5 P IDE_D10
AD14 AB20 7 8
AC15 AC21 9 10
AA14 AB21 11 12
AC14 AD24 13 14
Y14 AD23 15 16
Y13 AB23 17 18
P I DE_D0 PDD1 SDD1 S I DE_D0
AB16 AA22 19
PDD0 SDD0 P I DE_DREQ
X
21 22
P ID E _IOWJ AA17 Y22 S ID E _IOWJ P ID E _IOWJ 23 24
P ID E_DAKJ PDIOW# SDIOW# S ID E_DAKJ P ID E _IORJ
AC18 W20 25 26
P I DE_DREQ PDDACK# SDDACK# S I DE_DREQ P ID E _ RDY
AC17 Y20 27 28
P ID E _IORJ PDDREQ SDDREQ S ID E _IORJ P ID E_DAKJ
AD18 Y23 29 30
P ID E _ RDY PDIOR# SDIOR# S ID E _ RDY IR Q14
AA18 Y21 31 32
PIORDY SIORDY P I DE_A1 33 34
P I DE_A2 S I DE_A2 P I DE_A0 P I DE_A2 C B LID_P 24
AC19 W21 35 36
P I DE_A1 PDA2 SDA2 S I DE_A1 P I DE_CS1J P I DE_CS3J
AD19 W23 37 38
P I DE_A0 PDA1 SDA1 S I DE_A0 P I DE_LED BC200
AA19 W22 39 40
PDA0 SDA0
1
C
P I DE_CS3J Y18
PDCS3# SDCS3#
V20 S I DE_CS3J Header_2X20_20 (IDE)
47nF
R244 25V, Y5V, +80%/-20% * C
P I DE_CS1J AB19 V22 S I DE_CS1J 470 C0603

PDCS1# SDCS1# D UMMY
IR Q14 Y17 Y24 IR Q15
2
IRQ14 IRQ15
10K
R245
IC H 5
5 V_SYS
3 D 3V_SYS
IDE LED & IDE RST
1
3 D 3V_SYS
R246
SECONDARY IDE CONN 1K
2
R250
R251
R247
2
R248 1 2 33 P_IDERST J
4.7K
1
R249 1 2 33 S_IDERST J
D
1
Q36
B G B
S
2
2
8.2K
4.7K
R252 1 2 B1K Q37 2N7002

17,20,21,28,29 IC H_P_PCIREST J MMBT3904
C N8
E
S_IDERST J 1 2
S I DE_D7 3 4 S I DE_D8
S I DE_D6 5 6 S I DE_D9
S I DE_D5 7 8 S IDE_D10
S I DE_D2 13 14 S IDE_D13 D 10 BAT 54A
S I DE_D1 15 16 S IDE_D14 2 P I DE_LED
19 X 3
S I DE_DREQ 27 ID E_LED
21 22
S ID E _IOWJ 23 24 1 S I DE_LED
S ID E _IORJ 25 26
S ID E _ RDY 27 28
S ID E_DAKJ 29 30
IR Q15 31 32 D 11
S I DE_A1 33 34 1 2 SAT A_LED
C B LID_S 24 SAT A_LED 18
S I DE_A0 35 36 S I DE_A2
S I DE_CS1J 37 38 S I DE_CS3J 1N4148W
S I DE_LED 39 40
1
Header_2X20_20 (IDE) R253

47nF
BC201 *
470 C0603
A A
D UMMY
2
2 10K
R254
25V, Y5V, +80%/-20%
FOXCONN PCEG
Title
ICH5-2 IDE Connectors
Size D o cument Number R ev
C u s tom 848M02 F
D ate: Friday, August 27, 2004 Sheet 19 of 34

5 4 3 2 1

5 4 3 2 1
1D5V _CORE
3D3V _SB 3D3V _S YS
U15A
U15E
U 15F FRA ME J A D31 A D[ 31. .0] 21, 28,29
21, 28,29 FRA ME J D2 P2
IRDY J FRAME# AD31 A D30
B5 K10 21, 28,29 IRDY J M3 F4
VCC3_3 VCC1_5 TR D Y J IRDY# AD30 A D29
A1 G6 F6 K12 21, 28,29 TR D Y J E4 P4
VSS VSS VCC3_3 VCC1_5 DE V S E LJ TRDY# AD29 A D28
A7 G20 G1 K13 21, 28,29 DE V S E LJ L3 F5
VSS VSS VCC3_3 VCC1_5 S TOPJ DEVSEL# AD28 A D27
A10 G24 H6 L19 21, 28,29 S TOP J E5 N2
VSS VSS VCC3_3 VCC1_5 PAR STOP# AD27 A D26
A15 H1 K6 P19 21, 28,29 PAR F1 D3
VSS VSS VCC3_3 VCC1_5 P E RRJ PAR AD26 A D25
A17 H19 L6 R10 21, 28,29 P E RRJ K2 P3
VSS VSS 1D5V _CORE VCC3_3 VCC1_5 L OCK J PERR# AD25 A D24
A19 H22 M10 R6 28, 29 L OCK J L2 E6
VSS VSS VCC3_3 VCC1_5 S E RRJ PLOCK# AD24 A D23
D A21 J6 N10 H24 21, 28,29 S E RRJ L4 N4 D
VSS VSS VCC3_3 VCC1_5 SERR# AD23
BC202
A23 J21 P6 J19 PMEJ V2 C4 A D22
VSS VSS VCC3_3 VCC1_5 17, 21, 28,29 PMEJ PME# AD22
AA5 J23 R13 K19 P C IRS TJ V4 N5 A D21
VSS VSS VCC3_3 VCC1_5 PCIRST# AD21 A D20
AA7 K3 V19 M15 6 CK _33M_ICH N1 H3
VSS VSS D UMMY V C CRTC VCC3_3 VCC1_5 PCICLK AD20 A D19
AA9 K11 W15 N15 P5
AA11 VSS VSS K14 W17 VCC3_3 VCC1_5 N23 B3 AD19 B2 A D18
VSS VSS VCC3_3 VCC1_5 17, 28 I N TA J PIRQA# AD18
0.1uF
AA13 K20 W24 E15 17, 28 I N TB J E1 L1 A D17
VSS VSS VCC3_3 VCC1_5 PIRQB# AD17 A D16
AA21 K22 AD13 F15 28 I N TCJ A2 G4
AA24 VSS VSS K24 AD20 VCC3_3 VCC1_5 F14 C2 PIRQC# AD16 G5 A D15
VSS VSS VCC3_3 VCC1_5 28 I N TDJ PIRQD# AD15
AB5 L10 G19 W19 D7 K1 A D14
1 D5V _CORE VSS VSS VCC3_3 VCC1_5 28, 29 I N TE J PIRQE#/GPI2 AD14
AB7 L11 G21 R12 A6 G2 A D13
VSS VSS VCC3_3 VCC1_5 28, 29 I N TFJ PIRQF#/GPI3 AD13
AB9 L12 W9 E2 L5 A D12
VSS VSS VCC1_5 28, 29 I N TGJ PIRQG#/GPI4 AD12
AB11 L13 E18 W10 B1 H4 A D11
VSS VSS VCCSUS3_3 VCC1_5 21, 28,29 I N THJ PIRQH#/GPI5 AD11
BC203
AB15 L14 B15 W11 M4 A D10

VSS VSS VCCSUS3_3 VCC1_5 AD10 A D9
AB18 L15 E11 W6 28, 29 P RE Q0J D5 F2
AC2 VSS VSS L21 1D5V _CORE F10 VCCSUS3_3 VCC1_5 W7 C1 REQ0# AD9 K5 A D8
VSS VSS VCCSUS3_3 VCC1_5 28 P RE Q1J REQ1# AD8
AC4 L23 F11 W8 28 P RE Q2J C5 J2 A D7
VSS VSS VCCSUS3_3 VCC1_5 REQ2# AD7
BC204
D UMMY AC6 M1 E13 E22 B6 J3 A D6
VSS VSS VCCSUS3_3 VCC1_5 21, 28 P RE Q3J REQ3# AD6
0.1uF
AC8 M5 E14 C6 H2 A D5
VSS VSS VCCSUS3_3 28 P RE Q4J REQ4#/GPI40 AD5
AC10 M11 U6 AA6 A5 H5 A D4
VSS VSS VCCSUS3_3 VCCSATAPLL 28 P RE QA J REQA#/GPI0 AD4
AC13 M12 V6 AB6 E7 K4 A D3
VSS VSS VCCSUS3_3 VCCSATAPLL V CCP 28 P RE Q5J REQB#REQ5#/GPI1 AD3
AC23 M13 DUMMY F16 C24 G3 A D2
VSS VSS VCCSUS3_3 VCCUSBPLL AD2
0.1uF
AD4 M14 F17 D4 J5 A D1
VSS VSS VCCSUS3_3 29 G N T0J GNT0# AD1
AD6 M22 F18 F19 28 G N T1J A3 J4 A D0
VSS VSS VCCSUS3_3 VCCSUS1_5_A GNT1# AD0
AD8 M24 K15 Y5 28 G N T2J B7
VSS VSS VCCSUS3_3 VCCSUS1_5_B GNT2# CB E J3
AD17 N11 AA4 21 G N T3J C7 M2
VSS VSS RE F5V VCCSUS1_5_B GNT3# C/BE3# CB E J2 CB E J3 21, 28,29
AD21 N12 A8 AB4 A4 N3
VSS VSS V5REF VCCSUS1_5_B DISCONNECT THE GNT14 GNT4#/GPO48 C/BE2# CB E J1 CB E J2 21, 28,29
AD12 N13 W14 F7 E8 J1
B13 VSS VSS N14 V5REF VCCSUS1_5_C F8 B4 GNTA#/GPO16 C/BE1# E3 CB E J0 CB E J1 21, 28,29
VSS VSS VCCSUS1_5_C 28 G NTB J GNTB#/GNT5#/GPO17 C/BE0# CB E J0 21, 28,29
B17 N20 RE F5V _S US E16
VSS VSS V5REF_SUS ICH5
B19 P1 R15
B21 VSS VSS P10 AD11 V_CPU_IO R19
VSS VSS VCCRTC V_CPU_IO
B23 P11 T19
VSS VSS V_CPU_IO
C3 P12
VSS VSS ICH5
C8 P13
C16 VSS VSS P14
VSS VSS
C18 P15
VSS VSS
C20 P21
VSS VSS
BC205
BC206
BC207
BC208
BC209
C C22 R11 C
VSS VSS
D1 R14
VSS VSS
D6 T23
D11 VSS VSS T3
VSS VSS
D16 T6
VSS VSS
10nF
10nF
10nF
0.1uF
0.1uF
D18 U19
VSS VSS
D20 V1
VSS VSS
D22 V21
VSS VSS
D24 W16
VSS VSS
E17 W18
VSS VSS
E19 Y3
E20 VSS VSS Y6
VSS VSS
E21 Y7
E23 VSS VSS Y8
VSS VSS
F3 Y10
VSS VSS
F9
VSS
I C H5
3D3V _SB 3D3V _SB
14
14
U 1 6C U 16D
R 255
74LV C14A 74LV C14A
P C IRS TJ 5 6 9 8 1 2 I C H_P _P CIRE S TJ 17, 19, 21, 28,29
24. 9
7
BC210
33pF
BC211
B B
D UMMY
I C H _P CIRS TJ 13, 24,30
There are component place on solid site
3D3V _SB 1D5V _CORE V CCP 3D3V _SYS 5V _S YS 3D3V _S YS 5V _S B _SYS 3D3V _SB
1
1
7/7:DEl 1psc CAP
R 256 D 12 R 257 D 13
1K S D103AW 1K DUMMY
2
2
BC213
BC214
BC215
BC216
BC218
BC219
BC220
BC221
BC222
BC223
BC224
BC225
RE F5V RE F5V _S US
0.1uF
0.1uF
0.1uF
10nF
0.1uF
0.1uF
10nF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
A A
0.1uF
BC226
0.1uF
BC227
DUMMY
FOXCONN PCEG
Title
ICH5-3
C 848M02 F

5 4 3 2 1

5 4 3 2 1
R258 5 .6K 3 D 3V_SB

23 L A N _ L INK _ 1 0 0 0 J
R259 5 V _SB_SYS
23 L A N _ L INK _ 1 0 0 J
DU MMY 3 D 3 V _LAN
23 L A N _ A CT L E DJ
5 .6 K
U 17
B C 228 2 7pF L A N _ E E CS 1 8 B C 229
L A N_ E E S K CS VCC
D 2 7 D
1
L A N _ E E DI SK NC
3 6
X3 L A N _ E E DO DI ORG 0 .1 uF
4 5
DO GND
1 D 8 V _LAN
1 D 8 V _LAN
X T A L -2 5 MHz
A V D DH
2
B C 230 2 7pF A T 9 3 C4 6 -2 .7 V
R260 1 2 3 D 3 V _LAN
1 0K
22 C T R L _ 1 D8
DU MMY
22 D V DD_A
R 2 61 5 .6 K 3 D 3 V _ LAN
*
R32 value should be 5.6K (1%) at + / -1 %
A D0
A D1
R 0 603
RTL8100C application, and 2.49K
(1%) at RTL8110S(B) application.
2 D 5 V _LAN
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
U18
VSS
RSET
LV2
CTRL18
LG2
HG
XTAL2
XTAL1
HV
VSSPST
GND
LED0
VDD18
LED1
LED2
LED3
GND
EESK
VDD18
EEDI
EEDO
VDD33
EECS
LWAKE
AD0
AD1
1 102 A D2
23 M D I_0 MDI0+ AD2
23 M D I_ 0J 2 101
MDI0- VSSPST
3 100
AVDDL GND
4 99 1 D 8 V _LAN
VSS VDD18 A D3
23 M D I_1 5 98
C MDI1+ AD3 A D4 C
23 M D I_ 1J 6 97
MDI1- AD4 A D5
7 96
AVDDL AD5 A D6
22 C T R L _ 2 D5 8 95
CTRL25 AD6
9 94
VSS VDD33 A D7
A V DDH 10 93
R 2 62 DU MMY H S DA C AVDDH AD7
11 92 C B E J0 2 0 ,2 8 ,2 9
HSDAC+ CBE0B
22 V_12P 12 91
HSDAC- VSSPST A D8
0 13 90
VSS AD8 A D9
23 M D I_2 14 89
MDI2+ AD9 R 2 63 1
23 M D I_ 2J 15 88 2 1K R420
MDI2- M66EN DU MMY A D10
16 87 0
AVDDL AD10 A D11
17 86 * R 0 6 03
VSS AD11 A D12
23 M D I_3 18 85 +/-5 %
MDI3+ AD12
R T L 8100C
23 M D I_ 3J 19 84
MDI3- VDD33 A D13
20 83
AVDDL AD13 A D14
21 82
VSSPST AD14
22 81
L A N _ D I SABLEJ GND VSSPST
23 80
ISOLATEB GND A D15
1 D 8 V _LAN 24 79
VDD18 AD15
2 0 ,2 8 ,2 9 I NTHJ 25 78 1 D 8 V _LAN
INTAB VDD18
3 D 3 V _LAN 26 77 C B E J1 2 0 ,2 8 ,2 9
VDD33 CBE1B
1 7 , 1 9 ,2 0 ,2 8 ,2 9 I C H _ P _ P C I R E S T J 27 76 P AR 2 0 ,2 8 ,2 9
RSTB PAR
6 C K _ 3 3 M_ L A N 28 75 S E RRJ 2 0 ,2 8 ,2 9
CLK SERRB
20 G N T 3J 29 74 P S DA T A 1 8 , 2 8 ,2 9 ,3 1
30 GNTB SMBDATA 73
2 0 ,2 8 P R E Q 3J REQB GND
1 7 , 2 0 ,2 8 ,2 9 P ME J 31 72 P S CL K 1 8 , 2 8 ,2 9 ,3 1
PMEB SMBCLK
1 D 8 V _LAN 32 71
A D31 VDD18 VDD33
33 70 P E RRJ 2 0 ,2 8 ,2 9
A D30 AD31 PERRB
34 69 S T OP J 2 0 ,2 8 ,2 9
B
35 AD30 STOPB 68 B
GND DEVSELB D E V SELJ 2 0 ,2 8 ,2 9
A D29 36 67
AD29 TRDYB T R DY J 2 0 ,2 8 ,2 9
A D28 37 66
AD28 VSSPST
38 65
FRAMEB
VSSPST CLKRUNB
VSSPST
A D [ 3 1 . .0 ]
CBE3B
CBE2B
VDD33
VDD18
VDD18
VDD33
VDD18
2 0 ,2 8 ,2 9 A D [ 3 1 . .0 ]
IRDYB
IDSEL
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
GND
GND
GND
note: 7/6-del 0 ohm dummy and connected for PMEJ
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1 D 8 V _LAN
A D27
A D26
A D25
A D24
A D23
A D22
A D21
A D20
A D19
A D18
A D17
A D16
L A N _ I DS E L
IRDY J 2 0 ,2 8 ,2 9
3 D 3 V _LAN 3 D 3 V _LAN
2 0 ,2 8 ,2 9 C B E J3 3 D 3 V _SYS F RA MEJ 2 0 ,2 8 ,2 9
A D19 1 2 R265 C B E J2 2 0 ,2 8 ,2 9
1
1 00 R266
1K
A A
2
R267 1K
18 IC H _ G P IO _32 L A N _ D I SABLEJ 2 1
DUM MY TECHNOLOGY COPR.
LAN DISABLE(By disabling LAN clock) T itle
8100C
D o c u m e n t N u mb e r R ev
84 8M02 B
Da te : F r i d a y , A u g u st 2 7 , 2 0 0 4 S heet 21 of 34
5 4 3 2 1

5 4 3 2 1
F B4
* C40 to C46 are for U17 RTL8110S(B)/RTL8100C
VDD33 pins, such as 26, 41, 56, 71, 84, 94 and 107.
3D3V_SB 1 2 3 D 3V_LAN
EC41 BC231
1
FB L0805 100 Ohm 22uF BC232 BC233 BC234 BC235 BC236 BC237 BC238
25V, +/-20%
CE20D50H110 0.1uF
2
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
* C77 and C78 are for U17
D RTL8110S(B) AVDDH pins, D U MMY D U MMY D U MMY D
such as 10 and 120.
AVD D H
F B5 F B6
V_12P 21
25V,Y5V,+80%/-20%
1 2 R268 1 2 +/-5% 1 2 1 D 8V_LAN
25V,Y5V,+80%/-20%
D U MMY
BC239 BC240 D U MMY BC241
At RTL8100C application, keep L2. At * * D U MMY FB L0805 100 Ohm
* C76 is for U17
RTL8110S(B) application, remove L2. D U MMY 0.1uF RTL8110S(B)/RTL8100C pin 12.
1
3 D 3V_LAN
F B7
FB L0805 100 Ohm
2
At RTL8100C application, remove R57 and L7,keep L10. At
3
1 Q38 RTL8110S application, remove L10 and R57, keep L7. At

21 CT RL_2D5
D U MMY RTL8110SB application, remove L10, keep R57 and L7.
When use RT8110C, 2D5V_LAN is 3.3V
2
4
2 D 5V_LAN
C
*
EC42
10uF * BC242
D U MMY
BC243 BC244 BC245 BC246 C
16V, +/-20% 25V,Y5V,+80%/-20%

* C64 to C67 are for U17 RTL8110S(B)/RTL8100C
CE20D50H110 0.1uF 0.1uF 0.1uF 0.1uF
D U MMY AVDDL pins, such as 3, 7, 16, and 20.
3 D 3V_LAN * C47 to C55 are for U17

RTL8110S(B)/RTL8100C DVDD
pins, such as 24, 32, 45, 54, 64,
3
0 Q39
R269 D U MMY 1 BCP69T1 78, 99, 110 and 116.
21 CT RL_1D8
R270 0
2
4
21 CT RL_2D5 D VD D _A 21
F B8
1 2 1 D 8V_LAN
BC247
BC249
EC43 BC248 BC250 BC251 BC252 BC253 BC254 BC255 BC256 BC257
1
0.1uF
B 22uF FB L0805 100 Ohm B

25V, +/-20% 0.1uF
CE20D50H110 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
2
Check the difference between BCP69T1 and

2SB1188(Vendor's solution). It seemed that BCP69T1(1A)
is cheaper than 2SB1188(2A)
When use RT8110C, 1D8V_LAN is 2.5V
A A
TECHNOLOGY COPR.
Title
POWER_LAN
D o cument Number R ev
848 M02 B
5 4 3 2 1

5 4 3 2 1
5V_DUAL
BACK PANEL ( LAN + 2 USB Connector )

USE CONNECTOR(Foxconn P/N: JFM31U1A-01U5W) WITH GIGABIT DESIGN RN 99
2
4
6
8
USE CONNECTOR(Foxconn P/N: JFM25U13-01U5W) WITH 10/100 DESIGN
2
0
F1
F 1 8 1 3 _ 2 .6 A 5V_DUAL_F
D Reserved for RTL8110S (GIGA LAN) DU MMY
D
1
3
5
7
1
Can be change to cost down conn
P/N = JFM31U1A-01U5W For GIGA LAN
3 D 3V_SB 3 D 3V_SB 2 D 5 V _LAN R283
4 7K
1 2 US B _OC 18
B C 530
2
R547 B C 264
DUM MY R284 1nF
*
1
5 0 V , X 7 R, +/-1 0 %
R544 R546 DUM MY C 0 603
4 70 4 70 5 60K
1
B C 536 C N9
2
DU MMY
*
LED caps. should be placed
next to connector 27
R550 2 5 V , Y 5 V ,+8 0 % /-2 0 % 20 28
GRN_LED
0 19 29
21 L A N _ L INK _ 1 0 0 J
B C 5 35
USB-2
USB-1
30
R 5 51 0 DU MMY
21 L A N _ L INK _ 1 0 0 0 J
DU MMY
C 9 1 C
21 M D I_0 10 5
21 M D I_ 0J 11
RJ45-MJ2
12 2 U S B P 3 N _R
21 M D I_1
13 6 U S B P 2 N _R
21 M D I_ 1J
21 M D I_2 14
15 3 U S B P 3P_R
21 M D I_ 2J
16 7 U S B P 2P_R
21 M D I_3
21 M D I_ 3J 17
18 4
8
YLW_LED
1
22 23
1
R294 R295 R296 R297 R 2 79 R 2 81 L A N _ A C T L E DJ 21 24

21 L A N _ A CT L E DJ
4 9 .9 4 9 .9 4 9 .9 4 9 .9 R280 R282 25
26
DU MMY
2
DUM MY DU MMY
* B C 5 31
2
DU MMY R J 4 5 _ US B U S B 4 X 2 _ RJ4 5 P 1 0 _ L E D 5 0 V , N P O ,+/-5 %

4 7 0pF
C 0 6 03
B C 2 69 B C 2 70 B C 2 65 B C 2 66
1 0 nF 1 0 nF
* 5 0 V , X 7 R,+/-1 0 % * 5 0 V , X 7 R,+/-1 0 % * 5 0 V , X 7 R,+/-1 0 % * 5 0 V , X 7 R,+/-1 0 %
C 0 6 03 C 0 6 03
DUM MY
B Place these components close to the LAN controller DUM MY U S B P 3 N _R B
U S B P 3N 18
U S B P 3P_R
B C 5 32 U S BP3P 18
0 .1uF
Reserved for RTL8110S (GIGA LAN) U S B P 2 N _R

B C 5 37 U S B P 2N 18
U S B P 2P_R
U S BP2P 18
*
1nF
C 0 6 03
5 0 V , N P O , +/-5 %
DUM MY
A A
FOXCONN PCEG
T itle
LAN Connectors
S ize D o c u m e n t N u mb e r R ev
848m02 a
Da te : F r i d a y , A u g u st 2 7 , 2 0 0 4 S heet 23 of 34
5 4 3 2 1

5 4 3 2 1
D D
3D3V _S YS
3D3V _S YS
0.1uF
BC271
25
32
27
U 19
VCCA
VCC
VCC
3D3V _S YS
1 24 F W H _ INITJ
P W RGD_3V 13, 18,27 VPP INITJ
31 22 U19_1
6 CK _33M_FWH CLK RFU
21
RFU
29 20
R 298 IC RFU 19
1
B OA RD4 RFU
30 18
FGPI4 RFU PLCC
JP2
Header_1X3 2 32pin
13, 20,30 I C H _ P CIRS TJ RSTJ
4.7K
FWH4
23
L_FRA MEJ 18, 30 Socket
17 L_A D3
2
B OA RD3 FWH3 L_A D2

3 15
FGPI3 FWH2
3
2
1
B OA RD2 4 14 L_A D1
FGPI2 FWH1 L_A D0
5 13
3
2
1
19 C B LID_P FGPI1 FWH0 R N716

19 C B LID_S 6
C 7 FGPI0 12 C
8 7
WPJ ID0 P LCC-32
8 11 6 5
TBLJ ID1 L_A D[ 3. .0] 18, 30
10 4 3
ID2 9 2 * 1
ID3
GNDA
GND
GND
330
R 303 1 28.2K
8P 4R0603
+/-5%
16
26
28
P LCC-32-SKT
JP 2(P in1-2)
18 ICH_GP O22_UP DUMMY
Jumper_2P -Black
N/A 3D3V _S YS 3D3V _S YS
3D3V _S YS
1
R304 R 305
2.7K 1K
BC273
BC276
R726 RESERVE FOR TONGFANG
2
JP2 change 2 pin, Pin3 F W H _ INITJ
NA.
C
D UMMY D UMMY
0.1uF
0.1uF
JP2 FWH WP# B Q40
JP2 FWH WP#
C
R306 MMB T3904
E
Lock (1-2) 1 2 B Q41
11, 18 I N I TJ
Lock Open
Unlock (2-3) MMB T3904
E
D efault Unlock short 7/7:DEl 2psc CAP 3D3V _S YS 4.7K
B B
1
10K R 307 R308 R309
10K 10K
D UMMY DUMMY 2 D UMMY
2
B OA RD2
B OA RD3
B OA RD4
1
1
1
R312 R310 R 311
10K 10K 10K

2
2
2
H1 H2 H3 H4 H5 H6
Mount ing Hole Mount ing Hole Mount ing Hole Mount ing Hole Mount ing Hole Mount ing Hole
6
5
6
5
6
5
6
5
6
5
6
5
7 4 7 4 7 4 7 4 7 4 7 4
8 3 8 3 8 3 8 3 8 3 8 3
9 2 9 2 9 2 9 2 9 2 9 2
H8 H9 H7
1
FMA RK FMA RK FMA RK
A A
FOXCONN PCEG
Title
FWH
C 848M02 F

5 4 3 2 1

5 4 3 2 1
Rear Dual USB Connector

5V_DUAL_F
D D
11
10
C N10
7 USBP1P_R
6 U SBP1N_R
18 U SBP1N
TOP
U SBP1N U SBP1N_R
5 U S BPWR2
18 USBP1P USBP1P USBP1P_R
USBP0P_R
BOTTOM
3
2 U SBP0N_R
18 U SBP0N U SBP0N_R BC277 1 U S BPWR1

EC44
18 USBP0P USBP0P_R 0.1uF 1000uF
C C
USBX2
12
9
R e served
USB 3,4
Close to USB connector

5V_DUAL
USB Header1 EC1 update from
1000uF 16V D6
to 1000uF 10V
D8
USB Header2
2
4
6
8
R N98
2
0
7/7:del R313,314 F2
F1813_2.6A
B B
D U MMY
1
3
5
7
S V CC2
S V CC2
U S B_HDER1
U S B_HDER2
U SBP6N 1 2 U SBP7N
1 2 18 U SBP6N 3 4 U SBP7N 18
U SBP4N U SBP5N USBP6P USBP7P
18 U SBP4N 3 4 U SBP5N 18 18 USBP6P 5 6 USBP7P 18
USBP4P USBP5P
18 USBP4P 5 6 USBP5P 18 7 8
BC278
7 8 10
BC279
10 HEADER_2X5_K9
HEADER_2X5_K9
0.1uF
0.1uF
F_USB2 F_USB1
VerA to VerB
Delete F9, R634,
R315 EC51, R634,
47K R632, BC523
S V CC2 1 2
U SB_OC3 18
EC45
BC280
2
A A
EC50 update from R316
470uF 10V D6 to
1000uF
470uF 10V D8
1 nF
560K
FOXCONN PCEG
1
Title
USB Connector
Size D o cument Number R ev
C u s tom 848M02 F

5 4 3 2 1

5 4 3 2 1
R 317
4.7K
1 2
R318 4.7K
R319
3D3V _S YS A V REF
*
+5VA JD0
C 16 FB9
1uF FB L0603 80 Ohm
LFE _B P _OUT 16V , X7R, +/-10% 10K C 17
*
BC281
BC282
BC283
BC284
C0805 +/-5%
C N11A
1
R0603
5 1 uF
5
1
C 18 4 39
4 X1
3 40
2
470pF 3 X2
0.1uF
4.7uF
0.1uF
4.7uF
2
2
2
1
C 19 FB10 1
D D
C 20 1uF FB L0603 80 Ohm JA CK _A UDX3 V ertical
18pF D UMMY CE N_B P _OUT 16V , X7R, +/-10%
*
*
50V , NP O, +/-5% C0805
C0603 C 21 C 22 MIC-IN
DUMMY 22pF
*
25
38
1
9
50V , NP O, +/-5% U 20 470pF
(CEN/LFE)
DVdd1
DVdd2
AVdd1
AVdd2
3
XTL_OUT
2
6 A DU14MCLK XTL_IN AC97 CODEC
A C_97RS TJ 11 35 LINE _OUT_L
18 I C H _RS TJ
R324 47 R 325 33 6
RESET# 48 pin LINE_OUT_L
36 L INE _OUT_R
18 I C H_B CLK BIT_CLK LINE_OUT_R R 327
18 I C H _ S Y NC
10
SYNC package MONO_OUT
37
*
R 326 33 8 33 C 23 1uF R 328 1K JD2
18 I C H _ S DIN2 SDATA_IN NC1 F R ONT_MIC
5 34 1 2
18 I C H _S DOUT SDATA_OUT NC2 S _OUT_L C 24
39
R 329 10K B C285 1uF HP_OUT_L 10K
40
HP_COMM S _OUT_R C 25 FB 11 +/-5% 1uF
18, 27 S P K R 1 2 12 41
PC_BEEP HP_OUT_R C E N_OUT 1 uF FB L0603 80 Ohm C N 1 1CR 0603
13 43
1
PHONE GPIO0 LE F_OUT S URR_B P _R 16V , X7R, +/-10%

14 44 35
* *
R 330 DUMMY 22pF AUX_L GPIO1 JD0 C 29
0805 FB 12 5
15 45 34 36
C 26 C 27 C 28 AUX_R CID0 A V REF 1 uF FB L0603 80 Ohm 4 X5
16 46 33
1K R e s erved VIDEO_L CID1 S URR_B P _L 16V , X7R, +/-10% 3
17 32
33pF C D -L VIDEO_R A V REF C 0805 2
18 28
2
1
33pF C D - GND CD_L VREFOUT C 30
19 27
7
5
3
1
CD_GND VREF
*
CD-R 20 29 R 332 JA CK _A UDX3 V ertical
1
CE N_B P _OUT CD_R AFILT1 D UMMY R N708 C 71 C 72
21 30
2
LFE _B P _OUT MIC1 AFILT2 4. 7uF 100pF 100pF
22 31
S URR_B P _L 23 MIC2 NC/CAP1 32 DUMMY
22K
8P 4R0603
LINE-IN
2
7/7:change EC26~c28 to dummy S URR_B P _R LINE_IN_L CAP2
24
LINE_IN_R
DVss1
DVss2
+/-5%
AVss1
AVss2
C31
C32
C33
C34
0.1uF BC286
C35
S P DIF_IN 47
(SURR_OUT)
8
6
4
2
S P DIF_OUT EAPD
48
SPDIF
270pF
270pF
270pF
270pF
1uF
A LC655
4
7
26
C 42 C
note: 7/6-change RN708
+5VA
JD2 JD1
2
R335
10K CN12(P in5-6)
1
+5VA
C N 12
12V _SYS F R ONT_MIC Jumper_2P -Black
1 2
N/A
L INE _OUT_R 3 4 F R ONT_OUT_R
+
E C46 100uF
5 6
1
5V _S YS +5VA 7 8 F RONT_OUT_L
LINE _OUT_L E C47 100uF 9 10
+
FB 13 HE A DE R_2X5_K8
CN12(P in9-10)
1
L15 C 36
2
U 21 LM78L05 0. 1uF
2
1 2 1 3
OUT IN R e s erved Jumper_2P -Black
FB L0805 100 Ohm N/A
GND
D UMMY
C 38 C 39 C 40 C N 51
2
16V , X7R, +/-10% ** 100uF

10V , +/-20%
R e s erved * 100uF
16V , +/-20% * 16V , X7R, +/-10%
5
3
DUMMY CE 20D50H110 CE 20D50H110 D UMMY 5V _S YS 2 B C736 1 2 10nF R 640 100 S P DIF_OUT
*
B
C 37 DUMMY D UMMY 0. 1uF 1 B
C N13
4 * R 641
R 336 D UMMY colay 1 J A CK -RCA R CA 3 B C784
A U GND DGND colay 1 100pF
220
1
0
2
S P DIF_OUT 3
3
* R0603
+/-5%
R 337 1 2 4 C0603
4
HE A DE R_1X4O2
R 338
*
JD1
C41
10K
+/-5%
1uF
R0603
FB 14
FB L0603 80 Ohm C N11B
C N 14 F R ONT_OUT_R 25
C D -L C1
42 21uF R 339 4.7K FB 15 24 5 37
1 FB L0603 80 Ohm 4 X3
23 38
C D - GND C1
43 2 5 F RONT_OUT_L 3 X4
21uF R 340 2.7K 22
3 2
CD-R C1
44 4
21uF R 341 4.7K
1
JS T-CON4-2-B lack C 73 C 74 JA CK _A UDX3 V ertical
100pF 100pF
CD-IN
R342 22K
R343
2
22K
FRONT_OUT
A A
S P DIF_OUT C 70
100pF
* 50V , X7R, +/-10%
C0603 FOXCONN PCEG
Title
AC97 Codec
C 848M02 F

5 4 3 2 1

5 4 3 2 1
3D3V _S YS
ATX 12V CONNECTOR

Power CONN.
5V _S B _SYS
0.1uF
BC287
-12V _SYS 3D3V _S YS 12V _SYS 5V _S B _SYS
5V _SYS
1
5V _SYS 5V _SYS
R344
8.2K C N 15
1
11 1
3.3V* 3.3V* R 345 3D3V _SB 3D3V _SB
12 2
2
-12V 3.3V* 100K
D 13 3 D
COM COM
30 P S _ONJ 14 4
15 PS-ON 5V 5
14
14
2
COM COM R347 U16E U 16F
16 6
COM 5V 100 74LV C14A 74LV C14A
17 7
18 COM COM 8 P W RG_A TX 1 2 11 10 13 12
-5V PW-OK P W RGD_3V 13, 18,24
19 9
5V 5VSB
20 10
5V 12V
P W RG_A TX 8
7
A TX_2X10
0.1uF
BC288
P W RGD_3V J 31
0.1uF
BC289
0.1uF
BC290
0.1uF
BC291
0.1uF
BC292
0.1uF
BC293
1
R 348
R e s erved
R e s erved
R e s erved R e s ervedR e s erved 10K
note: 7/6-change power cap dummy
2
Front Panel For EMI
5V_DUAL
3D3V _SYS
C C
3D3V _SB
1
0.1uF
BC299
0.1uF
BC303
0.1uF
BC304
0.1uF
BC305
0.1uF
BC306
0.1uF
BC307
0.1uF
BC308
R 349
4.7K
5V _S B _SYS
2
I C H_S Y S _RS TJ 6, 12, 18

1
R 350 R 351
0.1uF
BC311
330 330
DUMMY
R 352 5V _S B _SYS
5V _S YS
2
1 2
1
330
D UMMY R 353
1-3: HD LED 330 3D3V _SB
6-8 : PW LED
1
R 354 9-11 : POWER BUTTON 1 R355 2
1
330 5-7 : RESET
R356
DUMMY 4.7K
2
C N 17 330
2
H DLE DP 1 2 LE DP
HD_LED_P FP_PWR/SLP
I DE _LE D 3 4 P MS LED S 1LED 18
19 I DE _LE D HD_LED_N FP_PWR/SLN
5 6 P B TN
RST_SW_N PWR_SW_P
I C H_S Y S _RS TJ 7 8
B RST_SW_P PWR_SW_N B
9
RSD KEY
Header_2X5_10
P B TNJ_S IO 30
5V _S YS
J 22
1
1
2
3 2
30 I R R X 3
4
4
30 I R TX 5
5
Header_1X5_2
B U Z1
1
Buzzer 2
+
BUZZER
-
5V _SYS
Buzzer
J 50
1
1
3
3
1 2 S P K RJ 4 DUMMY
R363 4 R364
100 Header_1X4_2 220 J1
D 14 1 2 1
B A T54C 18 I N TR U DE RJ
2
2
C
18, 26 SPKR R365

A Header_1X2 A
3 1 2 B Q44
MMB T3904 B C312
1
E
30 S IO_BEEP
2.2K 0. 1uF
FOXCONN PCEG
Title
note: 7/6-change buzzer to header MISC Connector / ATX Power Conn
C 848M02 F

5 4 3 2 1

5 4 3 2 1
5V _S YS
3D3V _S YS 3D3V _S YS 5V _SYS
-12V _SYS 5V _S YS 12V _SYS 3D3V _SYS 3D3V _S YS
-12V _SYS 5V _S YS 12V _S YS

Note: 20-24 mils
C N19
B1 A1
-12V TRST-
D B2 A2 C N20 D
TCK +12V
B3 A3 B1 A1
B4 GND1 TMS A4 B2 -12V TRST- A2
TDO TDI TCK +12V
B5 A5 B3 A3
+5V1 +5V7 I N TB J GND1 TMS
B6 A6 B4 A4
I N T CJ B7 +5V2 INTA- A7 I N T DJ B5 TDO TDI A5
I N TA J INTB- INTC- +5V1 +5V7 I N TGJ
B8 A8 B6 A6
INTD- +5V8 3D3V _SB I N T FJ +5V2 INTA- I N TE J
B9 A9 B7 A7
B10 PRSNT1- RSV_3 A10 I N T HJ B8 INTB- INTC- A8
RSV_1 +5V9 INTD- +5V8
B11 A11 B9 A9
PRSNT2- RSV PRSNT1- RSV_3
B12 A12 B10 A10
GND2 GND13 RSV_1 +5V9 3D3V _SB
B13 A13 B11 A11
B14 GND3 GND14 A14 B12 PRSNT2- RSV A12
RSV_2 3.3VAUX GND2 GND13
B15 A15 I CH_P _P CIRE S TJ 17, 19, 20, 21,29 B13 A13
33M_P1 GND4 RESET- GND3 GND14
6 CK _33M_P CI1 B16 A16 B14 A14
B17 CLK +5V10 A17 B15 RSV_2 3.3VAUX A15 I CH_P _P CIRE S TJ
GND5 GNT- G N T2J 20 GND4 RESET-
P RE Q2J B18 A18 6 CK _33M_P CI2 33M_P2 B16 A16
B19 REQ- GND15 A19 B17 CLK +5V10 A17
+5V3 PME- PMEJ 17, 20, 21,29 GND5 GNT- G N T1J 20
A D31 B20 A20 A D30 P RE Q1J B18 A18
A D29 AD(31) AD(30) REQ- GND15 PMEJ
B21 A21 B19 A19
AD(29) +3.3V7 A D28 A D31 +5V3 PME- A D30
B22 A22 B20 A20
A D27 GND6 AD(28) A D26 A D29 AD(31) AD(30)
B23 A23 B21 A21
A D25 AD(27) AD(26) AD(29) +3.3V7 A D28
B24 A24 B22 A22
AD(25) GND16 A D24 A D27 GND6 AD(28) A D26
B25 A25 B23 A23
CB E J3 +3.3V1 AD(24) IDS E L1 A D25 AD(27) AD(26)
20, 21,29 CB E J3 B26 A26 B24 A24
A D23 C/BE-(3) IDSEL AD(25) GND16 A D24
B27 A27 B25 A25
AD(23) +3.3V8 A D22 CB E J3 +3.3V1 AD(24) IDS E L2
B28 A28 B26 A26
A D21 GND7 AD(22) A D20 A D23 C/BE-(3) IDSEL
B29 A29 B27 A27
A D19 B30 AD(21) AD(20) A30 B28 AD(23) +3.3V8 A28 A D22
B31 A31 B29 A29
A D17 +3.3V2 AD(18) A D16 A D19 AD(21) AD(20)
B32 A32 B30 A30
B33 AD(17) AD(16) A33 B31 AD(19) GND17 A31 A D18
C/BE-(2) +3.3V9 FRA ME J A D17 +3.3V2 AD(18) A D16
20, 21,29 CB E J2 B34 A34 B32 A32
GND8 FRAME- FRA ME J 20, 21,29 AD(17) AD(16)
IRDY J B35 A35 CB E J2 B33 A33
20, 21,29 IRDY J IRDY- GND18 C/BE-(2) +3.3V9
B36 A36 TR D Y J B34 A34 FRA ME J
+3.3V3 TRDY- TR D Y J 20, 21,29 GND8 FRAME-
DE V S E LJ B37 A37 IRDY J B35 A35
20, 21,29 DE V S E LJ DEVSEL- GND19 IRDY- GND18
B38 A38 S TOPJ B36 A36 TR D Y J
GND9 STOP- S TOP J 20, 21,29 +3.3V3 TRDY-
L OCK J B39 A39 DE V S E LJ B37 A37
20, 29 L OCK J LOCK- +3.3V10 DEVSEL- GND19
C P E RRJ B40 A40 B38 A38 S TOPJ C
20, 21,29 P E RRJ PERR- SMB_CLK P S CLK 18, 21, 29,31 GND9 STOP-
B41 A41 L OCK J B39 A39
+3.3V4 SMB_DATA P S DA TA 18, 21, 29,31 LOCK- +3.3V10
S E RRJ B42 A42 P E RRJ B40 A40 P S CLK
20, 21,29 S E RRJ SERR- GND20 PERR- SMB_CLK
B43 A43 PAR B41 A41 P S DATA
+3.3V5 PAR P AR 20, 21,29 +3.3V4 SMB_DATA
CB E J1 B44 A44 A D15 S E RRJ B42 A42
20, 21,29 CB E J1 A D14 C/BE-(1) AD(15) SERR- GND20 PAR
B45 A45 B43 A43
AD(14) +3.3V11 A D13 CB E J1 +3.3V5 PAR A D15
B46 A46 B44 A44
A D12 GND10 AD(13) A D11 A D14 C/BE-(1) AD(15)
B47 A47 B45 A45
A D10 AD(12) AD(11) AD(14) +3.3V11 A D13
B48 A48 B46 A46
B49 A49 B47 A47
GND11 AD(09) A D10 AD(12) AD(11)
B48 A48
B49 AD(10) GND21 A49 A D9
A D8 CB E J0 GND11 AD(09)
B52 A52 C B E J0 20, 21,29
A D7 B53 AD(8) C/BE-(0) A53
AD(7) +3.3V12 A D6 A D8 CB E J0
B54 A54 B52 A52
A D5 +3.3V6 AD(06) A D4 A D7 AD(8) C/BE-(0)
B55 A55 B53 A53
A D3 B56 AD(5) AD(04) A56 B54 AD(7) +3.3V12 A54 A D6
AD(3) GND22 A D2 A D5 +3.3V6 AD(06) A D4
B57 A57 B55 A55
A D1 GND12 AD(02) A D0 A D3 AD(5) AD(04)
B58 A58 B56 A56
B59 AD(1) AD(00) A59 B57 AD(3) GND22 A57 A D2
A CK 64J +5V4 +5V11 RE Q64_1J A D1 GND12 AD(02) A D0
B60 A60 B58 A58
B61 ACK64- REQ64- A61 B59 AD(1) AD(00) A59
NC2
NC1
+5V5 +5V12 A CK 64J +5V4 +5V11 RE Q64_2J

B62 A62 B60 A60
+5V6 +5V13 B61 ACK64- REQ64- A61
NC2
NC1
+5V5 +5V12
B62 A62
NC2
NC1
+5V6 +5V13
P CI_S LOT P CI_S LOT
NC2
NC1
A D[ 0. . 31]
A D[ 0. . 31] 20, 21,29
-12V _SYS 5V _SYS 12V _SYS 3D3V _S YS 3D3V _SB
IDS E L1 R366 1 2 330 A D18

IDS E L2 R367 1 2 330 A D17 -12V _SYS 5V _SYS 3D3V _S YS 3D3V _SB
B B
P S CLK
S MB _CLK _RESUME 18, 21, 29,31
0.1uF
BC313
0.1uF
BC315
0.1uF
BC316
0.1uF
BC317
P S DATA
S MB _DA TA _RESUME 18, 21, 29,31
0.1uF
BC314
0.1uF
BC318
0.1uF
BC319
0.1uF
BC320
0.1uF
BC321
D UMMY DUMMY D UMMY D UMMY
DUMMY
D UMMY D UMMY DUMMY DUMMY

R 370 1 2 G NTB J 20
DUMMY
3D3V _SYS
7/7:change BC313~ BC321 to dummy
R N 34 Del EC48 ~EC54
*
1
3
2
4
I N T DJ
I N T CJ
I N TDJ
I N TCJ
20
20
5 6 I N TB J
I N TB J 17, 20
7 8 I N TA J 5V _SYS
I N TA J 17, 20 R N717
8.2K 8 7 RE Q64_3J
RE Q64_3J 29
6 5 RE Q64_2J
R N 35 4 3 RE Q64_1J
*
1
3
2
4
I N TE J
I N T FJ
I N TE J 20, 29 2 * 1 A CK 64J
A CK 64J 29
I N TFJ 20, 29
5 6 I N TGJ
I N TGJ 20, 29 2.7K
7 8 I N T HJ
I N THJ 20, 21,29 8P 4R0603
8.2K 3D3V _S YS +/-5%
R N 36 R N37
A
*
1
3
2
4
P RE Q2J
P RE Q1J
20
20
*
1
3
2
4
S E RRJ
DE V S E LJ A
5 6 5 6 IRDY J
P RE Q0J 20, 29
7 8 7 8 L OCK J
8.2K 8.2K
R N 38 R N39
*
1
3
2
4
P RE Q3J
P RE Q4J
20, 21
20
*
1
3
2
4
FRA ME J
TR D Y J
5 6 5 6 S TOPJ
7 8
P RE QA J
P RE Q5J
20
20 7 8 P E RRJ FOXCONN PCEG
8.2K 8.2K Title
PCI Connectors 1,2
C 848M02 F

5 4 3 2 1

5 4 3 2 1
PCI SLOT3
5V _SYS
3D3V _SYS 3D3V _S YS

D D
-12V _SYS 5V _S YS 12V _S YS
Note: 20-24 mils

C N21 3D3V _SB
B1 A1
-12V TRST-
B2 A2
B3 TCK +12V A3
GND1 TMS
B4 A4
TDO TDI
B5 A5
+5V1 +5V7
B6 A6 I N TFJ 20, 28
B7 +5V2 INTA- A7
20, 28 I N TGJ INTB- INTC- I N THJ 20, 21,28
20, 28 I N TE J B8 A8
INTD- +5V8
B9 A9
B10 PRSNT1- RSV_3 A10
RSV_1 +5V9
B11 A11
B12 PRSNT2- RSV A12
GND2 GND13
B13 A13
GND3 GND14
B14 A14
RSV_2 3.3VAUX
B15 A15 I CH_P _P CIRE S TJ 17, 19, 20, 21,28
33M_P3 GND4 RESET-
6 CK _33M_P CI3 B16 A16
CLK +5V10
B17 A17
GND5 GNT- G NT0J 20
20, 28 P RE Q0J B18 A18
REQ- GND15 PMEJ
B19 A19 PMEJ 17, 20, 21,28
A D31 +5V3 PME- A D30
B20 A20
A D29 AD(31) AD(30)
B21 A21
AD(29) +3.3V7 A D28
B22 A22
A D27 B23 GND6 AD(28) A23 A D26
A D25 AD(27) AD(26)
B24 A24
AD(25) GND16 A D24
B25 A25
CB E J3 B26 +3.3V1 AD(24) A26 IDS E L3
20, 21,28 CB E J3 C/BE-(3) IDSEL
A D23 B27 A27
AD(23) +3.3V8 A D22
B28 A28
A D21 GND7 AD(22) A D20
B29 A29
A D19 B30 AD(21) AD(20) A30
AD(19) GND17 A D18
B31 A31
A D17 +3.3V2 AD(18) A D16
B32 A32
C B33 AD(17) AD(16) A33 C
C/BE-(2) +3.3V9 FRA ME J
20, 21,28 CB E J2 B34 A34
GND8 FRAME- FRA MEJ 20, 21,28
IRDY J B35 A35
20, 21,28 IRDY J IRDY- GND18
B36 A36 TR D Y J
+3.3V3 TRDY- TR D Y J 20, 21,28
DE V S E LJ B37 A37
20, 21,28 DE V S E LJ DEVSEL- GND19
B38 A38 S TOPJ
GND9 STOP- S TOPJ 20, 21,28
L OCK J B39 A39
20, 28 L OCK J LOCK- +3.3V10
P E RRJ B40 A40
20, 21,28 P E RRJ PERR- SMB_CLK P S CLK 18, 21, 28,31
B41 A41 P S DATA 18, 21, 28,31
S E RRJ +3.3V4 SMB_DATA
20, 21,28 S E RRJ B42 A42
SERR- GND20 PAR
B43 A43 PAR 20, 21,28
CB E J1 B44 +3.3V5 PAR A44 A D15
20, 21,28 CB E J1 A D14 C/BE-(1) AD(15)
B45 A45
B46 AD(14) +3.3V11 A46 A D13
A D12 GND10 AD(13) A D11
B47 A47
A D10 AD(12) AD(11)
B48 A48
B49 AD(10) GND21 A49 A D9
GND11 AD(09)
A D8 B52 A52 CB E J0
AD(8) C/BE-(0) CB E J0 20, 21,28
A D7 B53 A53
B54 AD(7) +3.3V12 A54 A D6
A D5 +3.3V6 AD(06) A D4
B55 A55
A D3 B56 AD(5) AD(04) A56
AD(3) GND22 A D2
B57 A57
A D1 GND12 AD(02) A D0
B58 A58
B59 AD(1) AD(00) A59
A CK 64J +5V4 +5V11 RE Q64_3J
B60 A60
28 A CK 64J ACK64- REQ64- RE Q64_3J 28
B61 A61
NC2
NC1
+5V5 +5V12
B62 A62
+5V6 +5V13
P CI_S LOT
NC2
NC1
A D[ 0. . 31]
A D[ 0. . 31] 20, 21,28
B B
IDS E L3 R375 1 2 330 A D16
-12V _SYS 3D3V _S YS 3D3V _SB 5V _S YS 3D3V _S YS
B C325
0.1uF
BC322
0.1uF
BC323
0.1uF
BC324
0. 1uF
A A
FOXCONN PCEG
Title
PCI SLOT3
C 848M02 F

5 4 3 2 1

5 4 3 2 1
5 V_SYS 5V_SB_SYS N ote :

* Pla c e CA P c los e to I T8712. R376
BC326 BC327 T MPIN2 S I OVREF
S IOVREF
*
* 0.1uF
25V,X7R,+/-20% * 22uF
10V, Y5V, +80%/-20%
7/7:change BC327 to dummy
2
C0603 C1206 BC329 RT2 10K
D UMMY 0.1uF 10K +/-1% * BC328
* 16V,Y5V,+80%/-20%
T
R0603R0603
35
99
67
0.1uF
4
C0603 +/-5% C0603
D UMMY
del rn40 680ohm (com port pull low resistor) 0703 U22
VCC
VCC
VCC
VCCH
D 16V,Y5V,+80%/-20% D
1
PD[7..0]
PD[7..0] 32
DCDAJ 118 116 P D7
32 DCDAJ DCD1# PD7
R IA J 119 115 P D6
32 R IA J RI1# PD6
32 C T SAJ C T SAJ 120 114 P D5
D T RAJ CTS1# PD5 P D4 A
32 D T RAJ 121 113
DTR1#/JP1 PD4
Parallel Port
R T SAJ 122 112 P D3
32 R T SAJ RTS1#/JP2 PD3
D S R AJ 123 111 P D2
Serial Port 1/2

32 D S R AJ DSR1# PD2
N ote : 32 SOUT A
SOUT A 124
SOUT1/JP3 PD1
110 P D1
I f 75232 is c onne c te d, ple a s e us e 680 ohm to be the pull S INA 125 109 P D0
32 S INA SIN1 PD0
dow n r e s is tor va lue . Sinc e pow e r e d by 12V, 75232 has a 126 108 STBJ S T BJ 32 S I OVREF S I OVREF S IOVREF
DCD2# STB# AFDJ
127 107 AF DJ 32
ve r y s tr ong inte r na l pullup. I t is hard to be pulled low. RI2# AFD# ERRJ
128 106 E RRJ 32
( Ple a s e s e e s pe c if ic a tion f or de ta il of power on strapping CTS2# ERR# PINITJ
1 105 P INIT J 32
DTR2#/JP4 INIT# SLINJ 30.1K * BC330
s e tting) 2 104 S L INJ 32
RTS2# SLIN#
3 103 ACKJ
A C K J 3D3V_SB32
S IO_RSMRST J R377 0 R0603
R SMRST J 18 * R378 0.1uF D UMMY
*
DSR2# ACK# BUSY +/-5%
5 102 B US Y 32 C0603
SOUT2 BUSY PE +/-1%
FDC Connector 6
SIN2 IT8712F_v0.7 PE
101 PE 32 D UMMY 25V,Y5V,+80%/-20%
1 R916
100 SLCT R0603
SLCT SLCT 32
Power-on Control
5 V_SYS
4.7K
27 SIO_BEEP 20
JSBB2/GP27 T MPIN1 R380 0 +/-5% R0603
21 79 T HERMDA 11
**
JSBB1/GP26 GP40
*
1 2 R N41 T K00J 22 78
2
JSBCY/GP25 PWROK2/GP41
Gameport/MIDI
3 4 150 W PT J 23 77 T HRM_OUT2 BC331 R382 0 +/-5% R0603
JSBCX/GP24 GP53 IC H_ T HRM_UP 18 T HERMDC 11
+/-5% P S _ONJ 3.3nF
5
7
6
8 8P4R0603
R DAT AJ
D S K C HGJ
24
25
JSAB2/GP23 PSON#/GP42
76
75
P S O NJ
P A NS W HJ
P S _ ONJ
+/-1%
27
P BT NJ_SIO 27
* 16V,NPO,+/-5%
*
JSAB1/GP22 PANSWH#/GP43 P W R O NJ_SIO R0603 C0603
26 72 S IO PWRBT NJ 18
C R386 150 R0603 +/-5% IND E XJ JSACY/GP21 PWRON#GP44 BC332 R384 33 A C
27 71
*
JSACX/GP20 PSIN/GP45 1uF

J2
28
29
MIDI_OUT/GP17
MIDI_IN/GP16
5 V_SYS 3D3V_SB * D UMMY A
1 2 30 R ESETCONJ R387 +/-5% 10K R0603
**
1 2 RESETCON#/CIRTX/GP15 3D3V_SB
MISC.
4 85 S IO_RSMRST J R388 +/-5% 10K R0603
X 4 D E N SELJ RSMRST#/CIRRX/GP55
5 6 51 66
1
5 6 DENSEL# IRTX/GP47 IRT X 27
7 8 IND E XJ 63 70
7 8 INDEX# IRRX/GP46 IR RX 27 Voltage Monitor
R917
9 10 MOT EAJ 52 68 R389 1M +/-5% R0603 SIO_VBAT
*
9 10 MTRA# COPEN#
4.7K
11 12 D R V BJ 55
11 12 D R V AJ
DRVB# R390 10M
13 14 54 SIO_VBAT
*
13 14 DRVA#
Floppy I/F
15 16 MOT EBJ M T RBJ/T HRMOJ 53 84 +/-5%
15 16 MTRB#/THRMO# PCIRST4#/SCRPRES#/GP10 SLP_S3J 18
2
-12V_SYS
SCR I/F
17 18 D IR J 57 34 7/7:del R392,393 V CCP 3 D3V_SYS 5 V_SYS 12V_SYS
17 18 DIR# PCIRST3#/SCRCLK/GP11 S KT OCCJ 11
19 20 ST EPJ 58 33
19 20 W D AT AJ
STEP# PCIRST2#/SCRIO/GP12 P WROK1 R395 10K ADD IR CONNECT 07/10/04
21 22 56 32 5 V_SYS
*
21 22 W GAT EJ WDATA# PWROK1/SCRPFET#/GP13 +/-5%
23 24 60 31 +/-1% +/-1% +/-1% +/-1%
23 24 WGATE# PCIRST1#/SCRRST/GP14
25
27
25 26
26
28
T K00J
W PT J
62
64
TRK0#
98 V IN0
* R0603 * R0603 * R0603 * R0603
27 28 WPT# VIN0 10K 10K 6.81K 30K
29 30 R DAT AJ 61 97
29 30 RDATA# VIN1 R396 R398 R399 R400
31
33
31 32
32
34
S ID E1J
D S K C HGJ
59
65
HDSEL# VIN2
96
95
V IN2
V IN3
* R401
232K
33 34 DSKCHG# VIN3 V IN4 +/-1%
94
HEADER_2X17_3 (FDD) VIN4 V IN5 V IN0 R0603
93
VIN5
Hardware Monitoring
7/7:del R402 ,R404 L P CPDJ_SIO 36 92
18 L P C PDJ LPCPD# VIN6
F DD34MZO3 IC H_ P CIRST J 37 91 V IN2
13,20,24 IC H_ P CIRST J LRESET# VIN7
S I O_LDRQJ 38 90 V REF V IN3
18 L _DRQ0J LDRQ# VREF S IOVREF
S E RIRQ 39 89 T MPIN1 BC333 V IN4
18 S E R IRQ SERIRQ TMPIN1
B To
18,24 L _F RAMEJ
18,24 L_AD0
L _F RAMEJ
L_AD0
40
41
LFRAME#
LAD0
TMPIN2
TMPIN3
88
87
T MPIN2
* 1uF
10V,Y5V,+80%/-20% Note:
V IN5
B
L_AD1 42 12 C0603 Pla c e BC678 c los e to I T8712, a nd S I OVREF R403 R0603 56K
ICH
*
18,24 L_AD1 LAD1 FAN_CTL3/GP36 +/-5%
L_AD2 43 11
LPC I/F
18,24 L_AD2 LAD2 FAN_TAC3/GP37 D o N ot r e m ove this 1uF Ca p. of

L_AD3 44 10 F A NOUT2
18,24 L_AD3 LAD3 FAN_CTL2/GP51 F ANOUT 2 31 A V REF.
CK_33M_SIO 47 9 F A NI N2
6 CK_33M_SIO PCICLK FAN_TAC2/GP52 F ANOUT 1 F A NIN2 31
48 8 F ANOUT 1 31
CK_48M_SIO
CLKRUN#/GP50 FAN_CTL1 F A NI N1
6 CK_48M_SIO
49 7 F A NIN1 31
SIO_PME CLKIN FAN_TAC1 V I D0
18 L _PMEJ
73 19 V ID0 7,11
BC334 BC335 7/7:del R402 ,R404 PME#/GP54 VID0/GP30 V I D1
18 V ID1 7,11
VID1/GP31
* 22pF
50V,NPO,+/-10% * 22pF
50V,NPO,+/-10%
18 K BRST J
K BRST J 45
KRST#
VID2/GP32
VID3/GP33
17
16
V I D2
V I D3
V ID2
V ID3
7,11
7,11
C0603
0.1uF * *
+/-1%
R0603
D UMMY C0603 C0603
D UMMY 18
31
A20GATE
KBDAT A
A20GATE
KBDATA
46
80
GA20
KDAT
VID4/GP34
VID5/GP35
14
13
V I D4
V I D5
V ID4
V ID5
7,11
7,11
CONNECT SIO_VBAT TO VCCRTC 07/10/04 * BC336
R405
10K
K BCLK 81 Reserved +/-1% R406
31 K BCLK
KB/MS
MSDATA
KCLK 10K
31 MSDATA 82
MSCLK MDAT SIO_VBAT R0603
31 MSCLK 83 69 V CCRT C
R407 +/-5% 10K R0603 S E RIRQ
MCLK VBAT BC341
3 D3V_SYS
**
GNDD
GNDD
GNDD
GNDD
GNDA
R408 +/-5% 10K R0603

R N32
L _F RAMEJ
* 1uF
10V,Y5V,+80%/-20%
8P4R0603
3
*
1 2 D UMMY L_AD0
4 L_AD1
C0603
D UMMY
note: 7/6-change BC336 and BC337 to dummy
del BC338,BC339,BC340,BC337
15
50
74
117
86
5 6 +/-5% L_AD2
FB16
7 8 L_AD3 C0603 N ote :
P B T NJ_SIO 25V,Y5V,+80%/-20% Pla c e BC685 c los e to
R413 10K +/-5% 10K K BRST J S I O_GNDA A A A
1 2 I T8712 a s pos s ible
* * **
0.1uF
R414 10K +/-5% R0603 S I O_LDRQJ
* BC342 F B L0805 26 Ohm
+/-25%
A R415 +/-5% 2.2K R0603 SIO_PME 5 V_SYS A A
3D3V_SB
R416 +/-5% 2.2K R0603 L P CPDJ_SIO
BC343 BC344 BC345
0.1uF 0.1uF 0.1uF
for ESD solution
* 50V,Y5V,+80%/-20% * 50V,Y5V,+80%/-20% * 50V,Y5V,+80%/-20% FOXCONN PCEG
C0603 C0603 C0603
T itle
SIO8712
Size Document Number Rev
C ustom 848M02 F
Date: F riday, August 27, 2004 Sheet 30 of 34

5 4 3 2 1

5 4 3 2 1
5V _SYS 12V _S YS CPU FAN

CHASSIS FAN
12V _SYS R 775 12V _SYS
4.7K R 912
R 0603 0
* +/-5% R0603 *+/-5%
R e s erved R e s erved
* R907 DUMMY
4.7K
+/-5%
D
U55B
R0603
* R 496
0
D
8
* R 908 LM358M Q70 +/-5%
E
4.7K
+/-5%
* R499
0
*
E C69
100uF R 497 200K+/-5% R 0603
5
+
7
R909
2.2K B *
E C68
100uF
R 0805 5V _SYS
*
5V _SYS R0603 +/-5% 16V , +/-20% 6 +/-5% 16V , +/-20%
30 F A NOUT2
*
-
DUMMY R0805 CE 20D50H110 DUMMY D UMMY R0603 B CP 69 CE 20D50H110
DUMMY
C
4
4
12V _SYS D UMMY R 846
2
B C690 B C696 DUMMY 4.7K D 31
D UMMY
DUMMY
* R 774
4.7K
10uF
10V , Y 5V , +80%/-20% * * 0. 1uF
* +/-5%
R0603
8
+/-5% Q122 5V _SYS C1206 C0603 1N4148W
E
R 0603 3 R910 D UMMY
1
+
R 801 1 2.2K B 25V , X7R, +/-10%
*
200K 2 +/-5%
30 F A NOUT1
*
-
+/-5% U55A R0603 B CP 69 C N 22
2
R 0603 LM358M R 799 D 30 D UMMY 4 R 815
C
4
4
R 889 4
DUMMY D UMMY D UMMY 4.7K 3 4.7K
F A NIN2 30
*
+/-5% 3 +/-5%
2
DUMMY R 0603 1N4148W 2 R0603
* 1
B C689 B C697 1 B C447 R886
1
3.3K
** 0. 1uF
R890
* R887
1K R 0603 HE A DE R_1X4 (FA N4P) 25V , X7R, +/-10% * 10nF 10K
+/-5%
10uF C0603 +/-5% +/-5% E C61 C0603 * R0603
C1206
10V , Y 5V , +80%/-20% 25V , X7R, +/-10% C N 23 R 814
New FAN Header Definition R0603 DUMMY D UMMY * 100uF
16V , +/-20%
DUMMY
D UMMY D UMMY 3 4.7K pin1. GND CE 20D50H110

F A NIN1 30
*
3.3K pin2. Power
E C62 4 2 +/-5%
R0603
+/-5%
* 100uF
16V , +/-20%
1 R 0603
B C449 R885
pin3. Sense
DUMMY CE 20D50H110 10nF 10K pin4. Control DUMMY
* R888 F A N_CON * +/-5%

1K 25V , X7R, +/-10% C0603 * R0603 Peak fan current draw: 1.5A
+/-5% DUMMY
R0603 DUMMY
D UMMY Average fan current draw: 1.1A
Fan start-up current draw: 2.2A
Fan start-up current draw maximum duration: 1.0 second
C Fan header voltage: 12V +/- 10% C
SM BUS
3D3V _S YS 3D3V _SB
PS2 MS & KB R N 42
*
1
3
2
4
S MB _DA TA _RESUME
S MB _CLK _RESUME
5 6 S MB _DA TA_MAIN
7 8 S MB _CLK _MAIN
2.7K
5V_DUAL
12V _S YS
5V_DUAL
1
R 431
10K
B B
8
6
4
2
2
2
R N 43
FB 17
*
4.7K FB L0805 300 Ohm
D
D
7
5
3
1
G Q49
27 P W RGD_3V J
note: 7/9-short G 2N7002
D UMMY S
G
G
6,16 S MB _DA TA _MAIN S D S MB _DA TA _RESUME 18, 21, 28,29
D
C N 24
Q50
16
13 2N7002
FB 18 1 2 FB L0603 80 Ohm CLK _NE T03 5 11
G
30 K B CLK
G
3 9
FB 19 1 2 FB L0603 80 Ohm 1 7
30 K B DATA
2 17 6,16 S MB _CLK _MAIN
S D S MB _CLK _RESUME 18, 21, 28,29
4 8
D
6 10
B C346 B C347 Q51
12
14 2N7002
220pF 220pF
15
UP DOWN
P S 2-KBMS-2
P W R_NE T02
FB 20 1 2 FB L0603 80 Ohm CLK _NE T02

30 MS CLK
A FB 21 1 2 FB L0603 80 Ohm A
30 MSDATA
B C348
B C349 B C350
220pF 220pF 0. 1uF
FOXCONN PCEG
Title
Keyboard / Mouse / Fan
C 848M02 F

5 4 3 2 1

5 4 3 2 1
SERIAL PORTII
SERIAL PORT1
D D
5V _SYS 12V _SYS-12V _SYS
20
U 23
1 11
C N25 Removed
VCC +12V
16 9 N D C DA 1
30 RTS A J DA1 RA9 N DS RA
15 4 6
30 D TRA J DA2 RA3 N S INA
13 7 2
30 S OUTA
19 DA3 RA4 5 NRTS A 7
30 RIAJ RY1 DY1 NS OUTA
18 8 3
30 CTS A J RY2 DY3 NCTS A
17 3 8
30 D S RA J RY3 RA2 N D TRA
14 6 4
30 S INA RY4 DY2 N R IA
12 2 9
30 DCDAJ RY5 RA1
5
C45
C46
C47
C48
C49
C50
C51
C52
B C351 11 10
GND -12V
10
B C352 B C353
0. 1uF GD75232
150pF
150pF
150pF
150pF
150pF
150pF
150pF
150pF
0. 1uF 0. 1uF
< Implementation>
R e s erved
R e s erved
R e s erved
note: 7/6-change BC351,BC352,BC353 to dummy
C C
PRINTER PORT1
R 432
18 I C H _ R IJ N R IA
R 433
5V _S YS R e s erved
D
Q52
D 15 G
1 2
S
B B
R 434
S D103AW
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
*
R e s erved
30 P D[ 7. . 0] R N 48 R N 44 R N45 R N46 R N 47
P D0
P D1
*
1
3
2
4
R435
4.7K 26
C N26
R e s erved
P D2 5 6 1K 1K 1K 1K P RN1 1
P D3 7 8 P RN14 14
8
6
4
2
8
6
4
2
8
6
4
2
8
6
4
2
P RN2 2
33 P RN15 15
P RN15 P RN3 3 R e s erved
P RN14 P RN16 16
R N 49 P RN16 P RN4 4
30 S TB J *
1
3
2
4
P RN17 P RN17
P RN5
17
5
30 S L INJ P RN1
5 6 18
30 P I NITJ P RN2 P RN6
7 8 6
30 A F DJ P RN3 19
33 P RN4 P RN7 7 28
P RN5 20
P RN6 P RN8 8
R N 50 P RN7 21
P D4
P D5 *
1
3
2
4
P RN8
P RN9
P RN9 9
22
P D6 5 6 P RN10 P RN10 10
P D7 7 8 P RN11 23
P RN12 P RN11 11
33 P RN13 24
P RN12 12
25
C 53 C 54 C 55 C 56 C 57 C 58 C 59 C 60 C 61 C 62 C 63 C 64 C 65 C 66 C 67 C 68 C 69 P RN13 13
30 E R R J
27
PRINT PORT
P RNT25-M
30 A CK J
30 B US Y 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF
30 PE
A 30 S LCT 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF 180pF A
FOXCONN PCEG
Title
Serial / Parallel / CNR

C 848M02 F

5 4 3 2 1

5 4 3 2 1
ICH5 GPIO Summary

D Name Power Plane Type Description D
GPIO0 Main I REQA#

GPIO1 Main I REQB# or REQ5#
GPIO2 Main I PIRQE#
GPIO3 Main I PIRQF#
GPIO4 Main I PIRQG#
GPIO5 Main I PIRQH#
GPIO6 Main I PLC SMI#
GPIO7 Main I
GPIO8 Resume I LAN PME#
GPIO9 Resume I OC4#
GPIO10
GPIO11
Resume
Resume
I
I
OC5#
Pull-up Resistor 10K(Non-use)
FWH GPIO Summary
GPIO12 Resume I LPC PME#
Name Power Plane Type Description
GPIO13 Resume I Wake On LAN
GPIO14 Resume I OC6# FGPI0 Main I IDE1 Detect 33/66/100
GPIO15 Resume I OC7# FGPI1 Main I IDE2 Detect 33/66/100
GPIO16 Resume O GNTA#
FGPI2 Main I Unused
GPIO17 Main O GNTB# or GNT5# FGPI3 Main I Unused
C C
GPIO18 Main O
GPIO19 Main O
GPIO20 Main O
GPIO21 Main O
GPIO22
GPIO23
GPIO24
Main
Main
Resume
OD
O
I/O
Pull-up Resistor 10K(Non-use)
PCI Routing Summary
GPIO25 Resume I/O
GPIO26 Resume S1_LED PCI Dev Interrupt Req/Gnt ID Select
GPIO27 Resume I/O S3_LED PCI1 BCDA 2 AD18
GPIO28 Resume I/O PCI2 GFEH 1 AD17
GPIO29 PCI3 FGHE 0 AD16
GPIO30 LAN H 3 AD19
GPIO31
GPIO32 Main I/O Board ID1
GPIO33 Main I/O SATE_LED
GPIO34 Main I/O Board ID0
GPIO35 N/A
GPIO36 N/A
B B
GPIO37 N/A
GPIO38 N/A
GPIO39 N/A
GPIO40 Main I REQ4#
GPIO41 Main I LDRQ1#
GPIO42 N/A
GPIO43 N/A
GPIO44 N/A
GPIO45 N/A
GPIO46 N/A
GPIO47 N/A
GPIO48 Main O GNT4#
GPIO49 Main OD CPUPWRGD
A A
FOXCONN PCEG
Title
GPIO / IRQ / IDESEL Map

C 848M02 F

5 4 3 2 1

5 4 3 2 1
To Rev 1.1
For FMB1.5:
Del R714.
Add BC597,BC598,BC599_2200pF/NA.
Change BC117,BC118,BC151,BC152,BC153,BC159,BC160,BC 161,BC185,BC187,BC188,BC189,BC190,BC191,BC192 From 1uF to 22uF X5R.
D Change BC103~BC107,BC114~BC116,BC95~BC99 From 2.2uF to 22uF X5R. D
Change TC2,TC3 footprint to CTD.

NA BC559,BC547.
For VRM10.1:
Change R600 from 1k to 2k,R738,R737 from 470 to 1k.
Add R784 2k/NA,R776_30 k,R777_20k 1%,BC590_5600pF,R778_0/NA,R779_0,R780_0/NA.
Del Q90,Q94,BC541,BC552,Q92,Q96,R695,R709.
Change Q91,Q95 from 06N03L to 80N02R,Q89,Q93 from 12N03L to 60N02R.
Add Q101_60N02R,Q102_80N02R,L20_500nH,U47_SC1211,D25_1N4148,R781_1,R782_100,
R783_1,BC591_1uF/C0805,BC592_4.7uF/C1206,BC593_1uF/X7R,BC595_4700pF/X7R,BC596_4.7uF/C1206.
For Fan Speed:
Attach R496,R499_0.
For 1.5V_CORE:
C
Del U35,EC54. C
Add U46_LM358,BC586,BC588_0.01uF,BC587,BC589_0.1uF.
Change R237 value to 1.24k 1%,R235 to 0,R231 to 549 1%,R226 to 1.54k 1%.
NA Q83,R612.
Change Q38,Q39 to SDU3055L2.
08/21
For USB/1394: Change VCCVID_GD pull-up voltage to 1.2v.
NA TF1~TF8,F1,F2,F5~F8. NA R699.
Add R742~R769_0.
06/12/04
For Audio: Change R672 to C281
Add L19_120 ohm@100M,R791,R792_22k,R785,R786,R787,R790. Change BC449 to R9956
Change R27,R20,R8,R17 value to 80ohm@100M Ferri Bead.
NA U1,FB1,BC1,C276. 08/17/04
1. Add R5 at clock pin20 for reset issue
For DDR_VTT:
Del EC56,EC57,Q87,R679,R680.
B Add U43,R770,R771. B
For 3D3VSB:
Del U18,R225,R219.
Add U45_AIC1086,R772,R773.
For GMCH_VTT:
NA GMCH_VTT Module,Add RN83.
07/12
Add Board ID2.
07/15
For case open:
Add J3,R318
A For WOM: A
Add CN32,R579,R578,Q75
07/16
Modify Board ID0~4
FOXCONN PCEG
Title
07/16 Modify List
Final Sch is date 0716 Size
C
Doc ument Number
848M02
Rev
F

5 4 3 2 1

Foxconn 848M02 Rev A

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5 4 3 2 1

Foxconn Precision Co. Inc.

05. Power Delivery Map 24. FWH

14. Springdale-GMCH-2 33. GPIO Summary

Dat e: Friday , A ugus t 27, 2004 S heet 1 of 34

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400/533/800 FSB CK-409 Clock

AGP 4X / 8X 4x/8x AGP DDR 400/333/266 Channel A DDR

PS2 Parallel Floppy Firmware HUB AC 97 Code 2.3

Size Doc ument Number

Dat e: Friday , A ugus t 27, 2004 S heet 2 of 34

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Dat e: Friday , A ugus t 27, 2004 S heet 3 of 34

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100/133/200 MHz Diff Pair

100/133/200 MHz Diff Pair

66 MHz Channel A DDR

48 MHz Channel B DDR

100 MHz Diff Pair SRC

Dat e: Friday , A ugus t 27, 2004 S heet 4 of 34

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5V_SYS 1.5V VCCQ

12V _VRM C O R E _C PU_SYS C O R E _C PU_SYS

> VRD 10 > 0.8375V~1.6V 60A

12V_SYS > 3.3V

Power Delivery Map

Dat e: Friday , A ugus t 27, 2004 S heet 5 of 34

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3D3V_SYS 3D3V_SYS 3D3V_SYS

3D3V_CLK 166_P _GMCH

16, 31 S MB _CLK _MAIN SCLK *FS_E/PCIIF2

* 150K Internal Pull-up

**150K Internal Pull-down

Dat e: Friday , A ugus t 27, 2004 S heet 6 of 34

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R 0603 +/-5% VDIFF PVCC2/EN_PH3 B C512 B C514

C0603 C 0805 DUMMY Q106 C1206

R 0603 +/-5% VRM10 C0603 D UMMY

ISUM ISEN3 2.2

16 17 R 530 0 G DUMMY R529 C TD C TD E C118

R0603 +/-5% +/-5% R0603 25V , X7R, +/-10% 1nF DUMMY

DUMMY DUMMY C 0603 50V , X7R, +/-10%

B C526 22nF R 532 39K P HA SE1

C0603 25V , X7R, +/-10% R0603 +/-5%

R 533 39K P HA SE2

R534 39K P HA SE3

12V _SYS B C925 0. 1uF

L4 Chok e Coil 1. 2uH V RM_EN

1500uF 1500uF 1500uF 1500uF 3. 3uF

Dat e: Saturday, August 28, 2004 S heet 7 of 34

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3D3V _S YS 12V _SYS 5V _S B_SYS

18 S LP _S4J MMB T3904 R 100

5V_DUAL Circuit 3D3V_SV Regulator

Dat e: Friday , A ugus t 27, 2004 S heet 8 of 34

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Dat e: Friday , A ugus t 27, 2004 S heet 9 of 34

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change Q30 2N3904 to MMBT3904 FOR FOOTPRINT 0705

* * * * * * * * * **** * ***