1892 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO.

9, SEPTEMBER 2007

Design and Analysis of a Performance-Optimized

CMOS UWB Distributed LNA
Payam Heydari, Senior Member, IEEE

Abstract—In this paper, the systematic design and analysis of receiver utilizing all available sub-bands. Even if such signal
a CMOS performance-optimized distributed low-noise amplifier processing was possible, each sub-band would require a distinct
(DLNA) comprising bandwidth-enhanced cascode cells will be LNA circuit, which leads to a bank of LNAs in the receiver. Such
presented. Each cascode cell employs an inductor between the
common-source and common-gate devices to enhance the band- design solution is, however, inefficient from both chip area and
width, while reducing the high-frequency input-referred noise. performance perspectives, demanding alternative circuit design
The noise analysis and optimization of the DLNA accurately ac- techniques. [2] and [3] independently designed the first lumped
counts for the impact of thermal noise of line terminations and all LNA circuits for the UWB radio using a cascode circuit and
device noise sources of each CMOS cascode cell including flicker high order wideband bandpass filters (BPFs) to provide wide-
noise, correlated gate-induced noise and channel thermal noise
on the overall noise figure. A three-stage performance-optimized band input matching. The noise figures (NFs) reported in [2]
wideband DLNA has been designed and fabricated in a 0.18- m and [3] were not flat across the 7.5-GHz bandwidth and the min-
SiGe process, where only MOS transistors were utilized. Measure- imum NF obtained by these works were 4 dB, and 2.5 dB (in
ments of the test chip show a flat noise figure of 2.9 dB, a forward bipolar technology), respectively. The in-band NF of the LNA
gain of 8 dB, and input and output return losses below 12 dB and in [2] increases to as much as 8 dB. CMOS common-gate (CG)
10 dB, respectively, across the 7.5 GHz UWB band. The circuit
exhibits an average IIP3 of 3.55 dBm. The 872 m 872 m amplifier providing a wideband input match with good reverse
DLNA chip consumes 12 mA of current from a 1.8-V DC voltage. isolation and inherent stability has been used in [4] to design a
UWB LNA circuit. However, the NF of the CG LNA is consid-
Index Terms—CMOS, distributed amplifier, linearity, low-noise
amplifier, noise figure, radio-frequency (RF) integrated circuits, erably larger than that of the CMOS common-source or cascode
SiGe, stochastic analysis, ultra-wideband (UWB). LNAs. Previously employed in common-source LNAs in [5] and
[6], the -boosting technique was proposed by [7] to improve
the NF performance of a UWB CG LNA.
I. INTRODUCTION On the other hand, recent advances in high-speed integrated
circuits and continuous scaling of minimum feature sizes of

U LTRA-WIDEBAND (UWB) wireless radio is capable of

carrying extremely high data rates over a short distance
(e.g., less than 15 meters). The spread spectrum characteristics
silicon-based devices have increased the interest in on-chip
implementation of transmission lines (TLs), which are key
components of broadband distributed circuits. An important
of wideband wireless systems, and the ability of the UWB wire- concern regarding distributed topologies is, however, higher
less receivers to resolve multipath fading, make UWB systems power dissipation and larger chip area compared to lumped
a promising wireless scheme for a variety of high-rate, short- circuits. Both the power dissipation and the area of a dis-
to medium-range wireless communications. Despite attributes tributed circuit increase with the number of stages, suggesting
enumerated for the UWB wireless radios, the RF front-end, par- a compromise between power dissipation and gain-bandwidth
ticularly the low-noise amplifier (LNA), entails several design product (GBW). Despite consuming more power than the
challenges due to stringent requirements. A key building block conventional lumped circuits, the distributed architectures are
in the UWB receiver’s RF front-end, the UWB LNA must re- highly amenable to technology scaling, which makes them a
tain good performance (i.e., low noise figure and high gain) topology of choice for future developments of silicon-based
across the system’s wideband frequency spectrum from 3.1 to millimeter-wave (MMW) broadband ICs.
10.6 GHz. Importantly, the same set of design requirements Silicon-based distributed circuits have gained considerable
should be satisfied in a UWB LNA design regardless of the type attention during the past decade. Inspired by Beyer’s work in
of UWB system (i.e., impulse radio or multiband) being used [8], Kleveland et al. presented a CMOS distributed amplifier
[1]. In fact, the input signal power at the receiver after the UWB (DA) and distributed ring oscillator [9]. Ref. [10] presented the
antenna and the pre-filter circuit is too low to allow any pre-pro- design of a conventional DA and utilized a simulated-annealing-
cessing for appropriate sub-band filtering in a multiband UWB based optimization methodology to optimize the design perfor-
mance. Refs. [11] and [12] used the differential and conven-
tional DA topologies, respectively, and fabricated those circuits
Manuscript received August 14, 2006; revised March 29, 2007. This work
was supported in part by a National Science Foundation (NSF) CAREER Award
in advanced CMOS technologies to achieve better performance.
under Contract ECS-0449433 and by Intel Corporation through a UC-Micro Ref. [13] presented the noise analysis of the distributed am-
grant. Equipment was provided by Broadcom Corporation. Chip fabrication was plifier, which was utilized later by [14] to design and analyze
provided by Jazz Semiconductor. a low-power distributed LNA circuit. Despite providing useful
The author is with the Department of Electrical Engineering, University of
California, Irvine, CA 92697 USA (e-mail: payam@uci.edu). approach for the high-frequency noise analysis of the DA, [13]
Digital Object Identifier 10.1109/JSSC.2007.903046 (and [14]), however, suffers from an analytical misconception,
0018-9200/$25.00 © 2007 IEEE
HEYDARI: DESIGN AND ANALYSIS OF A PERFORMANCE-OPTIMIZED CMOS UWB DISTRIBUTED LNA 1893

Fig. 1. The block diagram of a distributed circuit incorporating (a) actual CPWs, or (b) artificial LC circuits.

which will be explained in details in Section III-A1. Briefly [9]–[11], distributed mixers [18], and distributed oscillators
speaking, [13] first calculated the Fourier transform of noise cur- [9], [19]. The renewed interest in distributed circuits is mainly
rent (and not the Fourier transform of the autocorrelation) at the due to the capability of designing on-chip TLs, and high-Q
load termination, which itself is a nonstationary random process inductors.
[15], while omitting the partial correlation between the gate-in- Fig. 1 shows the general block diagram of a DA comprising
duced and channel thermal noise. The power spectral density TLs and gain stages distributed along the TLs, where each gain
(PSD) of noise was then obtained by calculating the magnitude stage can simply be a common-source (or common-emitter in
square of its Fourier transform, and setting it equal to the PSD. bipolar technology) stage. The TLs can be realized using either
This paper presents the analysis and design of a perfor- coplanar waveguides [see Fig. 1(a)] or cascaded LC circuits [see
mance-optimized CMOS distributed LNA (DLNA) incorpo- Fig. 1(b)].
rating bandwidth-enhanced cascode cells. A brief summary As a fundamental property, integrated circuits incorporating
of the design methodology of this DLNA first appeared in on-chip TLs trade delay for bandwidth [8], [20]. In frequency
[16]. The DLNA’s noise analysis takes into account the impact domain, the transistor’s parasitic capacitances are absorbed
of thermal noise of line terminations and all existing device into the constants of the TL [20], as also demonstrated in
noise sources of each cascode cell including flicker noise, Fig. 1(a) and (b). Hence, the circuit bandwidth is set by the
correlated gate-induced noise and channel thermal noise on cutoff frequency of the TLs.
the overall noise figure. The proposed stochastic modeling of The design of silicon-based distributed integrated circuits is
noise can easily be extended to any other DA topology. As will a topic of active research (for example, see [12], [21], [22]).
be explained in details, the proposed LNA achieves a lower
flat NF over a wider bandwidth than lumped implementations III. CMOS PERFORMANCE-OPTIMIZED DLNA
presented in [2]–[4]. It is noteworthy that the design of prefilter
The LNA is a key building block in a UWB wireless receiver.
preceding the wideband LNA in the receiver chain, which is
Challenges in UWB LNA design involves achieving 1) a NF of
used to filter out of band frequencies below 3.5 GHz and to
around 3.5 dB [23], (2) a relatively flat gain of at least 6 dB [2],
reduce strong interference due to the 5 GHz UNII and ISM
3) a minimum reverse isolation of 20 dB [2], and 4) a good
bands, is beyond the scope of this paper.
linearity (e.g., IIP3 8 dB, as specified in [23]).
The remainder of this paper is organized as follows. Section II
The LNA in this work is based on distributed circuit topology.
gives a brief overview of distributed circuits. Section III de-
In addition to the attributes enumerated in Section II, distributed
scribes the circuit topology and a method to calculate the
circuits are capable of providing an inherent wideband input/
bandwidth-enhancing inductors. This section presents the noise
output matching. This property is particularly useful in UWB
analysis and performance optimization methodology for the
RFIC design.
proposed DLNA, by first giving a brief overview of the current
In a conventional CMOS DA, where each cell only employs
state of knowledge. Section IV provides measurement results of
a common-source transistor, the input-output coupling through
the fabricated DLNA. Finally, Section V presents conclusions
overlap gate-drain capacitance of each transistor causes the real-
of this paper.
part of the DA’s propagation constant to become negative, re-
sulting in the amplitude growth of the output waveform at the
II. BACKGROUND: DISTRIBUTED CIRCUITS far-end load termination. The conventional DA is thus poten-
The distributed topology incorporating transmission lines tially unstable. In addition, any voltage/current variation in ei-
(TLs) was originally proposed by Ginzton et al. [17]. In- ther gate or drain TL’s terminations will be coupled to the other
sufficient technological capability to design area-efficient TL through of the common-source transistor. A DA with
distributed circuits delayed the usability of these circuits for a cascode cell can mitigate these deleterious effects [16], [20],
long time. They reappeared in the 1980s using a variety of pro- [21]. However, common-gate transistors of each cascode cell
cesses, such as GaAs or other III-V technologies, and recently begin to contribute significant noise to the output at high fre-
in CMOS process. Examples include distributed amplifiers quencies, thereby degrading the circuit’s NF.
1894 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007

Fig. 2. Circuit schematic of the proposed N -stage distributed LNA (N = 3 in our design.

Indicated in Fig. 2 is the schematic of the proposed -stage gate transistor in each cascode cell (cf. Fig. 2). The inductance
UWB DLNA comprising uniform gate and drain artificial LC , which leads to less than 10% of ripple in the passband
TLs and identical cascode cells. Each cell employs a cascode and a maximum increase of bandwidth, along with this boosted
configuration to guarantee stability across the entire bandwidth bandwidth are determined using the following analysis.
by providing isolation between the cell’s input and output termi- Fig. 3(a) and (b) shows the AC equivalent and high-frequency
nals. The interstage inductors of the gate (drain) TL along with small-signal model of the th cascode cell with BW-enhancing
gate (drain) parasitic capacitances of transistors , inductor , seen from the internal node of the cascode cell. The
, constitute cascaded ladder circuits with charac- high-frequency model of Fig. 3(b) is used to obtain the transfer
teristic impedance of , function .
where is the input capacitance of the common-source stage makes the equivalent impedance , seen looking
and is the output capacitance of the common-gate stage up from and expressed as
within each cascode cell. Both and stay constant over a , behave inductively at high
wide range of frequencies. In this design, both and are frequencies. This impedance effectively determines the series
chosen to match the 50 source/load resistances. resonant frequency of the transfer func-
As indicated in Fig. 2, each cascode cell incorporates an in- tion of the th cell, and is in parallel with the
ductor , , for the following reason: recall that output impedance of common-source transistor which
the gate and drain TLs boost the BW by absorbing the input is capacitive. Using the circuit model of Fig. 3(b), the transfer
and output parasitic capacitances of each cell. These TLs do function of the th cell is readily obtained as
not, however, affect the frequency roll-off due to large para-
sitic capacitance seen at the internal node of a conventional cas-
code cell, where the drain of the common-source transistor is
short-circuited to the gate of the common-gate transistor. More-
over, the input-referred noise of each cascode cell in the ab-
sence of this BW-enhancing inductor may rise considerably at
high frequencies, because the internal node’s parasitic capaci-
tances will lower the equivalent impedance seen at this node to
ground. The above problems are alleviated by using inductors
. The proposed DLNA topology is based on a for (1)
uniform distributed architecture, therefore, ,
for all . In the absence of , the parallel resonant frequency of the
In the absence of , the circuit bandwidth is primarily transfer function should have been
limited by the pole associated to the internal node of the cas-
code cells whose value is ,
where is the output capacitance of the common-source , however, lowers the parallel resonant frequency down to
transistor, is the input capacitance of the common-gate which is smaller than
transistor, and is the transconductance of the common- . This loaded resonant frequency is, therefore,
HEYDARI: DESIGN AND ANALYSIS OF A PERFORMANCE-OPTIMIZED CMOS UWB DISTRIBUTED LNA 1895

(a) (b)

Fig. 3. (a) AC equivalent of the BW-enhanced cascode cell. (b) Small-signal model.

frequency-dependent. Because the goal is to obtain so as

to maximize the 3 dB bandwidth , the frequency offset
of the loaded resonant frequency is eval-
uated at frequencies close to . The parallel resonant fre-
quency thus approximately becomes

(2)

To increase the bandwidth while avoiding large frequency

peaking, the transfer function should hold spe-
cific characteristics including the following.
1) The numerator of (1) should be in the form of a maxi-
mally flat polynomial, implying that the damping factor
is (see Fig. 4).
2) The denominator of (1) should exhibit small peaking in fre-
quency domain, which leads to additional BW increase. A
damping factor of 1/2 (i.e., ) results in a peaking of
Fig. 4. (1) Normalized magnitude response without BW-enhancing inductor.
1.25 dB. Additionally, the parallel resonant frequency (2) Normalized magnitude response with BW-enhancing inductor. (3) Numer-
becomes equal to the 0-dB frequency, where the magnitude ator polynomial. (4) Denominator of the transfer function.
response of the transfer function crosses the 0 dB axis after
experiencing 1.25 dB peaking (see Fig. 4).
By choosing , the 0-dB cutoff frequency of the larger inductance per unit length than CPWs or microstrip lines
transfer function is boosted to . Moreover, at the UWB frequency range and also avoid the circuit floorplan
it results in a frequency peaking of less than 10%, as also shown to spread too much in one dimension. TL inductors are designed
in Fig. 4. This criterion along with the above design guidelines 1 such that the same characteristic impedance of 50 is obtained
and 2 provide sufficient information to calculate the inductance at each tap-point of the gate and drain lines so as to maximize
and the new 3-dB bandwidth as follows: the power transfer toward the load termination. The gate line’s
inductor is larger than the drain line’s inductor , because
(3) the input capacitance is larger than the output capacitance of
each cell. To verify the bandwidth improvement, the DLNA with
(4) and without the inductor was simulated. As will be exten-
sively discussed in Section III-A, a three-stage circuit will result
The bias for cascode transistors in all constituent cells is pro- in minimum NF. The simulation result is demonstrated in Fig. 5,
vided by a single current mirror, as shown in Fig. 2. The artificial showing approximately 3.5 GHz bandwidth improvement.
LC gate line provides the wideband input impedance matching, The circuit’s NF is a function of the load terminations, par-
thereby obviating the need for inductive degeneration for each asitic capacitances of the cascode stage, the propagation con-
cascade cell of the DLNA circuit. stants of the LC TLs, and the number of stages. A compre-
The spiral inductors with Q-factors of 10 at 10 GHz are de- hensive noise figure analysis of the DLNA will be provided in
signed to realize interstage delay lines because they exhibit a Section III-A. It intends to address specific issues arising from
1896 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007

Fig. 6. Block diagram schematic of a four-stage DA with a test current source

Fig. 5. Simulation results of a conventional cascode amplifier, a three-stage demonstrating the backward and forward propagations.
DLNA without L , and a three-stage DLNA with L .

the analysis presented in [13] by calculating the PSD of noise

in the DLNA more accurately.

A. Noise Analysis
The dominant intrinsic noise sources in the DLNA are:
1) thermal noise from the input source impedance ( ;
is the gate line’s characteristic impedance defined earlier),
2) thermal noise from the gate and drain terminations, and
3) dominant noise sources associated with each MOS tran-
sistor including the channel thermal noise, gate-induced noise,
and flicker noise. Despite the fact that flicker noise presents
negligible impact on a high-frequency LNA circuit, for the
sake of completeness, its contribution to the overall NF will be
accounted for. The distributed structure of the DLNA provides Fig. 7. Forward propagation of dominant device noise sources of the k th cell
of the DLNA.
several paths for any given signal/noise source in the circuit.
Depending on the traveling direction of the wave toward the
far-end termination, wave propagation falls into two classes,
namely forward and backward propagation. For the same input can be neglected. Measurement result in
and output matching impedances, the in-band forward power Section IV indeed verifies the accuracy of this observation. The
gain from the input terminal to the output is maximized when voltage across the input capacitance of each cascode cell is am-
drain and gate TLs have the same propagation constants (i.e., plified by the small-signal gain for , and
the current from each cell flows in both directions with a phase
). This maximum forward power gain is
constant per each LC section of the drain TL (cf.
expressed as (see [13] for more details)
Figs. 7 and 8). The noise analysis, described in the following,
accounts for the impact of high frequency gate-induced noise,
(5)
and therefore, is an extension of [18]. It is based on a rigorous
stochastic modeling with some similarities to the approach pre-
The backward power gain at the near-end drain termi- sented in [13]. Section III-A1 briefly overviews basic concepts
nation is expressed as [13] of the stationary random process and the procedure introduced
in [13] for noise analysis.
(6) 1) Background and Current State of Knowledge: Device
noise sources in electronic circuits are implicitly assumed to
To better clarify the forward and backward propagation phe- fall in the class of wide-sense stationary (WSS) processes [15].
nomena, consider Fig. 6 showing the block diagram of a four- For a WSS random process , the first-order (i.e., mean)
stage DA with a test current source applied to the input tap of statistical average is time-invariant, and the second-order (i.e.,
the third cell. This figure clearly demonstrates backward and autocorrelation function) statistical average at time values
forward propagations of the wave, generated by , toward and , defined as , depends only on
the load termination. the difference between and , . Subsequently, it only
For convenience, MOS transistors and gate/drain inductors needs to be indexed by one variable rather than two variables,
are assumed to be lossless. The use of the inductance in i.e., (see [15]). Most importantly,
(3) allows us to keep the source-terminal impedance of each the Fourier transform of the autocorrelation of a WSS process,
common-gate transistor large across the UWB frequency range. widely known as power spectral density (PSD), is a determin-
Therefore, the noise contribution of common-gate transistors istic function whose integral is the average power of noise. On
HEYDARI: DESIGN AND ANALYSIS OF A PERFORMANCE-OPTIMIZED CMOS UWB DISTRIBUTED LNA 1897

tial correlation between the gate-induced and thermal

noise sources.
2) Finally, the noise contributions from all stages are ob-
tained by adding all the noise contributions for all values
from 1 to .
We address the above problems by developing an analytical
approach based on calculation of auto-correlation of the
DLNA’s output noise. Considering that the properties of
Fourier transforms for deterministic signals also hold for
random signals, we will first calculate the Fourier transform of
the noise current due to forward and backward amplifications.
Additionally, we take into account the frequency response of
each cell. We will then calculate the autocorrelation functions
of the output noise at the load termination. The PSD of noise
Fig. 8. Backward propagation of dominant MOSFET noise sources of the k th will then be obtained by taking Fourier transform of the au-
cell of the DLNA. tocorrelation functions for the DLNA circuit of Fig. 2. This
approach will be illustrated in details in Section III-A2.
2) Noise Contribution of MOS Transistors: Figs. 7 and 8
the other hand, the Fourier transform of the noise demonstrate the forward and backward propagations of domi-
is defined as [15]. In contrast to nant noise sources of the th cell, respectively. To perform the
deterministic signals, the Fourier transform of a random process noise analysis of partially correlated channel thermal noise
does not carry useful insight with practical implications, as it is and gate-induced noise of the th stage, the gate-induced
a random process by itself. noise is first decomposed into its correlated and uncorrelated
In an original work presented in [13], the noise figure of the components [20], [24], [25], i.e.,
conventional DA, where each cell is simply a common-source
transistor, was calculated. The noise sources that were taken into
account in the analysis were channel thermal noise and gate-
induced noise of transistors and thermal noise of source and load
resistive terminations. For the sake of argument, the analytical for (7)
procedure in [13] is summarized:
1) The output noise contribution of the th stage in an -stage where is the Boltzmann’s constant
distributed amplifier is calculated. In doing so: Joule K , is the absolute temperature,
a) It calculates the Fourier transform of the output noise for , is a tech-
current due to forward and backward amplifications nology-dependent constant, and is the correlation coefficient
of noise generators of the th stage. [defined as ] whose value for
b) It calculates the magnitude square of the Fourier long-channel devices is approximately 0.395 [20], [24].
transform of the total current in the load termination Moreover, for .
due to the th section by combining currents due to All the cells distributed along constituent gate and drain TLs
forward and backward amplifications, vectorially. of the DLNA in Fig. 2 are contributors to the output noise power
c) It assumes that the magnitude square of Fourier trans- as well as the overall noise figure. Similar to the approach pre-
form of the total current obtained in step b is equal to sented in [13] and summarized in the previous subsection, the
the PSD of the noise current, i.e., noise contribution of MOSFETs of the th stage to the output is
where and denote the PSD and the calculated by accounting for both forward and backward prop-
Fourier transform of the noise current , respec- agations of these noise sources. Because of nonzero correlation
tively. This is false, as is a random process between correlated noise sources, the overall average power of
itself, and cannot be equal to the PSD of noise. In additive combination of these noise sources is not equal to sum
fact, a theorem, proved in [15] and restated in the of the average powers of individual noise sources [15]. This
following, clearly specifies the relationship between notion will be taken into consideration during the forthcoming
a random process and its Fourier transform: noise calculations.
Theorem 1 ([15, p. 515]): Suppose that is a sta- In calculating the noise contribution of MOSFETs, the
tionary random process with autocorrelation TLs are assumed to have identical propagation constants. The
and the PSD . The Fourier transform of DLNA’s power gain with the same input and output matching
, is nonstationary white random process impedances will be maximized if the TLs have identical
with autocorrelation expressed as: propagation constants [8].
where is the delta function. First, the forward amplification of noise sources associated
Consequently, , and with the th cell is studied. Besides widening the BW, the in-
not (which is a random process), is equal ductor reduces the noise contribution of the cascode tran-
to . More importantly, [13] ignores the par- sistor of the th cell in Fig. 2. The dominant noise sources
1898 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007

are, therefore, the gate-induced noise, channel thermal noise, The symbol in (11) denotes the convolution operation.
and low-frequency flicker noise of the common-source transis- and represent the impulse response and current-gain
tors . Fig. 7 shows the forward amplification of dominant transfer function of each cell, respectively. After a certain
noise sources of the th cell through the signal paths of this cell amount of mathematical effort, the upper-bound of the autocor-
and cells. Using Fig. 7, the Fourier transform of the relation is found using the following expression:
output noise current due to MOSFET noise sources associated
with the th cell and their forward-propagated replicas is

(8)

where denotes the Fourier transform of the output noise

current due to forward amplification of MOSFET noise sources
of the th cell. and represent the Fourier transforms
of the channel thermal noise and flicker noise currents of , (12)
respectively. and are the Fourier transforms of the
correlated and uncorrelated components of the gate-induced is the cross-correlation of stochastic processes
noise current of , respectively. is the input-output and with power spectral density of . The
transfer function of the th cell. With identical cells and iden- channel thermal noise of transistor is a white noise process,
tical TL’s inductors, the corresponding noise sources of the implying that its autocorrelation is an impulse function
DLNA will be identical, i.e., ; [see the first term of (12)].
; The PSD of the output noise current due to the
for . Furthermore, MOSFET noise sources of the th stage and all its forward- and
for . backward-propagated replicas is obtained by taking the Fourier
The backward propagations of gate and flicker noise sources transform of (12), which results in
of the th cell, shown in Fig. 8, contribute to the output noise
current. The backward-propagated noises are all correlated with
the original noise sources at the gate terminal of the th cell.
Therefore, the Fourier transform of the noise current is calcu-
lated as (cf. Fig. 8)

(13)

(9) where represents the real part of a complex variable. The

input and output capacitances of cascode cells have already been
The Fourier transform of backward-propagated noise current, absorbed into the gate and drain TLs. Moreover, has res-
onated out the effect of parasitic capacitances at the internal
, reaches its peak when for
node of each cascode cell. Therefore, is simplified to the
and .
DC current gain of each cell, where and
The time-domain noise current at the output, , defined
[ is the physical gate resistance].
as , due to MOSFET noise sources of
The 1/3 factor in is to model the distributed effect of
the th stage is a random process, meaning that its Fourier trans-
gate resistance in MOS devices with large widths. The PSD of
form is a random process itself. On the other hand, as pointed
the output noise current due to the MOSFET noise sources of the
out in Section III-A1, the PSD of noise is not equal to the mag-
th stage and all its forward- and backward-propagated replicas
nitude square of its Fourier transform. The PSD of noise
thus becomes
should therefore be obtained by taking the Fourier transform of
its autocorrelation function, , which is defined as

(10)

where
(14)

where ( is the channel thermal-noise coef-

ficient and is technology-dependent), , and
with being the average power of flicker
(11) noise voltage [25].
HEYDARI: DESIGN AND ANALYSIS OF A PERFORMANCE-OPTIMIZED CMOS UWB DISTRIBUTED LNA 1899

Consequently, the overall PSD of the output noise current, tion. When is close to zero or , this term adds an addi-
, due to MOSFET noise sources is tional factor of one to the circuit’s NF, setting the minimum
NF to 3 dB. However, for other values of , this term is less
than unity and decreases with number of stages . This notion
actually implies that for , ; the noise powers
are superimposed at the output incoherently whereas the signal
and its propagated replicas are added coherently. As a result, the
contribution of the gate termination to the overall NF becomes
inversely proportional to , and can be made to be smaller
than unity.
Both the second and the third terms are inversely proportional
(15) to , which can be assumed to be negligible momentarily to
simplify the calculations. Differentiating the circuit NF with re-
3) Noise Contribution of Source and Load Impedances: spect to yields
Simple calculations reveal that the noise contributions of the
source impedance , the gate-line termination , and
the drain-line termination to the output are calculated as
follows (see [13]):
(22)
(16) As an approximation, the noise contribution of the flicker
noise can be neglected, which simplifies (22) to

(23)
(17)

(18) The device sizes are to be calculated to maximize gain across

the UWB frequency band. [26] presented contours of constant
4) Calculation and Optimization of the Overall NF: So far, gain-bandwidth product as function of gate and drain TLs’ at-
noise contributions of various noise sources to the output noise tenuations without any consideration for the noise figure min-
power of the DLNA have been calculated [cf. (15)–(18)]. Sub- imization. The design guidelines presented in [8] and [26] to
stituting the results of (15)–(18) in the definition of the spot NF maximize the GBW are primarily based on calculation of op-
yields timum gate and drain attenuation factors without providing any
quantitative discussion on the impact of number of stages . In
(19) fact, [26] stated that for greater than 4 the DA’s frequency
response does not change appreciably.
where The design goal of this paper is to maximize the gain and
minimize the NF across the UWB band. To achieve this goal, we
introduce a design procedure based on the approach proposed
in [26] with being set to optimum number of stages
from (22). The design optimization procedure utilizes the GBW
(20)
expression obtained from [26, eq. (1)] in terms of the 3 dB
bandwidth, i.e.,
and denotes the high-frequency NF and
. (24)
The flicker noise corner frequency, , is simply deter-
mined by equating the midrange frequency value of with where
the low-frequency value of , resulting in
DC gain,
(21) 3 dB cutoff frequency of the amplifier (rad/s),
MOSFET's maximum frequency of oscillation (rad/s),
where is the process-dependent flicker noise constant with
,
typical values less than [25]. Eq. (21) states that
increases in proportion with . ,
Eqs. (19) and (20) provide us with interesting design guide-
lines regarding the distributed LNA circuit of Fig. 2. First, the ,
second term of (20) is inversely proportional to the forward ,
power-gain of the circuit, which will be significantly reduced by
increasing the power gain and increasing the number of stages. where denotes the output resistance of the common-gate
The third term represents the contribution of the gate termina- stage in each cascode cell.
1900 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007

Fig. 9. Normalized gain-bandwidth contours for number of stages varying from N = 3 to N = 6.

TABLE I
COMPARISON BETWEEN THE K X FOROPTIMUM a AND b VALUES AND K X FOR a AND b VALUES
WHEN N = 6 (a = 0:75; b = 0:32 FOR N = 6)

To ensure a flat frequency response across the UWB band- Procedure 1:

width, the 3 dB cut-off frequency is set to 13 GHz. The fac- 1) For a flat magnitude response across the UWB band, set
tors and are both functions of gate and drain line GHz. The TLs’ cutoff frequency , defined
attenuations as demonstrated in [8] and [26]. The GBW for our as , is calcu-
application is several orders of magnitude smaller than , lated so as to ensure that , . To achieve max-
implying that the cannot exceed 0.25. For , imum gain for frequencies up to the UWB upper corner
[26] plotted the normalized gain-bandwidth contours and no- frequency, we set and . Moreover,
ticed that there is a single maximum at and , and is obtained by (22) for minimum
and predicted a maximum value of 0.255. This value is about 2% NF.
greater than the expected value of 0.25, which is due to approxi- 2) The maximum bias current for which the MOS transistors
mations used for attenuations of gate and drain TLs in equations of each cell remain in saturation is calculated for the bias
used to derive [26]. To investigate the effect of on the circuit used in the DLNA of Fig. 2. This current is readily
maximum GBW, the normalized gain-bandwidth contours are calculated as .
simulated for the DLNA of Fig. 2 and with varying from 3 to 3) Using (24), calculate the maximum DC gain, .
6. Fig. 9 shows the simulation results. 4) [26, eq. (2)] gives the DC gain of a conventional distributed
Table I shows the factors for optimum values amplifier as
of and for a specific number of stages , and compares
those with the factors obtained for optimum (25)
and values when . This comparison shows a small
sensitivity of the factor with respect to and This equation holds for the DLNA of Fig. 2 with identically
values. Based on the assertion of [26] which was also confirmed matched transistors and for each cascode cell.
by simulation data in Table I, GBW will not change with All the parameters in (25) are expressed with respect to the
greater than 4. Therefore, and values for are gate aspect ratio of transistors, .
used. Procedure 1 summarizes the proposed approach for the 5) Using step 4, calculate the . This results in min-
performance-optimized DLA design. imum NF and maximum gain.
HEYDARI: DESIGN AND ANALYSIS OF A PERFORMANCE-OPTIMIZED CMOS UWB DISTRIBUTED LNA 1901

where represents the low-field mobility, is the saturated

drift velocity, and is the process-dependent parameter [25].
Assuming the input DC bias voltage to be equal to the threshold
voltage, the above equation is simplified to

(27)

where is a corrective factor ranging from 0.3 to 0.5 to im-

prove the accuracy of the approximation. To estimate the in-
tercept points we determine the DLNA output in response to
the input sinusoidal voltage , first. The
signal at the near-end input terminal travels down the gate line,
while being amplified by each cell once it arrives at that cell’s
input terminal. The amplified signal will then travel toward the
Fig. 10. NF comparison for different number of stages.
load termination, while being combined with the signals at sub-
sequent tap-points along the drain TL. The signal propagation
6) Using (19) and (20), obtain minimum NF. mechanism is quantified using
In calculating the NF and gain expression, the device data pro-
vided by the foundry have been used. In doing so, a test struc- (28)
ture on the same 0.18- m SiGe technology was fabricated to
experimentally characterize various individual components in- is the signal amplified by the th stage, i.e.,
cluding the MOS transistors and varactors, transmission lines, , and is related to the input voltage using the I–V
short structures, open structures, and thru structures. Measure- characteristic of each cascode cell.
ment of individual MOSFET transistors in the test structure
provides the technology dependent parameters. Applying the
design procedure 1 to the DLNA of Fig. 2, results in the op-
timum ratio of 240 m 0.18 m. Using (22), the optimum
number of stages for 50 load terminations will be readily (29)
calculated, once the optimum ratio is obtained. For the
DLNA circuit of Fig. 2, . To verify these calculations, The third-order input intercept point is thus obtained as
the DLNA was designed and simulated is Cadence. Four perfor-
mance-optimized DLNA circuits with number of stages varying IIP3
from to were separately designed and simulated.
To capture the gate-induced noise in simulations, the BMIS4 (30)
level 54 MOS model has been utilized. Fig. 10 shows simu-
lated noise figure with respect to frequency. It shows that the Eq. (30) states that the IIP3 of the DLNA is equal to that of a
three-stage DLNA achieves a minimum NF of 2.1 across the lumped LNA that uses the same cascode cell.
UWB spectral band. Section IV will summarize measurement
results of a three-stage DLNA prototype, which was designed IV. MEASUREMENT RESULTS
and fabricated in a 0.18- m SiGe process.
The UWB DLNA circuit of Fig. 2 was fabricated in a 0.18- m
B. Linearity Analysis SiGe BiCMOS process while only MOS devices were utilized.
Square spiral inductors were all fabricated on the top-most metal
A notch filter centered around the 802.11a 5 GHz frequency layer and exhibited a Q-factor of 10 at 10 GHz. The LNA test-
enhances the spurious-free dynamic range (SFDR) of the chip occupies a total area of 872 m 872 m including the
DLNA. Nevertheless, the proposed UWB DLNA must remain pad ring. The chip was directly mounted on a high-frequency
linear when receiving the desired weak wideband signal in the board. Both input and output terminals of the proposed dis-
presence of in-band narrowband interfering signals. An analyt- tributed LNA were terminated to on-chip square spiral induc-
ical study of the circuit’s linearity and the third intercept point tors for matched termination. DC pads incorporate ESD protec-
(IP3) provides useful insight about the circuit’s large-signal tion. To minimize the parasitic effects of chip-board interface,
performance. the chip was solder bumped, and flipped on the board. Fig. 11
To capture the short-channel effects of submicron CMOS shows the chip micrograph.
technology including mobility degradation and velocity satura- A test structure was separately fabricated in the same
tion, the analysis uses the well-known I–V characteristic of the 0.18- m SiGe technology to experimentally characterize
submicron MOS transistor [25], i.e., various individual passive and active components including
transistors, MOS varactors, transmission lines, short structures,
(26) open structures, and thru structures. Of particular interest is
characterization of noise parameters of the MOSFET, which
1902 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007

Fig. 11. Die photo of the UWB DLNA. Fig. 14. Comparison between the measured NF and (19).

Fig. 15. Measured and simulated input and output return losses.
Fig. 12. Measured forward gain and noise figure.

TABLE II
MEASURED IIP3 OF THE DLNA WITH RESPECT TO FREQUENCY

biasing was provided by the bias-Tees. Fig. 12 shows the mea-

sured and NF of the DLNA under operating conditions of
Fig. 13. Measured and simulated s versus frequency. and the overall current consumption of 12 mA.
The DLNA exhibits a flat NF of 2.9 dB across the entire 7.5 GHz
UWB frequency band. As explained in Section III-A4, at fre-
was carried out by the foundry. The measured average values quencies near or much lower than the lines’ cutoff frequency,
of , , and are 2.21, 4.1, and 5.2, respectively. Calculations the far-end termination impedance at the gate load will add 3 dB
using the holistic thermal model developed in BSIM4 model to the total NF, because the second term in (20) approaches its
results in , , and . maximum value of one. For , the second term is
-parameter measurements of the circuit were carried out less than unity and decreases with number of stages , and the
using the Anritsu 37247A vector network analyzer (VNA). Gate contribution of the gate termination to the overall NF becomes
HEYDARI: DESIGN AND ANALYSIS OF A PERFORMANCE-OPTIMIZED CMOS UWB DISTRIBUTED LNA 1903

TABLE III
PERFORMANCE COMPARISON OF LNA CIRCUITS PRESENTED IN PRIOR WORK AND THE PROPOSED DLNA

inversely proportional to , and can be made to be smaller

than unity. In our design, the gate line’s inductance is chosen to
be 942 pH and the gate input capacitance is 277 fF resulting in
a line cut-off frequency of GHz. Con-
sequently, the noise contribution of the gate load resistance be-
comes negligible. The measured forward gain of the LNA circuit
remains at 8 dB for frequencies up to 11 GHz. It experiences a
1.6 dB overshoot at 11.6 GHz, as also indicated in Fig. 12.
Designing a performance-optimized DLNA with eleven
inductors for a wideband frequency operation from 3.1 to
10.6 GHz demands careful layout development and post-layout
extraction/simulation. Fig. 13 demonstrate simulated and mea-
sured forward gain , verifying the accuracy of post-layout
simulation. Fig. 14 compares the measured NF of the DLNA
with (19). This comparison verifies an earlier analytical assess-
ment in Section III, which states that (19) sets an upper limit Fig. 16. Measured and simulated reverse isolation and gain.
for the NF of the DLNA.
Fig. 15 depicts the measured and simulated input and output
return losses, (dB) and (dB). and remain below measurement. The superior input–output isolation is partly due
12 dB and 10 dB, respectively, across the UWB frequency to the utilization of BW-enhanced cascode cells in the proposed
band. Post-layout simulation driven by electromagnetic extrac- DLNA.
tion of the entire circuit layout allows an accurate simulation The linearity and third-order intercept measurements were
result that closely follows the chip measurement. Good return performed using the Agilent 8565 spectrum analyzer. The mea-
losses from measurement, once again, proves an essential at- sured input-referred 1 dB compression-point at two
tribute of DAs in exhibiting wideband input/output matching. input frequencies of 4 GHz and 9 GHz was 13.1 dBm and
Simulations predicted slightly better and . The discrep- 12.2 dBm, respectively. The result from the two-tone test mea-
ancy can be attributed to the off-chip flip-chip measurements. surement at 7 GHz is shown in Fig. 17. The DLNA exhibits
Fig. 16 shows plots of measured and simulated reverse isola- an IIP3 of 3.4 dBm and an OIP3 of 6.2 dBm ay 7 GHz fre-
tion (dB) and the LNA’s gain (dB) versus frequency. The quency. Furthermore, the IP3 measurement was carried out for
in-band isolation varies between 50 dB and 27 dB, which is RF frequencies ranging from 3 GHz to 10 GHz. Table II sum-
verified by both simulation and measurement. Fig. 16 demon- marizes the result of IP3 measurement, where the average IIP3
strates the accuracy of and simulations compared to is 3.55 dBm.
1904 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 9, SEPTEMBER 2007

[6] A. Shameli and P. Heydari, “A novel ultra-low power (ULP) low noise
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HEYDARI: DESIGN AND ANALYSIS OF A PERFORMANCE-OPTIMIZED CMOS UWB DISTRIBUTED LNA 1905

Payam Heydari (S’98–M’00–SM’07) received the Society Darlington Best Paper Award, the 2005 National Science Foundation
B.S. and M.S. degrees (with honors) in electrical en- (NSF) CAREER Award, the 2005 Henry Samueli School of Engineering
gineering from the Sharif University of Technology, Teaching Excellence Award, the Best Paper Award at the 2000 IEEE Interna-
Tehran, Iran, in 1992 and 1995, respectively. He re- tional Conference on Computer Design (ICCD), the 2000 Honorable Award
ceived the Ph.D. degree in electrical engineering from from the Department of Electrical Engineering–Systems at the University of
the University of Southern California, Los Angeles, Southern California, and the 2001 Technical Excellence Award in the area
in 2001. of Electrical Engineering from the Association of Professors and Scholars of
During the summer of 1997, he was with Bell Iranian Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty
Labs, Lucent Technologies, Murray Hill, NJ, where at the EECS Department of the University of California, Irvine. His name
he worked on noise analysis in deep-submicron very was included in the 2006 Who’s Who in America and Who’s Who in Science
large-scale integrated (VLSI) circuits. During the and Engineering. He is an Associate Editor of the IEEE TRANSACTIONS ON
summer of 1998, he was with IBM T. J. Watson Research Center, Yorktown CIRCUITS AND SYSTEMS—PART I, and is a Guest Editor of the IEEE JOURNAL
Heights, NY, where he worked on gradient-based optimization and sensitivity OF SOLID-STATE CIRCUITS. He currently serves on the Technical Program
analysis of custom-integrated circuits. In August 2001, he joined the Uni- Committees of the IEEE Custom Integrated Circuits Conference (CICC),
versity of California, Irvine, where he is currently an Associate Professor of International Symposium on Low-Power Electronics and Design (ISLPED),
electrical engineering. His research interest is the design of high-speed analog, and International Symposium on Quality Electronic Design (ISQED). He was
radio-frequency (RF), and mixed-signal integrated circuits. He has authored or the Student Design Contest Judge for the DAC/ISSCC Design Contest Award
co-authored more than 55 journal and conference papers. in 2003, and a Technical Program Committee member of the IEEE Design and
Dr. Heydari is the recipient of the 2007 IEEE Circuits and Systems Society Test in Europe (DATE) from 2003 to 2004.
Guillemin-Cauer Best Paper Award, the 2005 IEEE Circuits and Systems