gd25q64 PDF

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GD25Q64C
DATASHEET
GD25Q64CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
- Content - Page
1. FEATURES ------------------------------------------------------------------------------------------------- 4
2. GENERAL DESCRIPTION ----------------------------------------------------------------------------- 5
3. MEMORY ORGANIZATION -------------------------------------------------------------------------- 6
4. DEVICE OPERATION ---------------------------------------------------------------------------------- 7
5. DATA PROTECTION ------------------------------------------------------------------------------------ 8
6. STATUS REGISTER ------------------------------------------------------------------------------------- 10
7. COMMANDS DESCRIPTION ------------------------------------------------------------------------- 12
7.1. Write Enable (WREN) (06H) ----------------------------------------------------------------------- 15
7.2. Write Disable (WRDI) (04H) ----------------------------------------------------------------------- 15
7.3. Write Enable for Volatile Status Register (50H) -------------------------------------------------- 15
7.4. Read Status Register (RDSR) (05H or 35H or 15H) -------------------------------------------- 16
7.5. Write Status Register (WRSR) (01H or 31H or 11H) ------------------------------------------- 16
7.6. Read Data Bytes (READ) (03H) -------------------------------------------------------------------- 17
7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH) ------------------------------------------- 17
7.8. Dual Output Fast Read (3BH) ---------------------------------------------------------------------- 18
7.9. Quad Output Fast Read (6BH) ---------------------------------------------------------------------- 19
7.10. Dual I/O Fast Read (BBH) ------------------------------------------------------------------------- 19
7.11. Quad I/O Fast Read (EBH) ------------------------------------------------------------------------- 20
7.12. Quad I/O Word Fast Read (E7H) ------------------------------------------------------------------ 22
7.13. Set Burst with Wrap (77H) -------------------------------------------------------------------------- 23
7.14. Page Program (PP) (02H) --------------------------------------------------------------------------- 24
7.15. Quad Page Program (32H) -------------------------------------------------------------------------- 25
7.16 Fast Page Program (FPP) (F2H) -------------------------------------------------------------------- 26
7.17. Sector Erase (SE) (20H) ----------------------------------------------------------------------------- 27
7.18. 32KB Block Erase (BE) (52H) --------------------------------------------------------------------- 28
7.19. 64KB Block Erase (BE) (D8H) --------------------------------------------------------------------- 28
7.20. Chip Erase (CE) (60/C7H) -------------------------------------------------------------------------- 29
7.21. Deep Power-Down (DP) (B9H) --------------------------------------------------------------------- 29
7.22. Release from Deep Power-Down or High Performance Mode and Read Device ID (RDI) (ABH) 30
7.23. Read Manufacture ID/Device ID (REMS) (90H) ------------------------------------------------- 31
7.24. Dual I/O Read Manufacture ID/Device ID (92H) ------------------------------------------------ 32
7.25. Quad I/O Read Manufacture ID/Device ID (94H) ----------------------------------------------- 32
7.26. Read Identification (RDID) (9FH) ------------------------------------------------------------------ 33
50 - 2 Rev.1.1
7.27. High Performance Mode (HPM) (A3H) ----------------------------------------------------------- 34

7.28. Program/Erase Suspend (PES) (75H) -------------------------------------------------------------- 34
7.29. Program/Erase Resume (PER) (7AH) -------------------------------------------------------------- 35
7.30. Erase Security Registers (44H) ---------------------------------------------------------------------- 35
7.31. Program Security Registers (42H) ------------------------------------------------------------------ 36
7.32. Read Security Registers (48H) ---------------------------------------------------------------------- 37
7.33. Enable Reset (66H) and Reset (99H) --------------------------------------------------------------- 38
7.34. Read Serial Flash Discoverable Parameter (5AH) ------------------------------------------------ 38
8. ELECTRICAL CHARACTERISTICS --------------------------------------------------------------- 43
8.1. Power-ON timing ------------------------------------------------------------------------------------- 43
8.2. Initial delivery state ---------------------------------------------------------------------------------- 43
8.3. Data retention and endurance ----------------------------------------------------------------------- 43
8.4. Absolute maximum ratings ------------------------------------------------------------------------- 44
8.5. Capacitance measurement conditions ------------------------------------------------------------- 44
8.6. DC characteristics ----------------------------------------------------------------------------------- 45
8.7. AC characteristics ----------------------------------------------------------------------------------- 45
9. ORDERING INFORMATION ------------------------------------------------------------------------- 48
10. PACKAGE INFORMATION --------------------------------------------------------------------------- 49
10.1. Package SOP8 208MIL ----------------------------------------------------------------------------- 49
10.2. Package WSON8 (6×5MM) ------------------------------------------------------------------------ 50
50 - 3 Rev.1.1
1. FEATURES
♦ 64M-bit Serial Flash ♦ Program/Erase Speed
- 8192K-byte - Page Program time: 0.6ms typical
- 256 bytes per programmable page - Sector Erase time: 50ms typical
- Block Erase time: 0.15/0.20s typical
♦ Standard, Dual, Quad SPI
- Chip Erase time: 25s typical
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD# ♦ Flexible Architecture
- Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3 - Sector of 4K-byte
- Block of 32/64K-byte
♦ High Speed Clock Frequency
- 120MHz for fast read with 30PF load ♦ Low Power Consumption
- Dual I/O Data transfer up to 240Mbits/s - 20mA maximum active current
- Quad I/O Data transfer up to 480Mbits/s - 5μA maximum power down current
- Continuous Read With 8/16/32/64-byte Wrap
♦ Advanced Security Features(1)
♦ Software/Hardware Write Protection - 3×1024-Byte Security Registers With OTP Locks
- Write protect all/portion of memory via software - Discoverable parameters(SFDP) register
- Enable/Disable protection with WP# pin
♦ Single Power Supply Voltage
- Top or Bottom, Sector or Block selection
- Full voltage range: 2.7~3.6V
♦ Cycling endurance
♦ Package Information
- Minimum 100,000 Program/Erase Cycles
- SOP8 (208mil)
♦ Data retention - WSON8 (6×5mm)
- 20-year data retention typical.
Note: (1) Please contact ELM for details.
50 - 4 Rev.1.1
2. GENERAL DESCRIPTION
The GD25Q64C(64M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#) and I/O3 (HOLD#).
The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad Output data is transferred
with speed of 480Mbits/s.
Connection Diagram
8-LEAD SOP 8-LEAD WSON
Pin Description
Pin Name I/O Description
CS# I Chip Select Input

SO (IO1) I/O Data Output (Data Input Output 1)
WP# (IO2) I/O Write Protect Input (Data Input Output 2)
VSS Ground
SI (IO0) I/O Data Input (Data Input Output 0)
SCLK I Serial Clock Input
HOLD# (IO3) I/O Hold Input (Data Input Output 3)
VCC Power Supply
Block Diagram
WP#(IO2) Write Control

Logic
Status
Write Protect Logic
Register
and Row Decode
Flash
High Voltage
HOLD#(IO3) Memory
Generators
SPI
SCLK Command &
Control Logic Page Address
Latch/Counter
CS#
SI(IO0) Column Decode And

256-Byte Page Buffer
SO(IO1)
Byte Address
Latch/Counter
50 - 5 Rev.1.1
3. MEMORY ORGANIZATION
GD25Q64C
Each device has Each block has Each sector has Each page has
8M 64/32K 4K 256 bytes

32K 256/128 16 - pages
2048 16/8 - - sectors
128/256 - - - blocks
Uniform Block Sector Architecture

GD25Q64C 64K Bytes Block Sector Architecture
Block Sector Address range
2047 7FF000H 7FFFFFH

127 ----- ----- -----
2032 7F0000H 7F0FFFH
2031 7EF000H 7EFFFFH
126 ----- ----- -----
2016 7E0000H 7E0FFFH
----- ----- -----
----- ----- ----- -----
----- ----- -----
----- ----- -----
----- ----- ----- -----
----- ----- -----
47 02F000H 02FFFFH
2 ----- ----- -----
32 020000H 020FFFH
31 01F000H 01FFFFH
1 ----- ----- -----
16 010000H 010FFFH
15 00F000H 00FFFFH
0 ----- ----- -----
0 000000H 000FFFH
50 - 6 Rev.1.1
4. DEVICE OPERATION
SPI Mode
Standard SPI
The GD25Q64C feature a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is
latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25Q64C supports Dual SPI operation when using the “Dual Output Fast Read” (3BH), “Dual I/O
Fast Read” (BBH) and “Read Manufacture ID/Device ID Dual I/O” (92H) commands. These commands allow
data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI
command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25Q64C supports Quad SPI operation when using the “Quad Output Fast Read”(6BH), “Quad I/O Fast
Read”(EBH), “Quad I/O Word Fast Read”(E7H), “Read Manufacture ID/Device ID Quad I/O” (94H) and“Quad
Page Program” (32H) commands. These commands allow data to be transferred to or from the device at four
times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional
I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the non-
volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# function is only available when QE=0, If QE=1, The HOLD# function is disabled, the pin acts as
dedicated data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation
of write status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK
signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD
condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD
operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high
during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the
HOLD# must be at high and then CS# must be at low.
Figure 1. Hold Condition
CS#
SCLK
HOLD#
HOLD HOLD
50 - 7 Rev.1.1
5. DATA PROTECTION
The GD25Q64C provides the following data protection methods:
♦ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
- Power-Up
- Write Disable (WRDI)
- Write Status Register (WRSR)
- Page Program (PP)
- Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
♦ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits define the section of the
memory array that can be read but not change.
♦ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
♦ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down Mode command.
Table1.0 GD25Q64C Protected area size (CMP=0)
Status Register Content Memory Content
BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion

× × 0 0 0 NONE NONE NONE NONE
0 0 0 0 1 126 to 127 7E0000H-7FFFFFH 128KB Upper 1/64
0 0 0 1 0 124 to 127 7C0000H-7FFFFFH 256KB Upper 1/32
0 0 0 1 1 120 to 127 780000H-7FFFFFH 512KB Upper 1/16
0 0 1 0 0 112 to 127 700000H-7FFFFFH 1MB Upper 1/8
0 1 0 0 1 0 to 1 000000H-01FFFFH 128KB Lower 1/64
0 1 1 0 0 0 to 15 000000H-0FFFFFH 1MB Lower 1/8
× × 1 1 1 0 to 127 000000H-7FFFFFH 8MB ALL
1 0 0 0 1 127 7FF000H-7FFFFFH 4KB Top Block
1 0 0 1 0 127 7FE000H-7FFFFFH 8KB Top Block
1 0 0 1 1 127 7FC000H-7FFFFFH 16KB Top Block
1 0 1 0 × 127 7F8000H-7FFFFFH 32KB Top Block
1 0 1 1 0 127 7F8000H-7FFFFFH 32KB Top Block
1 1 0 0 1 0 000000H-000FFFH 4KB Bottom Block
1 1 1 0 × 0 000000H-007FFFH 32KB Bottom Block
50 - 8 Rev.1.1
Table1.1. GD25Q64C Protected area size (CMP=1)
Status Register Content Memory Content
BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion

× × 0 0 0 ALL 000000H-7FFFFFH ALL ALL
0 0 0 0 1 0 to 125 000000H-7DFFFFH 8064KB Lower 63/64
0 0 0 1 0 0 to 123 000000H-7BFFFFH 7936KB Lower 31/32
× × 1 1 1 NONE NONE NONE NONE
1 0 0 0 1 0 to 127 000000H-7FEFFFH 8188KB L-2047/2048
1 0 0 1 0 0 to 127 000000H-7FDFFFH 8184KB L-1023/1024
1 0 0 1 1 0 to 127 000000H-7FBFFFH 8176KB L-511/512
1 0 1 0 × 0 to 127 000000H-7F7FFFH 8160KB L-255/256
1 0 1 1 0 0 to 127 000000H-7F7FFFH 8160KB L-255/256
1 1 0 0 1 0 to 127 001000H-7FFFFFH 8188KB U-2047/2048
1 1 0 1 0 0 to 127 002000H-7FFFFFH 8184KB U-1023/1024
1 1 0 1 1 0 to 127 004000H-7FFFFFH 8176KB U-511/512
1 1 1 0 × 0 to 127 008000H-7FFFFFH 8160KB U-255/256
1 1 1 1 0 0 to 127 008000H-7FFFFFH 8160KB U-255/256
50 - 9 Rev.1.1
6. STATUS REGISTER
S23 S22 S21 S20 S19 S18 S17 S16
Reserved DRV1 DRV0 HPF Reserved Reserved Reserved Reserved
S15 S14 S13 S12 S11 S10 S9 S8

SUS1 CMP LB3 LB2 LB1 SUS2 QE SRP1
S7 S6 S5 S4 S3 S2 S1 S0
SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP
The status and control bits of the Status Register are as follows:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register
progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when
WIP bit sets 0, means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the
internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status
Register, Program or Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase commands. These bits are written with the Write Status Register
(WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1 and BP0) bits are set to 1, the relevant
memory area (as defined in Table1). becomes protected against Page Program (PP), Sector Erase (SE) and Block
Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits can be written provided that
the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, only if the Block
Protect (BP2, BP1 and BP0) bits are 0 and CMP=0.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The
SRP bits control the method of write protection: software protection, hardware protection, power supply lock-
down or one time programmable protection.
SRP1 SRP0 #WP Status Register Description
The Status Register can be written to after a Write Enable
0 0 × Software Protected
command, WEL=1.(Default)
0 1 0 Hardware Protected
WP#=0, the Status Register locked and can not be written to.
WP#=1, the Status Register is unlocked and can be written to
0 1 1 Hardware Unprotected
after a Write Enable command, WEL=1.
Power Supply Status Register is protected and can not be written to again until
1 0 ×
Lock-Down(1)(2) the next Power-Down, Power-Up cycle.
1 1 × One Time Program(2) Status Register is permanently protected and can not be written to.
50 - 10 Rev.1.1
NOTE: (1). When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
(2). This feature is available on special order. (GD25Q64CxxSx)Please contact ELM for details.
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation.
When the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1,
the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI
operation if the WP# or HOLD# pins are tied directly to the power supply or ground).
LB3, LB2, LB1 bits.
The LB3, LB2, LB1 bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that
provide the write protect control and status to the Security Registers. The default state of LB3-LB1 are 0,
the security registers are unlocked. The LB3-LB1 bits can be set to 1 individually using the Write Register
instruction. The LB3-LB1 bits are One Time Programmable, once its set to 1, the Security Registers will become
read-only permanently.
CMP bit.
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-
BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection
table for details. The default setting is CMP=0.
SUS1, SUS2 bits.
The SUS1 and SUS2 bits are read only bit in the status register (S15 and S10) that are set to 1 after executing an
Program/Erase Suspend (75H) command (The Erase Suspend will set the SUS1 to 1, and the Program Suspend
will set the SUS2 to 1) . The SUS1 and SUS2 bits are cleared to 0 by Program/Erase Resume (7AH) command
as well as a power-down, power-up cycle.
HPF bit.
The High Performance Flag (HPF) bit indicates the status of High Performance Mode (HPM). When HPF bit
sets to 1, it means the device is in High Performance Mode, when HPF bit sets 0 (default), it means the device is
not in High Performance Mode.
DRV1/DRV0.
The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0 Driver Strength
00 100%
01 75% (default)
10 50%
11 25%
50 - 11 Rev.1.1
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit
on the first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in
to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last
bit of the command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or
Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-
out sequence. CS# can be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary,
otherwise the command is rejected, and is not executed. That means CS# must be driven high when the number
of clock pulses after CS# being driven low is an exact multiple of eight. For Page Program, if CS# is driven high
at any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
Table2. Commands (Standard/Dual/Quad SPI)
Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes
Write Enable 06H
Write Disable 04H
Volatile SR Write Enable 50H
Read Status Register-1 05H (S7-S0) (continuous)
Write Status Register-1 01H S7-S0
Read Data 03H A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) (continuous)
Fast Read 0BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous)
Dual Output Fast Read 3BH A23-A16 A15-A8 A7-A0 dummy D7-D0 (1) (continuous)
A7-A0 (Next
Dual I/O Fast Read BBH A23-A8 (2) (D7-D0) (1) (Next byte) (continuous)
M7-M0 (2) byte)
Quad Output Fast Read 6BH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (3) (continuous)
A23-A0 (Next
Quad I/O Fast Read EBH dummy (5) (D7-D0) (3) (Next byte) (continuous)
M7-M0 (4) byte)
Quad I/O Word Fast A23-A0 (Next
E7H dummy (6) (D7-D0) (3) (Next byte) (continuous)
Read (7) M7-M0 (4) byte)
Page Program 02H A23-A16 A15-A8 A7-A0 D7-D0 Next byte continuous
Quad Page Program 32H A23-A16 A15-A8 A7-A0 D7-D0 (3) Next byte continuous
Fast Page Program F2H A23-A16 A15-A8 A7-A0 D7-D0 Next byte continuous
Sector Erase 20H A23-A16 A15-A8 A7-A0
Block Erase (32K) 52H A23-A16 A15-A8 A7-A0
Block Erase (64K) D8H A23-A16 A15-A8 A7-A0
Chip Erase C7/60H
Enable Reset 66H
Reset 99H
50 - 12 Rev.1.1
Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes

dummy (9)
Set Burst with Wrap 77H
W7-W0
Program/Erase Suspend 75H
Program/Erase Resume 7AH
Release From Deep
(DID7-
Power-Down, ABH dummy dummy dummy (continuous)
DID0)
And Read Device ID
Release From Deep
ABH
Power-Down
Deep Power-Down B9H
Manufacturer/ (MID7- (DID7-
90H dummy dummy 00H (continuous)
Device ID MID0) DID0)
Manufacturer/ A7-A0, (MID7-MID0)
92H A23-A8 (continuous)
Device ID by Dual I/O M7-M0 (DID7-DID0)
dummy (10)
Manufacturer/ A23-A0,
94H (MID7- MID0) (continuous)
Device ID by Quad I/O M7-M0
(DID7-DID0)
(MID7- (JDID15- (JDID7-
Read Identification 9FH (continuous)
MID0) JDID8) JDID0)
High Performance Mode A3H dummy dummy dummy
Read Serial Flash
5AH A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous)
Discoverable Parameter
Erase Security
44H A23-A16 A15-A8 A7-A0
Registers (8)
Program Security
42H A23-A16 A15-A8 A7-A0 D7-D0 D7-D0 continuous
Registers (8)
Read Security
48H A23-A16 A15-A8 A7-A0 dummy (D7-D0) (continuous)
Registers (8)
NOTE:
(1) Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
(2) Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
(3) Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
50 - 13 Rev.1.1
(4) Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
(5) Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
(6) Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
(7) Fast Word Read Quad I/O Data: the lowest address bit must be 0.
(8) Security Registers Address:
Security Register1: A23-A16=00H, A15-A8=10H, A7-A0=Byte Address;
Security Register2: A23-A16=00H, A15-A8=20H, A7-A0=Byte Address;
Security Register3: A23-A16=00H, A15-A8=30H, A7-A0=Byte Address.
(9) Dummy bits and Wrap Bits
IO0 = (x, x, x, x, x, x, W4, x)
IO1 = (x, x, x, x, x, x, W5, x)
IO2 = (x, x, x, x, x, x, W6, x)
IO3 = (x, x, x, x, x, x, W7, x)
(10) Address, Continuous Read Mode bits, Dummy bits, Manufacture ID and Device ID
IO0 = (A20, A16, A12, A8, A4, A0, M4, M0, x, x, x, x, MID4, MID0, DID4, DID0, …)
Table Of ID Definitions:
GD25Q64C
Operation Code MID7-MID0 ID15-ID8 ID7-ID0
9FH C8 40 17
90H/92H/94H C8 16
ABH 16
50 - 14 Rev.1.1
7.1. Write Enable (WREN)(06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch
(WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE),
Write Status Register (WRSR) and Erase/Program Security Register command. The Write Enable (WREN)
command sequence: CS# goes low → sending the Write Enable command → CS# goes high.
Figure 2. Write Enable Sequence Diagram
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
06H
High-Z
SO
7.2. Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command
sequence: CS# goes low → Sending the Write Disable command → CS# goes high. The WEL bit is reset by
following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,
Block Erase, Chip Erase, Erase/Program Security Register and Reset commands.
Figure 3. Write Disable Sequence Diagram
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
04H
High-Z
SO
7.3. Write Enable for Volatile Status Register (50H)

The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to
change the system configuration and memory protection schemes quickly without waiting for the typical non-
volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for
Volatile Status Register command must be issued prior to a Write Status Register command. The Write Enable
for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status
Register command to change the volatile Status Register bit values.
50 - 15 Rev.1.1
Figure 4. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK 0 1 2 3 4 5 6 7
Command(50H)
SI
SO High-Z
7.4. Read Status Register (RDSR) (05H or 35H or 15H)

The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read
at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles
is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to
the device. It is also possible to read the Status Register continuously. For command code “05H”“35H”“15H”,
the SO will output Status Register bits S7~S0 / S15~S8 / S16~S23.
Figure 5. Read Status Register Sequence Diagram
7.5. Write Status Register (WRSR) (01H or 31H or 11H)

The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it
can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable
(WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S23, S20, S19, S18, S17, S16, S15, S10, S1
and S0 of the Status Register. CS# must be driven high after the eighth of the data byte has been latched in.
If not, the Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-
timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in
progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write
In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When
the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,
BP3, BP2, BP1 and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register
50 - 16 Rev.1.1
Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect
(SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is
entered.
Figure 6. Write Status Register Sequence Diagram
7.6. Read Data Bytes (READ) (03H)

The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in
during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being
shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read
Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 7. Read Data Bytes Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command 24-bit address

SI
03H 23 22 21 3 2 1 0
MSB Data Out1 Data Out2
SO High-Z
7 6 5 4 3 2 1 0
MSB
7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)

The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by
a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then
the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC,
during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out.
50 - 17 Rev.1.1
Figure 8. Read Data Bytes at Higher Speed Sequence Diagram
7.8. Dual Output Fast Read (3BH)

The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle
from SI and SO.
The command sequence is shown in followed Figure9. The first byte addressed can be at any location. The
address is automatically incremented to the next higher address after each byte of data is shifted out.
Figure 9. Dual Output Fast Read Sequence Diagram
50 - 18 Rev.1.1
7.9. Quad Output Fast Read (6BH)
The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
from IO3, IO2, IO1 and IO0. The command sequence is shown in followed Figure10. The first byte addressed
can be at any location. The address is automatically incremented to the next higher address after each byte of
data is shifted out.
Figure 10. Quad Output Fast Read Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

SI(IO0) 6BH 23 22 21 3 2 1 0
SO(IO1) High-Z
WP#(IO2) High-Z
HOLD#(IO3) High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI(IO0) 4 0 4 0 4 0 4 0 4
SO(IO1) 5 1 5 1 5 1 5 1 5
WP#(IO2) 6 2 6 2 6 2 6 2 6
HOLD#(IO3) 7 3 7 3 7 3 7 3 7
Byte1 Byte2 Byte3 Byte4
7.10. Dual I/O Fast Read (BBH)

The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability
to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit
from SI and SO. The command sequence is shown in followed Figure11. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out.
Dual I/O Fast Read with “Continuous Read Mode”
The Dual I/O Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-4) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4)
=(1, 0), then the next Dual I/O Fast Read command (after CS# is raised and then lowered) does not require the
BBH command code. The command sequence is shown in followed Figure12. If the “Continuous Read Mode”
bits (M5-4) do not equal (1, 0), the next command requires the first BBH command code, thus returning to
normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing
normal command.
50 - 19 Rev.1.1
Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0))
Figure 11. Dual I/O Fast Read Sequence Diagram (M5-4� (1, 0))
Figure 12. Dual I/O Fast Read Sequence Diagram (M5-4 = (1, 0))
Figure 12. Dual I/O Fast Read Sequence Diagram (M5-4= (1, 0))
7.11. Quad I/O Fast Read (EBH)

The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to
input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock
by IO0, IO1, IO2, IO3, each bit being latched in during the rising edge of SCLK, then the memory contents
are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed
Figure13. The first byte addressed can be at any location. The address is automatically incremented to the next
higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must
be set to enable for the Quad I/O Fast read command.
50 - 20 Rev.1.1
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous
=(1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the
EBH command code. The command sequence is shown in followed Figure14. If the “Continuous Read Mode”
bits (M5-4) do not equal to (1, 0), the next command requires the first EBH command code, thus returning
to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing
normal command.
Figure 13. Quad I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0) EBH 4 0 4 0 4 0 4 0 4 0 4 0 4
SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5
WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6
HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2
Figure 14. Quad I/O Fast Read Sequence Diagram (M5-4 = (1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4
SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5
WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6
HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Fast Read command can be used to access a specific portion within a page by issuing “Set Burst
with Wrap” (77H) commands prior to EBH. The “Set Burst with Wrap” (77H) command can either enable or
disable the “Wrap Around” feature for the following EBH commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data
starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte
section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate
the command.
50 - 21 Rev.1.1
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section
within a page.
7.12. Quad I/O Word Fast Read (E7H)

The Quad I/O Word Fast Read command is similar to the Quad I/O Fast Read command except that the lowest
address bit (A0) must equal 0 and only 2-dummy clock. The command sequence is shown in followed Figure15.
The first byte addressed can be at any location. The address is automatically incremented to the next higher
address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must be set to
enable for the Quad I/O Word Fast read command.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read command can further reduce command overhead through setting the “Continuous
=(1, 0), then the next Quad I/O Word Fast Read command (after CS# is raised and then lowered) does not
require the E7H command code. The command sequence is shown in followed Figure16. If the “Continuous
Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires the first E7H command code, thus
returning to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before
issuing normal command.
Figure 15. Quad I/O Word Fast Read Sequence Diagram (M5-4 ≠ (1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0) E7H 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4
SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5
WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6
HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3
50 - 22 Rev.1.1
Figure 16. Quad I/O Word Fast Read Sequence Diagram (M5-4 = (1, 0))
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4
SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5
WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6
HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
A23-16 A15-8 A7-0 M7-0 Dummy Byte1 Byte2 Byte3
Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Quad I/O Word Fast Read command can be used to access a specific portion within a page by issuing “Set
Burst with Wrap” (77H) commands prior to E7H. The “Set Burst with Wrap” (77H) command can either enable
or disable the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the
data being accessed can be limited to either an 8/16/32/64-byte section of a 256-byte page. The output data
starts at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte
section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate
the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” command allows three “Wrap Bits” W6-W4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section
within a page.
7.13. Set Burst with Wrap (77H)

The Set Burst with Wrap command is used in conjunction with “Quad I/O Fast Read” and “Quad I/O Word
Fast Read” command to access a fixed length of 8/16/32/64-byte section within a 256-byte page, in standard SPI
mode. The Set Burst with Wrap command sequence: CS# goes low → Send Set Burst with Wrap command →
Send 24 dummy bits → Send 8 bits “Wrap bits” → CS# goes high.
W4=0 W4=1 (default)
W6, W5
Wrap Around Wrap Length Wrap Around Wrap Length
0, 0 Yes 8-byte No N/A
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “Quad I/O Fast Read” and
“Quad I/O Word Fast Read” command will use the W6-W4 setting to access the 8/16/32/64-byte section within
any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap
command should be issued to set W4=1.
50 - 23 Rev.1.1
Figure 17. Set Burst with Wrap Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
Command
SI(IO0) 77H x x x x x x 4 x
SO(IO1) x x x x x x 5 x
WP#(IO2) x x x x x x 6 x
HOLD#(IO3) x x x x x x x x
W6-W4
7.14. Page Program (PP) (02H)

The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program
command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three
address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted data that goes beyond the end of the current page are programmed from the start address of the
same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the
entire duration of the sequence.
The Page Program command sequence: CS# goes low → sending Page Program command → 3-byte address
on SI → at least 1 byte data on SI → CS# goes high. The command sequence is shown in Figure18.
If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes
are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device,
they are correctly programmed at the requested addresses without having any effects on the other bytes of the
same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the
Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,
BP1 and BP0) is not executed.
50 - 24 Rev.1.1
Figure 18. Page Program Sequence Diagram
7.15. Quad Page Program (32H)

The Quad Page Program command is for programming the memory using four pins: IO0, IO1, IO2 and IO3.
To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1). A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the
Page Program command. The quad Page Program command is entered by driving CS# Low, followed by the
command code (32H), three address bytes and at least one data byte on IO pins.
The command sequence is shown in Figure19. If more than 256 bytes are sent to the device, previously latched
data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page.
If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without
having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last
data byte has been latched in; otherwise the Quad Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated.
While the Quad Page Program cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Quad Page Program
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset.
A Quad Page Program command applied to a page which is protected by the Block Protect (BP4, BP3, BP2,
BP1 and BP0) is not executed.
50 - 25 Rev.1.1
Figure 19. Quad Page Program Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command 24-bit address Byte1 Byte2

SI(IO0) 32H 23 22 21 3 2 1 0 4 0 4 0 4 0 4 0
MSB
SO(IO1) 5 1 5 1 5 1 5 1
WP#(IO2) 6 2 6 2 6 2 6 2
HOLD#(IO3) 7 3 7 3 7 3 7 3
CS#
537
539
540
542
536
538
541
543
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Byte11 Byte12 Byte253 Byte256

SI(IO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0
SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1
WP#(IO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
7.16. Fast Page Program (FPP) (F2H)

The Fast Page Program (FPP) command is used to program the memory. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program
command.
The Fast Page Program (FPP) command is entered by driving CS# Low, followed by the command code, three
address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted data that goes beyond the end of the current page are programmed from the start address of the
same page (from the address whose 8 least significant bits (A7-A0) are all zero). CS# must be driven low for the
entire duration of the sequence.
The Page Program command sequence: CS# goes low → sending Page Program command → 3-byte address
on SI → at least 1 byte data on SI → CS# goes high.
The command sequence is shown in Figure20. If more than 256 bytes are sent to the device, previously latched
data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page.
If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without
having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last
data byte has been latched in; otherwise the Fast Page Program (FPP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the
50 - 26 Rev.1.1
Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Fast Page Program (FPP) command is not executed when it is applied to a page protected by the Block
Protect (BP4, BP3, BP2, BP1, BP0).
Figure 20. Fast Page Program Sequence Diagram
7.17. Sector Erase (SE) (20H)

The Sector Erase (SE) command is used to erase all the data of the chosen sector. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE)
command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address
inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire
duration of the sequence.
The Sector Erase command sequence: CS# goes low → sending Sector Erase command → 3-byte address on
SI → CS# goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit
of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon
as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector
Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase
(SE) command applied to a sector which is protected by the Block Protect (BP4, BP3, BP2, BP1 and BP0) bit (see
Table1 & Table1.1.) is not executed.
Figure 21. Sector Erase Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
Command 24 Bits Address

SI
20H 23 22 2 1 0
MSB
50 - 27 Rev.1.1
7.18. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase
(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven
low for the entire duration of the sequence.
The 32KB Block Erase command sequence: CS# goes low → sending 32KB Block Erase command → 3-byte
address on SI→ CS# goes high. The command sequence is shown in Figure22. CS# must be driven high after
the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not
executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated.
While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when
it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4,
BP3, BP2, BP1 and BP0) bits (see Table1. & Table1.1.) is not executed.
Figure 22. 32KB Block Erase Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

SI
52H 23 22 2 1 0
MSB
7.19. 64KB Block Erase (BE) (D8H)

The 64KB Block Erase (BE) command used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase
(BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI.
Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven
low for the entire duration of the sequence.
The 64KB Block Erase command sequence: CS# goes low → sending 64KB Block Erase command → 3-byte
address on SI → CS# goes high. The command sequence is shown in Figure23. CS# must be driven high after
the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not
executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated.
While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when
it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP4,
BP3, BP2, BP1 and BP0) bits (see Table1. & Table1.1.) is not executed.
50 - 28 Rev.1.1
Figure 23. 64KB Block Erase Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

SI
D8H 23 22 2 1 0
MSB
7.20. Chip Erase (CE) (60/C7H)

The Chip Erase (CE) command is used to erase all the data of the chip. A Write Enable (WREN) command
must previously have been executed to set the Write Enable Latch (WEL) bit. The Chip Erase (CE) command is
entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low
for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low → sending Chip Erase command → CS# goes high. The
command sequence is shown in Figure24. CS# must be driven high after the eighth bit of the command code
has been latched in; otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-
timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status
Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed only if all
Block Protect (BP2, BP1 and BP0) bits are 0. The Chip Erase (CE) command is ignored if one or more sectors
are protected.
Figure 24. Chip Erase Sequence Diagram
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
60H or C7H
7.21. Deep Power-Down (DP) (B9H)

Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption
mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while
the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands.
Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle
currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode
can only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep
Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device
ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read
Device ID (RDI) command also allows the Device ID of the device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in the
Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the command
50 - 29 Rev.1.1
code on SI. CS# must be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low → sending Deep Power-Down command → CS#
goes high. The command sequence is shown in Figure25. CS# must be driven high after the eighth bit of the
command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon
as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-
Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 25. Deep Power-Down Sequence Diagram
CS#
0 1 2 3 4 5 6 7 tDP
SCLK
Command Stand-by mode Deep Power-down mode

SI
B9H
7.22. Release from Deep Power-Down or High Performance Mode and Read Device ID (RDI) (ABH)
The Release from Power-Down or High Performance Mode/Device ID command is a multi-purpose command.
It can be used to release the device from the Power-Down state or High Performance Mode or obtain the devices
electronic identification (ID) number.
To release the device from the Power-Down state or High Performance Mode, the command is issued by driving
the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure26. Release from
Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal
operation and other command are accepted. The CS# pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by
driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID
bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure27.
The Device ID value for the GD25Q64C is listed in Manufacturer and Device Identification table. The Device
ID can be read continuously. The command is completed by driving CS# high.
When used to release the device from the Power-Down state and obtain the Device ID, the command is the
same as previously described, and shown in Figure27, except that after CS# is driven high it must remain high
for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal
operation and other command will be accepted. If the Release from Power-Down/Device ID command is issued
while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not
have any effects on the current cycle.
Figure 26. Release Power-Down Sequence or High Performance Mode Sequence Diagram
CS#
0 1 2 3 4 5 6 7 t RES1
SCLK
Command
SI
ABH
Deep Power-down mode Stand-by mode
50 - 30 Rev.1.1
Figure 27. Release Power-Down and Read Device ID Sequence Diagram
7.23. Read Manufacture ID/Device ID (REMS) (90H)

The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down/Device ID
command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The command is initiated by driving the CS# pin low and shifting the command code “90H” followed by a
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure28. If the 24-bit address is
initially set to 000001H, the Device ID will be read first.
Figure 28. Read Manufacture ID/Device ID Sequence Diagram
50 - 31 Rev.1.1
7.24. Dual I/O Read Manufacture ID/Device ID (92H)
The Dual I/O Read Manufacturer/Device ID command is an alternative to the Release from Power-Down/
Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by
dual I/O.
24-bit address (A23-A0) of 000000H. After which, the Manufacturer ID and the Device ID are shifted out on
the falling edge of SCLK with most significant bit (MSB) first as shown in Figure29. If the 24-bit address is
initially set to 000001H, the Device ID will be read first.
Figure 29. Read Manufacture ID/Device ID Dual I/O Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0) 92H 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
A23-16 A15-8 A7-0 M7-0
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI(IO0) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
SO(IO1) 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
MFR ID Device ID MFR ID Device ID MFR ID Device ID
(Repeat) (Repeat) (Repeat) (Repeat)
7.25. Quad I/O Read Manufacture ID/Device ID (94H)

The Quad I/O Read Manufacturer/Device ID command is an alternative to the Release from Power-Down/
Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID by
quad I/O.
24-bit address (A23-A0) of 000000H. and 4 dummy clocks. After which, the Manufacturer ID and the Device
ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure30. If the
24-bit address is initially set to 000001H, the Device ID will be read first.
50 - 32 Rev.1.1
Figure 30. Read Manufacture ID/Device ID Quad I/O Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0) 94H 4 0 4 0 4 0 4 0 4 0 4 0
SO(IO1) 5 1 5 1 5 1 5 1 5 1 5 1
WP#(IO2) 6 2
6 2 6 2 6 2 6 2 6 2
HOLD#(IO3) 7 3 7 3 7 3 7 3 7 3 7 3
A23-16 A15-8 A7-0 M7-0 Dummy MFR ID DID
CS#
24 25 26 27 28 29 30 31
SCLK
SI(IO0) 4 0 4 0 4 0 4 0
SO(IO1) 5 1 5 1 5 1 5 1
WP#(IO2) 6 2 6 2 6 2 6 2
HOLD#(IO3) 7 3 7 3 7 3 7 3
MFR ID DID MFR ID DID
(Repeat)(Repeat)(Repeat)(Repeat)
7.26. Read Identification (RDID) (9FH)

The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by
two bytes of device identification. The device identification indicates the memory type in the first byte, and the
memory capacity of the device in the second byte. The Read Identification (RDID) command while an Erase
or Program cycle is in progress is not decoded, and has no effect on the cycle that is in progress. The Read
Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode.
The device is first selected by driving CS# to low. Then, the 8-bit command code for the command is shifted
in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data
Output, each bit being shifted out during the falling edge of Serial Clock. The command sequence is shown in
Figure31. The Read Identification (RDID) command is terminated by driving CS# to high at any time during
data output. When CS# is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the
device waits to be selected, so that it can receive, decode and execute commands.
50 - 33 Rev.1.1
Figure 31. Read Identification ID Sequence Diagram
7.27. High Performance Mode (HPM) (A3H)

The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when
operating at high frequencies (see fR and fC1 in AC Electrical Characteristics). This command allows pre-
charging of internal charge pumps so the voltages required for accessing the flash memory array are readily
available. The command sequence: CS# goes low → Sending A3H command → Sending 3-dummy byte →
CS# goes high. See Figure32. After the HPM command is executed, the device will maintain a slightly higher
standby current (Icc8) than standard SPI operation. The Release from Power-Down or HPM command (ABH)
can be used to return to standard SPI standby current (Icc1). In addition, Power-Down command (B9H) will
also release the device from HPM mode back to standard SPI standby state.
Figure 32. High Performance Mode Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
Command 3 Dummy Bytes t HPM
SI A3H 23 22 2 1 0
MSB
SO
High Performance Mode
7.28. Program/Erase Suspend (PES) (75H)

The Program/Erase Suspend command “75H”, allows the system to interrupt a page program or sector/
block erase operation and then read data from any other sector or block. The Write Status Register command
(01H/31H/11H) and Erase/Program Security Registers command (44H, 42H) and Erase commands (20H, 52H,
D8H, C7H, 60H) and Page Program command (02H/32H) are not allowed during Program/Erase suspend.
Program/Erase Suspend is valid only during the page program or sector/block erase operation. A maximum of
50 - 34 Rev.1.1
time of “tsus” (See AC Characteristics) is required to suspend the program/erase operation.
The Program/Erase Suspend command will be accepted by the device only if the SUS2/SUS1 bit in the Status
Register equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-
going. If the SUS2/SUS1 bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the
device. The WIP bit will be cleared from 1 to 0 within “tsus” and the SUS2/SUS1 bit will be set from 0 to 1
immediately after Program/Erase Suspend. A power-off during the suspend period will reset the device and
release the suspend state. The command sequence is show below.
Figure 33. Program/Erase Suspend Sequence Diagram
CS#
0 1 2 3 4 5 6 7 tSUS
SCLK
Command
SI
75H
High-Z
SO
Accept read command
7.29. Program/Erase Resume (PER) (7AH)

The Program/Erase Resume command must be written to resume the program or sector/block erase operation
after a Program/Erase Suspend command. The Program/Erase command will be accepted by the device only if
the SUS2/SUS1 bit equal to 1 and the WIP bit equal to 0. After issued the SUS2/SUS1 bit in the status register
will be cleared from 1 to 0 immediately, the WIP bit will be set from 0 to 1 within 200ns and the Sector or
Block will complete the erase operation or the page will complete the program operation. The Program/Erase
Resume command will be ignored unless a Program/Erase Suspend is active. The command sequence is show in
Figure34.
Figure 34. Program/Erase Resume Sequence Diagram
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
7AH
SO Resume Erase/Program
7.30. Erase Security Registers (44H)

The GD25Q64C provides three 1024-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other important
information separately from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low → sending Erase Security Registers command
50 - 35 Rev.1.1
→ CS# goes high. The command sequence is shown in Figure35. CS# must be driven high after the eighth bit
of the command code has been latched in; otherwise the Erase Security Registers command is not executed.
As soon as CS# is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated.
While the Erase Security Registers cycle is in progress, the Status Register may be read to check the value of the
Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Erase Security Registers
cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch (WEL) bit is reset. The Security Registers Lock Bit (LB3-1) in the Status Register can be used to OTP
protect the security registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the
Erase Security Registers command will be ignored.
Address A23-A16 A15-A12 A11-A10 A9-A0
Security Register #1 00H 0001 00 Byte Address
Figure 35. Erase Security Registers command Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK

SI 44H 23 22 2 1 0
MSB
7.31. Program Security Registers (42H)

The Program Security Registers command is similar to the Page Program command. It allows from 1 to 1024
bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been
executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The
Program Security Registers command is entered by driving CS# Low, followed by the command code (42H),
three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program
Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in
progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in
Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked.
Program Security Registers command will be ignored.
50 - 36 Rev.1.1
Figure 36. Program Security Registers command Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command 24-bit address Data Byte 1

SI
42H 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
CS#
2073
2075
2076
2078
2072
2074
2077
2079
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2 Data Byte 3 Data Byte 256

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB
7.32. Read Security Registers (48H)

The Read Security Registers command is similar to Fast Read command. The command is followed by a
3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then
the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC,
during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches the
last byte of the register (Byte 3FFH), it will reset to 000H, the command is completed by driving CS# high.

Figure 37. Read Security Registers command Sequence Diagram
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK

SI
48H 23 22 21 3 2 1 0
SO High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI 7 6 5 4 3 2 1 0
Data Out1 Data Out2
SO 7 6 5 4 3 2 1 0 7 6 5
MSB MSB
50 - 37 Rev.1.1
7.33. Enable Reset (66H) and Reset (99H)
If the Reset command is accepted, any on-going internal operation will be terminated and the device will
return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits,
Write Enable Latch status (WEL), Program/Erase Suspend status, Read Parameter setting (P7-P0), Continuous
Read Mode bit setting (M7-M0) and Wrap Bit Setting (W6-W4). The “Reset (99H)” command sequence as
follow: CS# goes low → Sending Enable Reset command → CS# goes high → CS# goes low → Sending
Reset command → CS# goes high. Once the Reset command is accepted by the device, the device will take
approximately tRST=60µs to reset. During this period, no command will be accepted. Data corruption may
happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence
is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before
issuing the Reset command sequence.
Figure 38.38.
Figure Enable
EnableReset
Resetand
and Reset commandSequence
Reset command Sequence Diagram
Diagram
7.34. Read Serial Flash Discoverable Parameter (5AH)

7.34. Read Serial Flash Discoverable Parameter (5AH)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC
Standard, JESD68 on CFI. SFDP is a standard of JEDEC Standard No.216.
FigureFigure
39. Read Serial Flash Discoverable Parameter command Sequence Diagram
39. Read Serial Flash Discoverable Parameter command Sequence Diagram
50 - 38 Rev.1.1
Table3. Signature and Parameter Identification Data Values
Add(H) DW Add
Description Comment Data Data
(Byte) (Bit)
00H 07:00 53H 53H
01H 15:08 46H 46H
SFDP Signature Fixed:50444653H
02H 23:16 44H 44H
03H 31:24 50H 50H
SFDF Minor Revision Number Start from 00H 04H 07:00 00H 00H
SFDF Major Revision Number Start from 01H 05H 15:08 01H 01H
Number of Parameters Headers Start from 00H 06H 23:16 01H 01H
Contains 0×FFH and
Unused 07H 31:24 FFH FFH
can never be changed
00H: It indicates a JEDEC
ID number (JEDEC) 08H 07:00 00H 00H
specified header
Parameter Table Minor Revision
Start from 0×00H 09H 15:08 00H 00H
Number
Parameter Table Major Revision
Start from 0×01H 0AH 23:16 01H 01H
Number
Parameter Table Length How many DWORDs
0BH 31:24 09H 09H
(in double word) in the Parameter Table
0CH 07:00 30H 30H
Fist address of JEDEC Flash
Parameter Table Pointer (PTP) 0DH 15:08 00H 00H
Parameter Table
0EH 23:16 00H 00H
Contains 0×FFH and
Unused 0FH 31:24 FFH FFH
ID Number It is indicates ELM
10H 07:00 C8H C8H
(ELM Manufacturer ID) manufacturer ID
Parameter Table Minor Revision
Start from 0×00H 11H 15:08 00H 00H
Number
Parameter Table Major Revision
Start from 0×01H 12H 23:16 01H 01H
Number
Parameter Table Length How many DWORDs in the
13H 31:24 03H 03H
(in double word) Parameter Table
14H 07:00 60H 60H
Fist address of ELM Flash
Parameter Table Pointer (PTP) 15H 15:08 00H 00H
Parameter Table
16H 23:16 00H 00H
Contains 0×FFH and
50 - 39 Rev.1.1
Table4. Parameter Table (0): JEDEC Flash Parameter Tables
Add(H) DW Add
(Byte) (Bit)
00: Reserved;
01: 4KB erase;
Block/Sector Erase Size 01:00 01b
10: Reserved;
11: not support 4KB erase
Write Granularity 0: 1Byte, 1: 64Byte or larger 02 1b
Write Enable Instruction 0: Nonvolatile status bit
Requested for Writing to Volatile 1: Volatile status bit 03 0b
Status Registers (BP status register bit) 30H E5H
0: Use 50H Opcode,
Write Enable Opcode Select for 1: Use 06H Opcode,
Writing to Volatile Status Note: If target flash status 04 0b
Registers register is Nonvolatile, then bits
3 and 4 must be set to 00b.
Contains 111b and can never be
Unused 07:05 111b
changed
4KB Erase Opcode 31H 15:08 20H 20H
(1-1-2) Fast Read 0=Not support, 1=Support 16 1b
Address Bytes Number used in 00: 3Byte only, 01: 3 or 4Byte,
18:17 00b
addressing flash array 10: 4Byte only, 11: Reserved
Double Transfer Rate (DTR)
0=Not support, 1=Support 19 0b
clocking 32H F1H
Unused 23 1b
Flash Memory Density 37H:34H 31:00 03FFFFFFH
(1-4-4) Fast Read Number of 00000b: Wait states (Dummy
04:00 00100b
Wait states Clocks) not support
38H 44H
(1-4-4) Fast Read Number of
000b: Mode Bits not support 07:05 010b
Mode Bits
(1-4-4) Fast Read Opcode 39H 15:08 EBH EBH
20:16 01000b
3AH 08H
Mode Bits
(1-1-4) Fast Read Opcode 3BH 31:24 6BH 6BH
04:00 01000b
3CH 08H
Mode Bits
(1-1-2) Fast Read Opcode 3DH 15:08 3BH 3BH
50 - 40 Rev.1.1
Add(H) DW Add
(Byte) (Bit)
20:16 00010b
3EH 42H
(1-2-2) Fast Read Number
of Mode Bits
(1-2-2) Fast Read Opcode 3FH 31:24 BBH BBH
(2-2-2) Fast Read 0=not support; 1=support 00 0b
Unused 03:01 111b
40H EEH
(4-4-4) Fast Read 0=not support; 1=support 04 0b
Unused 07:05 111b
Unused 43H:41H 31:08 0×FFH 0×FFH
20:16 00000b
46H 00H
Mode Bits
(2-2-2) Fast Read Opcode 47H 31:24 FFH FFH
20:16 00000b
4AH 00H
Mode Bits
(4-4-4) Fast Read Opcode 4BH 31:24 FFH FFH
Sector/block size=2^N bytes
Sector Type 1 Size 4CH 07:00 0CH 0CH
0×00b: this sector type don’t exist
Sector Type 1 erase Opcode 4DH 15:08 20H 20H
Sector Type 2 Size 4EH 23:16 0FH 0FH
Sector Type 2 erase Opcode 4FH 31:24 52H 52H
Sector Type 3 Size 50H 07:00 10H 10H
Sector Type 3 erase Opcode 51H 15:08 D8H D8H
Sector Type 4 Size 52H 23:16 00H 00H
Sector Type 4 erase Opcode 53H 31:24 FFH FFH
50 - 41 Rev.1.1
Table5. Parameter Table (1): ELM Flash Parameter Tables
Add(H) DW Add
(Byte) (Bit)
2000H=2.000V
Vcc Supply Maximum Voltage 2700H=2.700V 61H:60H 15:00 3600H 3600H
3600H=3.600V
1650H=1.650V
2250H=2.250V
Vcc Supply Minimum Voltage 63H:62H 31:16 2700H 2700H
2350H=2.350V
2700H=2.700V
HW Reset# pin 0=not support; 1=support 00 0b
HW Hold# pin 0=not support; 1=support 01 1b
Deep Power Down Mode 0=not support; 1=support 02 1b
SW Reset 0=not support; 1=support 03 1b
Should be issue Reset 1001 1001b
SW Reset Opcode 65H:64H 11:04 F99EH
Enable(66H) before Reset cmd. (99H)
Program Suspend/Resume 0=not support; 1=support 12 1b
Erase Suspend/Resume 0=not support; 1=support 13 1b
Unused 14 1b
Wrap-Around Read mode 0=not support; 1=support 15 1b
Wrap-Around Read mode
66H 23:16 77H 77H
Opcode
08H: support 8B wrap-around
read
Wrap-Around Read data length 16H: 8B & 16B 67H 31:24 64H 64H
32H: 8B & 16B & 32B
64H: 8B & 16B & 32B & 64B
Individual block lock 0=not support; 1=support 00 0b
Individual block lock bit
0=Volatile; 1=Nonvolatile 01 0b
(Volatile/Nonvolatile)
Individual block lock Opcode 09:02 FFH
Individual block lock Volatile
0=protect; 1=unprotect 10 0b EBFCH
protect bit default protect status 6BH:68H
Secured OTP 0=not support; 1=support 11 1b
Read Lock 0=not support; 1=support 12 0b
Permanent Lock 0=not support; 1=support 13 1b
Unused 15:14 11b
Unused 31:16 FFH FFH
50 - 42 Rev.1.1
8. ELECTRICAL CHARACTERISTICS
8.1. Power-On Timing
Figure 40. Power-on Timing Sequence Diagram
Table6. Power-Up Timing and Write Inhibit Threshold

Symbol Parameter Min Max Unit
tVSL VCC(min) To CS# Low 10 us
tPUW Time Delay From VCC(min) To Write Instruction 1 10 ms
VWI Write Inhibit Voltage VCC(min) 1 2.5 V
8.2. Initial Delivery State

The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status
Register bits are set to 0, except DRV0 bit (S21) is set to 1.
8.3. Data Retention And Endurance

Parameter Test Condition Min Unit
150°C 10 Years
Minimum Pattern Data Retention Time
125°C 20 Years
Erase/Program Endurance -40 to 85°C 100K Cycles
50 - 43 Rev.1.1
8.4. Absolute Maximum Ratings
Parameter Value Unit

Ambient Operating Temperature -40 to 85 °C
Storage Temperature -65 to 150 °C
Output Short Circuit Current 200 mA
Applied Input/Output Voltage -0.6 to VCC+4.0 V
Transient Input/Output Voltage(note: overshoot) -2.0 to VCC+2.0 V
VCC -0.6 to VCC+4.0 V
Figure 41. Maximum Negative/positive Overshoot Diagram

Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform
20ns 20ns 20ns

Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns 20ns
8.5. Capacitance Measurement Conditions
Symbol Parameter Min Typ Max Unit Conditions

CIN Input Capacitance 6 pF VIN=0V
COUT Output Capacitance 8 pF VOUT=0V
Load Capacitance 30 pF
Input Rise And Fall time 5 ns
CL Input Pulse Voltage 0.1VCC to 0.8VCC V
Input Timing Reference Voltage 0.2VCC to 0.7VCC V
Output Timing Reference Voltage 0.5VCC V
Figure 42. Input Test Waveform and Measurement Level Diagram
Input timing reference level Output timing reference level

0.8VCC 0.7VCC
AC Measurement Level 0.5VCC
0.1VCC 0.2VCC
Note: Input pulse rise and fall time are <5ns
50 - 44 Rev.1.1
8.6. DC Characteristics
(T= -40°C~85°C, VCC=2.7~3.6V)
Symbol Parameter Test Condition Min. Typ. Max. Unit.
ILI Input Leakage Current ±2 μA
ILO Output Leakage Current ±2 μA
ICC1 Standby Current CS#=VCC, VIN=VCC or VSS 1 5 μA
ICC2 Deep Power-Down Current CS#=VCC, VIN=VCC or VSS 1 5 μA
CLK=0.1VCC/0.9VCC at 120MHz,
15 20 mA
Q=Open(*1,*2,*4 I/O)
ICC3 Operating Current (Read)
CLK=0.1VCC/0.9VCC at 80MHz,
13 18 mA
Q=Open(*1,*2,*4 I/O)
ICC4 Operating Current (PP) CS#=VCC 15 mA
ICC5 Operating Current (WRSR) CS#=VCC 15 mA
ICC6 Operating Current (SE) CS#=VCC 15 mA
ICC7 Operating Current (BE) CS#=VCC 15 mA
ICC8 Operating Current (CE) CS#=VCC 15 mA
ICC9 High Performance Current 400 800 μA
VIL Input Low Voltage 0.2VCC V
VIH Input High Voltage 0.7VCC V
VOL Output Low Voltage IOL=100μA 0.2 V
VOH Output High Voltage IOH=-100μA VCC-0.2 V
8.7. AC Characteristics
(T= -40°C~85°C, VCC=2.7~3.6V, CL=30pf)
Symbol Parameter Min. Typ. Max. Unit.
Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH),
fC Quad Output(6BH) (Dual I/O & Quad I/O Without High DC. 104 MHz
Performance Mode), on 3.0V-3.6V power supply
fC1 Quad Output(6BH) (Dual I/O & Quad I/O Without High DC. 80 MHz
fC2 Quad Output(6BH) (Dual I/O & Quad I/O With High DC. 120 MHz
fR Serial Clock Frequency For: Read (03H) DC. 80 MHz
tCLH Serial Clock High Time 3.5 ns
tCLL Serial Clock Low Time 3.5 ns
tCLCH Serial Clock Rise Time (Slew Rate) 0.2 V/ns
tCHCL Serial Clock Fall Time (Slew Rate) 0.2 V/ns
tSLCH CS# Active Setup Time 5 ns
tCHSH CS# Active Hold Time 5 ns
50 - 45 Rev.1.1
Symbol Parameter Min. Typ. Max. Unit.

tSHCH CS# Not Active Setup Time 5 ns
tCHSL CS# Not Active Hold Time 5 ns
tSHSL CS# High Time (Read/Write) 20 ns
tSHQZ Output Disable Time 6 ns
tCLQX Output Hold Time 1.2 ns
tDVCH Data In Setup Time 2 ns
tCHDX Data In Hold Time 2 ns
tHLCH Hold# Low Setup Time (Relative to Clock) 5 ns
tHHCH Hold# High Setup Time (Relative to Clock) 5 ns
tCHHL Hold# High Hold Time (Relative to Clock) 5 ns
tCHHH Hold# Low Hold Time (Relative to Clock) 5 ns
tHLQZ Hold# Low To High-Z Output 6 ns
tHHQX Hold# High To Low-Z Output 6 ns
tCLQV Clock Low To Output Valid 7 ns
tWHSL Write Protect Setup Time Before CS# Low 20 ns
tSHWL Write Protect Hold Time After CS# High 100 ns
tDP CS# High To Deep Power-Down Mode 20 μs
tRES1 CS# High To Standby Mode Without Electronic Signature Read 20 μs
tRES2 CS# High To Standby Mode With Electronic Signature Read 20 μs
tSUS CS# High To Next Command After Suspend 20 μs
tRST CS# High To Next Command After Reset 20 μs
tW Write Status Register Cycle Time 5 30 ms
tBP1 Byte Program Time (First Byte) 30 50 μs
tBP2 Additional Byte Program Time (After First Byte) 2.5 12 μs
tPP Page Programming Time 0.6 2.4 ms
tSE Sector Erase Time (4K Bytes) 50 200/300(1) ms
tBE1 Block Erase Time (32K Bytes) 0.15 0.8/1.6(2) s
tBE2 Block Erase Time (64K Bytes) 0.20 1.2/2.0(3) s
tCE Chip Erase Time (GD25Q64C) 25 60 s
Note:
(1). Max Value 4KB tSE with≤50K cycles is 200ms and >50K & ≤100k cycles is 300ms.
(2). Max Value 32KB tBE with≤50K cycles is 0.8s and >50K & ≤100k cycles is 1.6s.
(3). Max Value 64KB tBE with≤50K cycles is 1.2s and >50K & ≤100k cycles is 2.0s.
50 - 46 Rev.1.1
Figure43. Serial Input Timing Diagram
tSHSL
CS#
tCHSL tSLCH tCHSH tSHCH

SCLK
tDVCH tCHCL
tCHDX tCLCH
SI MSB LSB
SO High-Z
Figure44. Output Timing Diagram
CS#
tCLH tSHQZ
SCLK
tCLQV tCLQV tCLL
tCLQX tCLQX
SO LSB
SI
Least significant address bit (LIB) in
Figure45. Hold Timing Diagram
CS#
tCHHL tHLCH tHHCH

SCLK
tCHHH
tHLQZ tHHQX
SO
HOLD#
SI do not care during HOLD operation.
50 - 47 Rev.1.1
9. ORDERING INFORMATION
GD 25 Q 64 C x I G x
Packing Type
Y: Tray
R: Tape & Reel
Green Code
G: Pb Free & Halogen Free Green Package
S: Pb Free & Halogen Free Green Package SRP1 available
Temperature Range
I: Industrial(-40°C to +85°C)
Package Type
S: SOP8 208mil
W: WSON8 (6×5mm)
Generation
C: Version
Density
64: 64Mb
Series
Q: 3V, 4KB Uniform Sector
Product Family
25: SPI Interface Flash
Rev.1.1
50 - 48
10. PACKAGE INFORMATION
10.1 Package SOP8 208MIL
8 5 �
E1 E
L1
L
1 4
C
D
A2 A
b A1
e
Dimensions
Symbol
A A1 A2 b c D E E1 e L L1 θ
Unit
Min - 0.05 1.70 0.31 0.18 5.13 7.70 5.18 - 0.50 1.21 0°
mm Nom - 0.15 1.80 0.41 0.21 5.23 7.90 5.28 1.27BSC 0.67 1.31 5°
Max 2.16 0.25 1.91 0.51 0.25 5.33 8.10 5.38 - 0.85 1.41 8°
Min - 0.002 0.067 0.012 0.007 0.202 0.303 0.204 - 0.020 0.048 0°
Inch Nom - 0.006 0.071 0.016 0.008 0.206 0.311 0.208 0.050BSC 0.026 0.052 5°
Max 0.085 0.010 0.075 0.020 0.010 0.210 0.319 0.212 - 0.033 0.056 8°
Note: Both package length and width do not include mold flash.
50 - 49 Rev.1.1
10.2 Package WSON8 (6×5mm)
D
A2
A1
A
Top View Side View
L D1
b 1
e E1
Bottom View
Dimensions
Symbol
A A1 A2 b D D1 E E1 e y L
Unit
Min 0.70 - 0.19 0.35 5.90 3.25 4.90 3.85 - 0.00 0.50
mm Nom 0.75 - 0.22 0.42 6.00 3.37 5.00 3.97 1.27 BSC 0.04 0.60
Max 0.80 0.05 0.25 0.48 6.10 3.50 5.10 4.10 - 0.08 0.75
Min 0.028 - 0.007 0.014 0.232 0.128 0.193 0.151 - 0.000 0.020
Inch Nom 0.030 - 0.009 0.016 0.236 0.133 0.197 0.156 0.05 BSC 0.001 0.024
Max 0.032 0.002 0.010 0.019 0.240 0.138 0.201 0.161 - 0.003 0.030
Note:
1. Both package length and width do not include mold flash.
2. The exposed metal pad area on the bottom of the package is connected to device ground (GND pin), so both
Floating and connecting GND of exposed pad are also available.
50 - 50 Rev.1.1

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7.27. High Performance Mode (HPM) (A3H) ----------------------------------------------------------- 34

Note: (1) Please contact ELM for details.

8-LEAD SOP 8-LEAD WSON

CS# I Chip Select Input

WP#(IO2) Write Control

SI(IO0) Column Decode And

8M 64/32K 4K 256 bytes

Uniform Block Sector Architecture

2047 7FF000H 7FFFFFH

Status Register Content Memory Content

BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion

Status Register Content Memory Content

BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion

S15 S14 S13 S12 S11 S10 S9 S8

Command Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes

7.2. Write Disable (WRDI) (04H)

7.3. Write Enable for Volatile Status Register (50H)

7.4. Read Status Register (RDSR) (05H or 35H or 15H)

7.5. Write Status Register (WRSR) (01H or 31H or 11H)

7.6. Read Data Bytes (READ) (03H)

Command 24-bit address

7.7. Read Data Bytes at Higher Speed (Fast Read) (0BH)

7.8. Dual Output Fast Read (3BH)

Command 24-bit address

7.10. Dual I/O Fast Read (BBH)

7.11. Quad I/O Fast Read (EBH)

7.12. Quad I/O Word Fast Read (E7H)

7.13. Set Burst with Wrap (77H)

7.14. Page Program (PP) (02H)

7.15. Quad Page Program (32H)

Command 24-bit address Byte1 Byte2

Byte11 Byte12 Byte253 Byte256

7.16. Fast Page Program (FPP) (F2H)

7.17. Sector Erase (SE) (20H)

Command 24 Bits Address

Command 24 Bits Address

7.19. 64KB Block Erase (BE) (D8H)

Command 24 Bits Address

7.20. Chip Erase (CE) (60/C7H)

7.21. Deep Power-Down (DP) (B9H)

Command Stand-by mode Deep Power-down mode

Deep Power-down mode Stand-by mode

7.23. Read Manufacture ID/Device ID (REMS) (90H)

7.25. Quad I/O Read Manufacture ID/Device ID (94H)

A23-16 A15-8 A7-0 M7-0 Dummy MFR ID DID

7.26. Read Identification (RDID) (9FH)

7.27. High Performance Mode (HPM) (A3H)

7.28. Program/Erase Suspend (PES) (75H)

7.29. Program/Erase Resume (PER) (7AH)

7.30. Erase Security Registers (44H)

Figure 35. Erase Security Registers command Sequence Diagram

Command 24 Bits Address

7.31. Program Security Registers (42H)

Command 24-bit address Data Byte 1

Data Byte 2 Data Byte 3 Data Byte 256

7.32. Read Security Registers (48H)

Address A23-A16 A15-A12 A11-A10 A9-A0

Figure 37. Read Security Registers command Sequence Diagram