MX25L1673E: High Performance Serial Flash Specification

MX25L1673E
MX25L1673E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
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MX25L1673E
Contents
1. FEATURES......................................................................................................................................................... 4
2. GENERAL DESCRIPTION................................................................................................................................ 6
Table 1. Additional Feature......................................................................................................................6
3. PIN CONFIGURATION....................................................................................................................................... 7
4. PIN DESCRIPTION............................................................................................................................................. 7
5. BLOCK DIAGRAM.............................................................................................................................................. 8
6. DATA PROTECTION........................................................................................................................................... 9
Table 2. Protected Area Sizes...............................................................................................................10
Table 3. 512-bit Secured OTP Definition...............................................................................................10
7. MEMORY ORGANIZATION...............................................................................................................................11
Table 4. Memory Organization.............................................................................................................. 11
8. DEVICE OPERATION....................................................................................................................................... 12
9. COMMAND DESCRIPTION.............................................................................................................................. 13
Table 5. Command Sets........................................................................................................................13
9-1. Write Enable (WREN)...........................................................................................................................15
9-2. Write Disable (WRDI)............................................................................................................................16
9-3. Read Identification (RDID)....................................................................................................................17
9-4. Read Status Register (RDSR)..............................................................................................................18
9-5. Write Status Register (WRSR)..............................................................................................................20
Table 6. Protection Modes.....................................................................................................................21
9-6. Read Data Bytes (READ).....................................................................................................................23
9-7. Read Data Bytes at Higher Speed (FAST_READ)...............................................................................24
9-8. Dual Read Mode (DREAD)...................................................................................................................25
9-9. 2 x I/O Read Mode (2READ)................................................................................................................26
9-10. Quad Read Mode (QREAD).................................................................................................................27
9-11. 4 x I/O Read Mode (4READ)................................................................................................................28
9-12. Performance Enhance Mode................................................................................................................29
9-13. Performance Enhance Mode Reset (FFh)............................................................................................29
9-14. Sector Erase (SE).................................................................................................................................32
9-15. Block Erase (BE)..................................................................................................................................33
9-16. Chip Erase (CE)....................................................................................................................................34
9-17. Page Program (PP)..............................................................................................................................35
9-18. 4 x I/O Page Program (4PP).................................................................................................................36
9-19. Deep Power-down (DP)........................................................................................................................37
9-20. Release from Deep Power-down (RDP), Read Electronic Signature (RES)........................................38
9-21. Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)......................................40
9-22. ID Read.................................................................................................................................................41
Table 7. ID Definitions ..........................................................................................................................41
9-23. Enter Secured OTP (ENSO).................................................................................................................41
9-24. Exit Secured OTP (EXSO)....................................................................................................................41
9-25. Read Security Register (RDSCUR)......................................................................................................42
Table 8. Security Register Definition.....................................................................................................42
9-26. Write Security Register (WRSCUR)......................................................................................................43
9-27. Read SFDP Mode (RDSFDP)...............................................................................................................44
Table 9. Signature and Parameter Identification Data Values ..............................................................45
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MX25L1673E
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables..........................................................46

Table 11. Parameter Table (1): Macronix Flash Parameter Tables........................................................48
10. POWER-ON STATE........................................................................................................................................ 50
11. ELECTRICAL SPECIFICATIONS................................................................................................................... 51
11-1. Absolute Maximum Ratings..................................................................................................................51
11-2. Capacitance..........................................................................................................................................51
Table 12. DC Characteristics.................................................................................................................53
Table 13. AC Characteristics.................................................................................................................54
12. TIMING ANALYSIS......................................................................................................................................... 55
Table 14. Power-Up Timing ..................................................................................................................56
12-1. Initial Delivery State..............................................................................................................................56
13. OPERATING CONDITIONS............................................................................................................................ 57
14. ERASE AND PROGRAMMING PERFORMANCE......................................................................................... 59
15. DATA RETENTION......................................................................................................................................... 59
16. LATCH-UP CHARACTERISTICS................................................................................................................... 59
17. ORDERING INFORMATION........................................................................................................................... 60
18. PART NAME DESCRIPTION.......................................................................................................................... 61
19. REVISION HISTORY ...................................................................................................................................... 64
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MX25L1673E
16M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY
1. FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure or 4,194,304 x 4 bits (four I/O
read mode) structure
• 512 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 32 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Permanent fixed QE bit, QE =1 and 4 I/O mode is enabled
PERFORMANCE
• High Performance
- Fast read
- 1 I/O: 104MHz with 8 dummy cycles
- Fast access time: 104MHz serial clock
- Serial clock of four I/O read mode : 85MHz, which is equivalent to 340MHz
- Fast program time: 0.6ms(typ.) and 3ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Fast erase time: 40ms (typ.)/sector (4K-byte per sector) ; 0.4s(typ.) /block (64K-byte per block); 5s(typ.) /chip
• Low Power Consumption
- Low active read current: 25mA(max.) at 104MHz and 10mA(max.) at 33MHz
- Low active programming current: 15mA (typ.)
- Low active sector erase current: 9mA (typ.)
- Low standby current: 15uA (typ.)
• Typical 100,000 erase/program cycles
• 20 years data retention
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MX25L1673E
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase
instructions
- Additional 512-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- Both REMS,REMS2 and REMS4 commands for 1-byte manufacturer ID and 1-byte device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SIO2
- Serial data Input/Output for 4 x I/O read mode
• SIO3
- Serial data Input/Output for 4 x I/O read mode
• PACKAGE
- 8-pin SOP (200mil)
- 8-WSON (6x5mm)
- All devices are RoHS Compliant & Halogen-free.
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MX25L1673E
2. GENERAL DESCRIPTION
The MX25L1673E are 16,777,216 bit serial Flash memory, which is configured as 2,097,152 x 8 internally. When it
is in two or four I/O read mode, the structure becomes 8,388,608 bits x 2 or 4,194,304 bits x 4. The MX25L1673E
feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input
and data output. When it is in four I/O read mode, the SI pin, SO pin become SIO0 pin and SIO1 pin, SIO2 pin and
SIO3 pin for address/dummy bits input and data Input/Output.
The MX25L1673E provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, and erase command is executes on sector (4K-byte), or block (64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L1673E utilizes Macronix proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Feature

Protection and Read
Identifier
Additional Security Performance
Features Flexible
Block 512-bit RES REMS REMS2 REMS4 RDID
Part 2 I/O 4 I/O
Protection secured (command: (command: (command: (command: (command:
Name Read Read
(BP0- OTP AB hex) 90 hex) EF hex) DF hex) 9F hex)
BP3)
C2 24 (hex) C2 24 (hex) C2 24 (hex) C2 24 15
MX25L1673E V V V V 24 (hex)
(if ADD=0) (if ADD=0) (if ADD=0) (hex)
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3. PIN CONFIGURATION 4. PIN DESCRIPTION

8-PIN SOP (200mil) SYMBOL DESCRIPTION
CS# Chip Select
CS# 1 8 VCC Serial Data Input (for 1 x I/O)/ Serial
SO/SIO1 2 7 SIO3 SI/SIO0 Data Input & Output (for 2xI/O or 4xI/
SIO2 3 SCLK
6
O read mode)
GND 4 5 SI/SIO0
Serial Data Output (for 1 x I/O)/
SO/SIO1 Serial Data Input & Output (for 2xI/O
or 4xI/O read mode)
8-WSON (6x5mm) SCLK Clock Input
Serial Data Input & Output (for 4xI/O
SIO2
CS# 1 8 VCC read mode)
SO/SIO1 2 7 SIO3 Serial Data Input & Output (for 4xI/O
SIO3
SIO2 3 6 SCLK read mode)
GND 4 5 SI/SIO0 VCC + 3.3V Power Supply
GND Ground
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MX25L1673E
5. BLOCK DIAGRAM
Address
X-Decoder
Generator
Memory Array
Page Buffer
Data
SI/SIO0 Register Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
SIO2 Mode State HV
SIO3 Logic Machine Generator
SCLK Clock Generator
Output
SO/SIO1
Buffer
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MX25L1673E
6. DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or pro-
gramming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register ar-
chitecture of the device constrains that the memory contents can only be changed after specific command sequenc-
es have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP, 4PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-
nature command (RES).
• Advanced Security Features: there are some protection and securuity features which protect content from inad-
vertent write and hostile access.
I. Block lock protection

- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits.
Please refer to table of "protected area sizes".
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MX25L1673E
Table 2. Protected Area Sizes

Status bit Protect Level
BP3 BP2 BP1 BP0 16Mb
0 0 0 0 0 (none)
0 0 0 1 1 (1block, protected block 31th)
0 0 1 0 2 (2blocks, protected block 30th-31th)
0 1 1 0 6 (32blocks, protected all)
II. Additional 512-bit secured OTP for unique identifier: to provide 512-bit one-time program area for setting de-
vice unique serial number - Which may be set by factory or system customer. Please refer to "Table 3. 512-bit
Secured OTP Definition"
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 512-bit secured OTP by entering 512-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) com-
mand to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security reg-
ister bit definition and table of "512-bit secured OTP definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512-bit secured
OTP mode, array access is not allowed.
Table 3. 512-bit Secured OTP Definition

Address range Size Standard Factory Lock Customer Lock
xxxx00~xxxx0F 128-bit ESN (electrical serial number)
Determined by customer
xxxx10~xxxx3F 384-bit N/A
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MX25L1673E
7. MEMORY ORGANIZATION
Table 4. Memory Organization

Block Sector Address Range Block Sector Address Range
511 1FF000h 1FFFFFh 255 0FF000h 0FFFFFh
31 : : : 15 : : :
496 1F0000h 1F0FFFh 240 0F0000h 0F0FFFh
495 1EF000h 1EFFFFh 239 0EF000h 0EFFFFh
30 : : : 14 : : :
480 1E0000h 1E0FFFh 224 0E0000h 0E0FFFh
479 1DF000h 1DFFFFh 223 0DF000h 0DFFFFh
29 : : : 13 : : :
464 1D0000h 1D0FFFh 208 0D0000h 0D0FFFh
463 1CF000h 1CFFFFh 207 0CF000h 0CFFFFh
28 : : : 12 : : :
448 1C0000h 1C0FFFh 192 0C0000h 0C0FFFh
447 1BF000h 1BFFFFh 191 0BF000h 0BFFFFh
27 : : : 11 : : :
432 1B0000h 1B0FFFh 176 0B0000h 0B0FFFh
431 1AF000h 1AFFFFh 175 0AF000h 0AFFFFh
26 : : : 10 : : :
416 1A0000h 1A0FFFh 160 0A0000h 0A0FFFh
415 19F000h 19FFFFh 159 09F000h 09FFFFh
25 : : : 9 : : :
400 190000h 190FFFh 144 090000h 090FFFh
399 18F000h 18FFFFh 143 08F000h 08FFFFh
24 : : : 8 : : :
384 180000h 180FFFh 128 080000h 080FFFh
383 17F000h 17FFFFh 127 07F000h 07FFFFh
23 : : : 7 : : :
368 170000h 170FFFh 112 070000h 070FFFh
367 16F000h 16FFFFh 111 06F000h 06FFFFh
22 : : : 6 : : :
352 160000h 160FFFh 96 060000h 060FFFh
351 15F000h 15FFFFh 95 05F000h 05FFFFh
21 : : : 5 : : :
336 150000h 150FFFh 80 050000h 050FFFh
335 14F000h 14FFFFh 79 04F000h 04FFFFh
20 : : : 4 : : :
320 140000h 140FFFh 64 040000h 040FFFh
319 13F000h 13FFFFh 63 03F000h 03FFFFh
19 : : : 3 : : :
304 130000h 130FFFh 48 030000h 030FFFh
303 12F000h 12FFFFh 47 02F000h 02FFFFh
18 : : : 2 : : :
288 120000h 120FFFh 32 020000h 020FFFh
287 11F000h 11FFFFh 31 01F000h 01FFFFh
17 : : : 1 : : :
272 110000h 110FFFh 16 010000h 010FFFh
271 10F000h 10FFFFh 15 00F000h 00FFFFh
16 : : : : : :
256 100000h 100FFFh 0 2 002000h 002FFFh
1 001000h 001FFFh
0 000000h 000FFFh
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MX25L1673E
8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended opera-
tion.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. For standard single data rate serial mode, input data is latched on the rising edge of Serial Clock(SCLK) and
data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as "Figure 1.
Serial Modes Supported (for Normal Serial mode)" .
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, 2READ, DREAD,
4READ, QREAD, RES, REMS, REMS2, and REMS4 the shifted-in instruction sequence is followed by a data-
out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN,
WRDI, WRSR, SE, BE, CE, PP, 4PP, RDP, DP, ENSO, EXSO,and WRSCUR, the CS# must go high exactly at
the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported (for Normal Serial mode)
CPOL CPHA shift in shift out
(Serial mode 0) 0 0 SCLK
(Serial mode 3) 1 1 SCLK
SI MSB
SO MSB
Note:
CPOL indicates clock polarity of Serial master,
-CPOL=1 for SCLK high while idle,
-CPOL=0 for SCLK low while not transmitting.
CPHA indicates clock phase.
The combination of CPOL bit and CPHA bit decides which Serial mode is supported.
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MX25L1673E
9. COMMAND DESCRIPTION
Table 5. Command Sets
Read Commands
DREAD QREAD
Command READ (read FAST READ RDSFDP 2READ (2 x I/O 4READ (4 x I/O
(1I / 2O read (1I / 4O read
(byte) data) (fast read data) (Read SFDP) read command) read command)
command) command)
1st byte 03 (hex) 0B (hex) 5A (hex) BB (hex) 3B (hex) EB (hex) 6B (hex)
AD1
2nd byte AD1 AD1 ADD AD1 ADD & Dummy AD1
(A23-A16)
AD2
3rd byte AD2 AD2 ADD & Dummy AD2 Dummy AD2
(A15-A8)
AD3
4th byte AD3 AD3 AD3 AD3
(A7-A0)
5th byte Dummy Dummy Dummy Dummy
n bytes read n bytes read Read SFDP n bytes n bytes read
out until CS# out until CS# mode read out out by 4 x I/O
Action
goes high goes high by 2 x I/O until until CS# goes
CS# goes high high
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MX25L1673E
Other Commands
RDID
Command WREN (write WRDI RDSR (read WRSR (write 4PP (quad SE (sector
(read identific-
(byte) enable) (write disable) status register) status register) page program) erase)
ation)
1st byte 06 (hex) 04 (hex) 9F (hex) 05 (hex) 01 (hex) 38 (hex) 20 (hex)

2nd byte Values AD1 AD1
3rd byte AD2
4th byte AD3
sets the (WEL) resets the outputs JEDEC to read out the to write new quad input to to erase the
write enable (WEL) write ID: 1-byte values of the values of the program the selected sector
Action latch bit enable latch bit Manufact-urer status register status register selected page
ID & 2-byte
Device ID
RDP (Release Release Read

Command BE (block PP (page DP (Deep RES (read
CE (chip erase) from deep Enhanced
(byte) erase) program) power down) electronic ID)
power down)
1st byte D8 (hex) 60 or C7 (hex) 02 (hex) B9 (hex) AB (hex) AB (hex) FFh (hex)
2nd byte AD1 AD1 x x
3rd byte AD2 AD2 x x
4th byte AD3 AD3 x x
to erase the to erase whole to program the enters deep release from to read out All these
selected block chip selected page power down deep power 1-byte Device commands
mode down mode ID FFh, 00h, AAh
Action or 55h will
escape the
performance
enhance mode
REMS (read
REMS2 (read REMS4 (read RDSCUR WRSCUR
Command electronic ENSO (enter EXSO (exit
ID for 2x I/O ID for 4x I/O (read security (write security
(byte) manufacturer & secured OTP) secured OTP)
mode) mode) register) register)
device ID)
1st byte 90 (hex) EF (hex) DF (hex) B1 (hex) C1 (hex) 2B (hex) 2F (hex)
2nd byte x X x
3rd byte x X x
4th byte ADD (Note3) ADD (Note3) ADD (Note3)
output the output the output the to enter the to exit the 512- to read value of to set the lock-
Manufacturer Manufacturer Manufacturer 512-bit secured bit secured security register down bit as
ID & Device ID ID & Device ID ID & Device ID OTP mode OTP mode "1" (once lock-
down, cannot
Action be update)
Note 3: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 4: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hid-
den mode.
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MX25L1673E
9-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP,
4PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the
WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high.
The SIO[3:1] are don't care in this mode.
Figure 2. Write Enable (WREN) Sequence (Command 06)
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI 06h
High-Z
SO
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MX25L1673E
9-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high.
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP, 4PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
Figure 3. Write Disable (WRDI) Sequence (Command 04)
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI 04h
High-Z
SO
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MX25L1673E
9-3. Read Identification (RDID)
The RDID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macro-
nix Manufacturer ID is C2(hex), the memory type ID is as the first-byte Device ID, and the individual Device ID of
second-byte ID are listed as table of "Table 7. ID Definitions".
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
Figure 4. Read Identification (RDID) Sequence (Command 9F)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31
SCLK
Command
SI 9Fh
Manufacturer Identification Device Identification

High-Z
SO 7 6 5 3 2 1 0 15 14 13 3 2 1 0
MSB MSB
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9-4. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO.
The SIO[3:1] are don't care when during this mode.
Figure 5. Read Status Register (RDSR) Sequence (Command 05)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
command
SI 05h
Status Register Out Status Register Out

High-Z
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB
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The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to "1", which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and
will reset WEL bit if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and
available for next program/erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit
confirmed, WEL bit needs to be confirm to be 0.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in "Table 2. Protected Area Sizes") of the device to against the program/erase instruction without hardware
protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register
(WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP),
Sector Erase (SE), Block Erase (BE) and Chip Erase (CE) instructions (only if all Block Protect bits set to 0, the CE
instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-protected.
QE bit. The Quad Enable (QE) bit, a non-volatile bit which is permanently set to "1". The flash always performs
Quad I/O mode.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, default value is "0".
Status Register
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
BP3 BP2 BP1 BP0
SRWD (status QE WEL WIP
(level of (level of (level of (level of
register write (Quad (write enable (write in
protected protected protected protected
protect) Enable) latch) progress bit)
block) block) block) block)
1=status
register write 1=write 1=write
disable 1=Quad enable operation
(Note) (Note) (Note) (Note)
0=status Enable 0=not write 0=not in write
register write enable operation
enable
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
volatile bit volatile bit
bit bit bit bit bit
Note: See the "Table 2. Protected Area Sizes".
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9-5. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the pro-
tected area of memory (as shown in "Table 2. Protected Area Sizes"). The WRSR can reset the Status Register
Write Disable (SRWD) bit, but has no effect on bit1 (WEL) and bit0 (WIP) of the status register.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ CS# goes high.
Figure 6. Write Status Register (WRSR) Sequence (Command 01)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
command Status
Register In
SI 01 7 6 5 4 3 2 1 0
High-Z MSB
SO
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MX25L1673E
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 6. Protection Modes
Mode Status register condition SRWD bit status Memory

Status register can be written
Software protection
in (WEL bit is set to "1") and The protected area cannot
mode (SPM) SRWD bit=0
the SRWD, BP0-BP3 be programmed or erased.
bits can be changed
Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in
"Table 2. Protected Area Sizes".
Software Protected Mode (SPM):

- When SRWD bit=0, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3,
BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM).
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MX25L1673E
Figure 7. WRSR flow
start
WREN command
RDSR command
No
WEL=1?
Yes
WRSR command
Write status register data
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,

and SRWD data
No
Verify OK?
Yes
WRSR successfully WRSR fail
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9-6. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→3-byte address on
SI →data out on SO→ to end READ operation can use CS# to high at any time during data out.
Figure 8. Read Data Bytes (READ) Sequence (Command 03)
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command 24 ADD Cycles
SI 03 A23 A22 A21 A3 A2 A1 A0
MSB
Data Out 1 Data Out 2
High-Z
SO D7 D6 D5 D4 D3 D2 D1 D0 D7
MSB MSB
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MX25L1673E
9-7. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_READ operation
can use CS# to high at any time during data out.
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; like-
wise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from
performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
Figure 9. Read at Higher Speed (FAST_READ) Sequence (Command 0B) (104MHz)
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK
Command 24 BIT ADDRESS
SI 0Bh 23 22 21 3 2 1 0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI 7 6 5 4 3 2 1 0
DATA OUT 1 DATA OUT 2
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB MSB
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9-8. Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc-
tion, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte address on
SI → 8-bit dummy cycle → data out interleave on SO1 & SO0 → to end DREAD operation can use CS# to high at
any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 10. Dual Read Mode Sequence (Command 3B)
CS#
0 1 2 3 4 5 6 7 8 9 30 31 32 39 40 41 42 43 44 45
SCLK
… …
Command 24 ADD Cycle 8 dummy Data Out Data Out
cycle 1 2
SI/SIO0 3B A23 A22 … A1 A0 D6 D4 D2 D0 D6 D4
High Impedance
SO/SIO1 D7 D5 D3 D1 D7 D5
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9-9. 2 x I/O Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruc-
tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address in-
terleave on SIO1 & SIO0→ 4-bit dummy cycles on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end
2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
Figure 11. 2 x I/O Read Mode Sequence (Command BB)
CS#
0 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 24 25 26 27 28 29
SCLK
…
Command 12 ADD Cycle 4 dummy Data Out Data Out
cycle 1 2
SI/SIO0 BB(hex) A22 A20 … A2 A0 P2 P0 D6 D4 D2 D0 D6 D4
High Impedance
SO/SIO1 A23 A21 … A3 A1 P3 P1 D7 D5 D3 D1 D7 D5
Note: SI/SIO0 or SO/SIO1 should be kept "0h" or "Fh" in the first two dummy cycles. In other words, P2=P0 or
P3=P1 is necessary.
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9-10. Quad Read Mode (QREAD)
The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge
of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum
frequency fQ. The first address byte can be at any location. The address is automatically increased to the next high-
er address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction.
The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction,
the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on
SI → 8-bit dummy cycle → data out interleave on SO3, SO2, SO1 & SO0→ to end QREAD operation can use
CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact
Figure 12. Quad Read Mode Sequence (Command 6B)
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 38 39 40 41 42
SCLK
… …
Command 24 ADD Cycles 8 dummy cycles Data Data Data
Out 1 Out 2 Out 3
SI/SO0 6B A23 A22 … A2 A1 A0 D4 D0 D4 D0 D4
High Impedance
SO/SO1 D5 D1 D5 D1 D5
High Impedance
SO2 D6 D2 D6 D2 D6
High Impedance
SO3 D7 D3 D7 D3 D7
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9-11. 4 x I/O Read Mode (4READ)
The 4READ instruction enables quad throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fQ. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruc-
tion, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address inter-
leave on SIO3, SIO2, SIO1 & SIO0→ 2+4 dummy cycles→ data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out.
Figure 13. 4 x I/O Read Mode Sequence (Command EB)

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 n
SCLK
4 dummy
8 Bit Instruction 6 Address cycles Data Output
Performance cycles
enhance
indicator (Note)
address data
SI/SIO0 EB(hex) P4 P0 bit4, bit0, bit4....
bit20, bit16..bit0
High Impedance address data

SO/SIO1 bit21, bit17..bit1 P5 P1 bit5 bit1, bit5....

SIO2 bit22, bit18..bit2 P6 P2 bit6 bit2, bit6....

Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
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Another sequence of issuing 4READ instruction especially useful in random access is : CS# goes low→ sending
4READ instruction→ 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit
P[7:0]→ 4 dummy cycles→ data out until CS# goes high → CS# goes low (reduce 4 Read instruction) → 24-bit ran-
dom access address (Please refer to "Figure 14. 4 x I/O Read enhance performance Mode Sequence (Command
EB)" ).
In the performance-enhancing mode (Notes of "Figure 14. 4 x I/O Read enhance performance Mode Sequence
(Command EB)"), P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this mode
continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise P[7:0]=FFh,
00h, AAh or 55h. These commands will reset the performance enhance mode. And afterwards CS# is raised and
then lowered, the system then will return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
9-12. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles. (Please note "Fig-
ure 14. 4 x I/O Read enhance performance Mode Sequence (Command EB)")
Please be noticed that “EBh” and “E7h” commands support enhance mode. The performance enhance mode is not
supported in dual I/O mode.
After entering enhance mode, following CSB go high, the device will stay in the read mode and treat CSB go low of
the first clock as address instead of command cycle.
To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue
”FFh” command to exit enhance mode.
9-13. Performance Enhance Mode Reset (FFh)
To conduct the Performance Enhance Mode Reset operation, FFh command code, 8 clocks, should be issued in 1I/
O sequence.
If the system controller is being Reset during operation, the flash device will return to the standard operation.
Upon Reset of main chip, Instruction would be issued from the system. Instructions like Read ID (9Fh) or Fast Read
(0Bh) would be issued.
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Figure 14. 4 x I/O Read enhance performance Mode Sequence (Command EB)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 n
SCLK
4 dummy
8 Bit Instruction 6 Address cycles Data Output
Performance cycles
enhance
indicator (Note)
address data
SI/SIO0 EB(hex) P4 P0 bit4, bit0, bit4....
bit20, bit16..bit0



CS#
n+1 ........... n+7 ...... n+9 ........... n+13 ...........
SCLK
4 dummy
6 Address cycles Data Output
Performance cycles
enhance
indicator (Note)
address data
SI/SIO0 P4 P0 bit4, bit0, bit4....
bit20, bit16..bit0
address data
address data
address data
Note: Performance enhance mode, if P7=P3 & P6=P2 & P5=P1 & P4=P0 (Toggling), ex: A5, 5A, 0F
Note: Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
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Figure 15. Performance Enhance Mode Reset for Fast Read Quad I/O
Mode Bit Reset

for Quad I/O
CS#
Mode 3 ０ 1 2 3 4 5 6 7 Mode 3
SCLK Mode ０ Mode ０
SIO0 FFh
SIO1 Don’t Care
SIO2 Don’t Care
SIO3 Don’t Care
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9-14. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see "Table 4. Memory Organization" ) is a valid address
for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address
byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Pro-
gress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE
timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page
is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
Figure 16. Sector Erase (SE) Sequence (Command 20)
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
Command 24 Bit Address
SI 20h 23 22 2 1 0
MSB
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9-15. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (see "Table 4. Memory Organization" ) is a valid
address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of
address byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code → 3-byte address on SI →
CS# goes high.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Pro-
gress (WIP) bit still can be checked out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE
timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page
is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.
Figure 17. Block Erase (BE) Sequence (Command D8)
CS#
0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
Command 24 Bit Address
SI D8h 23 22 2 1 0
MSB
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9-16. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go
high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low → sending CE instruction code → CS# goes high.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Pro-
gress (WIP) bit still can be checked out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is
protected, the Chip Erase (CE) instruction will not be executed, but WEL will be reset.
Figure 18. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI 60h or C7h
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9-17. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs
only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address bits, A7-A0)
should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that exceed page length
are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. If the
data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous
data will be disregarded. If the data bytes sent to the device has not exceeded 256, the data will be programmed at
the request address of the page. There will be no effort on the other data bytes of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked out during the Page Program cycle is in progress. The WIP sets 1 during
the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.
Figure 19. Page Program (PP) Sequence (Command 02)
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command 24-Bit Address Data Byte 1
SI 02h 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
CS#
2072
2073
2074
2075
2076
2077
2078
2079
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2 Data Byte 3 Data Byte 256
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB MSB
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9-18. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit. The Quad Page Programming takes four pins:
SIO0, SIO1, SIO2, and SIO3, which can raise programmer performance and the effectiveness of application of
lower clock less than 85MHz. For system with faster clock, the Quad page program cannot provide more actual
favors, because the required internal page program time is far more than the time data flows in. Therefore, we
suggest that while executing this command (especially during sending data), user can slow the clock speed down to
85MHz below. The other function descriptions are as same as standard page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→ CS# goes high.
If the page is protected by BP3~0, the array data will be protected (no change) and the WEL bit will still be reset.
Figure 20. 4 x I/O Page Program (4PP) Sequence (Command 38)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 524 525
SCLK
…
Command 6 ADD cycles Data Data Data
Byte 1 Byte 2 Byte 256
SI/SIO0 38 A20 A16 A12 A8 A4 A0 D4 D0 D4 D0 … D4 D0
SO/SIO1 A21 A17 A13 A9 A5 A1 D5 D1 D5 D1 … D5 D1
SIO2 A22 A18 A14 A10 A6 A2 D6 D2 D6 D2 … D6 D2
SIO3 A23 A19 A15 A11 A7 A3 D7 D3 D7 D3 … D7 D3
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9-19. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-
ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-
tive and all Write/Program/Erase instructions are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high.
Once the DP instruction is set, all instructions will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power-
down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code has been latched-in); otherwise, the instruction will not be executed. As soon as Chip Select (CS#) goes high,
a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
Figure 21. Deep Power-down (DP) Sequence (Command B9)
CS#
0 1 2 3 4 5 6 7 tDP
SCLK
Command
SI B9h
Stand-by Mode Deep Power-down Mode
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9-20. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the standby Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the standby Power mode is immediate. If the device was previously in the
Deep Power-down mode, though, the transition to the standby Power mode is delayed by tRES2, and Chip Select
(CS#) must remain High for at least tRES2(max), as specified in "Table 13. AC Characteristics". Once in the stand-
by mode, the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 7.
ID Definitions". This is not the same as RDID instruction. It is not recommended to use for new design. For new
design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be
executed, only except the device is in progress of program/erase/write cycles; there's no effect on the current pro-
gram/erase/write cycles in progress.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can receive, decode, and execute
instruction.
The RDP instruction is for releasing from Deep Power-down Mode.
Figure 22. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
SCLK
Command 3 Dummy Bytes tRES2
SI ABh 23 22 21 3 2 1 0
MSB
Electronic Signature Out
High-Z
SO 7 6 5 4 3 2 1 0
MSB
Deep Power-down Mode Stand-by Mode
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MX25L1673E
Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0 1 2 3 4 5 6 7 tRES1
SCLK
Command
SI ABh
High-Z
SO
Deep Power-down Mode Stand-by Mode
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MX25L1673E
9-21. Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4)
The REMS, REMS2, and REMS4 instruction provides both the JEDEC assigned Manufacturer ID and the specific
Device ID.
The instruction is initiated by driving the CS# pin low and shift the instruction code "90h", "DFh" or "EFh" followed
by two dummy bytes and one byte address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the
Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in the figure be-
low. The Device ID values are listed in "Table 7. ID Definitions". If the one-byte address is initially set to 01h, then
the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be
read continuously, alternating from one to the other. The instruction is completed by driving CS# high.
Figure 24. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Command 24 ADD Cycles
SI A3 A2 A1 A0
90 A23 A22 A21
Manufacturer ID Device ID
High-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB MSB MSB
Notes:
1. A0=0 will output the Manufacturer ID first and A0=1 will output Device ID first. A1~A23 are don't care.
2. Instruction is either 90(hex) or EF(hex) or DF(hex).
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MX25L1673E
9-22. ID Read
User can execute this ID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue ID
instruction is CS# goes low→sending ID instruction→→Data out on SO→CS# goes high. Most significant bit (MSB)
first.
After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,
memory type, and device ID data byte will be output continuously, until the CS# goes high.
Table 7. ID Definitions
manufacturer ID memory type memory density
RDID Command
C2 24 15
electronic ID
RES Command
24
REMS/REMS2/REMS4/ manufacturer ID device ID
Command C2 24
9-23. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 512-bit secured OTP mode. The additional 512-bit secured OTP
is independent from main array, which may use to store unique serial number for system identifier. After entering
the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data.
The Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once
security OTP is lock down, only read related commands are valid.
9-24. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 512-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→sending EXSO instruction to exit Secured OTP
mode→CS# goes high.
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MX25L1673E
9-25. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register. The Read Security Register can be read at
any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→ sending RDSCUR instruction → Security Regis-
ter data out on SO→ CS# goes high.
Figure 25. Read Security Register (RDSCUR) Sequence (Command 2B)
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
command
SI 2B
Security Register Out Security Register Out

High-Z
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB
The definition of the Security Register is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or
not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for custom-
er lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512-bit Secured OTP
area cannot be update any more. While it is in 512-bit secured OTP mode, main array access is not allowed.
Table 8. Security Register Definition

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
LDSO
Secured OTP
x x x x x x (indicate if
indicator bit
lock-down
0 = not lock-down
0 = non-factory
1 = lock-down
lock
reserved reserved reserved reserved reserved reserved (cannot
1 = factory
program/erase
lock
OTP)
volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit
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MX25L1673E
9-26. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. The WREN instruction is required be-
fore sending WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit) for customer
to lock-down the Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any
more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
Figure 26. Write Security Register (WRSCUR) Sequence (Command 2F)
CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI 2F
High-Z
SO
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MX25L1673E
9-27. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is same as CS# goes low→send RDSFDP instruction (5Ah)→send 3
address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can
use CS# to high at any time during data out.
SFDP is a JEDEC Standard. JESD216.
Figure 27. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK
Command 24 BIT ADDRESS
SI 5Ah 23 22 21 3 2 1 0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycle
SI 7 6 5 4 3 2 1 0
DATA OUT 1 DATA OUT 2
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB MSB
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MX25L1673E
Table 9. Signature and Parameter Identification Data Values

SFDP Table below is for MX25L1673EM2I-10G and MX25L1673EZNI-10G
Add (h) DW Add Data (h/b) Data
Description Comment
(Byte) (Bit) (Note1) (h)
00h 07:00 53h 53h
01h 15:08 46h 46h
SFDP Signature Fixed: 50444653h
02h 23:16 44h 44h
03h 31:24 50h 50h
SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h
SFDP Major Revision Number Start from 01h 05h 15:08 01h 01h
This number is 0-based. Therefore,
Number of Parameter Headers 06h 23:16 01h 01h
0 indicates 1 parameter header.
Unused 07h 31:24 FFh FFh
00h: it indicates a JEDEC specified
ID number (JEDEC) 08h 07:00 00h 00h
header.
Parameter Table Minor Revision
Start from 00h 09h 15:08 00h 00h
Number
Parameter Table Major Revision
Start from 01h 0Ah 23:16 01h 01h
Number
Parameter Table Length How many DWORDs in the
0Bh 31:24 09h 09h
(in double word) Parameter table
0Ch 07:00 30h 30h
First address of JEDEC Flash
Parameter Table Pointer (PTP) 0Dh 15:08 00h 00h
Parameter table
0Eh 23:16 00h 00h
Unused 0Fh 31:24 FFh FFh

ID number it indicates Macronix manufacturer
10h 07:00 C2h C2h
(Macronix manufacturer ID) ID
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length How many DWORDs in the
13h 31:24 04h 04h
(in double word) Parameter table
14h 07:00 60h 60h
First address of Macronix Flash
Parameter Table Pointer (PTP) 15h 15:08 00h 00h
Parameter table
16h 23:16 00h 00h
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MX25L1673E
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables

Description Comment
00: Reserved, 01: 4KB erase,
Block/Sector Erase sizes 10: Reserved, 01:00 01b
11: not support 4KB erase
Write Granularity 0: 1Byte, 1: 64Byte or larger 02 1b
Write Enable Instruction Required 0: not required
for Writing to Volatile Status 1: required 00h to be written to the 03 0b
Registers status register 30h E5h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Note: If target flash status register is 04 0b
Writing to Volatile Status Registers
nonvolatile, then bits 3 and 4 must
be set to 00b.
Contains 111b and can never be
Unused 07:05 111b
changed
4KB Erase Opcode 31h 15:08 20h 20h
(1-1-2) Fast Read (Note2) 0=not support 1=support 16 1b

Address Bytes Number used in 00: 3Byte only, 01: 3 or 4Byte,
18:17 00b
addressing flash array 10: 4Byte only, 11: Reserved
Double Transfer Rate (DTR)
0=not support 1=support 19 0b
Clocking
32h F1h
(1-2-2) Fast Read 0=not support 1=support 20 1b
Unused 23 1b
Flash Memory Density 37h:34h 31:00 00FF FFFFh
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00 0 0100b
states (Note3) Clocks) not support
38h 44h
(1-4-4) Fast Read Number of
000b: Mode Bits not support 07:05 010b
Mode Bits (Note4)
(1-4-4) Fast Read Opcode 39h 15:08 EBh EBh
20:16 0 1000b
states Clocks) not support
3Ah 08h
Mode Bits
(1-1-4) Fast Read Opcode 3Bh 31:24 6Bh 6Bh
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MX25L1673E

Description Comment
04:00 0 1000b
3Ch 08h
Mode Bits
(1-1-2) Fast Read Opcode 3Dh 15:08 3Bh 3Bh
20:16 0 0100b
3Eh 04h
Mode Bits
(1-2-2) Fast Read Opcode 3Fh 31:24 BBh BBh
Unused 03:01 111b
40h EEh
Unused 07:05 111b
Unused 43h:41h 31:08 FFh FFh
20:16 0 0000b
46h 00h
Mode Bits
(2-2-2) Fast Read Opcode 47h 31:24 FFh FFh
20:16 0 0000b
4Ah 00h
Mode Bits
(4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh
Sector/block size = 2^N bytes (Note5)
Sector Type 1 Size 4Ch 07:00 0Ch 0Ch
0x00b: this sector type doesn't exist
Sector Type 1 erase Opcode 4Dh 15:08 20h 20h
Sector/block size = 2^N bytes
Sector Type 2 Size 4Eh 23:16 10h 10h
Sector Type 2 erase Opcode 4Fh 31:24 D8h D8h
Sector Type 3 Size 50h 07:00 00h 00h
Sector Type 3 erase Opcode 51h 15:08 FFh FFh
Sector Type 4 Size 52h 23:16 00h 00h
Sector Type 4 erase Opcode 53h 31:24 FFh FFh
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MX25L1673E
Table 11. Parameter Table (1): Macronix Flash Parameter Tables

Description Comment
2000h=2.000V
07:00 00h 00h
Vcc Supply Maximum Voltage 2700h=2.700V 61h:60h
15:08 36h 36h
3600h=3.600V
1650h=1.650V
2250h=2.250V 23:16 00h 00h
Vcc Supply Minimum Voltage 63h:62h
2350h=2.350V 31:24 27h 27h
2700h=2.700V
H/W Reset# pin 0=not support 1=support 00 0b
H/W Hold# pin 0=not support 1=support 01 0b

Deep Power Down Mode 0=not support 1=support 02 1b
S/W Reset 0=not support 1=support 03 0b
Reset Enable (66h) should be 65h:64h 1111 1111b 4FF4h
S/W Reset Opcode 11:04
issued before Reset Opcode (FFh)
Program Suspend/Resume 0=not support 1=support 12 0b
Erase Suspend/Resume 0=not support 1=support 13 0b
Unused 14 1b
Wrap-Around Read mode 0=not support 1=support 15 0b
Wrap-Around Read mode Opcode 66h 23:16 FFh FFh
08h:support 8B wrap-around read
16h:8B&16B
Wrap-Around Read data length 67h 31:24 FFh FFh
32h:8B&16B&32B
64h:8B&16B&32B&64B
Individual block lock 0=not support 1=support 00 0b
Individual block lock bit
0=Volatile 1=Nonvolatile 01 1b
(Volatile/Nonvolatile)
1111 1111b
Individual block lock Opcode 09:02
(FFh)
Individual block lock Volatile
0=protect 1=unprotect 10 1b CFFEh
protect bit default protect status
6Bh:68h
Secured OTP 0=not support 1=support 11 1b
Read Lock 0=not support 1=support 12 0b
Permanent Lock 0=not support 1=support 13 0b
Unused 15:14 11b
Unused 31:16 FFh FFh
Unused 6Fh:6Ch 31:00 FFh FFh
MX25L1673EM2I-10G-SFDP_2014-01-14
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MX25L1673E
Note 1: h/b is hexadecimal or binary.

Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: All unused and undefined area data is blank FFh.
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MX25L1673E
10. POWER-ON STATE
The device is at below states when power-up:

- Standby mode (please note it is not Deep Power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal Power-on Reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.
(generally around 0.1uF)
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MX25L1673E
11. ELECTRICAL SPECIFICATIONS
11-1. Absolute Maximum Ratings
Rating Value
Ambient Operating Temperature Industrial grade -40°C to 85°C
Storage Temperature -65°C to 150°C
Applied Input Voltage -0.5V to 4.6V
Applied Output Voltage -0.5V to 4.6V
VCC to Ground Potential -0.5V to 4.6V
NOTICE:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the de-
vice. This is stress rating only and functional operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see the
figures below.
Figure 28. Maximum Negative Overshoot Waveform Figure 29. Maximum Positive Overshoot Waveform
20ns
20ns 20ns
Vss Vcc + 2.0V
Vss-2.0V Vcc
20ns 20ns 20ns
11-2. Capacitance
TA = 25°C, f = 1.0 MHz

Symbol Parameter Min. Typ. Max. Unit Conditions
CIN Input Capacitance 6 pF VIN = 0V
COUT Output Capacitance 8 pF VOUT = 0V
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MX25L1673E
Figure 30. Input Test Waveforms and Measurement Level
Input timing reference level Output timing reference level
0.8VCC
0.7VCC AC
Measurement 0.5VCC
0.3VCC Level
0.2VCC
Note: Input pulse rise and fall time are <5ns
Figure 31. Output Loading
DEVICE UNDER 2.7K ohm

TEST +3.3V
CL
6.2K ohm DIODES=IN3064
OR EQUIVALENT
CL=30/15pF Including jig capacitance
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MX25L1673E
Table 12. DC Characteristics
Temperature = -40°C to 85°C for Industrial grade
SYMBOL PARAMETER NOTES MIN. TYP. MAX. UNITS TEST CONDITIONS

VCC = VCC Max,
ILI Input Load Current 1 ±2 uA
VIN = VCC or GND
VCC = VCC Max,
ILO Output Leakage Current 1 ±2 uA
VIN = VCC or GND
VIN = VCC or GND,
ISB1 VCC Standby Current 1 15 25 uA
CS# = VCC
Deep Power-down VIN = VCC or GND,
ISB2 2 20 uA
Current CS# = VCC
f=104MHz,
fQ=85MHz (4 x I/O read)
25 mA
SCLK=0.1VCC/0.9VCC,
SO=Open
fT=85MHz (2 x I/O read)
ICC1 VCC Read 1 20 mA SCLK=0.1VCC/0.9VCC,
SO=Open
f=33MHz,
10 mA SCLK=0.1VCC/0.9VCC,
SO=Open
VCC Program Current Program in Progress,
ICC2 1 15 20 mA
(PP) CS# = VCC
VCC Write Status Program status register in
ICC3 3 20 mA
Register (WRSR) Current progress, CS#=VCC
VCC Sector Erase
ICC4 1 9 20 mA Erase in Progress, CS#=VCC
Current (SE)
VCC Chip Erase Current
ICC5 1 15 20 mA Erase in Progress, CS#=VCC
(CE)
VIL Input Low Voltage -0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage 0.4 V IOL = 1.6mA
VOH Output High Voltage VCC-0.2 V IOH = -100uA
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
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MX25L1673E
Table 13. AC Characteristics

Temperature = -40°C to 85°C for Industrial grade
Symbol Alt. Parameter Min. Typ. Max. Unit
Clock Frequency for the following instructions:
fSCLK fC FAST_READ, RDSFDP, SE, BE, CE, DP, RES, RDP, D.C. 104 MHz
WREN, WRDI, RDID, RDSR, WRSR
fP Clock Frequency for PP instructions D.C. 86 MHz
fPSCLK
f4P Clock Frequency for 4PP instructions D.C. 85 MHz
fRSCLK fR Clock Frequency for READ instructions 33 MHz
fT Clock Frequency for 2READ/DREAD instructions 85 MHz
fTSCLK
fQ Clock Frequency for 4READ/QREAD instructions 85 MHz
fC=104MHz 4.7 ns
tCH(1) tCLH Clock High Time
fR=33MHz 13 ns
fC=104MHz 4.7 ns
tCL(1) tCLL Clock Low Time
fR=33MHz 13 ns
tCLCH Clock Rise Time (peak to peak) 0.1 V/ns
tCHCL Clock Fall Time (peak to peak) 0.1 V/ns
tSLCH tCSS CS# Active Setup Time (relative to SCLK) 5 ns
tCHSL CS# Not Active Hold Time (relative to SCLK) 5 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH CS# Active Hold Time (relative to SCLK) 5 ns
tSHCH CS# Not Active Setup Time (relative to SCLK) 5 ns
Read 15 ns
tSHSL tCSH CS# Deselect Time
Write/Erase/Program 50 ns
2.7V-3.6V 10 ns
tSHQZ(2) tDIS Output Disable Time
3.0V-3.6V 8 ns
Clock Low to Output Valid 2.7V-3.6V 9/8 ns
tCLQV tV
Loading: 30pF/15pF 3.0V-3.6V 8/6 ns
tCLQX tHO Output Hold Time 1 ns
tWHSL(3) Write Protect Setup Time 20 ns
tSHWL(3) Write Protect Hold Time 100 ns
tDP CS# High to Deep Power-down Mode 10 us
CS# High to Standby Mode without Electronic Signature
tRES1 8.8 us
Read
tRES2 CS# High to Standby Mode with Electronic Signature Read 8.8 us
tW Write Status Register Cycle Time 40 100 ms
tBP Byte-Program 9 50 us
tPP Page Program Cycle Time 0.6 3 ms
tSE Sector Erase Cycle Time 40 200 ms
tBE Block Erase Cycle Time 0.4 2 s
tCE Chip Erase Cycle Time 5 20 s
Notes:
1. tCH + tCL must be greater than or equal to 1/ f (fC or fR).
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Test condition is shown as "Figure 30. Input Test Waveforms and Measurement Level" and "Figure 31. Output
Loading".
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MX25L1673E
12. TIMING ANALYSIS
Figure 32. Serial Input Timing
tSHSL
CS#
tCHSL tSLCH tCHSH tSHCH
SCLK
tDVCH tCHCL
tCHDX tCLCH
SI MSB LSB
High-Z
SO
Figure 33. Output Timing
CS#
tCH
SCLK
tCLQV tCLQV tCL tSHQZ
tCLQX tCLQX
SO LSB
SI ADDR.LSB IN
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MX25L1673E
Figure 34. Power-Up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
tVSL Device is fully accessible
time
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 14. Power-Up Timing

Symbol Parameter Min. Max. Unit
tVSL(1) VCC(min) to CS# low 200 us
Note: The parameter is characterized only.
12-1. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
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13. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 35. AC Timing at Device Power-Up" and "Figure 36. Power-Down Sequence" are
for the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is
ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 35. AC Timing at Device Power-Up
VCC(min)
VCC
GND tVR tSHSL
CS#
tCHSL tSLCH tCHSH tSHCH
SCLK
tDVCH tCHCL
tCHDX tCLCH
SI MSB IN LSB IN
High Impedance
SO
Symbol Parameter Notes Min. Max. Unit

tVR VCC Rise Time 1 5 500000 us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer
to "Table 13. AC Characteristics".
P/N: PM1912 REV. 1.2, JAN. 14, 2014

57
MX25L1673E
Figure 36. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
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58
MX25L1673E
14. ERASE AND PROGRAMMING PERFORMANCE

PARAMETER Min. TYP. (1) Max. (2) UNIT
Write Status Register Cycle Time 40 100 ms
Sector Erase Cycle Time 40 200 ms
Block Erase Cycle Time 0.4 2 s
Chip Erase Cycle Time 5 20 s
Byte Program Time (via page program command) 9 50 us
Page Program Cycle Time 0.6 3 ms
Erase/Program Cycle 100,000 cycles
Notes:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checkerboard pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
15. DATA RETENTION

PARAMETER Condition Min. Max. UNIT
Data retention 55˚C 20 years
16.
LATCH-UP CHARACTERISTICS
MIN. MAX.
Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax
Input Voltage with respect to GND on SO -1.0V VCC + 1.0V
Current -100mA +100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1912 REV. 1.2, JAN. 14, 2014

59
MX25L1673E
17. ORDERING INFORMATION
PART NO. CLOCK (MHz) TEMPERATURE PACKAGE Remark

8-SOP
MX25L1673EM2I-10G 104 -40°C~85°C
(200mil)
8-WSON
MX25L1673EZNI-10G 104 -40°C~85°C
(6x5mm)
P/N: PM1912 REV. 1.2, JAN. 14, 2014

60
MX25L1673E
18. PART NAME DESCRIPTION
MX 25 L 1673E M2 I 10 G
OPTION:
G: RoHS Compliant & Halogen-free
SPEED:
10: 104MHz
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
M2: 200mil 8-SOP
ZN: 6x5mm 8-WSON
DENSITY & MODE:

1673E: 16Mb standard type
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1912 REV. 1.2, JAN. 14, 2014

61
MX25L1673E
P/N: PM1912 REV. 1.2, JAN. 14, 2014

62
MX25L1673E
P/N: PM1912 REV. 1.2, JAN. 14, 2014

63
MX25L1673E
19. REVISION HISTORY
Revision No. Description Page Date

0.00 1. Initial released All OCT/09/2012
1.0 1. Removed Advanced Information state P4 JAN/02/2013
2. Kept MX25L1673EZNI-10G as Advanced Information P60
3. Modified tCLQX value in AC Characteristics Table P54
1.1 1. Updated parameters for DC Characteristics. P4,53 NOV/06/2013
2. Updated Erase and Programming Performance. P4,54,59
1.2 1. Removed Advanced Information status of MX25L1673EZNI-10G P60 JAN/14/2014
P/N: PM1912 REV. 1.2, JAN. 14, 2014

64
MX25L1673E
Except for customized products which have been expressly identified in the applicable agreement, Macronix's products are
designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and
not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In
the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to
ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macro-
nix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2012~2014. All rights reserved, including the trademarks and tradename thereof,
such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, Hy-
bridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP,
Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification
purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
65

MX25L1673E: High Performance Serial Flash Specification

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MX25L1673E

SERIAL FLASH SPECIFICATION

P/N: PM1912 REV. 1.2, JAN. 14, 2014

P/N: PM1912 REV. 1.2, JAN. 14, 2014

Table 10. Parameter Table (0): JEDEC Flash Parameter Tables..........................................................46

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The MX25L1673E provides sequential read operation on whole chip.

Table 1. Additional Feature

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3. PIN CONFIGURATION 4. PIN DESCRIPTION

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SCLK Clock Generator

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I. Block lock protection

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Table 2. Protected Area Sizes

Table 3. 512-bit Secured OTP Definition

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Table 4. Memory Organization

P/N: PM1912 REV. 1.2, JAN. 14, 2014

Figure 1. Serial Modes Supported (for Normal Serial mode)

CPOL CPHA shift in shift out

(Serial mode 0) 0 0 SCLK

(Serial mode 3) 1 1 SCLK

P/N: PM1912 REV. 1.2, JAN. 14, 2014

P/N: PM1912 REV. 1.2, JAN. 14, 2014

1st byte 06 (hex) 04 (hex) 9F (hex) 05 (hex) 01 (hex) 38 (hex) 20 (hex)

RDP (Release Release Read

P/N: PM1912 REV. 1.2, JAN. 14, 2014

9-1. Write Enable (WREN)

The SIO[3:1] are don't care in this mode.

Figure 2. Write Enable (WREN) Sequence (Command 06)

P/N: PM1912 REV. 1.2, JAN. 14, 2014

9-2. Write Disable (WRDI)

Figure 3. Write Disable (WRDI) Sequence (Command 04)

P/N: PM1912 REV. 1.2, JAN. 14, 2014

9-3. Read Identification (RDID)

Figure 4. Read Identification (RDID) Sequence (Command 9F)

Manufacturer Identification Device Identification

P/N: PM1912 REV. 1.2, JAN. 14, 2014

9-4. Read Status Register (RDSR)

The SIO[3:1] are don't care when during this mode.

Figure 5. Read Status Register (RDSR) Sequence (Command 05)

Status Register Out Status Register Out

P/N: PM1912 REV. 1.2, JAN. 14, 2014

The definition of the status register bits is as below:

Note: See the "Table 2. Protected Area Sizes".

P/N: PM1912 REV. 1.2, JAN. 14, 2014

9-5. Write Status Register (WRSR)

Figure 6. Write Status Register (WRSR) Sequence (Command 01)

P/N: PM1912 REV. 1.2, JAN. 14, 2014

Table 6. Protection Modes

Mode Status register condition SRWD bit status Memory

Software Protected Mode (SPM):

P/N: PM1912 REV. 1.2, JAN. 14, 2014

Figure 7. WRSR flow

Write status register data