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    UPF Example: UPF For The Above Power Intent: ######## Create Power Domains ###########

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    Mayur Agarwal
    The document describes a UPF (Unified Power Format) example for an LVDS system. It defines four power domains - TOP, TX_AON, RECIEVER, CRC_GEN. It then defines the power and ground connections between the different domains and modules. Isolation cells and retention logic are added to help control power for the RECIEVER and CRC_GEN domains. A power state table with four states is also created to control the power switches.

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    © All Rights Reserved
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    UPF Example: UPF For The Above Power Intent: ######## Create Power Domains ###########

    Uploaded by

    Mayur Agarwal
    916 views4 pages
    The document describes a UPF (Unified Power Format) example for an LVDS system. It defines four power domains - TOP, TX_AON, RECIEVER, CRC_GEN. It then defines the power and ground connections between the different domains and modules. Isolation cells and retention logic are added to help control power for the RECIEVER and CRC_GEN domains. A power state table with four states is also created to control the power switches.

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    UPF example

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    The document describes a UPF (Unified Power Format) example for an LVDS system. It defines four power domains - TOP, TX_AON, RECIEVER, CRC_GEN. It then defines the power and ground connections between the different domains and modules. Isolation cells and retention logic are added to help control power for the RECIEVER and CRC_GEN domains. A power state table with four states is also created to control the power switches.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    916 views4 pages

    UPF Example: UPF For The Above Power Intent: ######## Create Power Domains ###########

    Uploaded by

    Mayur Agarwal
    The document describes a UPF (Unified Power Format) example for an LVDS system. It defines four power domains - TOP, TX_AON, RECIEVER, CRC_GEN. It then defines the power and ground connections between the different domains and modules. Isolation cells and retention logic are added to help control power for the RECIEVER and CRC_GEN domains. A power state table with four states is also created to control the power switches.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    At a glance
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    The document describes the creation of a power intent for an LVDS system with multiple power domains and power gating logic for certain modules. It defines power domains for the top level, transmitter, receiver and CRC generator modules. Isolation cells and retention logic are used for power and noise isolation.

    The power domains created are TOP, TX_AON, RECIEVER, and CRC_GEN. The transmitter, power controller and receiver are assigned to TX_AON. The receiver is assigned to RECIEVER. The CRC generator is assigned to CRC_GEN.

    Power switches controlled by the power controller module are used to gate the power to the receiver and CRC modules. Isolation cells are also used to isolate the inputs and outputs of these modules when powered down.

    UPF example

    UPF for the above Power Intent:

    ######## Create Power Domains ###########

    create_power_domain TOP
    create_power_domain TX_AON -elements {transmitter power_controller}
    create_power_domain RECIEVER -elements reciever
    create_power_domain CRC_GEN -elements checker

    ## Toplevel Connections ######

    # VDD_HIGH (1.08V)
    create_supply_port VDD_HIGH
    create_supply_net VDD_HIGH -domain TOP
    create_supply_net VDD_HIGH -domain TX_AON -reuse
    create_supply_net VDD_HIGH -domain CRC_GEN -reuse
    connect_supply_net VDD_HIGH -ports VDD_HIGH

    # VDD_LOW (0.864V)
    create_supply_port VDD_LOW
    create_supply_net VDD_LOW -domain TOP
    create_supply_net VDD_LOW -domain RECIEVER -reuse
    connect_supply_net VDD_LOW -ports VDD_LOW
    # VSS (0.0V)
    create_supply_port VSS
    create_supply_net VSS -domain TOP
    create_supply_net VSS -domain TX_AON -reuse
    create_supply_net VSS -domain RECIEVER -reuse
    create_supply_net VSS -domain CRC_GEN -reuse
    connect_supply_net VSS -ports VSS

    ### RECIEVER/CRC DOMAIN Power Connections ##########

    create_supply_net VDD_LOW_RX_VIRTUAL -domain RECIEVER


    create_supply_net VDD_HIGH_CRC_VIRTUAL -domain CRC_GEN

    ### Establish Connections ################

    set_domain_supply_net TOP -primary_power_net VDD_HIGH -primary_ground_net


    VSS
    set_domain_supply_net TX_AON -primary_power_net VDD_HIGH -
    primary_ground_net VSS
    set_domain_supply_net RECIEVER -primary_power_net VDD_LOW_RX_VIRTUAL -
    primary_ground_net VSS
    set_domain_supply_net CRC_GEN -primary_power_net VDD_HIGH_CRC_VIRTUAL -
    primary_ground_net VSS

    ########## Shut-Down Logic for Reciever #######

    create_power_switch rx_sw
    -domain RECIEVER
    -input_supply_port {in VDD_LOW}
    -output_supply_port {out VDD_LOW_RX_VIRTUAL}
    -control_port {rx_sd power_controller/rx_sd}
    -on_state {state2008 in {!rx_sd}}

    ######### Isolation cell Settings for Reciever #######

    set_isolation rx_iso_out
    -domain RECIEVER
    -isolation_power_net VDD_HIGH -isolation_ground_net VSS
    -clamp_value 1
    -applies_to outputs

    set_isolation_control rx_iso_out
    -domain RECIEVER
    -isolation_signal power_controller/rx_iso
    -isolation_sense low
    -location parent
    ########## Create Shut-Down Logic for CRC #######

    create_power_switch crc_sw -domain CRC_GEN -input_supply_port {in VDD_HIGH} -


    output_supply_port {out VDD_HIGH_CRC_VIRTUAL} -control_port {crc_sd
    power_controller/crc_sd} -on_state {state2009 in {!crc_sd}}

    ######### Isolation cell Settings for CRC #########


    set_isolation crc_iso_in -domain CRC_GEN -isolation_power_net VDD_HIGH -
    isolation_ground_net VSS -clamp_value 1 -applies_to inputs

    set_isolation_control crc_iso_in -domain CRC_GEN -isolation_signal


    power_controller/crc_iso -isolation_sense high -location parent

    set_isolation crc_iso_out -domain CRC_GEN -isolation_power_net VDD_HIGH -


    isolation_ground_net VSS -applies_to outputs
    set_isolation_control crc_iso_out -domain CRC_GEN -isolation_signal
    power_controller/crc_iso -location parent

    #### Retention Logic for CRC ##############

    set_retention crc_retain -domain CRC_GEN -retention_power_net VDD_HIGH -


    retention_ground_net VSS
    set_retention_control crc_retain -domain CRC_GEN -save_signal
    {power_controller/crc_save high} -restore_signal {power_controller/crc_restore high}
    map_retention_cell crc_retain -domain CRC_GEN -lib_cell_type LIB_CELL_NAME

    #### Level Shifter for AON domain #################

    set_level_shifter tx_aon_ls_out -domain TX_AON -applies_to outputs -location self -rule


    both

    ### Create Power State Table ##################

    add_port_state VDD_HIGH -state {HighVoltage 1.08}


    add_port_state VDD_LOW -state {LowVoltage 0.864}
    add_port_state crc_sw/out -state {HighVoltage 1.08} -state {CRC_OFF off}
    add_port_state rx_sw/out -state {LowVoltage 0.864} -state {RX_OFF off}

    create_pst lvds_system_pst -supplies {VDD_HIGH VDD_LOW


    VDD_HIGH_CRC_VIRTUAL VDD_LOW_RX_VIRTUAL}
    add_pst_state PRE_BOOT -pst lvds_system_pst -state { HighVoltage LowVoltage
    CRC_OFF RX_OFF}
    add_pst_state CRC_ON -pst lvds_system_pst -state { HighVoltage LowVoltage
    HighVoltage RX_OFF}
    add_pst_state RX_ON -pst lvds_system_pst -state { HighVoltage LowVoltage
    CRC_OFF LowVoltage}
    add_pst_state ALL_ON -pst lvds_system_pst -state { HighVoltage LowVoltage
    HighVoltage LowVoltage}

    RTL For the Top Level:

    // This block needs to be Always on, it generates


    // sd – shut_down for Switches
    // save – save for RFF
    // restore – restore for RFF
    // iso – isolation_enable signals for Isolation cell
    // reset – Reset signal to reset the block after wake-up
    // Created on : 01/07/2008
    // —————————————————————

    module lvds_system ( clk, reset_n, frame_in, data_in, power_data, data_out, data_ok );


    input [15:0] data_in;
    input [3:0] power_data;
    output [15:0] data_out;
    input clk, reset_n, frame_in;
    output data_ok;
    wire serial_out, tx_frame, rx_frame;
    wire rx_iso,crc_iso, crc_save,crc_restore, rx_sd,crc_sd,rx_power_ack,crc_power_ack;

    piso transmitter ( .clk(clk), .reset_n(reset_n), .p_data_in(data_in), .load(


    frame_in), .serial_out(serial_out), .tx_frame(tx_frame) );

    sipo reciever ( .clk(clk), .reset_n(reset_n), .serial_in(serial_out),


    .tx_frame(tx_frame), .parallel_out(data_out), .rx_frame(rx_frame) );

    checker checker ( .clk(clk), .reset_n(reset_n), .load_tx_data(frame_in),


    .load_rx_data(rx_frame), .tx_data(data_in), .rx_data(data_out),
    .data_ok(data_ok) );

    power_controller power_controller(.clock(clk),
    .reset(reset_n),
    .power_data(power_data),
    .rx_iso(rx_iso),
    .crc_iso(crc_iso),
    .crc_save(crc_save),
    .crc_restore(crc_restore),
    .rx_sd(rx_sd),
    .crc_sd(crc_sd),
    .rx_power_ack(rx_power_ack),
    .crc_power_ack(crc_power_ack));

    endmodule

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