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Beginning FPGA Programming - Partie66

This document discusses updating a previous FPGA design to include an accelerometer sensor. It describes adding a SPI master module to interface with the accelerometer chip. New command and status registers are defined to control the SPI master. Example VHDL code is provided for the new SPI_MASTER module and updated top-level design file to interface the accelerometer sensor. The document explains how the updated design can be built and programmed on an FPGA board to read acceleration data from the sensor.

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ali alilou
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93 views

Beginning FPGA Programming - Partie66

This document discusses updating a previous FPGA design to include an accelerometer sensor. It describes adding a SPI master module to interface with the accelerometer chip. New command and status registers are defined to control the SPI master. Example VHDL code is provided for the new SPI_MASTER module and updated top-level design file to interface the accelerometer sensor. The document explains how the updated design can be built and programmed on an FPGA board to read acceleration data from the sensor.

Uploaded by

ali alilou
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 14 ■ How Fast Can You Run? Ask the Accelerometer!

Figure 14-16.  Accelerometer sensor design block diagram

Figure 14-17.  Temperature sensor design structure

In Figure 14-17 you can see that temperature_sensor_top is the top-level design. The top-level
design replaces the uartTOi2c (from the example in Chapter 13) with the uartTOi2cspi module. The new
uartTOi2cspi module is the uartTOi2c module with SPI master module (spi_master).
We are going to update the Chapter 13 design to include the Accelerometer. We will start from the
lowest-level module which is uartTOi2c. We need to update three things on this module.
1.
Add spi_master to the uartTOi2c.vhd
2.
Add new control and status registers for the UART to control the SPI master
3.
Save as a new file with a new entity name of uartTOi2cspi.vhd with the new port
list (SPI)

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Chapter 14 ■ How Fast Can You Run? Ask the Accelerometer!

Before moving on to update the design, let us show you where the accelerometer chip is on the BeMicro
MAX10. Figure 14-18 shows the back of the board and the location of the chip.

Figure 14-18.  The back side of the BeMicro MAX10 with the Accelerometer

All of the commands and status definition are in the next.


In the example code section we will have both a new design VHDL file (spi_master.vhd) and modified
versions of the temperature_sensor_top.vhd and uartTOi2cspi.vhd files. The simulation test bench file
will be updated as an exercise for you.

14.3.1 Add New Command and Status Registers


We need two new commands and three new status registers for the SPI master interfaces. The two new
command address locations are 0x0100 and 0x0101. Tables 14-1 and 14-2 are for someone who wants to
get deeper into designing FPGAs. We will provide the initial UART command in the section “Initialize the
Accelerometer—ADXL362.”

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Chapter 14 ■ How Fast Can You Run? Ask the Accelerometer!

Table 14-1.  PC UART 6-Byte Write Command Register version 2

Address Bit 31 downto 24 Bit 23 downto 16 Bit 15 Bit 7


downto 8 downto 0
0x0000 LED 7
downto 2
0x0010 Bit 31 Bit 30 Not Bit 23 Bit 22 downto Second First Byte
I2C ena 2Bytes use I2C rw 16 Byte to to write
I2C 1= Read I2C 7 Bit write "I2C
CMD 0 = Write Address "I2C Register
= 0x48 Register Address"
(ADT7420) Value"
0x0100 Bit 22 Bit 21 Bit 16 Bit 15
cpol CPHA CSPOL downto 0
Clock
diver
0x0101 ENA Bit 8 Bit 7
1 = Last downto 0
byte Write Byte

0x8000 Need to set all zero to read back three registers

Table 14-2.  PC UART 6-Byte Read Status Register version 2

Address Bit 31 downto 24 Bit 23 downto 16 Bit 15 downto 8 Bit 7 downto 0


0x0000 Not use LED 7 downto 0
0x0010 Last command to I2C Master
0x0011 Temperature value in degree Celsius Raw Temperature
value read from
ADT7420
0x0100 Bit 22 Bit 21 Bit 16 Bit 15 downto 0
CPOL CPHA CSPOL Clock divider

0x0101 Last command to SPI Master


0x0110 Last Read Byte Last Read Byte Current Read
Byte

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Chapter 14 ■ How Fast Can You Run? Ask the Accelerometer!

In Table 14-1, we defined that the register with the address 0x0000 can control the external LED and
turn it on and off. The register gets updated to control only the top six LEDs. The low two LEDs (1 and 0) are
connected to the SPI slave INT 1 and INT 2. So LED 1 and LED 0 are used to indicate the interrupts from the
Accelerometer.
The register 0x0100 is used to set up the SPI master module clock speed, polarity, and clock phase. It is
reported back to the status section.
The register 0x0101 is used to request the SPI master to send/receive one byte. Bit 31 is set to '1' to
indicate a valid request with the write value in the bit 7 to 0. If this request is the last byte to write/read, bit 8
(the last byte) also needs to be set HIGH. This register will report back to the status section too.
The register 0x0110 status reports three bytes. These three bytes are the last three times read result from
the acceleration sensor. It works like a byte shift register. On every new read request from the acceleration
sensor (register 0x0101), this register will shift left by one byte (8 bits), which means that it will show the last
three read bytes from the acceleration sensor. This three bytes read back are used to report the value of three
axis acceleration from teh Accelerometer.
The section “Example Design Codes” will show all of the foregoing updates.

14.3.2 Create the Temperature Sensor Project Design and


Program It
Copy the Chapter 13 project into a new directory and copy the following new SPI_master, uartTOi2cspi, and
temperature_accelerometer_sensor_top vhdl files into the project. You should use the same method you
used in Chapter 13 to build the project for the FPGA.

■■Note  Remember to select the temperature_accelerometer_sensor_top.vhd as the top entity design file in
the project before compiling the project.

14.3.3 Example Design Codes


14.3.3.1 SPI_MASTER.VHD code
Listing 14-1 is the SPI master main module design.

Listing 14-1.  spi_master.vhd


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity spi_master is
port(
clk : in std_logic; --system clock
reset_n : in std_logic; --active low reset
clk_div : in std_logic_vector(15 downto 0); -- spi_sclk = clk/(clk_div x 2)
cspol : in std_logic; -- chip select polarity (0 = active low)
cpha : in std_logic;
cpol : in std_logic;
ena : in std_logic;
write_byte : in std_logic_vector(7 downto 0);

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Chapter 14 ■ How Fast Can You Run? Ask the Accelerometer!

last_byte : in std_logic;
read_byte : out std_logic_vector(7 downto 0);
done : out std_logic;
spi_sclk : out std_logic; -- run in 230kHz
spi_cs : out std_logic;
spi_mosi : out std_logic;
spi_miso : in std_logic
);
end spi_master;

architecture rtl of spi_master is

signal ena_dly : std_logic;


signal running : std_logic;
signal count : unsigned(16 downto 0); --timing for clock generation
signal data_clk, data_clk_dly : std_logic;
signal bit_count : unsigned(3 downto 0);
signal reg_shift_out : std_logic_vector(8 downto 0);
signal reg_shift_in : std_logic_vector(7 downto 0);
signal clk_div2 : unsigned(16 downto 0);
begin

clk_div2 <= unsigned(clk_div) & '0'; -- double the clk_div value to clk_div2

--generate the timing for the spi clock (spi_sclk) and the data clock (data_clk)
clk_gen_p : process(clk, reset_n)
begin
if(reset_n = '0') then --reset asserted
count <= (others => '0');
spi_sclk <= '0';
data_clk <= '0';
elsif rising_edge(clk) then
if(count = clk_div2-1) then --end of timing cycle
count <= (others => '0'); --reset timer
else
count <= count + 1; --continue clock generation timing
end if;

if(running = '1' and bit_count < 8) then


if(count < unsigned(clk_div)) then --first 1/2 cycle of clocking
if(cpha = cpol) then -- both equal 0 or 1
spi_sclk <= '0';
else
spi_sclk <= '1';
end if;
data_clk <= '0';
elsif(count >= unsigned(clk_div)) then --second 1/2 cycle of clocking
if(cpha = cpol) then
spi_sclk <= '1';
else
spi_sclk <= '0';
end if;

327

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