CXP83408/83412/83416

CXP83409/83413/83417
CMOS 8-bit Single Chip Microcomputer

Description
CXP83408/83412/83416
The CXP83408/83412/83416 and CXP83409/83413/
80 pin QFP (Plastic) 80 pin LQFP (Plastic)
83417 are a CMOS 8-bit microcomputer which consists of
A/D converter, serial interface, timer/counter, time
base timer, 32kHz timer/counter, LCD controller/
driver, remote control receiving circuit and PWM
output, as well as basic configurations like 8-bit CPU,
ROM, RAM and I/O port. They are integrated into a
single chip.
Also CXP83408/83412/83416 and CXP83409/83413/ CXP83409/83413/83417
83417 sleep/ stop function which enables to lower power 80 pin QFP (Plastic)
consumption.

Features
• A wide instruction set (213 instructions) which
covers various types of data
– 16-bit arithmetic/multiplication and division/
Boolean bit operation instructions
• Minimum instruction cycle 400ns at 10MHz operation (4.5 to 5.5V)
122µs at 32kHz operation (2.7 to 5.5V)
• Incorporated ROM capacity 8K bytes (CXP83408, 83409)
12K bytes (CXP83412, 83413)
16K bytes (CXP83416, 83417)
• Incorporated RAM capacity 448 bytes (LCD display data area included)
• Peripheral functions
– A/D converter 8 bits, 8 channels, successive approximation system
(Conversion time: 32µs/10MHz)
– Serial interface Incorporated 8-bit and 8-stage FIFO
(1 to 8 bytes auto transfer), 1 circuit 2 channels
– Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter
– LCD controller/driver Maximum 128 segments display possible (During 1/4 duty)
4 common outputs, 32 segment outputs
Display method: Static, 1/2, 1/3 and 1/4 duty
Bias method: 1/2 and 1/3 bias
– Remote control receiving circuit 8-bit pulse measurement counter, 6-stage FIFO
– PWM output 14 bits 1 channel, 8 bits 1 channel
• Interruption 12 factors, 12 vectors, multi-interruption possible
• Standby mode SLEEP/STOP
• Package 80-pin plastic QFP/LQFP
• Piggyback/evaluator CXP83400 (CXP83408, 83412, 83416)
CXP83401 (CXP83409, 83413, 83417)

Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93Z15C72-PS
 Block Diagram

TEX
VDD

XTAL

TX
Vss

RST

EXTAL

INT1
INT0
NMI/INT3
INT2
2

AN0 to AN7 8 A/D CONVERTER 8

CLOCK GENERATOR/ PA0 to PA7
SPC700
PORT A

CPU CORE SYSTEM CONTROL

SEG0 to SEG31 32

LCD 8 PB0 to PB7

COM0 to COM3 4
PORT B

CONTROLLER/
VL DRIVER
VLC1
VLC2 8 PC0 to PC7
ROM RAM
PORT C

VLC3
8K/12K/16K BYTES 448 BYTES
PWM0 14BIT PWM GENERATOR

INTERRUPT CONTROLLER

–2–
PWM1 8BIT PWM GENERATOR
8 PD0 to PD7
PORT D

RMC REMOCON FIFO

CS0 5 PE0 to PE4

SI0 2 PRESCALER/ 32kHz
2 PE5 to PE6
PORT E

SO0 TIME BASE TIMER TIMER/COUNTER

SERIAL
SCK0 INTERFACE FIFO
CS1 UNIT 0
SI1 8 PF0 to PF7
PORT F

SO1
SCK1
EC 8BIT TIMER/COUNTER 0
1 PH0
TO 8BIT TIMER 1
PORT H

ADJ 2
CXP83408/83412/83416, CXP83409/83413/83417
 CXP83408/83412/83416, CXP83409/83413/83417

Pin Assignment (Top View) CXP83408/83412/83416 (QFP package)

PE0/INT0/EC

PD7/SEG23
PF5/SEG29
PF4/SEG28
PF3/SEG27
PF2/SEG26
PF1/SEG25
PF0/SEG24
PF7/SEG31
PF6/SEG30
PE2/INT2
PE1/INT1

TEX

VDD
NC

TX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

PE3/INT3/NMI 1 64 PD6/SEG22
PE4/RMC 2 63 PD5/SEG21
PE5/PWM0 3 62 PD4/SEG20
PE6/TO/ADJ 4 61 PD3/SEG19
PB0/CS1 5 60 PD2/SEG18
PB1/CS0 6 59 PD1/SEG17
PB2/SCK0 7 58 PD0/SEG16
PB3/SI0 8 57 SEG15
PB4/SO0 9 56 SEG14
PB5/SCK1 10 55 SEG13
PB6/SI1 11 54 SEG12
PB7/SO1 12 53 SEG11
PC0 13 52 SEG10
PC1 14 51 SEG9
PC2 15 50 SEG8
PC3 16 49 SEG7
PC4 17 48 SEG6
PC5 18 47 SEG5
PC6 19 46 SEG4
PC7 20 45 SEG3
PH0/PWM1 21 44 SEG2
PA0/AN0 22 43 SEG1
PA1/AN1 23 42 SEG0
PA2/AN2 24 41 COM3

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VSS
VL
VLC3
VLC2
VLC1
COM0
COM1
COM2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
RST
EXTAL
XTAL

Note) NC (Pin 75) is always connected to VDD.

–3–
 CXP83408/83412/83416, CXP83409/83413/83417

Pin Assignment (Top View) CXP83408/83412/83416 (LQFP package)

PE3/INT3/NMI

PE0/INT0/EC

PD7/SEG23
PD6/SEG22
PD5/SEG21
PF5/SEG29
PF4/SEG28
PF3/SEG27
PF2/SEG26
PF1/SEG25
PF0/SEG24
PF7/SEG31
PF6/SEG30
PE4/RMC

PE2/INT2
PE1/INT1

TEX

VDD
NC

TX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

PE5/PWM0 1 60 PD4/SEG20

PE6/TO/ADJ 2 59 PD3/SEG19

PB0/CS1 3 58 PD2/SEG18

PB1/CS0 4 57 PD1/SEG17

PB2/SCK0 5 56 PD0/SEG16

PB3/SI0 6 55 SEG15

PB4/SO0 7 54 SEG14

PB5/SCK1 8 53 SEG13

PB6/SI1 9 52 SEG12

PB7/SO1 10 51 SEG11

PC0 11 50 SEG10

PC1 12 49 SEG9

PC2 13 48 SEG8

PC3 14 47 SEG7

PC4 15 46 SEG6

PC5 16 45 SEG5

PC6 17 44 SEG4

PC7 18 43 SEG3

PH0/PWM1 19 42 SEG2

PA0/AN0 20 41 SEG1

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SEG0
RST
EXTAL
XTAL
VSS
VL
VLC3
VLC2
VLC1
COM0
COM1
COM2
COM3
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7

Note) NC (Pin 73) is always connected to VDD.

–4–
 CXP83408/83412/83416, CXP83409/83413/83417

Pin Assignment (Top View) CXP83409/83413/83417 (QFP package)

PE3/INT3/NMI

PE0/INT0/EC

PD7/SEG23
PD6/SEG22
PD5/SEG21
PF5/SEG29
PF4/SEG28
PF3/SEG27
PF2/SEG26
PF1/SEG25
PF0/SEG24
PF7/SEG31
PF6/SEG30
PE4/RMC

PE2/INT2
PE1/INT1

TEX

VDD
NC

TX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

PE5/PWM0 1 60 PD4/SEG20

PE6/TO/ADJ 2 59 PD3/SEG19

PB0/CS1 3 58 PD2/SEG18

PB1/CS0 4 57 PD1/SEG17

PB2/SCK0 5 56 PD0/SEG16

PB3/SI0 6 55 SEG15

PB4/SO0 7 54 SEG14

PB5/SCK1 8 53 SEG13

PB6/SI1 9 52 SEG12

PB7/SO1 10 51 SEG11

PC0 11 50 SEG10

PC1 12 49 SEG9

PC2 13 48 SEG8

PC3 14 47 SEG7

PC4 15 46 SEG6

PC5 16 45 SEG5

PC6 17 44 SEG4

PC7 18 43 SEG3

PH0/PWM1 19 42 SEG2

PA0/AN0 20 41 SEG1

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PA7/AN7
RST
EXTAL
XTAL
VSS
VL
VLC3
VLC2
VLC1
COM0
COM1
COM2
COM3
SEG0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6

Note) NC (Pin 73) is always connected to VDD.

–5–
 CXP83408/83412/83416, CXP83409/83413/83417

Pin Description

Symbol I/O Functions

(Port A)
8-bit I/O port. I/O can be
set in a unit of single bits.
PA0/AN0
Incorporation of pull-up Analog inputs to A/D converter.
to I/O/Analog input
resistor can be set (8 pins)
PA7/AN7
through the software in a
unit of 4 bits.
(8 pins)
PB0/CS1 I/O/Input Chip select input for serial interface (CH1).
PB1/CS0 I/O/Input (Port B) Chip select input for serial interface (CH0).
PB2/SCK0 I/O/I/O 8-bit I/O port. I/O can be Serial clock I/O (CH0).
set in a unit of single bits.
PB3/SI0 I/O/Input Incorporation of pull-up Serial data input (CH0).
PB4/SO0 I/O/Output resistor can be set Serial data output (CH0).
through the software in a
PB5/SCK1 I/O/I/O unit of 4 bits. Serial clock I/O (CH1).
PB6/SI1 I/O/Input (8 pins) Serial data input (CH1).
PB7/SO1 I/O/Output Serial data output (CH1).
(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving
PC0 to PC7 I/O 12mA sync current. Incorporation of pull-up resistor can be set through
the software in a unit of 4 bits.
(8 pins)
External event inputs
PE0/INT0/EC Input/Input/Input for timer/counter.

PE1/INT1 Input/Input External interruption

request input. (4 pins)
PE2/INT2 Input/Input (Port E)
7-bit port. Lower 5 bits Non-maskable intrruption
PE3/INT3/NMI Input/Input/Input are for inputs; upper request input.
2 bits are for outputs.
PE4/RMC Input/Input Remote control receiving circuit input.
(7 pins)
PE5/PWM0 Output/Output 14-bit PWM output.
Rectangular wave output for 8-bit timer/
Output/Output/
PE6/TO/ADJ counter and 32kHz oscillation frequency
Output divider output.
(Port H)
1-bit I/O port. Incorporation
PH0/PWM1 I/O/Output of pull-up resistor can be 8-bit PWM output.
set through the software.
(1 pin)

–6–
 CXP83408/83412/83416, CXP83409/83413/83417

Symbol I/O Functions

PD0/SEG16 (Port D)
to Output/Output 8-bit output port.
PD7/SEG23 (8 pins) LCD segment signal output.
PF0/SEG24 (Port F) (16 pins)
to Output/Output 8-bit output port.
PF7/SEG31 (8 pins)
SEG0 to SEG15 Output LCD segment signal output.
COM0 to COM3 Output LCD common signal output.
VLC1 to VLC3 LCD bias power supply.
Control pin to cutt off the current flowing to external LCD bias resistor
VL Output
during standby.
EXTAL Input Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
XTAL Output input to XTAL.

TEX Input Crystal connectors for 32kHz timer/counter clock generation circuit.
For usage as event counter, connect clock oscillation source to TEX,
TX Output and leave TX open.
RST Input Low-level active, system reset.
NC NC. Under normal operating conditions, connect to VDD.
VDD Positive power supply.
Vss GND.

–7–
 CXP83408/83412/83416, CXP83409/83413/83417

I/O Circuit Format for Pins

Pin Circuit format When reset
Port A
∗
Pull-up resistor
“0” when reset
Port A data

PA0/AN0 Port A direction IP Input protection

to “0” when reset circuit
PA7/AN7 Hi-Z
Data bus

RD (Port A)

Port A input selection

Input multiplexer
“0” when reset
A/D converter
∗ Pull-up resistors
8 pins
approx. 100kΩ

Port B
∗
Pull-up resistor
“0” when reset

Port B data
PB0/CS1
PB1/CS0
PB3/SI0 Port B direction IP
Hi-Z
PB6/SI1 “0” when reset
Schmitt input
Data bus

RD (Port B)
CS1
CS0
SI0
∗ Pull-up transistors
SI1
4 pins approx. 100kΩ

Port B

∗
Pull-up resistor
“0” when reset
SCK OUT
Output enable
Port B output
PB2/SCK0 selection
“0” when reset
PB5/SCK1
Port B data Hi-Z
IP
Port B direction
“0” when reset
Schmitt input
Data bus

RD (Port B)

SCK in ∗ Pull-up transistors

2 pins approx. 100kΩ

–8–
 CXP83408/83412/83416, CXP83409/83413/83417

Pin Circuit format When reset

Port B
∗
Pull-up resistor
“0” when reset
SO
Output enable
Port B output
selection
PB4/SO0 “0” when reset
PB7/SO1 Port B data Hi-Z
IP
Port B direction
“0” when reset

Data bus

RD (Port B)
∗ Pull-up transistors
2 pins approx. 100kΩ

Port C
∗2
Pull-up resistor
“0” when reset
Port C data

PC0 to PC7
∗1 Hi-Z
Port C direction IP
“0” when reset

Data bus

RD (Port C) ∗1 Large current 12mA

∗2 Pull-up transistors
8 pins approx. 100kΩ

PE0/INT0/EC Port E
INT0/EC
PE1/INT1 Schmitt input
INT1
PE2/INT2 INT2
IP INT3/NMI
PE3/INT3/NMI RMC Hi-Z
PE4/RMC Data bus

5 pins RD (Port E)

–9–
 CXP83408/83412/83416, CXP83409/83413/83417

Pin Circuit format When reset

Port E
PWM0

Port E output selection

PE5/PWM0 “0” when reset

High level
Port E data
“1” when reset
Data bus

1 pin RD (Port E)

Port E

∗1
Internal reset signal
Port E data
“1” when reset
MPX
TO High level
PE6/TO/ADJ ∗2

( )
ADJ16K with pull-up
ADJ2K transistor ON
Port E output selection (upper) resistor when
Port E output selection (lower) reset
∗1 Pull-up transistors approx. 150kΩ.
TO Output enable ∗2 ADJ signals are frequency divider outputs
for 32kHz oscillation frequency adjustment.
ADJ2K provides usage as buzzer output.

1 pin

AAAA
Port H

AAAA
Pull-up resistor ∗

“0” when reset

AAAA AA
PWM1

Port H output selection

AAAA AAAA
PH0/PWM1 “0” when reset
Hi-Z

AAAA
Port H data
IP

Port H direction
“0” when reset

Data bus

RD (Port H) ∗ Pull-up transistors

1 pin approx. 100kΩ

– 10 –
 CXP83408/83412/83416, CXP83409/83413/83417

Pin Circuit format When reset

Port D
Port F
Port data

PD0 to PD7 PD7 to PD4 by a bit unit

PF0 to PF7 PD3 to PD0 by 4-bit unit Port/segment output Segment
selection
PF7 to PF0 output
“0” when reset (VDD level)

Segment
Segment data
driver

24 pins

Segment

VCH
SEG0 to SEG15
VDD level

VCL
16 pins

Common

VDD

VLC1
COM0 to COM3
VDD level

VLC2

VLC3
4 pins

VL
LCD control
(DSP bit)
Hi-Z
1 pin “0” when reset

– 11 –
 CXP83408/83412/83416, CXP83409/83413/83417

Pin Circuit format When reset

• Diagram shows circuit

EXTAL composition during oscillation.
EXTAL IP IP
XTAL
• Feedback resistor is removed Oscillation
during stop, and XTAL
becomes “High” level.
XTAL
2 pins

• Diagram shows circuit

composition during oscillation.
TEX TEX IP IP
TX
Oscillation
• When the operation of the oscillation circuit is
TX stopped by the software, the feedback
resistor is removed and TEX and TX become
2 pins “Low” level and “High” level respectively.

AA Pull-up resistor

AA
RST Mask option

OP Low level
IP

Schmitt input
1 pin

– 12 –
 CXP83408/83412/83416, CXP83409/83413/83417

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Rating Unit Remarks

Supply voltage VDD –0.3 to +7.0 V

–0.3 to +7.0∗1
VLC1, VLC2,
LCD bias voltage V
VLC3
Input voltage VIN –0.3 to +7.0∗1 V
Output voltage VOUT –0.3 to +7.0∗1 V
High level output current IOH –5 mA Output (value per pin)
High level total output current ∑IOH –50 mA Total for all output pins
All pins excluding large current output
IOL 15 mA
Low level output current (value per pin)
IOLC 20 mA Large current outputs (value per pin∗2)
Low level total output current ∑IOL 100 mA Total for all output pins
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +150 °C
600 mW QFP-80P-L01
Allowable power dissipation PD 380 mW LQFP-80P-L01
380 mW QFP-80P-L03

∗1 VIN and VOUT must not exceed VDD + 0.3V.

∗2 The large current drive transistor is the N-ch transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.

– 13 –
 CXP83408/83412/83416, CXP83409/83413/83417

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks

During 1/2 and 1/4 frequency division
4.5 5.5
operating modes guaranteed operation range
During 1/16 frequency division operating mode
Supply voltage VDD 3.5 5.5 V or sleep mode quaranteed operation range
2.7 5.5 Guaranteed operation range with TEX clock
2.5 5.5 Guaranteed data hold range during STOP
VLC1
LCD bias voltage VLC2 Vss VDD V LCD power supply range∗4
VLC3
VIH 0.7VDD VDD V ∗1

High level input voltage VIHS 0.8VDD VDD V Hysteresis input∗2

VIHEX VDD – 0.4 VDD + 0.3 V EXTAL∗3
VIL 0 0.3VDD V ∗1

Low level input voltage VILS 0 0.2VDD V Hysteresis input∗2

VILEX –0.3 0.4 V EXTAL∗3
Operating temperature Topr –20 +75 °C
∗1 Value for each pin of normal input ports (PA, PB4, PB7, PC and PH0).
∗2 Value of the following pins: RST, CS0, CS1, SI0, SI1, SCK0, SCK1, EC/INT0, INT1, INT2, NMI/INT3, and RMC.
∗3 Specifies only during external clock input.
∗4 Optimal values are determined by LCD used.

– 14 –
 CXP83408/83412/83416, CXP83409/83413/83417

Electrical Characteristics
DC Characteristics (Ta = –20 to +75°C, Vss = 0V reference)
Item Symbol Pins Conditions Min. Typ. Max. Unit

High level PA, PB, VDD = 4.5V, IOH = –0.5mA 4.0 V

VOH
output current PC, PD∗1, VDD = 4.5V, IOH = –1.2mA 3.5 V
PE5, PE6,
PF, PH0, VDD = 4.5V, IOL = 1.8mA 0.4 V
Low level VL (VoL only)
output current VOL VDD = 4.5V, IOL = 3.6mA 0.6 V
PC VDD = 4.5V, IOL = 12.0mA 1.5 V
IIHE VDD = 5.5V, VIH = 5.5V 0.5 40 V
EXTAL
IILE VDD = 5.5V, VIL = 0.4V –0.5 –40 µA
IIHT VDD = 5.5V, VIH = 5.5V 0.1 10 µA
TEX
Input current IILT –0.1 –10 µA
RST∗2
VDD = 5.5V,
IILR –1.5 –400 mA
VIL = 0.4V
IIL
PA to PC∗3, –45 µA
IIH PH∗3, VDD = 4.5V, VIH = 4.0V –2.78 µA
PE0 to PE4,
I/O leakage
RST∗2
VDD = 5.5V,
IIZ ±10 µA
current VI = 0, 5.5V
Common COM0
output RCOM to VDD = 5V, 3 5 kΩ
impedance COM3 VLC1 = 3.75V
Segment SEG0 to SEG15, VLC2 = 2.5V
output RSEG SEG16 to VLC3 = 1.25V 5 15 kΩ
impedance SEG31 ∗ 1

High-speed mode operation

(1/2 frequency divider clock)
IDD1 18 40 mA
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
IDD2 35 100 µA
(C1 = C2 = 47pF)

Supply SLEEP mode

VDD
current∗4 IDDS1 VDD = 5.5V, 10MHz crystal oscillation 1.1 8 mA
(C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal oscillation
IDDS2 9 30 µA
(C1 = C2 = 47pF)
STOP mode
IDDS3 VDD = 5.5V termination of 10MHz 10 µA
and 32kHz crystal oscillation

– 15 –
 CXP83408/83412/83416, CXP83409/83413/83417

Item Symbol Pins Conditions Min. Typ. Max. Unit

PA to PC,
Clock 1MHz
PE1 to PE4,
Input capacity CIN 0V for all pins excluding 10 20 pF
EXTAL, TEX,
measured pins
RST

∗1 Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24, PF7/SEG31, PD and PF are the case when the
common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output.
∗2 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
∗3 PA to PC, and PH0 specify the input current when pull-up resistor has been selected; leakage current when
no resistor has been selected. (PE0 to PE4 specify the leakage current.)
∗4 When all output pins are left open.

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 CXP83408/83412/83416, CXP83409/83413/83417

AC Characteristics
(1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pin Conditions Min. Typ. Max. Unit
XTAL
System clock frequency fC Fig. 1, Fig. 2 1 10 MHz
EXTAL
System clock input tXL, Fig. 1, Fig. 2
EXTAL 37.5 ns
pulse width tXH External clock drive
System clock input tCR, Fig. 1, Fig. 2
EXTAL 200 ns
rise and fall time tCF External clock drive
Event count input clock tEH,
pulse width tEL EC Fig. 3 tsys + 50∗1 ns

Event count input clock tER, EC Fig. 3 20 ms

rise and fall time tEF
VDD = 2.7 to 5.5V
TEX
System clock frequency fC Fig. 2 (32kHz clock 32.768 kHz
TX
applied condition)
Event count input clock tTL, TEX Fig. 3 10 µs
input pulse width tTH
Event count input clock tTR, TEX Fig. 3 20 ms
rise and fall time tTF
∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control registor (CLC: 00FEH).
tsys (ns) = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)

Fig. 1. Clock timing 1/fc

VDD – 0.4V
EXTAL
0.4V

tXH tCF tXL tCR

Fig. 2. Clock applied conditions

AAAA AAAA AAAA

Crystal oscillation 32kHz clock applied condition

AAAA AAAA AAAA

Ceramic oscillation External clock Crystal oscillation

AAAA AAAAAAAA
EXTAL XTAL EXTAL XTAL TEX TX

C1 C2 74HC04 C1 C2

Fig. 3. Event count clock timing

TEX 0.8VDD
EC
0.2VDD

tEH tEF tEL tER

tTH tTF tTL tTR

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 CXP83408/83412/83416, CXP83409/83413/83417

(2) Serial transfer (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pin Conditions Min. Max. Unit
CS0 ↓ → SCK0 (CS1 ↓ → SCK1) tDCSK SCK0 Chip select transfer mode tsys + 200 ns
delay time (SCK1) (SCK0 (SCK1) = output mode)
CS0 ↑ → SCK0 (CS1 ↑ → SCK1) tDCSKF SCK0 Chip select transfer mode tsys + 200 ns
floating delay time (SCK1) (SCK0 (SCK1) = output mode)
CS0 ↓ → SO0 (CS1 ↓ → SO1) tDCSO SO0 tsys + 200 ns
Chip select transfer mode
delay time (SO1)
CS0 ↑ → SO0 (CS1 ↑ → SO1) tDCSOF SO0 tsys + 200 ns
Chip select transfer mode
floating delay time (SO1)

CS0 (CS1) high level width tWHCS CS0 Chip select transfer mode tsys + 200 ns
(CS1)
SCK0 Input mode 2tsys + 200 ns
SCK0 (SCK1) cycle time tKCY (SCK1) Output mode 16000/fc ns

SCK0 (SCK1) tKH SCK0 Input mode tsys + 100 ns

high and low level widths tKL (SCK1) Output mode 8000/fc – 50 ns

SI0 (SI1) input setup time SI0 SCK0 (SCK1) input mode 100 ns
(for SCK0↑ (SCK1↑) ) tSIK (SI1) SCK0 (SCK1) output mode 200 ns

SI0 (SI1) input hold time SI0 SCK0 (SCK1) input mode tsys + 200 ns
(for SCK0↑ (SCK1↑) ) tKSI (SI1) SCK0 (SCK1) output mode 100 ns

SCK0 ↓ → SO0 (SCK1 ↓ → SO1) SO0 SCK0 (SCK1) input mode tsys + 200 ns
delay time tKSO (SO1) SCK0 (SCK1) output mode 100 ns

Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEH).
tsys (ns) = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.

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 CXP83408/83412/83416, CXP83409/83413/83417

Fig. 4. Serial transfer CH0 timing

tWHCS

CS0 0.8VDD
(CS1)

0.2VDD

tKCY

tDCSK tDCSKF
tKL tKH

0.8VDD 0.8VDD

SCK0
(SCK1)
0.2VDD

tSIK tKSI

0.8VDD
SI0 Input
(SI1) data
0.2VDD

tDCSO tKSO tDCSOF

0.8VDD
SO0
(SO1) Output data
0.2VDD

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 CXP83408/83412/83416, CXP83409/83413/83417

(3) A/D converter characteristics

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = 0V reference)

Item Symbol Pin Conditions Min. Typ. Max. Unit

Resolution 8 Bits
Linearity error ±3 LSB
Ta = 25°C
Zero transition voltage VZT∗1 –10 10 70 mV
VDD = 5.0V
VSS = 0V
VFT∗2
Full-scale transition
4910 4970 5030 mV
voltage
Conversion time tCONV 160/fADC∗3 µs
Sampling time tSAMP 12/fADC∗3 µs
Analog input voltage VIAN AN0 to AN7 0 VDD + 0.3 V

Fig. 5. Definition of A/D converter terms

FFH
FEH ∗1 VZT: Value atwhich the digital conversion value changes
Digital conversion value

from 00H to 01H and vice versa.

∗2 VFT: Value at which the digital conversion value changes
from FEH to FFH and vice versa.
∗3 fADC indicates the below values due to the contents of bit 6
(CK3) of the A/D control registor (ADC: 00F9H) and bit 7
Linearity error (PCK1) and bit 6 (PCK0) of the clock control resistor (CLC:
00FEH).
01H
00H CKS
0 (φ/2 selection) 0 (φ selection)
VZT VFT PCK1, PCK0
Analog input
00 (φ = fEX/2) fADC = fc/2 fADC = fc
01 (φ = fEX/4) fADC = fc/4 fADC = fc/2
11 (φ = fEX/16) fADC = fc/16 fADC = fc/8

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 CXP83408/83412/83416, CXP83409/83413/83417

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Conditions Min. Max. Unit

INT0
External interruption tIH INT1
1 µs
high and low level widths tIL INT2
NMI/INT3
Reset input low level width tRSL RST 32/fc µs

Fig 6. Interruption input timing

tIH tIL

0.8VDD

INT0 0.2VDD
INT1
INT2 tIL tIH
NMI/INT3
(NMI is specified only for
the falling edge)

Fig. 7. RST input timing

tRSL

RST
0.2VDD

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 CXP83408/83412/83416, CXP83409/83413/83417

Appendix

Fig. 8. SPC700 Series recommended oscillation circuit

AAAA
(i) Main clock

AAAA
(ii) Main clock

AAAAA
(iii) Sub clock

AAAA AAAA AAAAA

AAAA AAAA AAAAA
EXTAL XTAL EXTAL XTAL EXTAL
TEX XTAL
TX

Rd Rd Rd

C1 C2 C1 C2
C 1 C2

Circuit
Manufacturer Model fc (MHz) C1 (pF) C2 (pF) Rd (Ω)
example
CSA4.19MG 4.19
CSA8.00MG 8.00 (i)
MURATA CSA10.0MT 10.00
MFG 30 30 0
CO., LTD. CST4.19MGW∗1 4.19
CST8.00MTW∗1 8.00 (ii)
CST10.00MTW∗1 10.00
4.19
RIVER 2.2k
ELETEC HC-49/U03 8.00 15 15
CO., LTD.
10.00 470
(i)
4.19 22 22 560
KINSEKI
HC-49/U (-S) 8.00
LTD. 18 18 0
10.00
Models with an asterisk (∗1) have the built-in ground capacitance (C1, C2).

Mask Option Table

Item Content
Reset pin pull-up resistor Non-existent Existent

Package Table
Product name Package
CXP83408/83412/83416 80-pin plastic QFP/LQFP
CXP83409/83413/83417 80-pin plastic QFP (0.65mm pitch)

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 CXP83408/83412/83416, CXP83409/83413/83417

Characteristic Curves

IDD vs. VDD IDD vs. fc

(fc = 10MHz, Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, typical)

20.0 1/2 dividing mode

10.0
SLEEP mode
20
5.0
IDD – Supply current [mA]

IDD – Supply current [mA]

1/2 dividing mode

1.0 15

0.5

32kHz mode
(instruction) 10
0.1
(100µA)
32kHz
0.05 SLEEP mode
(50µA)
5

0.01 SLEEP mode

(10µA)

2 3 4 5 6 7 0 5 10 16
VDD – Supply voltage [V] fc – System clock [MHz]

Package Outline Unit : mm

CXP83408/83412/83416
80PIN QFP (PLASTIC)

23.9 ± 0.4
+ 0.1
+ 0.4 0.15 – 0.05
20.0 – 0.1
0.15
64 41

65 40
17.9 ± 0.4
+ 0.4
14.0 – 0.1

16.3

80 25 + 0.2
0.1 – 0.05

1 24
0.8 ± 0.2

+ 0.15 + 0.35
0.8 0.35 – 0.1 2.75 – 0.15
0.12 M

0° to 10°

DETAIL A PACKAGE STRUCTURE

PACKAGE MATERIAL EPOXY RESIN

SONY CODE QFP-80P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE ∗QFP080-P-1420-A LEAD MATERIAL COPPER / 42 ALLOY

JEDEC CODE PACKAGE WEIGHT 1.6g

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 CXP83408/83412/83416, CXP83409/83413/83417

CXP83408/83412/83416
80PIN LQFP (PLASTIC)

14.0 ± 0.2
∗ 12.0 ± 0.1

60 41

61 40

(13.0)
A

0.5 ± 0.2
21
80
(0.22)

1 + 0.08 20 + 0.05
0.5 ± 0.08 0.18 – 0.03 0.127 – 0.02
+ 0.2
1.5 – 0.1
0.1
0.1 ± 0.1
0.5 ± 0.2

0° to 10° NOTE: Dimension “∗” does not include mold protrusion.

DETAIL A

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY / PHENOL RESIN

SONY CODE LQFP-80P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE ∗QFP080-P-1212-A LEAD MATERIAL 42 ALLOY

JEDEC CODE PACKAGE WEIGHT 0.5g

CXP83409/83413/83417

80PIN QFP (PLASTIC)

+ 0.35
1.5 – 0.15
+ 0.1
16.0 ± 0.4 0.127 – 0.05
+ 0.4
14.0 – 0.1
0.1

60 41

61 40
(15.0)

+ 0.15
80 21 0.1 – 0.1

1 20
+ 0.15
0.5 ± 0.2

0.65 0.3 – 0.1

± 0.12 M
0° to 10°

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE QFP-80P-L03 LEAD TREATMENT SOLDER PLATING

EIAJ CODE LQFP080-P-1414 LEAD MATERIAL COPPER / 42 ALLOY

JEDEC CODE PACKAGE WEIGHT 0.6g

– 24 –