Latha Mathavan Engineering College Latha Madhavan Nagar, Kidaripatti Madurai - 625301

LATHA MATHAVAN ENGINEERING COLLEGE
Latha Madhavan Nagar,Kidaripatti
Madurai – 625301.
DEPARTMENT OF ELECTRICAL AND

ELECTRONICS ENGINEERING
EE8351 DIGITAL LOGIC CIRCUITS
II Year - III Semester

(2020 –2021 ODD)
Regulation 2017
Multiple Choice Questions & Answers
(MCQs)
PREPARED BY
N.PRIYADHARSHINI AP/EEE
DIGITAL
LOGIC
CIRCUITS
Digital Circuits Questions and Answers
BINARY NUMBERS
1. Any signed negative binary number is recognised by its ________

a) MSB
b) LSB
c) Byte
d) Nibble
Answer: a
Explanation: Any negative number is recognized by its MSB (Most Significant Bit).
If it’s 1, then ít’s negative, else if it’s 0, then positive.
2. The parameter through which 16 distinct values can be represented is known as

________
a) Bit
b) Byte
c) Word
d) Nibble
Answer: c
Explanation: It can be represented up to 16 different values with the help of a Word. Nibble is a
combination of four bits and Byte is a combination of 8 bits. It is “word” which is said to be a
collection of 16-bits on most of the systems.
3. If the decimal number is a fraction then its binary equivalent is obtained by ________
the number continuously by 2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting
Answer: b
Explanation: On multiplying the decimal number continuously by 2, the binary equivalent is
obtained by the collection of the integer part. However, if it’s an integer, then it’s binary
equivalent is determined by dividing the number by 2 and collecting the remainders.
4. The representation of octal number (532.2)8 in decimal is ________

a) (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10
Answer: a
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base
index along with the value at that index position.
(532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 = (346.25)10
5. The decimal equivalent of the binary number (1011.011)2 is ________

a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
Answer: a
Explanation: Binary to Decimal conversion is obtained by multiplying 2 to the power of base
1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2-2 + 1 * 2-3 = (11.375)10
Hence, (1011.011)2 = (11.375)10
6. An important drawback of binary system is ________

a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) It requires small string of 1’s and large string of 0’s to represent a decimal number
Answer: a
Explanation: The most vital drawback of binary system is that it requires very large string of 1’s
and 0’s to represent a decimal number. Hence, Hexadecimal systems are used by processors for
calculation purposes as it compresses the long binary strings into small parts.
7. The decimal equivalent of the octal number (645)8 is ______

a) (450)10
b) (451)10
c) (421)10
d) (501)10
Answer: c
Explanation: Octal to Decimal conversion is obtained by multiplying 8 to the power of base
The decimal equivalent of the octal number (645)8 is 6 * 82 + 4 * 81 + 5 * 80 = 6 * 64 + 4 * 8 + 5
= 384 + 32 + 5 = (421)10.
8. The largest two digit hexadecimal number is ________

a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
Answer: c
Explanation: (FE)16 is 254 in decimal system, while (FD)16 is 253. (EF)16 is 239 in decimal
system. And, (FF)16 is 255. Thus, The largest two-digit hexadecimal number is (FF)16.
9. Representation of hexadecimal number (6DE)H in decimal:

a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
Answer: a
Explanation: Hexadecimal to Decimal conversion is obtained by multiplying 16 to the power of
base index along with the value at that index position.
In hexadecimal number D & E represents 13 & 14 respectively.
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160.
10. The quantity of double word is ________
a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits
Answer: b
Explanation: One word means 16 bits, Thus, the quantity of double word is 32 bits.
VHDL Questions and Answers – RTL Simulation
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “RTL
Simulation”.
11. What does RTL in digital circuit design stand for?

a) Register transfer language
b) Register transfer logic
c) Register transfer level
d) Resistor-transistor logic
Answer: c
Explanation: RTL in digital circuit design stands for register transfer level, used in HDL.
Register transfer language is a type of intermediate representation close to assembly language.
Resistor-transistor logic is used in BJTs as switching devices. Register transfer logic is used in
state machine designs.
12. RTL is a design abstraction of what kind of circuit?

a) Asynchronous digital circuit
b) Synchronous digital circuit
c) Asynchronous sequential circuit
d) Analog circuit
Answer: b
Explanation: RTL is a design abstraction that shapes a synchronous digital circuit with
reference to digital signals that flow between hardware registers and the logical operations are
carried out on those signals.
13. RTL is used in HDL to create what level of representations in the circuit?
a) High-level
b) Low-level
c) Mid-level
d) Same level
Answer: a
Explanation: RTL is used in HDL for creating HIGH-LEVEL of representations in the circuit,
from which lower-level of representations can be derived. Designing at the RTL level is a
representative practice in modern digital design.
14. RTL mainly focuses on describing the flow of signals between ________
a) Logic gates
b) Registers
c) Clock
d) Inverter
Answer: b
Explanation: RTL focuses on describing the flow of signals between registers. There is a
regularly repeated path of logic from the output of the register to its input, that is the reason it is
called register transfer level.
15. Which flip-flop is usually used in the implementation of the registers?

a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) J-K flip-flop
Answer: a
Explanation: Registers are generally implemented as D flip-flops because connection for the
shift register is the simplest with D flip-flop, as there is a single data input in it. The flip-flop also
stores the output of whatever logic is applied to its data input as long as the clock input is high.
16. Which of the following tool performs logic optimization?

a) Simulation tool
b) Synthesis tool
c) Routing tool
d) RTL compiler
Answer: b
Explanation: Synthesis tool performs logic optimization in RTL by converting high-level
description of the design circuit into an optimized gate level representation by the use of basic
logic gates like and, or, nor, etc.
17. Hold time is the time needed for the data to ________ after the edge of the clock is triggered.
a) Decrease
b) Increase
c) Remain constant
d) Negate
Answer: c
Explanation: Hold time is the time needed for the data to remain constant after the edge of the
clock is triggered. Data must remain stable, if the incorrect data is latched then, it leads to hold
violation.
18. Simulator enters in which phase after the initialization phase?

a) Execution phase
b) Compilation phase
c) Elaboration phase
d) Simulation phase
Answer: a
Explanation: Simulator enters in execution phase after the initialization phase, the actual
simulation of the behaviour of the design takes place in the execution phase. Each simulation
process in the active queue is taken out and executed until it suspends.
19. Conversion of RTL description to Boolean _______ description is a function of the
translation procedure in the synthesis process.
a) Optimized
b) Unoptimized
c) Translation
d) PLA format
Answer: b
Explanation: Conversion of RTL description to Boolean unoptimized description is a function
of translation procedure in the synthesis process. The logic synthesis tool converts the
description to an unoptimized, intermediate, internal representation.AS
Digital Circuits Questions and Answers – Register-Transistor Logic(RTL)
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers

(MCQs) focuses on “Register-Transistor Logic(RTL)”.
20. All input of NOR as low produces result as __________

a) Low
b) Mid
c) High
d) Floating
Answer: c
Explanation: All input of NOR as low produces the result as high, whereas, rest all conditions
produce output as low.
21. In RTL NOR gate, the output is at logic 1 only when all the inputs are at __________
a) logic 0
b) logic 1
c) +10V
d) Floating
Answer: a
Explanation: RTL NOR gate behaves as NOR gate and the output of NOR gate will be 1 only
when all the inputs are at logic 0 and in rest conditions of the input, the output is 0.
22. Resistor–transistor logic (RTL) is a class of digital circuits built using _______ as the
input network and _______ as switching devices.
a) Resistors, bipolar junction transistors (BJTs)
b) Bipolar junction transistors (BJTs), Resistors
c) Capacitors, resistors
d) Resistors, capacitors
Answer: a
Explanation: Resistor–transistor logic (RTL) is a class of digital circuits built using resistors as
the input network and bipolar junction transistors (BJTs) as switching devices.
23. RTL consists of a common emitter stage with a _______ connected between the base
and the input voltage source.
a) collector
b) base resistor
c) capacitor
d) inductor
Answer: b
Explanation: RTL consist of a common emitter stage with a base resistor connected between the
base and the input voltage source. The role of base resistor is to expand the negligible transistor
input voltage range (about 0.7 V) to the logical “1” level (about 3.5 V) by converting the input
voltage into a current. Thus, base resistor plays a major role in biasing of the transistor.
24. The role of the _______ is to convert the collector current into a voltage in RTL.
a) Collector resistor
b) Base resistor
c) Capacitor
d) Inductor
Answer: a
Explanation: The role of the collector resistor is to convert the collector current into a voltage;
its resistance is chosen high enough to saturate the transistor and low enough to obtain low
output resistance. Base Resistor is to provide the necessary biasing to the base of the transistor in
order to activate it.
25. The limitations of the one transistor RTL NOR gate are overcome by __________
a) Two-transistor RTL implementation
b) Three-transistor RTL implementation
c) Multi-transistor RTL implementation
d) Four-transistor RTL implementation
Answer: c
Explanation: The limitations of the one transistor RTL NOR gate are overcome by the use of
multi transistor RTL. It consists of a set of parallel connected transistor switches driven by the
logic inputs.
26. The primary advantage of RTL technology was that __________

a) It results as low power dissipation
b) It uses a minimum number of resistors
c) It uses a minimum number of transistors
d) It operates swiftly
Answer: c
Explanation: The primary advantage of RTL technology was that it uses a minimum number of
transistors. It consists of registers in large amount and it results in as high power dissipation. The
resistors act as the input network and the transistors performs the switching operation.
27. The disadvantage of RTL is that __________

a) It uses a maximum number of resistors
b) It results in high power dissipation
c) High noise creation
d) It uses minimum number of transistors
Answer: b
Explanation: The disadvantage of RTL is its high power dissipation when the transistor is
switched on by current flowing in the collector and base resistor. This requires that more current
be supplied to and heat be removed from RTL circuits. In contrast, TTL circuits with “totem-
pole” output stage minimize both of these requirements.
28. TTL circuits with “totem-pole” output stage minimize __________
a) The power dissipation in RTL
b) The time consumption in RTL
c) The speed of transferring rate in RTL
d) Propagation delay in RTL
Answer: a
Explanation: TTL circuits with “totem-pole” output stage minimize the power dissipation and
heating effect in RTL.
29. The minimum number of transistors can be used by 2 input AND gate is __________
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: The minimum number of transistors can be used by 2 input AND gate is 2 and
maximum up to 3.
Digital Circuits Questions and Answers – Diode-Transistor Logic(DTL)
This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Diode-Transistor Logic(DTL)”.
30. Diode–transistor logic (DTL) is the direct ancestor of _____________

a) Register-transistor logic
b) Transistor–transistor logic
c) High threshold logic
d) Emitter Coupled Logic
Answer: b
Explanation: Diode–transistor logic (DTL) is a class of digital circuits that is the direct ancestor
of transistor–transistor logic. To overcome the shortcomings of DTL, TTL came into existence.
31. In DTL logic gating function is performed by ___________
a) Diode
b) Transistor
c) Inductor
d) Capacitor
Answer: a
Explanation: Diode serves as the input network and the switching operation is performed by the
transistor.
32. In DTL amplifying function is performed by ___________

a) Diode
b) Transistor
c) Inductor
d) Capacitor
Answer: b
Explanation: The amplifying and switching function is performed by a transistor and the diode
acts an input network in DTL.
33. How many stages a DTL consist of?

a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: The DTL circuit shown in the picture consists of three stages: an input diode logic
stage, an intermediate level shifting stage and an output common-emitter amplifier stage.
34. The full form of CTDL is ___________

a) Complemented transistor diode logic
b) Complemented transistor direct logic
c) Complementary transistor diode logic
d) Complementary transistor direct logic
Answer: a
Explanation: The full form of CTDL is Complemented transistor diode logic.
35. The DTL propagation delay is relatively ___________

a) Large
b) Small
c) Moderate
d) Negligible
Answer: a
Explanation: Propagation delay refers to the time taken by the output to change it’s state when
the input is altered. When the transistor goes into saturation from all inputs being high charge is
stored in the base region. When it comes out of saturation (one input goes low) this charge has to
be removed and will dominate the propagation time which results as a large propagation delay.
Thus, it has small clock frequency.
36. The way to speed up DTL is to add an across intermediate resister is ___________
a) Small “speed-up” capacitor
b) Large “speed-up” capacitor
c) Small “speed-up” transistor
d) Large ” speed-up” transistor
Answer: a
Explanation: One way to speed up DTL is to add a small “speed-up” capacitor across
intermediate resister. The capacitor helps to turn off the transistor by removing the stored base
charge; the capacitor also helps to turn on the transistor by increasing the initial base drive.
37. The process to avoid saturating the switching transistor is performed by ___________
a) Baker clamp
b) James R. Biard
c) Chris Brown
d) Totem-Pole
Answer: a
Explanation: Another way to speed up DTL other than adding a small “speed-up” capacitor
across intermediate resister is to avoid saturating the switching transistor which can be done with
a Baker clamp. The name Baker clamp is given at the name of Richard H. Baker, who described
it in his 1956 technical report “Maximum Efficiency Switching Circuits”.
38. A major advantage of DTL over the earlier resistor–transistor logic is the ___________
a) Increased fan out
b) Increased fan in
c) Decreased fan out
d) Decreased fan in
Answer: b
Explanation: A major advantage over the earlier resistor–transistor logic is the increased fan in.
Fan-in is the measure of the maximum number of inputs that a single gate output can accept.
39. To increase fan-out of the gate in DTL ___________

a) An additional capacitor may be used
b) An additional resister may be used
c) An additional transistor and diode may be used
d) Only an additional diode may be used
Answer: c
Explanation: To increase fan-out of the gate in DTL, an additional transistor and diode may be
used. Here, the fan out means the number of maximum input that a single gate output can feed.
40. A disadvantage of DTL is ___________
a) The input transistor to the resister
b) The input resister to the transistor
c) The increased fan-in
d) The increased fan-out
Answer: b
Explanation: A disadvantage of DTL is the input resistor to the transistor and its presence tends
to slow the circuit down. Hence limiting the speed at which the transistor is able to switch states.
Thus, the propagation delay increases.
Digital Circuits Questions and Answers – Compatibility or Interfacing
on “Compatibility or Interfacing”.
41. Compatibility refers to ____________

a) The output of a circuit should match with the input of another circuit
b) The output of a circuit should match with the input of the same circuit
c) The input of a circuit should match with the output of another circuit
d) The input of a circuit should match with the output of same circuit
Answer: a
Explanation: The output(s) of a circuit or a system should match the input(s) of another circuit
or system that has different electrical characteristics. This is referred to as compatibility.
42. The method of connecting a driving device to a loading device is known as ___________
a) Compatibility
b) Interface
c) Sourcing
d) Sinking
Answer: b
Explanation: The method of connecting a driving device to a loading device is known as
interface. The output(s) of a circuit or a system should match the input(s) of another circuit or
system that has different electrical characteristics. This is referred to as compatibility.
43. The first CML logic was introduced by General Electric in ___________
a) 1960
b) 1981
c) 1961
d) 1990
Answer: c
Explanation: CML stands for Current Mode Logic. The first CML logic was introduced by
General Electric in 1961.
44. Commercial ECL families are not nearly as popular as TTL and CMOS mainly because
they ___________
a) Produces too much noise
b) Consume too much power
c) Have high fan-in
d) Have high fan-out
Answer: b
Explanation: Commercial ECL families are not nearly as popular as TTL and CMOS mainly
because they consume too much power. CMOS consumes the least power while TTL provides
high speed.
45. The key to propagation delay in bipolar logic family is to prevent the transistors in a
gate from ___________
a) Fan-in
b) Fan-out
c) Saturation
d) Cut-off
Answer: c
Explanation: The key to propagation delay in bipolar logic family is to prevent the transistors in
a gate from saturation. In Saturation mode, the transistor is in “ON”mode, where it seems like a
short circuit between collector and emitter.
46. Schottky families prevent the saturating using ___________

a) Transistors
b) Schottky transistors
c) Diodes
d) Schottky diodes
Answer: d
Explanation: Schottky families prevent the saturating using Schottky diodes across the base-
collector junctions of transistors. In Saturation mode, the transistor is in “ON”mode, where it
seems like a short circuit between collector and emitter.
47. The basic idea of basic CML circuit came from an ___________
a) Inverter
b) Buffer
c) Transistor
d) Both inverter and buffer
Answer: d
Explanation: CML is Current Mode Logic in which data is transmitted at high speed of Mbps.
Since this circuit has both inverting and non-inverting output. So, It behaves like an
inverter/buffer.
48. The full form of MECL is ___________

a) Mono emitter coupled logic
b) Motorola emitter coupled logic
c) Motorola emitter capacitor logic
d) Both mono emitter and motorola coupled logic
Answer: b
Explanation: The full form of MECL is Motorola emitter coupled logic. ECL is a high speed
BJT. It uses BJT differential amplifier with single input and restricted current to avoid the
transistor going into saturation and thus turning off operation.
49. Motorola has offered MECL circuits in ______ logic families.

a) 3
b) 4
c) 5
d) 6
Answer: c
Explanation: Motorola has offered MECL circuits in five logic families: MECL I, MECL II,
MECL III, MECL 10000 (MECL 10K) and MECL 10H000 (MECL 10KH). The full form of
MECL is Motorola emitter coupled logic. ECL is a high speed BJT. It uses BJT differential
amplifier with single input and restricted current to avoid the transistor going into saturation and
thus turning off operation.
50. The latest entrant to the ECL family is ___________

a) ECL 10K
b) ECL 100K
c) ECL 1000K
d) ECL 10000K
Answer: b
Explanation: The latest entrant to the ECL family is ECL 100K, having 6-digit part numbers.
This family offers functions, in general, different from those offered by 10K series. This family
operates with a reduced power supply voltage -4.5 V, has shorter propagation delay of 0.75 ns,
and transition time of 0.7 ns. However, the power consumption per gate is about 40 mW.
51. All input of NOR as low produces result as ___________

a) Low
b) Mid
c) High
d) High Impedance
Answer: c
Explanation: According to the properties of NOR gate, if all the input of NOR as low produces
result as high. While if any input of NOR is high, then it produces low output.
52. In RTL NOR gate, the output is at logic 1 only when all the inputs are at ___________
a) logic 0
b) logic 1
c) +10v
d) floating
Answer: a
Explanation: RTL NOR gate behaves as NOR gate and the output of NOR gate will be 1 only
when all the inputs are at logic 0. The output of NOR will be 0 if any of the input is 1.
Digital Circuits Questions and Answers – Characteristics of CMOS
on “Characteristics of CMOS”.
53. The full form of CMOS is ____________

a) Capacitive metal oxide semiconductor
b) Capacitive metallic oxide semiconductor
c) Complementary metal oxide semiconductor
d) Complemented metal oxide semiconductor
Answer: c
Explanation: The full form of CMOS is complementary metal oxide semiconductor. In this type
of device, both n-type and p-type transistors are used in a complementary way.
54. The full form of COS-MOS is ____________

a) Complementary symmetry metal oxide semiconductor
b) Complementary systematic metal oxide semiconductor
c) Capacitive symmetry metal oxide semiconductor
d) Complemented systematic metal oxide semiconductor
Answer: a
Explanation: The full form of COS-MOS is complementary systematic metal oxide
semiconductor. In this type of device, both n-type and p-type transistors are used in a
complementary way. Usually, the transistors used are MOSFETs.
55. CMOS is also sometimes referred to as ____________

a) Capacitive metal oxide semiconductor
b) Capacitive symmetry metal oxide semiconductor
c) Complementary symmetry metal oxide semiconductor
d) Complemented symmetry metal oxide semiconductor
Answer: c
Explanation: CMOS is also sometimes referred to as complementary systematic metal oxide–
semiconductor (COS-MOS). In this type of device, both n-type and p-type transistors are used in
a complementary way. Usually, the transistors used are MOSFETs.
56. CMOS technology is used in ____________

a) Inverter
b) Microprocessor
c) Digital logic
d) Both microprocessor and digital logic
Answer: d
Explanation: CMOS technology is used in Microprocessor, Microcontroller, static RAM and
other digital logic circuits. CMOS technology is also used for several analog circuits such as
image sensors (CMOS sensor), data converters and highly integrated transceivers for many types
of communication.
57. Two important characteristics of CMOS devices are ____________

a) High noise immunity
b) Low static power consumption
c) High resistivity
d) Both high noise immunity and low static power consumption
Answer: d
Explanation: Two important characteristics of CMOS devices are high noise immunity and low
static power consumption. Since one transistor of the pair is always off and the series
combination draws significant power only momentarily during switching between on and off
states. Also, the performance of CMOS is not altered with the presence of noise and thus it has
high noise immunity.
58. CMOS behaves as a/an ____________

a) Adder
b) Subtractor
c) Inverter
d) Comparator
Answer: c
Explanation: Since, the outputs of the PMOS and NMOS transistors are complementary such
that when the input is low, the output is high and when the input is high, the output is low.
Because of this behaviour of input and output, the CMOS circuit’s output is the inverse of the
input. Whereas, adders and subtractors are combinational circuits.
59. An important characteristic of a CMOS circuit is the ____________

a) Noise immunity
b) Duality
c) Symmetricity
d) Noise Margin
Answer: b
Explanation: An important characteristic of a CMOS circuit is the duality that exists between its
PMOS transistors and NMOS transistors. Due to the presence of two different types of
transistors, the device has the complementary function.
60. CMOS logic dissipates _______ power than NMOS logic circuits.
a) More
b) Less
c) Equal
d) Very High
Answer: b
Explanation: CMOS logic dissipates less power than NMOS logic circuits because CMOS
dissipates power only when switching (“dynamic power”). Thus, CMOS has less power
consumption and is more efficient.
61. Semiconductors are made of ____________

a) Ge and Si
b) Si and Pb
c) Ge and Pb
d) Pb and Au
Answer: a
Explanation: Semiconductors are made of Silicon (Si) and Germanium (Ge). Semiconductors
are devices having conductivity between conductors and insulators.
62. Which chip were the first RTC and CMOS RAM chip to be used in early IBM
computers, capable of storing a total of 64 bytes?
a) The Samsung 146818
b) The Samsung 146819
c) The Motorola 146818
d) The Motorola 146819
Answer: c
Explanation: The Motorola 146818 was the first RTC and CMOS RAM chip to be used in early
IBM computers; capable of storing a total of 64 bytes.
Digital Circuits Questions and Answers – Emitter-Coupled Logic(ECL)
on “Emitter-Coupled Logic(ECL)”.
63. The full form of ECL is __________

a) Emitter-collector logic
b) Emitter-complementary logic
c) Emitter-coupled logic
d) Emitter-cored logic
Answer: c
Explanation: The full form of ECL is emitter-coupled logic.
64. Which logic is the fastest of all the logic families?
a) TTL
b) ECL
c) HTL
d) DTL
Answer: b
Explanation: ECL is the fastest of all the logic families because of the emitters of many
transistors are coupled together which results in the highest transmission rate.
65. Sometimes ECL can also be named as __________

a) EEL
b) CEL
c) CML
d) CCL
Answer: c
Explanation: ECL (Emitter Coupled Logic) can also be named as CML(Collector Mode Logic).
66. In an ECL the output is taken from __________

a) Emitter
b) Base
c) Collector
d) Junction of emitter and base
Answer: c
Explanation: Though, the emitter and collector of the ECL are coupled together. So, the output
will be taken from a collector.
67. The ECL behaves as __________

a) NOT gate
b) NOR gate
c) NAND gate
d) AND gate
Answer: b
Explanation: The ECL behaves as NOR gate because if any of the input voltages go high as
compared to the reference voltage, the output is low and the output is high only when all the
input voltages are low.
68. In ECL the fanout capability is __________
a) High
b) Low
c) Zero
d) Sometimes high and sometimes low
Answer: a
Explanation: If the input impedance is high and the output resistance is low; as a result, the
transistors change states quickly, gate delays are low, and the fanout capability is high. Fan-out is
the measure of the maximum number of inputs that a single gate output can accept.
69.ECL’s major disadvantage is that __________

a) It requires more power
b) It’s fanout capability is high
c) It creates more noise
d) It is slow
Answer: a
Explanation: ECL’s major disadvantage is that each gate continuously draws current, which
means it requires (and dissipates) significantly more power than those of other logic families.
But ECL logic gates have clock frequency. Thus, they have a fast operation.
70. The full form of SCFL is __________

a) Source-collector logic
b) Source-coupled logic
c) Source-complementary logic
d) Source Cored Logic
Answer: b
Explanation: The full form of SCFL is source-coupled logic.
71. The equivalent of emitter-coupled logic made out of FETs is called __________
a) CML
b) SCFL
c) FECL
d) EFCL
Answer: b
Explanation: The equivalent of emitter-coupled logic made out of FETs is called Source-
coupled logic(SCFL). Like ECL, SCL is also the fastest among the logic families.
72. ECL was invented in _______ by __________

a) 1956, Baker clamp
b) 1976, James R. Biard
c) 1956, Hannon S. Yourke
d) 1976, Yourke
Answer: c
Explanation: ECL was invented in August 1956 at IBM by Hannon S Yourke.
73. At the time of invention, an ECL was called as __________
a) Source-coupled logic
b) Current Mode Logic
c) Current-steering logic
d) Emitter-coupled logic
Answer: c
Explanation: At the time of invention, an ECL was called as current-steering logic because it
involved current switching.
74. The ECL circuits usually operates with __________

a) Negative voltage
b) Positive voltage
c) Grounded voltage
d) High Voltage
Answer: a
Explanation: The ECL circuits usually operate with negative power supplies (positive end of the
supply is connected to ground), in comparison to other logic families in which negative end of
the supply is grounded. It is done mainly to minimize the influence of the power supply
variations on the logic levels as ECL is more sensitive to noise on the VCC and relatively
immune to noise on VEE.
75. Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of
__________
a) ECL
b) VECL
c) PECL
d) LECL
Answer: c
Explanation: Low voltage positive emitter coupled logic (LVPECL) is a power optimized
version of PECL using a +3.3 V instead of 5 V supply.
Digital Circuits Questions and Answers – Transistor Transistor Logic(TTL)
Transistor Logic(TTL This set of Digital Electronics/Circuits Multiple Choice Questions &
Answers (MCQs) focuses on “Digital Circuits Questions and Answers – Transistor or T2L)”.
76. Transistor–transistor logic (TTL) is a class of digital circuits built from ____________
a) JFET only
b) Bipolar junction transistors (BJT)
c) Resistors
d) Bipolar junction transistors (BJT) and resistors
Answer: d
Explanation: Transistor–transistor logic (TTL) is a class of digital circuits built from bipolar
junction transistors (BJT) and resistors. However, resistors have a small role to play and both
logic gating and amplifying functions are performed by the transistors.
77. TTL is called transistor–transistor logic because both the logic gating function and the
amplifying function are performed by ____________
a) Resistors
b) Bipolar junction transistors
c) One transistor
d) Resistors and transistors respectively
Answer: b
Explanation: TTL is called transistor–transistor logic because both the logic gating function and
the amplifying function are performed by bipolar junction transistors (BJTs).
78. TTL was invented in 1961 by ____________

a) Baker clamp
b) James L. Buie
c) Chris Brown
d) Frank Wanlass
Answer: b
Explanation: TTL was invented in 1961 by James L Buie.
79. The full form of TCTL is ____________

a) Transistor-coupled transistor logic
b) Transistor-capacitor transistor logic
c) Transistor-complemented transistor logic
d) Transistor-complementary transistor logic
Answer: a
Explanation: The full form of TCTL is transistor-coupled transistor logic.
80. The _______ ancestor to the first personal computers.

a) PARAM 1
b) SATYAM 1
c) KENBAK 1
d) MITS Altair
Answer: c
Explanation: The KENBAK 1, ancestor to the first personal computers.
81. TTL inputs are the emitters of a ____________

a) Transistor-transistor logic
b) Multiple-emitter transistor
c) Resistor-transistor logic
d) Diode-transistor logic
Answer: b
Explanation: TTL inputs are the emitters of a multiple-emitter transistor.
82. TTL is a ____________

a) Current sinking
b) Current sourcing
c) Voltage sinking
d) Voltage sourcing
Answer: a
Explanation: Like DTL, TTL is a current-sinking logic since a current must be drawn from
inputs to bring them to a logic 0 level. Current Sink means it accepts current coming out from a
source.
83. Standard TTL circuits operate with a __ volt power supply.

a) 2
b) 4
c) 5
d) 3
Answer: c
Explanation: Standard TTL circuits operate with a 5-volt power supply.
84. TTL devices consume substantially ______ power than equivalent CMOS devices at
rest.
a) Less
b) More
c) Equal
d) Very High
Answer: b
Explanation: TTL devices consume substantially more power than equivalent CMOS devices at
rest. Thus, CMOS devices are faster than TTL devices.
85. A TTL gate may operate inadvertently as an ____________
a) Digital amplifier
b) Analog amplifier
c) Inverter
d) Regulator
Answer: b
Explanation: A TTL gate may operate inadvertently as an analog amplifier if the input is
connected to a slowly changing input signal that traverses the unspecified region from 0.7V to
3.3V.
86. The speed of ______ circuits is limited by the tendency of common emitter circuits to go
into saturation.
a) TTL
b) ECL
c) RTL
d) DTL
Answer: a
Explanation: The speed of TTL circuits is limited by the tendency of common emitter circuits to
go into saturation due to the injection of minority carriers into the collector region. Hence, it
functions slowly compared to CMOS devices.
Digital Circuits Questions and Answers – K-Map Simplification
on “K-Map Simplification”.
87. Which statement below best describes a Karnaugh map?

a) It is simply a rearranged truth table
b) The Karnaugh map eliminates the need for using NAND and NOR gates
c) Variable complements can be eliminated by using Karnaugh maps
d) A Karnaugh map can be used to replace Boolean rules
Answer: a
Explanation: K-map is simply a rearranged truth table. It is a pictorial representation of truth
table having a specific number of cells or squares, where each cell represents a Maxterm or a
Minterm.
88. Which of the examples below expresses the commutative law of multiplication?
a) A + B = B + A
b) A • B = B + A
c) A • (B • C) = (A • B) • C
d) A • B = B • A
Answer: d
Explanation: The commutative law of multiplication is (A * B) = (B * A).
The commutative law of addition is (A + B) = (B + A).
89. The Boolean expression Y = (AB)’ is logically equivalent to what single gate?
a) NAND
b) NOR
c) AND
d) OR
Answer: a
Explanation: If A and B are the input for AND gate the output is obtained as AB and after
inversion we get (AB)’, which is the expression of NAND gate. NAND gate produces high
output when any of the input is 0 and produces low output when all inputs are 1.
90. The observation that a bubbled input OR gate is interchangeable with a bubbled output
AND gate is referred to as:
a) A Karnaugh map
b) DeMorgan’s second theorem
c) The commutative law of addition
d) The associative law of multiplication
Answer: b
Explanation: DeMorgan’s Law: ~(P+Q) <=> (~P).(~Q) Also,~(P.Q) <=> (~P)+(~Q).
91. The systematic reduction of logic circuits is accomplished by:
a) Symbolic reduction
b) TTL logic
c) Using Boolean algebra
d) Using a truth table
Answer: c
Explanation: The systematic reduction of logic circuits is accomplished by using boolean
algebra.
92. Each “1” entry in a K-map square represents:

a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
Answer: a
Explanation: Each “1” entry in a K-map square represents a HIGH for each input truth table
condition that produces a HIGH output. Thus, it represents a minterm.
93. Each “0” entry in a K-map square represents:

a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
Answer: a
Explanation: Each “0” entry in a K-map square represents a LOW output for all possible HIGH
input conditions. Thus, it represents a Maxterm.
94. Which of the following statements accurately represents the two BEST methods of logic
circuit simplification?
a) Actual circuit trial and error evaluation and waveform analysis
b) Karnaugh mapping and circuit waveform analysis
c) Boolean algebra and Karnaugh mapping
d) Boolean algebra and actual circuit trial and error evaluation
Answer: c
Explanation: The two BEST methods of logic circuit simplification are Boolean algebra and
Karnaugh mapping. Boolean Algebra uses the Laws of Boolean Algebra for minimization of
Boolean expressions while Karnaugh Map is a pictorial representation and reduction of the
Boolean expression.
95. Looping on a K-map always results in the elimination of __________

a) Variables within the loop that appear only in their complemented form
b) Variables that remain unchanged within the loop
c) Variables within the loop that appear in both complemented and uncomplemented form
d) Variables within the loop that appear only in their uncomplemented form
Answer: c
Explanation: Looping on a K-map always results in the elimination of variables within the loop
that appear in both complemented and uncomplemented form.
96. Which of the following expressions is in the sum-of-products form?

a) (A + B)(C + D)
b) (A * B)(C * D)
c) A* B *(CD)
d) A * B + C * D
Answer: d
Explanation: Sum of product means that it is the sum of all product terms. Thus, the number is
multiplied first and then it is added: A * B + C * D.
97. Which of the following is an important feature of the sum-of-products form of

expressions?
a) All logic circuits are reduced to nothing more than simple AND and OR operations
b) The delay times are greatly reduced over other forms
c) No signal must pass through more than two gates, not including inverters
d) The maximum number of gates that any signal must pass through is reduced by a factor of two
Answer: a
Explanation: An important feature of the sum-of-products form of expressions in the given
option is that all logic circuits are reduced to nothing more than simple AND and OR operations.
Sum Of Product means it is the sum of product terms containing variables in complemented as
well as uncomplemented forms.
98. Which of the following expressions is in the product-of-sums form?

a) (A + B)(C + D)
b) (AB)(CD)
c) AB(CD)
d) AB + CD
Answer:
Explanation: (A + B)(C + D) represents the product-of-sums form.
Digital Circuits Questions and Answers – Flip Flops
This set of Digital Electronic/Circuits online quiz focuses on “Flip Flops – 2”.
99. What is an ambiguous condition in a NAND based S’-R’ latch?

a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0
Answer: d
Explanation: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’)
goes HIGH and this condition is called as ambiguous/forbidden state. This state is also known as
an Invalid state as the system goes into an unexpected situation.
100. In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is
____________
a) No change
b) Set
c) Reset
d) Forbidden
Answer: a
Explanation: In a NAND based S’-R, latch if S’=1 & R’=1 then there is no any change in the
state. It remains in its prior state. This state is used for the storage of data.
101. A NAND based S’-R’ latch can be converted into S-R latch by placing ____________
a) A D latch at each of its input
b) An inverter at each of its input
c) It can never be converted
d) Both a D latch and an inverter at its input
Answer: d
Explanation: A NAND based S’-R’ latch can be converted into S-R latch by placing either a D
latch or an inverter at its input as it’s operations will be complementary.
102. The characteristic equation of S-R latch is ____________

a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R
Answer: a
Explanation: A characteristic equation is needed when a specific gate requires a specific output
in order to satisfy the truth table. The characteristic equation of S-R latch is Q(n+1) = (S +
Q(n))R’.
103. The difference between a flip-flop & latch is ____________

a) Both are same
b) Flip-flop consist of an extra output
c) Latches has one input but flip-flop has two
d) Latch has two inputs but flip-flop has one
Answer: c
Explanation: Flip-flop is a modified version of latch. To determine the changes in states, an
additional control input is provided to the latch.
104. How many types of flip-flops are?
a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: There are 4 types of flip-flops, viz., S-R, J-K, D, and T. D flip-flop is an advanced
version of S-R flip-flop, while T flip-flop is an advanced version of J-K flip-flop.
105. The S-R flip flop consist of ____________

a) 4 AND gates
b) Two additional AND gates
c) An additional clock input
d) 3 AND gates
Answer: b
Explanation: The S-R flip flop consist of two additional AND gates at the S and R inputs of S-R
latch.
106. What is one disadvantage of an S-R flip-flop?

a) It has no Enable input
b) It has a RACE condition
c) It has no clock input
d) Invalid State
Answer: d
Explanation: The main drawback of s-r flip flop is invalid output when both the inputs are high,
which is referred to as Invalid State.
107. One example of the use of an S-R flip-flop is as ____________

a) Racer
b) Stable oscillator
c) Binary storage register
d) Transition pulse generator
Answer: c
Explanation: S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it is
referred to as binary storage element. It functions as memory storage during the No Change
State.
108. When is a flip-flop said to be transparent?

a) When the Q output is opposite the input
b) When the Q output follows the input
c) When you can see through the IC packaging
d) When the Q output is complementary of the input
Answer: b
Explanation: Flip-flop have the property of responding immediately to the changes in its inputs.
This property is called transparency.
109. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
Answer: c
Explanation: Edge triggered device will follow when there is transition. It is a positive edge
triggered when transition takes place from low to high, while, it is negative edge triggered when
the transition takes place from high to low.
110. What is the hold condition of a flip-flop?

a) Both S and R inputs activated
b) No active S or R input
c) Only S is active
d) Only R is active
Answer: b
Explanation: The hold condition in a flip-flop is obtained when both of the inputs are LOW. It
is the No Change State or Memory Storage state if a flip-flop.
111. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the
R input goes to 0, the latch will be ________
a) SET
b) RESET
c) Clear
d) Invalid
Answer: b
Explanation: If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no
change. So, it remains in reset. If S=1, R=0, the flip flop is at the set condition.
112. The circuit that is primarily responsible for certain flip-flops to be designated as edge-
triggered is the _____________
a) Edge-detection circuit
b) NOR latch
c) NAND latch
d) Pulse-steering circuit
Answer: a
Explanation: The circuit that is primarily responsible for certain flip-flops to be designated as
edge-triggered is the edge-detection circuit.
Digital Circuits Questions and Answers – Flip Flops – 1
on “Flip Flops – 1”.
113. Latches constructed with NOR and NAND gates tend to remain in the latched
condition due to which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling
Answer: d
Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of a
latch are directly connected to the other’s output. Such types of structure is called cross coupling
and due to which latches remain in the latched condition.
114. One example of the use of an S-R flip-flop is as ___________

a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator
Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce, which
is the unwanted noise caused during the switching of electronic devices.
115. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state. The
Invalid or Undefined State occurs at both S and R being at 1.
116. When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume J=0
and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1 cycle
complete). The J & K flip-flop has 4 stable states: Latch, Reset, Set and Toggle.
117. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
Answer: a
Explanation: In D flip flop, when the clock is high then the output depends on the input
otherwise reminds previous output. In a state of clock high, when D is high the output Q also
high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an invalid
state at both inputs being 1.
118. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
Answer: c
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND
gates. Cross coupling means the output of second gate is fed to the input of first gate and vice-
versa.
119. The logic circuits whose outputs at any instant of time depends only on the present
input but also on the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The
circuits whose outputs at any instant of time depends only on the present input but also on the
past outputs are called sequential circuits. Unlike sequential circuits, if output depends only on
the present state, then it’s known as combinational circuits.
120. Whose operations are more faster among the following?
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since, the
combinational circuits do not require memory elements whereas the sequential circuits need
memory devices to perform their operations in sequence. Latches and Flip-flops come under
sequential circuits.
121. How many types of sequential circuits are?

a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii)
asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the presence of a
clock signal, whereas, Asynchronous Sequential Circuits function in the absence of a clock
signal.
122. The sequential circuit is also called ___________

a) Flip-flop
b) Latch
c) Strobe
d) Adder
Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell, which
are capable of storing one bit of information.
123. The basic latch consists of ___________
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders
Answer: a
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q = 0
then the second output Q’ = 1 and vice versa.
124. In S-R flip-flop, if Q = 0 the output is said to be ___________

a) Set
b) Reset
c) Previous state
d) Current state
Answer: b
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.
125. The output of latches will remain in set/reset untill ___________

a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered
Answer: a
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to
change the state.
126. What is a trigger pulse?

a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation
Answer: a
Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.
127. The circuits of NOR based S-R latch classified as asynchronous sequential circuits,
why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionality
Answer: c
Explanation: The cross-coupled connections from the output of one gate to the input of the
other gate constitute a feedback path. For this reason, the circuits of NOR based S-R latch
classified as asynchronous sequential circuits. Moreover, they are referred to as asynchronous
because they function in the absence of a clock pulse.
Digital Circuits Questions and Answers – Latches
on “Latches”.
128. A latch is an example of a ___________

a) Monostable multivibrator
b) Astable multivibrator
c) Bistable multivibrator
d) 555 timer
Answer: c
Explanation: A latch is an example of a bistable multivibrator. A Bistable multivibrator is one
in which the circuit is stable in either of two states. It can be flipped from one state to the other
state and vice-versa.
129. Latch is a device with ___________

a) One stable state
b) Two stable state
c) Three stable state
d) Infinite stable states
Answer: b
Explanation: Since, a latch works on the principal of bistable multivibrator. A Bistable
multivibrator is one in which the circuit is stable in either of two states. It can be flipped from
one state to the other state and vice-versa. So a latch has two stable states.
130. Why latches are called a memory devices?

a) It has capability to stare 8 bits of data
b) It has internal memory of 4 bit
c) It can store one bit of data
d) It can store infinite amount of data
Answer: c
Explanation: Latches can be memory devices, and can store one bit of data for as long as the
device is powered. Once device is turned off, the memory gets refreshed.
131. Two stable states of latches are ___________

a) Astable & Monostable
b) Low input & high output
c) High output & low output
d) Low output & high input
Answer: c
Explanation: A latch has two stable states, following the principle of Bistable Multivibrator.
There are two stable states of latches and these states are high-output and low-output.
132. How many types of latches are ___________

a) 4
b) 3
c) 2
d) 5
Answer: a
Explanation: There are four types of latches: SR latch, D latch, JK latch and T latch. D latch is a
modified form of SR latch whereas, T latch is an advanced form of JK latch.
133. The full form of SR is ___________
a) System rated
b) Set reset
c) Set ready
d) Set Rated
Answer: b
Explanation: The full form of SR is set/reset. It is a type of latch having two stable states.
134. The SR latch consists of ___________

a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
Answer: b
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two
stable states.
The diagram of SR latch is shown below:
135. The outputs of SR latch are ___________

a) x and y
b) a and b
c) s and r
d) q and q’
Answer: d
stable states. The inputs of SR latch are s and r while outputs are q and q’. It is clear from the
diagram:
136. The first step of analysis procedure of SR latch is to ___________

a) label inputs
b) label outputs
c) label states
d) label tables
Answer: b
Explanation: All flip flops have at least one output labeled Q (i.e. inverted). This is so because
the flip flops have inverting gates inside them, hence in order to have both Q and Q complement
available, we have atleast one output labelled.
137. The inputs of SR latch are ___________

a) x and y
b) a and b
c) s and r
d) j and k
Answer: c
stable states. The inputs of SR latch are s and r while outputs are q and q’. It is clear from the
diagram:
139. When a high is applied to the Set line of an SR latch, then ___________
a) Q output goes high
b) Q’ output goes high
c) Q output goes low
d) Both Q and Q’ go high
Answer: a
Explanation: S input of a SR latch is directly connected to the output Q. So, when a high is
applied Q output goes high and Q’ low.
140. When both inputs of SR latches are low, the latch ___________
a) Q output goes high
b) Q’ output goes high
c) It remains in its previously set or reset state
d) it goes to its next set or reset state
Answer: c
Explanation: When both inputs of SR latches are low, the latch remains in it’s present state.
There is no change in the output.
141. When both inputs of SR latches are high, the latch goes ___________
a) Unstable
b) Stable
c) Metastable
d) Bistable
Answer: c
Explanation: When both gates are identical and this is “metastable”, and the device will be in an
undefined state for an indefinite period.
Digital Circuits Questions and Answers – MOS Digital Integrated Circuits
on “MOS Digital Integrated Circuits”.
142. The full form of MOS is ___________

a) Metal oxide semiconductor
b) Metal oxygen semiconductor
c) Metallic oxide semiconductor
d) Metallic oxygen semiconductor
Answer: a
Explanation: The full form of MOS is “Metal Oxide Semiconductor”. It is a type of transistor
having 3 layers: a metal conductor, an insulating silicon layer and a semiconductor silicon layer.
143. What are the types of MOSFET devices available?

a) P-type enhancement type MOSFET
b) N-type enhancement type MOSFET
c) Depletion type MOSFET
d) All of the mentioned
Answer: d
Explanation: MOSFET are of two types: enhancement and depletion type. Further, these are
classified into n-type and p-type device. The depletion type is switched on without the
application of gate bias voltage and the enhancement type is switched on with the application of
gate voltage
.
146. Which insulating layer used in the fabrication of MOSFET?
a) Aluminium oxide
b) Silicon Nitride
c) Silicon dioxide
d) Aluminium Nitrate
Answer: c
Explanation: Silicon dioxide is used as an insulating layer in the fabrication of MOSFET. It
gives an extremely high input resistance in the order of 10^10 to 10^15 Ω for MOSFET.
147. Which of the following plays an important role in improving device performance of
MOSFET?
a) Dielectric constant
b) Threshold voltage
c) Power supply voltage
d) Gate to drain voltage
Answer: b
Explanation: In MOSFET, the threshold voltage is typically 3 to 6V. This large voltage is not
compatible with the supply of 5V which is used in digital ICs. So, for the improvement of the
device’s performance the magnitude of threshold voltage should be reduced.
148. A technique used to reduce the magnitude of threshold voltage of MOSFET is the
___________
a) Use of complementary MOSFET
b) Use of Silicon nitride
c) Using thin film technology
d) Increasing potential of the channel
Answer: b
Explanation: Silicon nitride is sandwiched between two SiO2 layer and provide necessary
barrier. The dielectric constant of Si3N4 is 7.5, whereas that of SiO2 is 4. This increase in
overall dielectric constant reduces threshold voltage.
149. What is used to higher the speed of operation in MOSFET fabrication?
a) Ceramic gate
b) Silicon dioxide
c) Silicon nitride
d) Poly silicon gate
Answer: d
Explanation: In conventional metal gate small overlap capacitance is present, which lowers the
speed of operation. With the presence of self aligning property of the poly silicon gate it
eliminates this capacitance. Using a process called ion-implantation, polysilicon, the drain and
the source get doped. However, the thin oxide under silicon gate acting as a mask for the process
and thus develops the gate aligning property.
150. Find the sequence of steps involved in fabrication of poly silicon gate MOSFET?
Step 1: Entire wafer surface of a Si3N4 is coated and is etched away with the help of mask to
include source, gate and drain.
Step 2: The contact areas are defined using photolithographic process.
Step 3: Selective etching of Si3N4 and growth of thin oxide.
Step 4: The deposition of poly silicon gate.
Step 5: The growth of thick oxide is called field oxide and P implantation.
Step 6: The metallization and interconnection between substrate and source.
a) 1->5->3->4->2->6
b) 1->3->4->2->5->6
c) 1->5->4->3->2->6
d) 1->4->2->5->3->6
Answer: a
Explanation: These steps are the sequence of steps involved in fabrication of poly silicon gate
MOSFET. With the help of poly silicon gate doping, it highers the speed of operation of the
MOSFET.
151. Why MOSFET is preferred over BJT in IC components?
a) MOSFET has low packing density
b) MOSFET has medium packing density
c) MOSFET has high packing density
d) MOSFET has no packing density
Answer: a
Explanation: MOSFET is preferred over BJT because of its low packaging density. Thus, more
number of MOSFET memory cells can be accommodated in a particular area as compared to
BJT.
152. Critical defects per unit chip area is ________ for a MOS transistor.
a) High
b) Low
c) Neutral
d) Very High
Answer: b
Explanation: Critical defects per unit chip area is low for a MOS transistor because it involves
fewer steps in the fabrication of a MOS transistor. Also, MOSFET has low packaing density.
153. MOS is being used in ___________

a) LSI
b) VLSI
c) MSI
d) Both LSI and VLSI
Answer: d
Explanation: Since more transistor and circuitry functions can be achieved on a single chip with
MOS technology that is why MOS is being used in LSI and VLSI. LSI stands for Large Scale
Integration and VLSI stands for Very Large Scale Integration.
Digital Circuits Questions and Answers – D Flip Flop
on “D Flip Flop”.
154. In D flip-flop, D stands for _____________

a) Distant
b) Data
c) Desired
d) Delay
Answer: b
Explanation: The D of D-flip-flop stands for “data”. It stores the value on the data line.
155. The D flip-flop has _______ input.

a) 1
b) 2
c) 3
d) 4
Answer: a
Explanation: The D flip-flop has one input. The D of D-flip-flop stands for “data”. It stores the
value on the data line.
156. The D flip-flop has ______ output/outputs.

a) 2
b) 3
c) 4
d) 1
Answer: a
Explanation: The D flip-flop has two outputs: Q and Q complement. The D flip-flop has one
input. The D of D-flip-flop stands for “data”. It stores the value on the data line.
157. A D flip-flop can be constructed from an ______ flip-flop.
a) S-R
b) J-K
c) T
d) S-K
Answer: a
Explanation: A D flip-flop can be constructed from an S-R flip-flop by inserting an inverter
between S and R and assigning the symbol D to the S input.
158. In D flip-flop, if clock input is HIGH & D=1, then output is ___________
a) 0
b) 1
c) Forbidden
d) Toggle
Answer: a
Explanation: If clock input is HIGH & D=1, then output is 0. It can be observed from this
diagram:
159. Which statement describes the BEST operation of a negative-edge-triggered D flip-
flop?
a) The logic level at the D input is transferred to Q on NGT of CLK
b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH
c) The Q output is ALWAYS identical to the D input when CLK = PGT
d) The Q output is ALWAYS identical to the D input
Answer: a
Explanation: By the truth table of D flip flop, we can observe that Q always depends on D.
Hence, for every negative trigger pulse, the logic at input D is shifted to Output Q.
160. Which of the following is correct for a gated D flip-flop?

a) The output toggles if one of the inputs is held HIGH
b) Only one of the inputs can be HIGH at a time
c) The output complement follows the input when enabled
d) Q output follows the input D when the enable is HIGH
Answer: d
Explanation: If clock is high then the D flip-flop operate and we know that input is equals to
output in case of D flip-flop. It stores the value on the data line.
161. With regard to a D latch ________
a) The Q output follows the D input when EN is LOW
b) The Q output is opposite the D input when EN is LOW
c) The Q output follows the D input when EN is HIGH
d) The Q output is HIGH regardless of EN’s input state
Answer: c
Explanation: Latch is nothing but flip flop which holds the o/p or i/p state. And in D flip-flop
output follows the input. It stores the value on the data line.
162. Which of the following is correct for a D latch?

a) The output toggles if one of the inputs is held HIGH
b) Q output follows the input D when the enable is HIGH
c) Only one of the inputs can be HIGH at a time
d) The output complement follows the input when enabled
Answer: b
Explanation: If the clock is HIGH then the D flip-flop operates and we know that input equals
to output in case of D flip flop. It stores the value on the data line.
163. Which of the following describes the operation of a positive edge-triggered D flip-flop?
a) If both inputs are HIGH, the output will toggle
b) The output will follow the input on the leading edge of the clock
c) When both inputs are LOW, an invalid state exists
d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the
output on the trailing edge of the clock
Answer: b
Explanation: Edge-triggered flip-flop means the device will change state during the rising or
falling edge of the clock pulse. The main phenomenon of the D flip-flop is that the o/p will
follow the i/p when the enable pin is HIGH.
164. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input
actions will cause it to change states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1
Answer: d
Explanation: PGT refers to Positive Going Transition and NGT refers to negative Going
Transition. Earlier, the DFF is in a clear state (output is 0). So, if D = 1 then in the next stage
output will be 1 and hence the stage will be changed.
165. A positive edge-triggered D flip-flop will store a 1 when ________

a) The D input is HIGH and the clock transitions from HIGH to LOW
b) The D input is HIGH and the clock transitions from LOW to HIGH
c) The D input is HIGH and the clock is LOW
d) The D input is HIGH and the clock is HIGH
Answer: b
Explanation: A positive edge-triggered D flip-flop will store a 1 when the D input is HIGH and
the clock transitions from LOW to HIGH. While a negative edge-triggered D flip-flop will store
a 0 when the D input is HIGH and the clock transitions from HIGH to LOW.
166. Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?
a) Due to its capability to receive data from flip-flop
b) Due to its capability to store data in flip-flop
c) Due to its capability to transfer the data into flip-flop
d) Due to erasing the data from the flip-flop
Answer: c
Explanation: Due to its capability to transfer the data into flip-flop. D-flip-flops stores the value
on the data line.
165. The characteristic equation of D-flip-flop implies that ___________
a) The next state is dependent on previous state
b) The next state is dependent on present state
c) The next state is independent of previous state
d) The next state is independent of present state
Answer: d
Explanation: A characteristic equation is needed when a specific gate requires a specific output
in order to satisfy the truth table. The characteristic equation of D flip-flop is given by Q(n+1) =
D; which indicates that the next state is independent of the present state.
Digital Circuits Questions and Answers – Master-Slave Flip-Flops
on “Master-Slave Flip-Flops”.
166. The asynchronous input can be used to set the flip-flop to the ____________
a) 1 state
b) 0 state
c) either 1 or 0 state
d) forbidden State
Answer: c
Explanation: The asynchronous input can be used to set the flip-flop to the 1 state or clear the
flip-flop to the 0 state at any time, regardless of the condition at the other inputs.
167. Input clock of RS flip-flop is given to ____________

a) Input
b) Pulser
c) Output
d) Master slave flip-flop
Answer: b
Explanation: Pulser behaves like an arithmetic operator, to perform the operation or
determination of corresponding states.
168. D flip-flop is a circuit having ____________
a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates
Answer: c
Explanation: D flip-flop is a circuit having 4 NAND gates. Two of them are connected with
each other.
169. In JK flip flop same input, i.e. at a particular time or during a clock pulse, the output
will oscillate back and forth between 0 and 1. At the end of the clock pulse the value of
output Q is uncertain. The situation is referred to as?
a) Conversion condition
b) Race around condition
c) Lock out state
d) Forbidden State
Answer: b
Explanation: A race around condition is a flaw in an electronic system or process whereby the
output and result of the process is unexpectedly dependent on the sequence or timing of other
events.
170. Master slave flip flop is also referred to as?

a) Level triggered flip flop
b) Pulse triggered flip flop
c) Edge triggered flip flop
d) Edge-Level triggered flip flop
Answer: b
Explanation: The term pulse triggered means the data is entered on the rising edge of the clock
pulse, but the output does not reflect the change until the falling edge of the clock pulse.
171. In a positive edge triggered JK flip flop, a low J and low K produces?
a) High state
b) Low state
c) Toggle state
d) No Change State
Answer: d
Explanation: In JK Flip Flop if J = K = 0 then it holds its current state. There will be no change.
172. If one wants to design a binary counter, the preferred type of flip-flop is ____________
a) D type
b) S-R type
c) Latch
d) J-K type
Answer: d
Explanation: If one wants to design a binary counter, the preferred type of flip-flop is J-K type
because it has capability to recover from toggle condition. SR flip-flop is not suitable as it
produces the “Invalid State”.
173. S-R type flip-flop can be converted into D type flip-flop if S is connected to R through
____________
a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
Answer: c
Explanation: S-R type flip-flop can be converted into D type flip-flop if S is connected to R
through an Inverter gate.
174. Which of the following flip-flops is free from the race around the problem?
a) T flip-flop
b) SR flip-flop
c) Master-Slave Flip-flop
d) D flip-flop
Answer: a
Explanation: T flip-flop is free from the race around condition because its output depends only
on the input; hence there is no any problem creates as like toggle.
175. Which of the following is the Universal Flip-flop?

a) S-R flip-flop
b) J-K flip-flop
c) Master slave flip-flop
d) D Flip-flop
Answer: b
Explanation: There are lots of flip-flops can be prepared by using J-K flip-flop. So, the name is
a universal flip-flop. Also, the JK flip-flop resolves the Forbidden State.
176. How many types of triggering takes place in a flip flops?

a) 3
b) 2
c) 4
d) 5
Answer: a
Explanation: There are three types of triggering in a flip-flop, viz., level triggering, edge
triggering and pulse triggering.
177. The term synchronous means ____________
a) The output changes state only when any of the input is triggered
b) The output changes state only when the clock input is triggered
c) The output changes state only when the input is reversed
d) The output changes state only when the input follows it
Answer: b
Explanation: The term synchronous means the output changes state only when the clock input is
triggered. That is, changes in the output occur in synchronization with the clock.
178. The S-R, J-K and D inputs are called ____________

a) Asynchronous inputs
b) Synchronous inputs
c) Bidirectional inputs
d) Unidirectional inputs
Answer: b
Explanation: The S-R, J-K and D inputs are called synchronous inputs because data on these
inputs are transferred to the flip-flop’s output only on the triggering edge or level triggering of
the clock pulse. Moreover, flip-flops have a clock input whereas latches don’t. Hence, known as
synchronous inputs.
179. The circuit that generates a spike in response to a momentary change of input signal is
called ____________
a) R-C differentiator circuit
b) L-R differentiator circuit
c) R-C integrator circuit
d) L-R integrator circuit
Answer: a
Explanation: The circuit that generates a spike in response to a momentary change of input
signal is called R-C differentiator circuit.
Digital Circuits Questions and Answers – Flip Flops – 3
This set of Digital Electronic/Circuits question bank focuses on “Flip Flops – 3”.
180. Which circuit is generated from D flip-flop due to addition of an inverter by causing
reduction in the number of inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch
Answer: d
Explanation: Since, both inputs of the D flip-flop are connected through an inverter. And this
causes reduction in the number of inputs.
181. The characteristic of J-K flip-flop is similar to _____________

a) S-R flip-flop
b) D flip-flop
c) T flip-flop
d) Gated T flip-flop
Answer: a
Explanation: In an S-R flip-flop, S refers to “SET” whereas R refers to “RESET”. The same
behaviour is shown by J-K flip-flop.
182. A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting
___________
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) Two OR gates
Answer: a
Explanation: A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting two
AND gates.
183. How is a J-K flip-flop made to toggle?
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
Answer: d
Explanation: When j=k=1 then the race condition is occurs that means both output wants to be
HIGH. Hence, there is toggle condition is occurs, where 0 becomes 1 and 1 becomes 0. That is
device is either set or reset.
184. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse)
is HIGH is called ___________
a) Parity error checking
b) Ones catching
c) Digital discrimination
d) Digital filtering
Answer: b
Explanation: Ones catching means that the input transitioned to a 1 and back very briefly
(unintentionally due to a glitch), but the flip-flop responded and latched it in anyway, i.e., it
caught the 1. Similarly for 0’s catching.
185. In J-K flip-flop, “no change” condition appears when ___________

a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0
Answer: d
Explanation: If J = 0, K = 0, the output remains unchanged. This is the memory storing state.
186. What is the significance of the J and K terminals on the J-K flip-flop?
a) There is no known significance in their designations
b) The J represents “jump,” which is how the Q output reacts whenever the clock goes high and
the J input is also HIGH
c) The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit
d) All of the other letters of the alphabet are already in use
Answer: c
Explanation: The letters J & K were chosen in honour of Jack Kilby, the inventory of the
integrated circuit. In J&K flip-flops, the invalid state problem is resolved, thus leading to the
toggling of states.
187. On a J-K flip-flop, when is the flip-flop in a hold condition?

a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
Answer: a
Explanation: At J=0 k=0 output continues to be in the same state. This is the memory storing
state.
188. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as
counters. After four input clock pulses, the binary count is ________
a) 00
b) 11
c) 01
d) 10
Answer: a
Explanation: Every O/P repeats after its mod. Here mod is 4 (because 2 flip-flops are used. So
mod = 22 = 4). So after 4 clock pulses the O/P repeats i.e. 00.
189. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input
frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz
Answer: b
Explanation: 32/2=16:-first flip-flop, 16/2=8:- second flip-flop, 8/2=4:- third flip-flop, 4/2=2:-
fourth flip-flop. Since the output frequency is determined on basis of the 4th flip-flop.
190. Determine the output frequency for a frequency division circuit that contains 12 flip-
flops with an input clock frequency of 20.48 MHz.
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz
Answer: b
Explanation: 12 flip flops = 212 = 4096
Input Clock frequency = 20.48*106 = 20480000
Output Clock frequency = 20480000/4096 = 5000 i.e., 5 kHz.
191. How many flip-flops are in the 7475 IC?

a) 2
b) 1
c) 4
d) 8
Answer: c
Explanation: There are 4 flip-flops used in 7475 IC and those are D flip-flops only.
Digital Circuits Questions and Answers – Half Adder & Full Adder
on “Half Adder & Full Adder”.
192. In parts of the processor, adders are used to calculate ____________

a) Addresses
b) Table indices
c) Increment and decrement operators
d) All of the Mentioned
Answer: d
Explanation: Adders are used to perform the operation of addition. Thus, in parts of the
processor, adders are used to calculate addresses, table indices, increment and decrement
operators, and similar operations.
193. Total number of inputs in a half adder is __________

a) 2
b) 3
c) 4
d) 1
Answer: a
Explanation: Total number of inputs in a half adder is two. Since, an EXOR gates has 2 inputs
and carry is connected with the input of EXOR gates. The output of half-adder is also 2, them
being, SUM and CARRY. The output of EXOR gives SUM and that of AND gives carry.
194. In which operation carry is obtained?

a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
Answer: b
Explanation: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example
carry is obtained after 1st addition (i.e. 1 + 1 = 1 0). In subtraction, borrow is obtained. Like, 0 –
1 = 1 (borrow 1).
195. If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: c
Explanation: If A and B are the inputs of a half adder, the sum is given by A XOR B, while the
carry is given by A AND B.
196. If A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
Answer: a
Explanation: If A and B are the inputs of a half adder, the carry is given by: A(AND)B, while
the sum is given by A XOR B.
197. Half-adders have a major limitation in that they cannot __________

a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
Answer: c
Explanation: Half-adders have a major limitation in that they cannot accept a carry bit from a
previous stage, meaning that they cannot be chained together to add multi-bit numbers. However,
the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both
being high.
198. The difference between half adder and full adder is __________
a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
Answer: c
Explanation: Half adder has two inputs while full adder has three outputs; this is the difference
between them, while both have two outputs SUM and CARRY.
199. If A, B and C are the inputs of a full adder then the sum is given by __________
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C
Answer: c
Explanation: If A, B and C are the inputs of a full adder then the sum is given by A XOR B
XOR C.
200. If A, B and C are the inputs of a full adder then the carry is given by __________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
Answer: a
Explanation: If A, B and C are the inputs of a full adder then the carry is given by A AND B
OR (A OR B) AND C, which is equivalent to (A AND B) OR (B AND C) OR (C AND A).
201. How many AND, OR and EXOR gates are required for the configuration of full
adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
Answer: b
Explanation: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full
adder, provided using half adder. Otherwise, configuration of full adder would require 3 AND, 2
OR and 2 EXOR.
Digital Circuits Questions and Answers – Half & Full Subtractor
on “Half & Full Subtractor”.
202. Half subtractor is used to perform subtraction of ___________

a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
Answer: a
Explanation: Half subtractor is a combinational circuit which is used to perform subtraction of
two bits, namely minuend and subtrahend and produces two outputs, borrow and difference.
203. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.
a) Carry
b) Borrow
c) Input
d) Output
Answer: b
Explanation: For subtracting 1 from 0, we use to take a borrow from neighbouring bits because
carry is taken into consideration during addition process.
204. How many outputs are required for the implementation of a subtractor?
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: There are two outputs required for the implementation of a subtractor. One for the
difference and another for borrow.
205. Let the input of a subtractor is A and B then what the output will be if A = B?
a) 0
b) 1
c) A
d) B
Answer: a
Explanation: The output for A = B will be 0. If A = B, it means that A = B = 0 or A = B = 1. In
both of the situation subtractor gives 0 as the output.
206. Let A and B is the input of a subtractor then the output will be ___________
a) A XOR B
b) A AND B
c) A OR B
d) A EXNOR B
Answer: a
Explanation: The subtractor has two outputs BOROW and DIFFERENCE. Since, the difference
output of a subtractor is given by AB’ + BA’ and this is the output of a XOR gate. So, the final
difference output is AB’ + BA’.
207. Let A and B is the input of a subtractor then the borrow will be ___________
a) A AND B’
b) A’ AND B
c) A OR B
d) A AND B
Answer: b
Explanation: The borrow of a subtractor is received through AND gate whose one input is
inverted. On that basis the borrow will be (A’ AND B).
208. What does minuend and subtrahend denotes in a subtractor?

a) Their corresponding bits of input
b) Its outputs
c) Its inputs
d) Borrow bits
Answer: c
Explanation: Minuend and subtrahend are the two bits of input of a subtractor. If A and B are
the two inputs of a subtractor then A is called minuend and B as subtrahend.
209. Full subtractor is used to perform subtraction of ___________

a) 2 bits
b) 3 bits
c) 4 bits
d) 8 bits
Answer: b
Explanation: Full subtractor is used to perform subtraction of 3 bits, namely minuend bit,
subtrahend bit and borrow from the previous stage. However, it also produces 2 outputs
BORROW and DIFFERENCE.
210. The full subtractor can be implemented using ___________
a) Two XOR and an OR gates
b) Two half subtractors and an OR gate
c) Two multiplexers and an AND gate
d) Two comparators and an AND gate
Answer: b
Explanation: A full subtractor has 3 input bits and two outputs bits BORROW and
DIFFERENCE. The full subtractor can be implemented using two half subtractors and an OR
gate.
211. The output of a subtractor is given by (if A, B and X are the inputs).
a) A AND B XOR X
b) A XOR B XOR X
c) A OR B NOR X
d) A NOR B XOR X
Answer: b
Explanation: The difference output of a subtractor is given by (if A, B and X are the inputs) A
XOR B XOR X.
212. The output of a full subtractor is same as ____________

a) Half adder
b) Full adder
c) Half subtractor
d) Decoder
Answer: b
Explanation: The sum and difference output of a full adder and a full subtractor are same. If A,
B and C are the input of a full adder and a full subtractor then the output will be given by (A
XOR B XOR C), respectively.
Digital Circuits Questions and Answers – Registers
on “Registers”.
213. A register is defined as ___________

a) The group of latches for storing one bit of information
b) The group of latches for storing n-bit of information
c) The group of flip-flops suitable for storing one bit of information
d) The group of flip-flops suitable for storing binary information
Answer: d
Explanation: A register is defined as the group of flip-flops suitable for storing binary
information. Each flip-flop is a binary cell capable of storing one bit of information. The data in
a register can be transferred from one flip-flop to another.
214. The register is a type of ___________

a) Sequential circuit
b) Combinational circuit
c) CPU
d) Latches
Answer: a
Explanation: Register’s output depends on the past and present states of the inputs. The device
which follows these properties is termed as a sequential circuit. Whereas, combinational circuits
only depend on the present values of inputs.
215. How many types of registers are?

a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: There are 4 types of shift registers, viz., Serial-In/Serial-Out, Serial-In/Parallel-
Out, Parallel-In/Serial-Out and Parallel-In/Parallel-Out.
216. The main difference between a register and a counter is ___________

a) A register has no specific sequence of states
b) A counter has no specific sequence of states
c) A register has capability to store one bit of information but counter has n-bit
d) A register counts data
Answer: a
Explanation: The main difference between a register and a counter is that a register has no
specific sequence of states except in certain specialised applications.
217. In D register, ‘D’ stands for ___________

a) Delay
b) Decrement
c) Data
d) Decay
Answer: c
Explanation: D stands for “data” in case of flip-flops and not delay. Registers are made of a
group of flip-flops.
218. Registers capable of shifting in one direction is ___________

a) Universal shift register
b) Unidirectional shift register
c) Unipolar shift register
d) Unique shift register
Answer: b
Explanation: The register capable of shifting in one direction is unidirectional shift register. The
register capable of shifting in both directions is known as a bidirectional shift register.
219. A register that is used to store binary information is called ___________
a) Data register
b) Binary register
c) Shift register
d) D – Register
Answer: b
Explanation: A register that is used to store binary information is called a binary register. A
register in which data can be shifted is called shift register.
220. A shift register is defined as ___________

a) The register capable of shifting information to another register
b) The register capable of shifting information either to the right or to the left
c) The register capable of shifting information to the right only
d) The register capable of shifting information to the left only
Answer: b
Explanation: The register capable of shifting information either to the right or to the left is
termed as shift register. A register in which data can be shifted only in one direction is called
unidirectional shift register, while if data can shifted in both directions, it is known as a
bidirectional shift register.
221. How many methods of shifting of data are available?

a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: There are two types of shifting of data are available and these are serial shifting &
parallel shifting.
222. In serial shifting method, data shifting occurs ____________
a) One bit at a time
b) simultaneously
c) Two bit at a time
d) Four bit at a time
Answer: a
Explanation: As the name suggests serial shifting, it means that data shifting will take place one
bit at a time for each clock pulse in a serial fashion. While in parallel shifting, shifting will take
place with all bits simultaneously for each clock pulse in a parallel fashion.
Digital Circuits Questions and Answers – Shift Register Counters
on “Shift Register Counters”.
223. What is a recirculating register?

a) Serial out connected to serial in
b) All Q outputs connected together
c) A register that can be used over again
d) Parallel out connected to Parallel in
Answer: a
Explanation: A recirculating register is a register whose serial output is connected to the serial
input in a circulated manner.
224. When is it important to use a three-state buffer?

a) When two or more outputs are connected to the same input
b) When all outputs are normally HIGH
c) When all outputs are normally LOW
d) When two or more outputs are connected to two or more inputs
Answer: a
Explanation: When two or more outputs are connected to the same input, in such situation we
use of tristate buffer always because it has the capability to take upto three inputs. A buffer is a
circuit where the output follows the input.
225. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The
nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the
shift register is storing ________
a) 1110
b) 0111
c) 1000
d) 1001
Answer: d
Explanation: Stored nibble | waiting nibble
0111 | 1110, Initially
111 | 1100, 1st pulse
11 | 1001, 2nd pulse.
226. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After

three clock pulses, the data outputs are ________
a) 1110
b) 0001
c) 1100
d) 1000
Answer: b
Explanation: Parallel in parallel out gives the same output as input. Thus, after three clock
pulses, the data outputs are 0001.
227. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel
output shift register with an initial state 11110000. After two clock pulses, the register
contains
a) 10111000
b) 10110111
c) 11110000
d) 11111100
Answer: d
Explanation: After first clock pulse, the register contains 11111000. After second clock pulse,
the register would contain 11111100. Since, the bits are shifted to the right at every clock pulse.
228. By adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a
________ ________ and ________ out register.
a) Parallel-in, serial, parallel
b) Serial-in, parallel, serial
c) Series-parallel-in, series, parallel
d) Bidirectional in, parallel, series
Answer: a
Explanation: One bit shifting takes place just after the output obtained on every register. Hence,
by adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a Parallel-
in, Serial, and Parallel-out register. Since, the bots can be inputted all at the same time, while the
data can be outputted either one at a time or simultaneously.
229. What type of register would have a complete binary number shifted in one bit at a
time and have all the stored bits shifted out one at a time?
a) Parallel-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-in Parallel-out
Answer: c
Explanation: Serial-in Serial-out register would have a complete binary number shifted in one
bit at a time and have all the stored bits shifted out one at a time. Since in serial transmission, bits
are transmitted or received one at a time and not simultaneously.
230. In a 4-bit Johnson counter sequence, there are a total of how many states, or bit
patterns?
a) 1
b) 3
c) 4
d) 8
Answer: d
Explanation: In johnson counter, total number of states are determined by 2N = 2*4 = 16
Total Number of Used states = 2N = 2*4 = 8
Total Number of Unused states = 16 – 8 = 8.
231. If a 10-bit ring counter has an initial state 1101000000, what is the state after the
second clock pulse?
a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000
Answer: b
Explanation: After shifting 2-bit we get the output as 0011010000 (Since two zeros are at
1st position and 2nd position which came from the last two bits). As in a ring counter, the bits
rotate in clockwise direction.
232. How much storage capacity does each stage in a shift register represent?
a) One bit
b) Two bits
c) Four bits
d) Eight bits
Answer: a
Explanation: A register is made of flip-flops. And each flip-flop stores 1 bit of data. Thus, a
shift register has the capability to store one bit and if another bit is to store, in such situation it
deletes the previous data and stores them.
Digital Circuits Questions and Answers – BCD Adder
on “BCD Adder”.
233. The decimal number system represents the decimal number in the form of
____________
a) Hexadecimal
b) Binary coded
c) Octal
d) Decimal
Answer: b
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers
where each decimal digit is represented by a fixed number of bits, usually four or eight.
Hexadecimal and Octal are number systems having base 16 and 8 respectively.
234. 29 input circuit will have total of ____________

a) 32 entries
b) 128 entries
c) 256 entries
d) 512 entries
Answer: d
Explanation: 29 input circuit would have 512(2*2*2*2*2*2*2*2*2 = 512) entries.
235. BCD adder can be constructed with 3 IC packages each of ____________

a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
Answer: c
where each decimal digit is represented by a fixed number of bits, usually four or eight. BCD
adder can be constructed with 3 IC packages. Each of 4-bit adders is an MSI(Medium scale
Integration) function and 3 gates for the correction logic need one SSI (Small Scale Integration)
package.
236. The output sum of two decimal digits can be represented in ____________
a) Gray Code
b) Excess-3
c) BCD
d) Hexadecimal
Answer: c
Explanation: The output sum of two decimal digits can be represented in BCD(Binary-coded
decimal). Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where
each decimal digit is represented by a fixed number of bits, usually four or eight.
237. The addition of two decimal digits in BCD can be done through ____________
a) BCD adder
b) Full adder
c) Ripple carry adder
d) Carry look ahead
Answer: a
Explanation: The addition of two decimal digits in BCD can be done through BCD adder. Every
input inserted, in addition by the user converted into binary and then proceed for the addition.
Whereas, Full Adder, Ripple Carry Adder and Carry Look Adder are for the addition of binary
bits.
238. 3 bits full adder contains ____________

a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
Answer: d
Explanation: 3 bits full adder contains 23 = 8 combinational inputs.
239. The simplified expression of full adder carry is ____________

a) c = xy+xz+yz
b) c = xy+xz
c) c = xy+yz
d) c = x+y+z
Answer: a
Explanation: A full adder is a combinational circuit having 3 inputs and 2 outputs, namely SUM
and CARRY. The simplified expression of full adder carry is c = xy+xz+yz.
240. Complement of F’ gives back __________

a) F’
b) F
c) FF
d) FF’
Answer: b
Explanation: Complement means inversion. So, complement of F’ gives back F, as per the Law
of Involution.
241. Decimal digit in BCD can be represented by ____________
a) 1 input line
b) 2 input lines
c) 3 input lines
d) 4 input lines
Answer: d
where each decimal digit is represented by a fixed number of bits, usually four or eight. Decimal
digit in BCD can be represented by 4 input lines. Since it is constructed with 4-bits.
242. The number of logic gates and the way of their interconnections can be classified as
____________
a) Logical network
b) System network
c) Circuit network
d) Gate network
Answer: a
Explanation: The number of different levels of logic gates is represented in a fashion which is
known as a logical network.
Digital Circuits Questions and Answers – Erasable Programmable Read Only

Memory
on “Erasable Programmable Read Only Memory”.
243. EPROM uses an array of _______________

a) p-channel enhancement type MOSFET
b) n-channel enhancement type MOSFET
c) p-channel depletion type MOSFET
d) n-channel depletion type MOSFET
Answer: b
Explanation: EPROMs are Erasable Programmable ROMs which can be erased using UV
radiation and re-programmed. EPROM uses an array of n-channel enhancement type MOSFET
with an insulated gate structure.
244. The EPROM was invented by ______________

a) Wen Tsing Chow
b) Dov Frohman
c) Luis O Brian
d) J P Longwell
Answer: b
Explanation: The EPROM was invented by Dov Frohman of Intel in 1971. EPROMs are
Erasable Programmable ROMs which can be erased using UV radiation and re-programmed.
245. Address decoding for dynamic memory chip control may also be used for
______________
a) Chip selection and address location
b) Read and write control
c) Controlling refresh circuits
d) Memory mapping
Answer: a
Explanation: Address decoding for dynamic memory chip control may also be used for chip
selection and address location. Chip Selection enables or disables the functioning of the chip.
246. Which of the following describes the action of storing a bit of data in a mask ROM?
a) A 0 is stored by connecting the gate of a MOS cell to the address line
b) A 0 is stored in a bipolar cell by shorting the base connection to the address line
c) A 1 is stored by connecting the gate of a MOS cell to the address line
d) A 1 is stored in a bipolar cell by opening the base connection to the address line
Answer: c
Explanation: The action of storing a bit of data in a mask ROM is that when a 1 is stored by
connecting the gate of a MOS cell to the address line. Mask ROMs are programmed by the
manufacturer and are custom made as per the user.
247. The check sum method of testing a ROM ______________

a) Allows data errors to be pinpointed to a specific memory location
b) Provides a means for locating and correcting data errors in specific memory locations
c) Indicates if the data in more than one memory location is incorrect
d) Simply indicates that the contents of the ROM are incorrect
Answer: d
Explanation: If checking of a sum method goes wrong, it simply indicates that the contents of
the ROM are incorrect.
248. The initial values in all the cells of an EPROM is ______________

a) 0
b) 1
c) Both 0 and 1
d) Alternate 0s and 1s
Answer: b
Explanation: The initial values in all the cells of a EPROM is 1.
249. To store 0 in such a cell, the floating point must be ______________

a) Reprogrammed
b) Restarted
c) Charged
d) Power off
Answer: c
radiation and re-programmed. To store 0 in the cell of an EPROM, the floating point must be
charged.
250. The major disadvantage of RAM is?
a) Its access speed is too slow
b) Its matrix size is too big
c) It is volatile
d) High power consumption
Answer: c
Explanation: RAM is volatile memory. Thus, RAM stores the data as long as it is powered on
and once the power goes out, it loses its data.
251. Which one of the following is used for the fabrication of MOS EPROM?
a) TMS 2513
b) TMS 2515
c) TMS 2516
d) TMS 2518
Answer: c
radiation and re-programmed. TMS 2516 is a MOS EPROM device.
252. How many addresses a MOS EPROM have?

a) 1024
b) 512
c) 2516
d) 256
Answer: c
radiation and re-programmed. MOS EPROM (i.e. TMS 2516) has 2048 (2^11 = 2048) addresses.
253. To read from the memory, the select input and the power down/program input must
be ______________
a) HIGH
b) LOW
c) Sometimes HIGH and sometimes LOW
d) Alternate HIGH and LOW
Answer: b
Explanation: To read from the memory, the select input and the power down/program input
must be LOW.
254. ROMs retain data when ______________

a) Power is on
b) Power is off
c) System is down
Answer: d
Explanation: ROM retains the data when power is off/on/down because it has to read the data
from memory only and it is done in every condition. It is non-volatile memory.
255. Suppose that a certain semiconductor memory chip has a capacity of 8K × 8. How
many bytes could be stored in this device?
a) 8,000
b) 65,536
c) 8,192
d) 64,000
Answer: c
Explanation: 8K = 8 * 1024 = 8192.
256. When a RAM module passes the checker board test it is ______________
a) Able to read and write only 0s
b) Faulty
c) Probably good
d) Able to read and write only 1s
Answer: c
Explanation: When a RAM module passes the checker board test it is probably good. It is a
volatile memory. Thus, RAM stores the data as long as it is powered on and once the power goes
out, it loses its data.
257. What is the difference between static RAM and dynamic RAM?
a) Static RAM must be refreshed, dynamic RAM does not
b) There is no difference
c) Dynamic RAM must be refreshed, static RAM does not
d) SRAM is slower than DRAM
Answer: c
Explanation: Dynamic RAM must be refreshed because it made up of capacitor, and capacitor
required refresh. Static RAM made up of flip flop and it doesn’t required a refresh.
Digital Circuits Questions and Answers – Asynchronous Counter
on “Asynchronous Counter”.
258. How many natural states will there be in a 4-bit ripple counter?
a) 4
b) 8
c) 16
d) 32
Answer: c
Explanation: In an n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.
259. A ripple counter’s speed is limited by the propagation delay of _____________
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
Answer: a
Explanation: A ripple counter is something that is derived by other flip-flops. It’s like a series of
Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed
of FF only and no gates are there other than FF, so only propagation delay of FF will be taken
into account. Propagation delay refers to the amount of time taken in producing an output when
the input is altered.
260. One of the major drawbacks to the use of asynchronous counters is that ____________
a) Low-frequency applications are limited because of internal propagation delays
b) High-frequency applications are limited because of internal propagation delays
c) Asynchronous counters do not have major drawbacks and are suitable for use in high- and
low-frequency counting applications
d) Asynchronous counters do not have propagation delays, which limits their use in high-
frequency applications
Answer: b
Explanation: One of the major drawbacks to the use of asynchronous counters is that High-
frequency applications are limited because of internal propagation delays. Propagation delay
refers to the amount of time taken in producing an output when the input is altered.
261. Internal propagation delay of asynchronous counter is removed by ____________

a) Ripple counter
b) Ring counter
c) Modulus counter
d) Synchronous counter
Answer: d
Explanation: Propagation delay refers to the amount of time taken in producing an output when
the input is altered. Internal propagation delay of asynchronous counter is removed by
synchronous counter because clock input is given to each flip-flop individually in synchronous
counter.
262. What happens to the parallel output word in an asynchronous binary down counter
whenever a clock pulse occurs?
a) The output increases by 1
b) The output decreases by 1
c) The output word increases by 2
d) The output word decreases by 2
Answer: b
Explanation: In an asynchronous counter, there isn’t any clock input. The output of 1st flip-flop
is given to second flip-flop as clock input. So, in case of binary down counter the output word
decreases by 1.
263. How many flip-flops are required to construct a decade counter?

a) 4
b) 8
c) 5
d) 10
Answer: a
Explanation: Number of flip-flop required is calculated by this formula: 2(n-1) <= N< = 2n.
24=16and23=8, therefore, 4 flip flops needed.
264. The terminal count of a typical modulus-10 binary counter is ____________

a) 0000
b) 1010
c) 1001
d) 1111
Answer: c
Explanation: A binary counter counts or produces the equivalent binary number depending on
the cycles of the clock input. Modulus-10 means count from 0 to 9. So, terminal count is 9
(1001).
265 How many different states does a 3-bit asynchronous counter have?
a) 2
b) 4
c) 8
d) 16
Answer: c
Explanation: In a n-bit counter, the total number of states = 2n.
266. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns
propagation delay. The total propagation delay (tp(total)) is ____________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
Answer: d
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay in
the counter occurs only due to the flip-flops. Each bit has propagation delay = 12ns. So, 5 bits =
12ns * 5 = 60ns.
267. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How
many transitional states are required?
a) 1
b) 2
c) 8
d) 15
Answer: d
Explanation: Transitional state is given by (2n – 1). Since, it’s a 4-bit counter, therefore,
transition states = 24 – 1 = 15. So, total transitional states are 15.
268. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from
clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of
____________
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
Answer: d
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay in
the counter occurs only due to the flip-flops. One bit change is 15 ns, so 4-bit change = 15 * 4 =
60.
269. Three cascaded decade counters will divide the input frequency by ____________
a) 10
b) 20
c) 100
d) 1000
Answer: d
Explanation: Decade counter has 10 states. So, three decade counters are cascaded i.e.
10*10*10=1000 states.
270. A ripple counter’s speed is limited by the propagation delay of ____________

a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
Answer: a
Explanation: A ripple counter is something that is derived by other flip-flops. Its like a series of
Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is composed
of FF only and no gates are there other than FF, so only propagation delay of FF will be taken
into account. Propagation delay refers to the amount of time taken in producing an output when
the input is altered.
271. A 4-bit counter has a maximum modulus of ____________

a) 3
b) 6
c) 8
d) 16
Answer: d
Explanation: In a n-bit counter, the total number of states = 2n.
272. A principle regarding most display decoders is that when the correct input is present,
the related output will switch ____________
a) HIGH
b) To high impedance
c) To an open
d) LOW
Answer: d
Explanation: A principle regarding most display decoders is that when the correct input is
present, the related output will switch LOW. Since it’s an active-low device.
Digital Circuits Questions and Answers – Up down counter
on “Up down counter”.
273. UP-DOWN counter is a combination of ____________

a) Latches
b) Flip-flops
c) UP counter
d) Up counter & down counter
Answer: d
Explanation: As the name suggests UP-DOWN, it means that it has up-counter and down-
counter as well. It alternatively counts up and down.
274. UP-DOWN counter is also known as ___________

a) Dual counter
b) Multi counter
c) Multimode counter
d) Two Counter
Answer: c
Explanation: UP-DOWN counter is also known as multimode counter because it has capability
of counting upward as well as downwards.
275. In an UP-counter, each flip-flop is triggered by ___________

a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop
Answer: b
Explanation: In an UP-counter, each flip-flop is triggered by the normal output of the preceding
flip-flop. UP-counter counts from 0 to a maximum value.
276. In DOWN-counter, each flip-flop is triggered by ___________
a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop
Answer: d
Explanation: In DOWN-counter, each flip-flop is triggered by the inverted output of the
preceding flip-flop. DOWN-counter counts from a maximum value to 0.
277. Binary counter that count incrementally and decrement is called ___________
a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter
Answer: a
Explanation: Binary counter that counts incrementally and decrement is called UP-DOWN
counter/multimode counter. It alternately counts up and down.
278. Once an up-/down-counter begins its count sequence, it ___________

a) Starts counting
b) Can be reversed
c) Can’t be reversed
d) Can be altered
Answer: d
Explanation: In up/down ripple counter once the counting begins, we can simply change the
pulse M (mode control) M = 0 or 1 respectively for UP counter or Down counter.
279. In 4-bit up-down counter, how many flip-flops are required?
a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: An n-bit bit counter requires n number of FFs. In a 4-bit up-down counter, there
are 4 J-K flip-flops required.
280. A modulus-10 counter must have ________

a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
d) Synchronous clocking
Answer: b
Explanation: 2n-1 < = N < = 2n
For modulus-10 counter, N = 10. Therefore, 23 < = 10 < = 24. Thus, n = 4, and therefore, we
require 4 FFs.
281. Which is not an example of a truncated modulus?

a) 8
b) 9
c) 11
d) 15
Answer: a
Explanation: An n-bit counter whose modulus is less than the maximum possible is called a
truncated counter. Here, 9, 11 and 15 modulus counters are truncated counters. Whereas,
modulus-8 is not a truncated counter.
282. The designation means that the ________
a) Up count is active-HIGH, the down count is active-LOW
b) Up count is active-LOW, the down count is active-HIGH
c) Up and down counts are both active-LOW
d) Up and down counts are both active-HIGH
Answer: a
Explanation: The designation means that the up count is active-HIGH, the down count is active-
LOW. Active-High means that up-count would be triggered when clock is 1 else when clock is 0,
down-count would be triggered, which is referred to as Active-low.
283. An asynchronous binary up counter, made from a series of leading edge-triggered flip-
flops, can be changed to a down counter by ________
a) Taking the output on the other side of the flip-flops (instead of Q)
b) Clocking of each succeeding flip-flop from the other side (instead of Q)
c) Changing the flip-flops to trailing edge triggering
Answer: d
Explanation: By all of the mentioned ideas, an asynchronous binary up counter, made from a
series of leading edge-triggered flip-flops, can be changed to a down counter. Edge-triggered FFs
refer to FFs being triggered during a clock transition from LOW to HIGH or HIGH to LOW.
284. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of
the most significant bit is ________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz
Answer: a
Explanation: Input clock is given by 20/2 kHz. So, count on the basis of 10 kHz clock. And
MSB changes on 8th stage; Hence, f = 10/8 = 1.25 kHz.
Digital Circuits Questions and Answers – Shift Registers
on “Shift Registers”.
285. Based on how binary information is entered or shifted out, shift registers are classified
into _______ categories.
a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: The registers in which data can be shifted serially or parallelly are known as shift
registers. Based on how binary information is entered or shifted out, shift registers are classified
into 4 categories, viz., Serial-In/Serial-Out(SISO), Serial-In/Parallel-Out (SIPO), Parallel-
In/Serial-Out (PISO), Parallel-In/Parallel-Out (PIPO).
286. The full form of SIPO is ___________

a) Serial-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-In Peripheral-Out
Answer: a
Explanation: SIPO is always known as Serial-in Parallel-out.
287. A shift register that will accept a parallel input or a bidirectional serial load and
internal shift features is called as?
a) Tristate
b) End around
c) Universal
d) Conversion
Answer: c
Explanation: A shift register can shift it’s data either left or right. The universal shift register is
capable of shifting data left, right and parallel load capabilities.
288. How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF
Answer: d
Explanation: Because no other flip-flops are connected with the output Q, therefore one can use
the Q out of each FF to take out parallel data.
289. What is meant by parallel load of a shift register?

a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) All FFs are set with data
Answer: a
Explanation: At Preset condition, outputs of flip-flops will be 1. Preset = 1 means Q = 1, thus
input is definitely 1.
290. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel
output shift register with an initial state 01110. After three clock pulses, the register
contains ________
a) 01110
b) 00001
c) 00101
d) 00110
Answer: c
Explanation: LSB bit is inverted and feed back to MSB:
01110->initial
10111->first clock pulse
01011->second
00101->third.
291. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store
the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit
first)
a) 1100
b) 0011
c) 0000
d) 1111
Answer: c
Explanation: In Serial-In/Serial-Out shift register, data will be shifted one at a time with every
clock pulse. Therefore,
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.
292. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble
0111 is waiting to enter. After four clock pulses, the register contains ________
a) 0000
b) 1111
c) 0111
d) 1000
Answer: c
Explanation: In Serial-In/Parallel-Out shift register, data will be shifted all at a time with every
clock pulse. Therefore,
Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk
X | 1111 4th clk.
293. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register
in ________
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
Answer: b
Explanation: f = 200 KHZ; T = (1/200) m sec = (1/0.2) micro-sec = 5 micro-sec;
In serial transmission, data enters one bit at a time. After 8 clock cycles only 8 bit will be loaded
= 8 * 5 = 40 micro-sec.
294. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to
achieve a time delay (td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us
Answer: c
Explanation: One clock period is = (½) micro-s = 0.5 microseconds. In serial transmission, data
enters one bit at a time. So, the total delay = 0.5*8 = 4 micro seconds time is required to transmit
information of 8 bits.
Digital Circuits Questions and Answers – Counters
on “Counters”.
295. In digital logic, a counter is a device which ____________

a) Counts the number of outputs
b) Stores the number of times a particular event or process has occurred
c) Stores the number of times a clock pulse rises and falls
d) Counts the number of inputs
Answer: b
Explanation: In digital logic and computing, a counter is a device which stores (and sometimes
displays) the number of times a particular event or process has occurred, often in relationship to
a clock signal.
296. A counter circuit is usually constructed of ____________

a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade form
Answer: c
Explanation: A counter circuit is usually constructed of a number of flip-flops connected in
cascade. Preferably, JK Flip-flops are used to construct counters and registers.
297. What is the maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
Answer: c
Explanation: The maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops is 0 to 2n-1. For say, there is a 2-bit counter, then it will
count till 22-1 = 3. Thus, it will count from 0 to 3.
298. How many types of the counter are there?

a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: Counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and
multi-mode & (iii)modulus counter. These further can be subdivided into Ring Counter, Johnson
Counter, Cascade Counter, Up/Down Counter and such like.
299. A decimal counter has ______ states.

a) 5
b) 10
c) 15
d) 20
Answer: b
Explanation: Decimal counter is also known as 10 stage counter. So, it has 10 states. It is also
known as Decade Counter counting from 0 to 9.
300. Ripple counters are also called ____________

a) SSI counters
b) Asynchronous counters
c) Synchronous counters
d) VLSI counters
Answer: b
Explanation: Ripple counters are also called asynchronous counter. In Asynchronous counters,
only the first flip-flop is connected to an external clock while the rest of the flip-flops have their
preceding flip-flop output as clock to them.
301. Synchronous counter is a type of ____________

a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
Answer: c
Explanation: Synchronous Counter is a Medium Scale Integrated (MSI). In Synchronous
Counters, the clock pulse is supplied to all the flip-flops simultaneously.
302. Three decade counter would have ____________

a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
Answer: b
Explanation: Three decade counter has 30 states and a BCD counter has 10 states. So, it would
require 3 BCD counters. Thus, a three decade counter will count from 0 to 29.
303. BCD counter is also known as ____________

a) Parallel counter
b) Decade counter
c) Synchronous counter
d) VLSI counter
Answer: b
Explanation: BCD counter is also known as decade counter because both have the same number
of stages and both count from 0 to 9.
304. The parallel outputs of a counter circuit represent the _____________
a) Parallel data word
b) Clock frequency
c) Counter modulus
d) Clock count
Answer: d
Explanation: The parallel outputs of a counter circuit represent the clock count. A counter
counts the number of times an event takes place in accordance to the clock pulse.
Digital Circuits Questions and Answers – Programmable Read Only Memory – 1
on “Programmable Read Only Memory -1”.
305. The time from the beginning of a read cycle to the end of tACS/tAA is called as
____________
a) Write enable time
b) Data hold
c) Read cycle time
d) Access time
Answer: d
Explanation: The time from the beginning of a read cycle to the end of tACS/tAA is called as
access time. It is the time in which data is fetched from the storage.
306. Why did PROM introduced?

a) To increase the storage capacity
b) To increase the address locations
c) To provide flexibility
d) To reduce the size
Answer: c
Explanation: In order to provide some flexibility in the possible applications of ROM, PROM is
introduced. PROM stands for Programmable ROM, in which the ROM is programmed by the
user.
307. Which of the following is programmed electrically by the user?
a) ROM
b) EPROM
c) PROM
d) EEPROM
Answer: c
Explanation: Programmable ROMs can be programmed electrically by the user but can’t be
reprogrammed. EEPROMs can be electrically erased and re-programmed by the user.
308. PROMs are available in ___________

a) Bipolar and MOSFET technologies
b) MOSFET and FET technologies
c) FET and bipolar technologies
d) MOS and bipolar technologies
Answer: d
Explanation: PROMs (Programmable ROMs) can be programmed electrically by the user but
can’t be reprogrammed. PROMs are available in both bipolar and MOS (Metal Oxide
Semiconductor) technologies.
309. The bit capacity of a memory that has 2048 addresses and can store 8 bits at each
address is ___________
a) 4096
b) 16384
c) 32768
d) 8129
Answer: b
Explanation: 1 address can store 8 bits. Therefore, total capacity of a memory having n
addresses = 8 * n.
Therefore, for 2048 addresses,
total capacity of a memory = 2048 * 8 = 16384 bits.
310. How many 8 k × 1 RAMs are required to achieve a memory with a word capacity of 8
k and a word length of eight bits?
a) Eight
b) Two
c) One
d) Four
Answer: a
Explanation: RAM stands for Random Access Memory in which any memory address can be
accessed in any order. It requires word of length 8 bits. So, one word needs of 1 bit and 8 bit
requires 8 bits.
311. Which of the following best describes the fusible-link PROM?

a) Manufacturer-programmable, reprogrammable
b) Manufacturer-programmable, one-time programmable
c) User-programmable, reprogrammable
d) User-programmable, one-time programmable
Answer: d
Explanation: The fusible-link PROM is user programmable and one time programmable. It
means that a written program can not be reprogrammed. EPROMs can be erased and re-
programmed.
312. How can ultraviolet erasable PROMs be recognized?

a) There is a small window on the chip
b) They will have a small violet dot next to the #1 pin
c) Their part number always starts with a “U”, such as in U12
d) They are not readily identifiable, since they must always be kept under a small cover
Answer: a
Explanation: An ultraviolet erasable PROMs have small window on the chip with black
marked. Such type of PROMS are called EPROMS which are cleared by exposing it to UV
radiation. They are re-programmable.
313. Which part of a Flash memory architecture manages all chip functions?
a) Program verify code
b) Floating-gate MOSFET
c) Command code
d) Input/Output pins
Answer: b
Explanation: MOSFET technology is the best one in the manufacturing of chip because it has
high flexibility and storage capacity. Thus, Floating-Gate MOSFET part of a Flash Memory
architecture manages all chip functions.
314. How much locations an 8-bit address code can select in memory?
a) 8 locations
b) 256 locations
c) 65,536 locations
d) 131,072 locations
Answer: b
Explanation: An 8 bit address code requires 32 memory locations and it can hold maximum
upto 32 * 8 = 256 locations = 28.
315. What is a fusing process?

a) It is a process by which data is passed to the memory
b) It is a process by which data is read through the memory
c) It is a process by which programs are burnout to the diode/transistors
d) It is a process by which data is fetched through the memory
Answer: c
Explanation: Fusing is a process by which programs are burnout to the diode/transistors and it
can not be reprogrammed if any error occurs.
316. Fusing process is ___________
a) Reversible
b) Irreversible
c) Synchronous
d) Asynchronous
Answer: b
Explanation: Since, any program cannot be reprogrammed in a PROM, so this process is
irreversible as PROMs are programmed using the Fusing process. Fusing is a process by which
programs are burnout to the diode/transistors and it can not be reprogrammed if any error occurs.
317. The cell type used inside a PROM is ___________

a) Link cells
b) Metal cells
c) Fuse cells
d) Electric cells
Answer: c
Explanation: The cell type used inside a PROM is fuse cells by which a program is burnout.
Fusing is a process by which programs are burnout to the diode/transistors and it can not be
reprogrammed if any error occurs.
318. How many types of fuse technologies are used in PROMs?

a) 2
b) 3
c) 4
d) 5
Answer: b
Explanation: Fusing is a process by which programs are burnout to the diode/transistors and it
can not be reprogrammed if any error occurs. Three types of fuse technologies are used in
PROMs and these are: (i) Metal links, (ii) Silicon links, & (iii) p-n junctions.
319. Metal links are made up of ___________
a) Polycrystalline
b) Magnesium sulphide
c) Nichrome
d) Silicon dioxide
Answer: c
Explanation: Metal links are made up of Nichrome materials.
Digital Circuits Questions and Answers – Programmable Read Only Memory
This set of Digital Electronic/Circuits Problems focuses on “Programmable Read Only

Memory”.
320. Silicon links are made up of _____________

a) Polycrystalline silicon
b) Polycrystalline magnesium
c) Nichrome
d) Silicon dioxide
Answer: a
Explanation: Metal links are made up of Nichrome materials. Silicon links are made up of
polycrystalline silicon.
322. During programming p-n junction is _____________

a) Avalanche reverse biased
b) Avalanche forward biased
c) Zener reverse biased
d) Zener reverse biased
Answer: a
Explanation: The sudden heavy flow of electrons in the reverse direction and heat cause
aluminium ions to migrate. So, during programming p-n junction is avalanche reversed biased.
323. The full form of FAMOS is _____________
a) Floating Gate Avalanche Injection MOS
b) Float Gate Avalanche Injection MOS
c) Floating Gate Avalanche Induction MOS
d) Float Gate Avalanche Induction MOS
Answer: a
Explanation: The full form of FAMOS is Floating Gate Avalanche Injection MOS. It is a
floating gate transistor in which the trapped electrons is responsible for the dropping of the
voltage.
324. PROM is programmed by _____________

a) EPROM programmer
b) EEPROM programmer
c) PROM programmer
d) ROM programmer
Answer: c
Explanation: PROM is programmed by plugging it into a special device called PROM
programmer. The ROM cannot be clear and hence PROM is a one-time programmable device.
325. The PROM starts out with _____________

a) 1s
b) 0s
c) Null
d) Both 1s and 0s
Answer: b
Explanation: PROM is a one-time programmable device, which is programmed by the user. The
PROM starts out with all 0s. These current pulses blow the fuse links, thus creating the desire
pattern.
326. For implementation of PROM, which IC is used?
a) IC 74187
b) IC 74186
c) IC 74185
d) IC 74184
Answer: b
Explanation: For implementation of PROM, IC 74186 is used. IC 74186 is of 512 bits (62 * 8 =
512). Thus, it has 62 rows and 8 columns.
327. IC 74186 is of ______________

a) 1024 bits
b) 32 bits
c) 512 bits
d) 64 bits
Answer: c
Explanation: IC 74186 is of 512 bits (62 * 8 = 512). Thus, it has 62 rows and 8 columns.
328. How many memory locations are addressed using 18 address bits?
a) 165,667
b) 245,784
c) 262,144
d) 212,342
Answer: c
Explanation: For n address bits, the memory location will consist of 2n bits. Using 18 address
bits, 2^18 = 262,144 (= 256 K) words are addressed.
329. How many address bits are needed to operate a 2K * 8-bit memory?
a) 10
b) 11
c) 12
d) 13
Answer: b
Explanation: For n address bits, the memory location will consist of 2n bits. Thus, for 2K, only
11 address bits are required, because 211 = 2K.
330. What is the bit storage capacity of a ROM with a 1024 × 8 organization?
a) 1024
b) 4096
c) 2048
d) 8192
Answer: d
Explanation: For n address bits, the memory location will consist of 2n bits. 1024 = 210. So,
210 * 23 = 1024 * 8 = 8192 bit.
Digital Circuits Questions and Answers – Sum of Products and Products of Sum
on “Sum of Products and Products of Sum”.
331. The logical sum of two or more logical product terms is called __________
a) SOP
b) POS
c) OR operation
d) NAND operation
Answer: a
Explanation: The logical sum of two or more logical product terms, is called SOP (i.e. sum of
product). The logical product of two or more logical sum terms, is called POS (i.e. product of
sums).
332. The expression Y=AB+BC+AC shows the _________ operation.
a) EX-OR
b) SOP
c) POS
d) NOR
Answer: b
Explanation: The given expression has the operation product as well as the sum of that. So, it
shows SOP operation. POS will be the product of sum terms.
333. The expression Y=(A+B)(B+C)(C+A) shows the _________ operation.

a) AND
b) POS
c) SOP
d) NAND
Answer: b
Explanation: The given expression has the operation sum as well as the product of that. So, it
shows POS(product of sum) operation. SOP will be the sum of product terms.
334. A product term containing all K variables of the function in either complemented or
uncomplemented form is called a __________
a) Minterm
b) Maxterm
c) Midterm
d) ∑ term
Answer: a
Explanation: A product term containing all K variables of the function in either complemented
or uncomplemented form is called a minterm. A sum term containing all K variables of the
function in either complemented or uncomplemented form is called a maxterm.
335. According to the property of minterm, how many combination will have value equal to
1 for K input variables?
a) 0
b) 1
c) 2
d) 3
Answer: b
Explanation: The main property of a minterm is that it possesses the value 1 for only one
combination of K input variables and the remaining will have the value 0.
336. The canonical sum of product form of the function y(A,B) = A + B is __________
a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) AB’ + A’B + A’B’
Answer: b
Explanation: A + B = A.1 + B.1 = A(B + B’) + B(A + A’) = AB + AB’ + BA +BA’ = AB +
AB’ + A’B = AB + AB’ + A’B.
337. A variable on its own or in its complemented form is known as a __________

a) Product Term
b) Literal
c) Sum Term
d) Word
Answer: b
Explanation: A literal is a single logic variable or its complement. For example — X, Y, A’, Z,
X’ etc.
338. Maxterm is the sum of __________ of the corresponding Minterm with its literal
complemented.
a) Terms
b) Words
c) Numbers
d) Nibble
Answer: a
Explanation: Maxterm is the sum of terms of the corresponding Minterm with its literal
complemented.
339. Canonical form is a unique way of representing ____________

a) SOP
b) Minterm
c) Boolean Expressions
d) POS
Answer: c
Explanation: Boolean Expressions are represented through canonical form. An example of
canonical form is A’B’C’ + AB’C + ABC’.
340. There are _____________ Minterms for 3 variables (a, b, c).

a) 0
b) 2
c) 8
d) 1
Answer: c
Explanation: Minterm is given by 2n. So, 23 = 8 minterms are required.
341. _____________ expressions can be implemented using either (1) 2-level AND-OR logic
circuits or (2) 2-level NAND logic circuits.
a) POS
b) Literals
c) SOP
d) POS
Answer: c
Explanation: SOP expressions can be implemented using either (1) 2-level AND-OR logic
circuits or (2) 2-level NAND logic circuits.
Digital Circuits Questions and Answers – Demultiplexers (Data Distributors) – 2
This set of Digital Electronic/Circuits Multiple Choice Questions & Answers focuses on
“Demultiplexers(Data Distributors) – 2”.
342. Why is a demultiplexer called a data distributor?

a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input gives single output
Answer: a
Explanation: A demultiplexer sends a single input to multiple outputs, depending on the select
lines. For one input, the demultiplexer gives several outputs. That is why it is called a data
distributor.
343. Most demultiplexers facilitate which type of conversion?

a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Answer: b
lines. Demultiplexer converts single input into multiple outputs.
345. In 1-to-4 demultiplexer, how many select lines are required?

a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: The formula for total no. of outputs is given by 2n, where n is the no. of select
lines. Therefore, for 1:4 demultiplexer, 2 select lines are required.
346. In a multiplexer the output depends on its ____________

a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
Answer: b
lines. As the select input changes, the output of the multiplexer varies according to that input.
347. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ____________

a) Y0
b) Y1
c) Y2
d) Y3
Answer: d
Explanation: It can be calculated from the figure shown below:
For C0 =1 and C1 =1, Y3 will be the output as 0 and 1 are the bit combinations of 1.
348. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
Answer: b
lines. In this case n = 3 since 23 = 8.
349. How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 8
d) 5
Answer: c
Explanation: The number of AND gates required will be equal to the number of outputs in a
demultiplexer, which are 8.
350. Which IC is used for the implementation of 1-to-16 DEMUX?
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answer: a
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is
inverted input.
Digital Circuits Questions and Answers – Demultiplexers (Data Distributors) – 1

on “Demultiplexers (Data Distributors) – 1”.
351. The word demultiplex means ___________

a) One into many
b) Many into one
c) Distributor
d) One into many as well as Distributor
Answer: d
Explanation: The word demultiplex means “one into many” and distributor. A demultiplexer
sends a single input to multiple outputs, depending on the select lines. It is clear from the
diagram:
352. Why is a demultiplexer called a data distributor?
a) The input will be distributed to one of the outputs
b) One of the inputs will be selected for the output
c) The output will be distributed to one of the inputs
d) Single input to Single Output
Answer: a
lines. For one input, the demultiplexer gives several outputs. That is why, it is called a data
distributor.
353. Most demultiplexers facilitate which type of conversion?

a) Decimal-to-hexadecimal
b) Single input, multiple outputs
c) AC to DC
d) Odd parity to even parity
Answer: b
lines. Demultiplexer converts single input into multiple outputs.
354. In 1-to-4 demultiplexer, how many select lines are required?

a) 2
b) 3
c) 4
d) 5
Answer: a
lines. Therefore, for 1:4 demultiplexer, 2 select lines are required.
355. In a multiplexer the output depends on its ___________
a) Data inputs
b) Select inputs
c) Select outputs
d) Enable pin
Answer: b
lines. As the select input changes, the output of the multiplexer varies according to that input.
356. In 1-to-4 multiplexer, if C1 = 0 & C2 = 1, then the output will be ___________

a) Y0
b) Y1
c) Y2
d) Y3
Answer: b
357. In 1-to-4 multiplexer, if C1 = 1 & C2 = 1, then the output will be ___________
a) Y0
b) Y1
c) Y2
d) Y3
Answer: d
358. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3
c) 4
d) 5
Answer: b
lines. In this case n = 3 since 23 = 8.
359. How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 8
d) 5
Answer: c
Explanation: The number of AND gates required will be equal to the number of outputs in a
demultiplexer, which are 8.
360. The output Q4 of this 1-to-8 demultiplexer is ____________

a) Q2.(Q1)’.Q0.I
b) Q2.Q1.(Q0)’.I
c) Q2.(Q1)’.(Q0)’.I
d) Q2.(Q1).Q0.I
Answer: c
Explanation: The output Y4 = Q2.(Q1)’.(Q0)’.I. since the bit combinations of 4 are 100.
361. Which IC is used for the implementation of 1-to-16 DEMUX?

a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138
Answer: a
Explanation: IC 74154 is used for the implementation of 1-to-16 DEMUX, whose output is
inverted input.
Digital Circuits Questions and Answers – Arithmetic Operation
on “Arithmetic Operation”
362. What is the addition of the binary numbers 11011011010 and 010100101?
a) 0111001000
b) 1100110110
c) 11101111111
d) 10011010011
Answer: c
Explanation: The rules for Binary Addition are :
0+0=0
0+1=1
1+0=1
1 + 1 = 0 ( Carry 1)
1
11011011010
+00010100101
_______________________
11101111111
_______________________
363. Perform binary addition: 101101 + 011011 = ?

a) 011010
b) 1010100
c) 101110
d) 1001000
Answer: d
Explanation:The rules for Binary Addition are :
0+0=0
0+1=1
1+0=1
1 + 1 = 0 ( Carry 1)
111111
101101
+011011
_______________
1001000
_______________
Therefore, the addition of 101101 + 011011 = 1001000.

364. Binary subtraction of 100101 – 011110 is
a) 000111
b) 111000
c) 010101
d) 101010
Answer: a
Explanation: The rules for Binary Subtraction are :
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
100101
-011110
___________
000111
___________
Therefore, The subtraction of 100101 – 011110 = 000111.
365. Perform multiplication of the binary numbers: 01001 × 01011 = ?

a) 001100011
b) 110011100
c) 010100110
d) 101010111
Answer: a
Explanation: The rules for binary multiplication are:
0*0=0
0*1=0
1*0=0
1*1=1
01001
x01011
____________
01001
010010
0000000
01001000
000000000
___________________
001100011
___________________
Therefore, 01001 × 01011 = 001100011.
366. 100101 × 0110 = ?

a) 1011001111
b) 0100110011
c) 101111110
d) 0110100101
Answer: c
0*0=0
0*1=0
1*0=0
1*1=1
100101
x 0110
___________
000000
1001010
10010100
000000000
__________________
011011110
___________________
Therefore, 100101 x 0110 = 011011110.
367. On multiplication of (10.10) and (01.01), we get

a) 101.0010
b) 0010.101
c) 011.0010
d) 110.0011
Answer: c
0*0=0
0*1=0
1*0=0
1*1=1
1 0.1 0
x 0 1.0 1
__________
1010
00000
101000
0000000
_______________
0 1 1.0 0 1 0
_________________
Therefore, 10.10 x 01.01 = 011.0010.

368. Divide the binary numbers: 111101 ÷ 1001 and find the remainder
a) 0010
b) 1010
c) 1100
d) 0011
Answer: d
Explanation: Binary Division is accomplished using long division method.
1001)111101(11
1001
__________
01100
1001
___________
0111
Therefore, the remainder of 111101 ÷ 1001 = 0111.
369. Divide the binary number (011010000) by (0101) and find the quotient
a) 100011
b) 101001
c) 110010
d) 010001
Answer: b
Explanation:
0101)011010000(010111
0000
_____________________
01101
00101
______________
010000
000000
______________________
10000
00101
____________________
010110
000101
____________________
100010
000101
________________________
111010
000101
________________________
10101
00101
________________________
10000
Therefore, the quotient of 011010000 ÷ 1001 = 101001.
370. Binary subtraction of 101101 – 001011 = ?

a) 100010
b) 010110
c) 110101
d) 101100
Answer: a
Explanation: The rules for binary subtraction are:
0–0=0
0 – 1 = 1 ( Borrow 1)
1–0=1
1–1=0
101101
-001011
____________
100010
____________
Therefore, the subtraction of 101101 – 001011 = 100010.
VHDL Questions and Answers – Designing Counters with VHDL

This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Designing
Counters with VHDL”.
371. Which of the following flip-flop is used by the ring counter?

a) D flip-flops
b) SR flip-flops
c) JK flip-flops
d) T flip-flops
Answer: a
Explanation: Ring counter comprises of a few single bit D flip-flops, one flip-flop for one data
bit, either a logic 1 or a 0. They are connected together to form a sequence so that the output
from the first flip-flop becomes the input of the second flip-flop and so on.
372. ‘shift_reg’ is used to initialize the _____________ in the shift register.

a) LSB
b) MSB
c) Register type
d) Register bits
Answer: b
Explanation: Shift register uses ‘shift_reg’ for the initialization. It sets the value of MSB in the
shift register with the following code:
(signal shift_reg : STD_LOGIC_VECTOR(7 downto 0) := X”80″;)
373. How many types of shift operators are there in VHDL?
a) Three
b) Four
c) Five
d) Six
Answer: d
Explanation: There are six types of shift operators in VHDL: rol (rotate left logical), ror (rotate
right logical), sll (shift left logical), srl (shift right logical), sla (shift left arithmetic), sra (shift
right arithmetic).
374. How many types of the data type are there in the ring counter?
a) One
b) Two
c) Three
d) More than three
Answer: d
Explanation: There are more than three data types in VHDL, some of them are:
STD_LOGIC_VECTOR data type – for more than one bit, the STD_LOGIC data type – for a
single bit, the BIT_VECTOR data type – for two or more bits, STD_LOGIC_UNSIGNED data
type – for addition and subtraction.
375. In __________ counter universal clock is not used.

a) Synchronous counter
b) Asynchronous counter
c) Decade counter
d) Ring counter
Answer: b
Explanation: In asynchronous counter, the universal clock is not used, only the first flip-flop is
operated by the main clock and output of the previous flip-flops operates the clock input of the
rest of the counters.
376. Synchronous counter use ________ global clock, unlike asynchronous counter.
a) One
b) Two
c) Three
d) zero
Answer: a
Explanation: Synchronous counter use one global clock that operates each flip flop and changes
the output in parallel. One advantage of the synchronous counter as compared to asynchronous
counter is, it can work on a much higher frequency than the asynchronous counter.
377. How many different states does a decade counter count?

a) Eight
b) Nine
c) Ten
d) Eleven
Answer: c
Explanation: Ten different states are counted by a decade counter. It then resets to its initial
state. A simple decade counter counts from 0 to 9. Also, counters could be made which can go
through any ten states between 0 to 15.
378. The number of flip-flops used in a counter is _________ number of states in the
counter.
a) Greater than
b) Less than
c) Equal to
d) Greater than equal to
Answer: d
Explanation: Number of flip-flops used in a counter is greater than equal to the number of states
in the counter. It can be calculated by using ‘log2 n’ where n=number of states in the counter.
379. Two decade counters cascaded together will divide the input frequency by ________
a) 10
b) 100
c) 1000
d) 10000
Answer: b
Explanation: A decade counter has 10 states, so it divides the input frequency by 10. Two
decade counters will divide the input frequency by 10*10=100.
VHDL Questions and Answers – Designing Moore Type FSM with VHDL
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Designing Moore
Type FSM with VHDL”.
380. Output values of Moore type FSM are determined by its ________
a) Input values
b) Output values
c) Clock input
d) Current state
Answer: d
Explanation: The output values of a Moore type FSM are determined only by its current state.
The output is computed by the state outputs which serve as the input in the flip-flop. The output
changes synchronously with the clock edge and state transition.
381.What happens if the input is high in FSM?

a) Change of state
b) No transition in state
c) Remains in a single state
d) Invalid state
Answer: a
Explanation: The system changes the state as long the input is high. The system also has an
output which is 1 if the input is high since there is a change in state which leads to the output.
382. What happens if the input is low in FSM?

a) Change of state
b) No transition in state
c) Remains in a single state
d) Invalid state
Answer: b
Explanation: There is no transition in the state if the input is low. If the system is in a particular
state, it remains in that state only until the input becomes high. The system also has an output
which is 0 if the input is low since there is no change in the state, it doesn’t reach the output
state.
383.. In FSM diagram what does circle represent?

a) Change of state
b) State
c) Output value
d) Initial state
Answer: b
Explanation: In FSM diagram circle represent the states. For example: Assume there are four
states in an FSM i.e. A, B, C and D. The encircled one out of the four will represent the state. If
B is encircled, it shows FSM is in state B.
384. In the FSM diagram, what does arrow between the circles represent?
a) Change of state
b) State
c) Output value
d) Initial state
Answer: a
Explanation: In the FSM diagram, arrows between the circles represent the change of one state
to another state. For example: Assume there are four states in an FSM i.e. A, B, C and D. The
arrow between the states A and B show the transition of state from A to B.
385.. In the FSM diagram, what does the information below the line in the circle represent?
a) Change of state
b) State
c) Output value
d) Initial state
Answer: c
Explanation: In the FSM diagram the information below the line in the circle represents the
output value when in each state. It is represented by 1 and 0. If there is a state change then 1,
otherwise 0.
386. Moore machine has _________ states than a mealy machine.

a) Fewer
b) More
c) Equal
d) Negligible
Answer: b
Explanation: In Moore type FSM, more logic is required to decipher the outputs which result in
more circuit delays. Moore machines generally respond one clock cycle later while mealy
machines respond in the same clock cycle. That is why Moore machines require more states.
389. State transition happens _______ in every clock cycle.

a) Once
b) Twice
c) Thrice
d) Four times
Answer: a
Explanation: Every arrow shows a transition from one state to another, transition of state
happens once in one clock cycle. Depending on the present input, it may go to a different state
every time so there is a change of state only one time.
VHDL Questions and Answers – Designing Mealy Type FSM with VHDL
This set of VHDL Puzzles focuses on “Designing Mealy Type FSM with VHDL”.
390. Output values of mealy type FSM are determined by its ________
a) Input values
b) Output values
c) Both input values and current state
d) Current state
Answer: c
Explanation: The output values of a mealy type FSM are determined by its current state and
present input values both. Output can change after a change at the inputs immediately,
independent of the clock.
391. What kind of output does mealy machine produce?

a) Asynchronous
b) Synchronous
c) Level
d) Pulsed
Answer: a
Explanation: Output of the mealy type FSM is asynchronous it can change in response to any
change in the input regardless of the clock. Moore type FSM gives a synchronous output.
392. States in FSM are represented by ________
a) Bits
b) Bytes
c) Word
d) Character
Answer: a
Explanation: Transition states in FSM are represented by bits. The number of bits that are
required to represent all the states in FSM is equal to the number of flip-flops required to
implement that state machine.
393. What is the first step in writing the VHDL for an FSM?
a) To define the VHDL entity
b) Naming the entity
c) Defining the data type
d) Creating the states
Answer: a
Explanation: The first step in writing the VHDL for an FSM is defining the VHDL entity. The
VHDL entity defines the external interface of the system that is being designed, which includes
the name of the entity, the inputs and the outputs.
394. Which of the following react faster to inputs?

a) Sequencer
b) Generators
c) Mealy machines
d) Moore machines
Answer: c
Explanation: Mealy machines react faster to the inputs because they react in the same cycle,
they don’t wait for the clock. Moore machines react one cycle later.
395. What is the first state of FSM?
a) Wait loop state
b) Initial state
c) Output state
d) Activate pulse state
Answer: b
Explanation: The first state of the finite state machine is the initial-standby state. It waits until a
1 is read at the input to get started. It then goes to activate pulse state and transmits a high pulse.
396. Mealy machines have _________ states than Moore machine.

a) Fewer
b) More
c) Equal
d) Negligible
Answer: a
Explanation: Mealy machines have fewer states than Moore machine because they respond
faster to the input in one cycle only, as they don’t have to wait for the clock. Moore machines
generally respond one clock cycle later.
397. In mealy type FSM, the path is labelled by which of the following?
a) Inputs
b) Outputs
c) Both inputs and outputs
d) Current state
Answer: c
Explanation: In mealy machines, each transition path is labelled with both, the inputs and the
outputs and the circle contains the code for the internal state. In Moore machines path is labelled
only with the inputs and the circle contains the output and the state code.
VHDL Questions and Answers – Implementing Combinational Circuits with VHDL – 2
This set of Tough VHDL Questions and Answers focuses on “Implementing Combinational
Circuits with VHDL – 2”.
398. The process statement used in combinational circuits is called ______ process.
a) Combinational
b) Clocked
c) Unclocked
d) Sequential
Answer: a
Explanation: The process, in which no clock signal is used, is called a combinational process. In
a combinational process, the sensitivity list doesn’t include any clock signal for synchronization.
In the case of sequential circuits the clock signal is used.
399. Why we need to include all the input signals in the sensitivity list of the process?
a) To monitor the output continuously
b) To monitor the input continuously
c) To make the circuit synthesizable by EDA tools
d) No special purpose
Answer: b
Explanation: If the input signals are not in the sensitivity list of the process, then one can’t
monitor the change in input. Any change in input signal will not change the output
simultaneously by running the process again.
400. If only two bit vectors are allowed to use in the VHDL code, then how many number of
MUX will be required to implement 4 to 1 MUX?
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: Since we have inputs with two bits only, so we can use 2 to 1 MUX to implement
the required design. So, to design 4 to 1 MUX, we need 3 2 to 1 MUX and hence we can get the
desired circuit by using 3 multiplexers.
401. A package is designed called mux4to1_package, in which a component called mux4to1

is defined, which is a 4 to 1 multiplexer. Now a user wants to design a 16 to 1 MUX by using
the same component only, how many times he needs to use the PORT MAP statement?
a) 2
b) 3
c) 4
d) 5
Answer: d
Explanation: The problem statement says that a 16:1 MUX is to be designed by using 4:1
multiplexers only. This can be done by using 5 numbers of 4 to 1 multiplexers. Here, 4 MUXs
are required to collect all the inputs and one is used to select one from the 4 multiplexers outputs.
402. In designing a 2 to 1 demultiplexer with input d, output y and select line s, which of the
following is a correct process statement?
a) PROCESS(d)
b) PROCESS(d(0), d(1), s)
c) PROCESS(d(0), d(1))
d) PROCESS(d, s, y)
Answer: a
Explanation: In a combinational process, the sensitivity list must include all the inputs. For a 2
to 1 MUX, there must be 2 inputs which are d(0) and d(1); also the process should be sensitive to
the select line, so s also should be in the sensitivity list.
403. The given code represents a convertor. Which kind of convertor it is?
ENTITY convert IS
PORT(b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
x : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END convert;
ARCHITECTURE convertor OF covert IS
BEGIN
PROCESS(b)
BEGIN
CASE b IS
WHEN “0000” => x <= “1111110”;
WHEN “0001” => x <= “0110000”;
WHEN “0010” => x <= “1101101”;
WHEN “0011” => x <= “1111001”;
WHEN “0100” => x <= “0110011”;
WHEN “0101” => x <= “1011011”;
WHEN “0110” => x <= “1011111”;
WHEN “0111” => x <= “1110000”;
WHEN “1000” => x <= “1111111”;
WHEN “1001” => x <= “1110011”;
WHEN OTHERS => x <= “0000000”;
END CASE;
END PROCESS;
END convertor;
a) Gray to BCD
b) 7 segment to BCD
c) BCD to gray
d) BCD to 7 segment display
Answer: d
Explanation: Clearly, it is a BCD to 7 segment display convertor. This circuit takes a 4 bit BCD
input and convert it into 7 bits output which may be used for LED output and hence the 7
segment display can be operated.
404. What is the function of the below code?
ENTITY my_logic IS
PORT (din : STD_LOGIC_VECTOR(7 DOWNTO 0);
Count : STD_LOGIC_VECTOR(3 DOWNTO 0));
END my_logic;
ARCHITECTURE behavior OF my_logic IS
BEGIN
Count <= “0000”
PROCESS(din)
BEGIN
L1: FOR i IN 0 TO 7 LOOP
IF(din(i) = ‘1’) THEN
Count = count+1;
ELSE
NEXT L1;
END LOOP;
END PROCESS;
END behavior;
a) To count number of ones in the given data

b) To count number of zeroes in the given data
c) To reverse the order of given data
d) To perform binary multiplication of two data inputs
Answer: a
Explanation: Because a loop is used and din is monitored for every bit. If any bit in the din is
one then the counter is incremented by one. Therefore, the code is counting the number of ones
in a given vector of bits.
405. What will be the value of count output, if the data din is 11001111?
ENTITY my_logic IS
PORT (din : STD_LOGIC_VECTOR(7 DOWNTO 0);
Count : STD_LOGIC_VECTOR(3 DOWNTO 0));
END my_logic;
ARCHITECTURE behavior OF my_logic IS
BEGIN
Count <= “0000”
PROCESS(din)
BEGIN
L1: FOR i IN 0 TO 7 LOOP
IF(din(i) = ‘1’) THEN
Count = count+1;
ELSE
NEXT L1;
END LOOP;
END PROCESS;
END behavior;
a) 6
b) 0110
c) 2
d) 0010
Answer: b
Explanation: The count is a signal of bit vector type and hence the output will be a stream of
bits. In this case there are 6 ones in the input, which corresponds to 0110 in the binary number
system.
VHDL Questions and Answers – Designing Shift Registers with VHDL
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Designing Shift
Registers with VHDL”.
406. Shift registers comprise of which flip-flops?

a) D flip-flops
b) SR flip-flops
c) JK flip-flops
d) T flip-flops
Answer: a
Explanation: Shift registers comprise of a few single bit D flip-flops, one flip-flop for one data
bit, either logic “1” or a “0”. They are connected together to form a sequence so that the output
from the first flip-flop becomes the input of the second flip-flop and so on.
407. In serial input serial output register, the data of ______ is accessed by the circuit.
a) Last flip-flop
b) First flip-flop
c) All flip-flops
d) No flip-flop
Answer: b
Explanation: In serial input serial output register, the data of first flip-flop is accessed by the
rest of the circuit and in serial input parallel output register, the data of the last flip-flop is
accessed by the circuit.
408. In PIPO shift register, parallel data can be taken out by ______
a) Using the Q output of the first flip-flop
b) Using the Q output of the last flip-flop
c) Using the Q output of the second flip-flop
d) Using the Q output of each flip-flop
Answer: d
Explanation: In PIPO shift register there are parallel input pins to which data is presented in a
parallel format and then the data is transferred to their respective output pins altogether by the
same clock pulse. One clock pulse unloads and loads the data of one register, which requires it to
use all the output pins of each and every flip-flop.
409. Four bits shift register enables shift control signal in how many clock pulses?
a) Two clock pulses
b) Three clock pulses
c) Four clock pulses
d) Five clock pulses
Answer: c
Explanation: One bit is shifted into the register in one clock cycle for data conversion so four
bits will be shifted into the register in four clock pulses.
410. Time taken by the shift register to transfer the content is called _______
a) Clock duration
b) Bit duration
c) Word duration
d) Duration
Answer: c
Explanation: Serial computer needs less hardware because one circuit can be used over and over
again to manipulate the bits that come out of the shift register. The time required by the shift
register to shift the entire content is called word duration.
411. Transfer of one bit of information at a time is called _______

a) Rotating
b) Serial transfer
c) Parallel transfer
d) Shifting
Answer: b
Explanation: Movement of data at a rate of one bit per clock pulse from one end of the shift
register to the other end is called serial transfer. Movement of data into all flip-flops at the same
time is called parallel transfer.
412. In gated D latch, which of the following is the input symbol?

a) D
b) Q
c) EN
d) CLK
Answer: a
Explanation: In the gated D latch, D is the data input, EN is active high enable, Q is the data
output, CLK is the clock pulse.
413. Which register is used in the following code?
library ieee;
use ieee.std_logic_1164.all;
entity shift_siso is
port (Clock, Sin : in std_logic;
Sout : out std_logic);
end shift_siso;
architecture behav of shift_siso is
signal temp: std_logic_vector(7 downto 0);
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
for i in 0 to 6 loop
temp(i+1) <= temp(i);
end loop;
temp(0) <= Sin;
end if ;
end process;
Sout <= temp(7);
end behav;
a) Serial in serial out

b) Serial in parallel out
c) Parallel in parallel out
d) Parallel in serial out
Answer: a
Explanation: In the above code, serial in serial out 8-bit register is used. It delays the data and
stores it for each register. It may be 64 bits in length, longer if registers and packages are
cascaded.
VHDL Questions and Answers – Package
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Package”.
414. Which of the following is true about packages?

a) Package is collection of libraries
b) Library is collection of packages
c) Package is collection of entities
d) Entity is collection of packages
Answer: b
Explanation: A library contains many packages and it is used to collect and describe elements
that can be shared globally among all the design units. It may contain any commonly used data
type, functions or constants.
415. A package may consist of _________ design units.
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: A package may consist of two separate design units which are package declaration
and package body. Package declaration is necessary part for any package whereas package body
is an optional part. Package declaration, like entity declaration, describes the interface of the
design and package body is similar to architecture in the VHDL code.
416. Any item declared in a package declaration section are visible to _______
a) Every design unit
b) Package body only
c) Library containing that package
d) Design unit that USE the package
Answer: d
Explanation: To use any component, constant, signal, subprogram or function declared in a
package, one needs to declare the package in the code itself by using the USE clause. When the
package is declared in the library declaration part of the code then the functions or datatypes
defined in the package will be visible to the design unit.
417. What do you call a constant declared in the package declaration, without its initial
value specified?
a) Constant
b) Package constant
c) Deferred constant
d) Undefined constant
Answer: c
Explanation: Deferred constants are constants that have their name and type declared in the
package declaration section but the actual value is specified in the package body section. It is
important to use package body when a deferred constant is declared in the package declaration
body.
418. Which of the following is the correct syntax to declare a package?

a)
PACKAGE package_name IS
declarations;
END package_name;
PACKAGE BODY package_name IS
Functions and procedures descriptions;
END package_name;
b)
declarations;
PACKAGE BODY package_body_name IS
END package_name;
c)
declarations;
END package_name;
PACKAGE BODY package_body_name IS
END package_name;
d)
declarations;
PACKAGE BODY package_name IS
END package_name;
Answer: a
Explanation: The PACKAGE keyword is followed by the name of package and after which
there is an declaration part of the package. If any subprogram or deferred constant is declared in
the package declaration, then a package body must be defined. Note that the package body
doesn’t have a separate name. It uses the same name as that of package.
419. How to use a package in a VHDL design unit?

a)
USE PACKAGE package_name.part;
b)
LIBRARY library_name;
USE package_name.part;
c)
LIBRARY library_name;
USE library_name.package_name.part;
d)
USE library_name.package_name;
Answer: c
Explanation: To use a package, first we want to define the library in which it is actually
declared. After that to use the package, we need to use the USE clause which is followed by
library name and the package name and then the part of package which we need to include to the
design.
420. Which of the following package is not synthesizable?

a)
PACKAGE my_pack IS
SIGNAL x : IN std_logic;
END my_pack;
b)
PACKAGE my_pack IS
CONSTANT x : INTEGER := 5;
END my_pack;
c)
PACKAGE my_pack IS
FUNCTION my_func RETURN BOOLEAN IS;
END my_pack;
PACKAGE BODY my_pack IS
Function description;
END my_pack;
d)
PACKAGE my_pack IS
TYPE color IS (red, green, blue);
END PACKAGE;
Answer: a
Explanation: Though it is possible to use and declare signals in packages but signal declaration
may cause some problems in synthesis because a signal can’t be shared by two entities.
However, it is possible to declare global signals in the design itself.
421. Among which of the following, it is necessary to declare a package body?

a)
PACKAGE my_pack IS
SIGNAL x : IN std_logic;
END my_pack;
b)
PACKAGE my_pack IS
CONSTANT x : INTEGER := 5;
END my_pack;
c)
PACKAGE my_pack IS
FUNCTION my_func RETURN BOOLEAN IS;
END my_pack;
d)
PACKAGE my_pack IS
TYPE color IS (red, green, blue);
END PACKAGE;
Answer: c
Explanation: Package declaration is always mandatory but package body is optional. When a
function or deferred constant is declared in the package declaration, then it is necessary to use a
package body so as to assign value to the constant or to describe the function.
422. Which of the following is not a in-built package in VHDL?
a) STD_LOGIC_1164
b) TEXTIO
c) STANDARD
d) STD
Answer: d
Explanation: STD is not a package but it is a library. All other STD_LOGIC_1164, TEXTIO,
STANDARD etc. are some in built packages of VHDL. STD_LOGIC_1164 is declared in the
IEEE library. TEXTIO and STANDARD libraries are declared in STD library.
423. Packages increases _______ of the code.

a) Reusability
b) Readability
c) Managing
d) Resolution
Answer: a
Explanation: Since packages can be used again and again in the different design units. So, same
data types, functions, subprograms, constants can be used many times without any declaration.
So, packages increase the reusability of the code.
424.Which of the following can’t have multiple assignments or drivers?

a) STD_LOGIC
b) INTEGER
c) STD_ULOGIC
d) BIT
Answer: c
Explanation: The resolving functions for all except STD_ULOGIC has been defined in the
respective packages. Only STD_ULOGIC is of unresolved type. So, multiple values can’t be
assigned to the STD_ULOGIC type since there is no means of resolving the value.
VHDL Questions and Answers – Implementing Combinational Circuits with VHDL – 1
This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Implementing
Combinational Circuits with VHDL – 1”.
425. Which of the following is a not a characteristics of combinational circuits?

a) The output of combinational circuit depends on present input
b) There is no use of clock signal in combinational circuits
c) The output of combinational circuit depends on previous output
d) There is no storage element in combinational circuit
Answer: c
Explanation: A combinational circuit is the one which has no storage of previous output. The
next state or output of the combinational circuit depends only on its present input and hence no
clock signal is required.
426. Which of the following is not a combinational circuit?

a) Adder
b) Code convertor
c) Multiplexer
d) Counter
Answer: d
Explanation: Since counter makes use of either clock signal or previous output to determine
next state. Therefore, counter is a sequential circuit and all the others like multiplexer, adder and
code convertors are the examples of combinational circuit.
427. The code given below is a VHDL implementation of _________
ARCHITECTURE my_circuit OF my_logic IS

BEGIN
WITH ab SELECT
y <= x0 WHEN “00”;
x1 WHEN “01”;
x2 WHEN “10”;
x3 WHEN “11”;
END my_circuit;
a) 4 to 1 MUX
b) 1 to 4 DEMUX
c) 8 to 1 MUX
d) 1 to 8 DEMUX
Answer: a
Explanation: In the given architecture, the output is single (y), which is selected with the help of
a and b. So, a and b are select lines and y is the output which is selected from 4 inputs.
Therefore, it is the multiplexer circuit with 4 inputs and 1 output.
428. Which of the following line of the code contains an error?
L1: ARCHITECTURE mux1 OF mux IS

L2: BEGIN
L3: y<= x0 WHEN x = ‘0’ ELSE
L4: <= x1 WHEN x = ‘1’;
L5: END mux1;
a) L2
b) L3
c) L4
d) No error
Answer: d
Explanation: There is no error in the given piece of the code. However, there was no need to use
WHEN in the line L4 because there is no other case to be selected from many inputs. Last case
can be directly expressed without any use of WHEN.
429. In a given combinational circuit, the concurrent statements are used with selected
assignments using WHEN and ELSE keyword. What is the other alternative to implement
the same?
a) WITH-SELECT
b) WITH-SELECT-WHEN
c) IF-ELSE
d) CASE
Answer: b
Explanation: Because only concurrent statements can be used, therefore, WITH-SELECT is the
correct alternative for the method used by the user. But, WITH-SELECT also requires WHEN
keyword to implement the selected assignment.
430. Which of the following entity declares the ports of a 3 by 8 decoder?

a)
ENTITY decoder IS
PORT( inp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Outp: OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END decoder;
b)
ENTITY decoder IS
END decoder;
c)
ENTITY decoder IS
END decoder;
d)
ENTITY decoder IS
END decoder;
Answer: d
Explanation: In a 3 by 8 decoder, there must be 3 inputs and 8 outputs. For 3 inputs the
dimension of vector must be 2 DOWNTO 0 and for output the dimensions should be 7
DOWNTO 0. Therefore, option d is the correct port entity of the 3 by 8 decoder.
430. For using a process to implement a combinational circuit, which signals should be in
the sensitivity list?
a) Inputs of the circuit
b) Outputs of the circuit
c) Both of the Inputs and Outputs
d) No signal should be in the sensitivity list
Answer: a
Explanation: In a process used for the implementation of the combinational circuit, all the input
signals used which are to be read, should appear in its sensitivity list. In a combinational circuit,
there can be many inputs and those inputs should appear in the sensitivity list of the process.
431. A 4 to 16 decoder can be used as a code converter. What will be the inputs and outputs
of the converter respectively?
a) Binary, Octal
b) Octal, Binary
c) Hexadecimal, Binary
d) Binary, Hexadecimal
Answer: c
Explanation: Since, 24 = 16, therefore, the decoder can act as hexadecimal to binary converter.
Because, 4 bits input is converted to 16 bits output. Each bit corresponding to 4 output bits. So,
clearly it is a hexadecimal to binary convertor.
432. Following entity may represent a ________ circuit.
ENTITY my_circuit IS
PORT (a, b : IN STD_LOGIV_VECTOR(3 DOWNTO 0);
x : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
y : OUT STD_LOGIC);
END my_circuit;
a) Half adder
b) Full adder
c) Multiplexer
d) Parallel adderr
Answer: d
Explanation: The entity gives information about inputs and outputs of the circuit. The circuit
has two inputs and both are of vector type. There is one vector output and another single bit
output. Therefore, it has to be an adder, but because 4 bits are there in the input and output so it
is a 4-bit parallel adder.

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LATHA MATHAVAN ENGINEERING COLLEGE

Latha Madhavan Nagar,Kidaripatti

DEPARTMENT OF ELECTRICAL AND

EE8351 DIGITAL LOGIC CIRCUITS

II Year - III Semester

Multiple Choice Questions & Answers

1. Any signed negative binary number is recognised by its ________

2. The parameter through which 16 distinct values can be represented is known as

4. The representation of octal number (532.2)8 in decimal is ________

5. The decimal equivalent of the binary number (1011.011)2 is ________

6. An important drawback of binary system is ________

7. The decimal equivalent of the octal number (645)8 is ______

8. The largest two digit hexadecimal number is ________

9. Representation of hexadecimal number (6DE)H in decimal:

VHDL Questions and Answers – RTL Simulation

11. What does RTL in digital circuit design stand for?

12. RTL is a design abstraction of what kind of circuit?

15. Which flip-flop is usually used in the implementation of the registers?

16. Which of the following tool performs logic optimization?

18. Simulator enters in which phase after the initialization phase?

Digital Circuits Questions and Answers – Register-Transistor Logic(RTL)

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers

20. All input of NOR as low produces result as __________

26. The primary advantage of RTL technology was that __________

27. The disadvantage of RTL is that __________

Digital Circuits Questions and Answers – Diode-Transistor Logic(DTL)

30. Diode–transistor logic (DTL) is the direct ancestor of _____________

32. In DTL amplifying function is performed by ___________

33. How many stages a DTL consist of?

34. The full form of CTDL is ___________

35. The DTL propagation delay is relatively ___________

39. To increase fan-out of the gate in DTL ___________

41. Compatibility refers to ____________

46. Schottky families prevent the saturating using ___________

48. The full form of MECL is ___________

49. Motorola has offered MECL circuits in ______ logic families.

50. The latest entrant to the ECL family is ___________

51. All input of NOR as low produces result as ___________

53. The full form of CMOS is ____________

54. The full form of COS-MOS is ____________

55. CMOS is also sometimes referred to as ____________

56. CMOS technology is used in ____________

57. Two important characteristics of CMOS devices are ____________

58. CMOS behaves as a/an ____________

59. An important characteristic of a CMOS circuit is the ____________

61. Semiconductors are made of ____________

Digital Circuits Questions and Answers – Emitter-Coupled Logic(ECL)

63. The full form of ECL is __________

65. Sometimes ECL can also be named as __________

66. In an ECL the output is taken from __________

67. The ECL behaves as __________

69.ECL’s major disadvantage is that __________

70. The full form of SCFL is __________

72. ECL was invented in _______ by __________

74. The ECL circuits usually operates with __________

Digital Circuits Questions and Answers – Transistor Transistor Logic(TTL)

78. TTL was invented in 1961 by ____________

79. The full form of TCTL is ____________

72. ECL was invented in _ by ____