MITSUBISHI

MITSUBISHI
SEMICONDUCTOR
SEMICONDUCTOR
<Dual-In-Line
<Dual-In-Line
Package
Package
Intelligent
Intelligent
Power
Power
Module>
Module>

PS21869/-A
PS21869/-A
TRANSFER-MOLD
TRANSFER-MOLD
TYPE
TYPE
INSULATED
INSULATED
TYPE
TYPE

PS21869
INTEGRATED POWER FUNCTIONS
600V/50A low-loss CSTBT inverter bridge for 3 phase
DC-to-AC power conversion

INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS

• For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (UV) protection.
• For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). (Fig.3)
• Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply).
• Input interface : 5V line CMOS/TTL compatible. (High Active)
• UL Approved : Yellow Card No. E80276

APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.

Fig. 1 PACKAGE OUTLINES Dimensions in mm

TERMINAL CODE
1. UP 14. VN1
27×2.8(=75.6) 2. VP1 15. VNC
±0.3
3. VUFB 16. CIN
2.8 4. VUFS 17. CFO
C Heat sink side
(8.5) (2.4) (14.4) (2.5) (17.6) (2.4) 5. VP 18. FO
(4.5)

(2.2)
(3.1)

6. VP1 19. UN
(1)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
7. VVFB 20. VN
27 28 30 31 33 35 8. VVFS 21. WN
21.4±0.5

29 32 34 36 9. WP 22. P
10. VP1 23. U
(4.65) (10)

2-f4.5±0.2 37
34.9±0.5

(11)
(10)

11. VPC 24. V

31±0.5
(2.9)

38
(3.5) (4.65)

39
12. VWFB 25. W
Type name , Lot No. 13. VWFS 26. N
(1.5)
13.4±0.5

41 40
DUMMY TERMINAL CODE
(3.5)

(0.6) 27. VPC 35. UNG

11.5±0.5

22 23 24 25 26
(2) (1.5) 28. UPG 36. VNC
8.5±0.3 10±0.3 10±0.3 10±0.3 20±0.3 (0.6) 3.8±0.2 29. P 37. VNO
Irregular solder remains

Irregular solder remains

(2) 30. VPC 38. WNG

67±0.3 31. VPG 39. VNG
32. U 40. W
79±0.5
1.9±0.05 1.7±0.05 33. WPG 41. P
1±0.2 0.8±0.2 34. V
0.5MAX
0.5MAX

A B
1.6±0.5
1.6±0.5
(16.0)±0.5
12.8±0.5
✽

(0~5°)

3.25MAX 1.85MAX
7±0.5

Detail : A Detail : B Detail : C

Heat sink side (t=0.7) (t=0.7)

✽ -A : Long terminal type (16.0mm)

Jul. 2003
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21869/-A
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)

CBW+
CBW–
CBV+
CBU–

CBV–
CBU+
High-side input (PWM)
C1 : Tight tolerance, temp-compensated electrolytic type (5V line) (Note 1,2)
(Note : The capacitance value depends on the PWM control C2
scheme used in the applied system). C1
Input signal Input signal Input signal
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering. conditioning conditioning conditioning

Level shifter Level shifter Level shifter

Protection Protection Protection
(Note 6)
circuit (UV) circuit (UV) circuit (UV)

DIP-IPM
Drive circuit Drive circuit Drive circuit
Inrush current
limiter circuit
P

AC line input
H-side IGBTS
U
V
(Note 4)
W
M
C Fig. 3 AC line output
Z
N1 N
VNC L-side IGBTS
CIN
Z : ZNR (Surge absorber)
Drive circuit
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line Protection
Control supply
Input signal conditioning Fo logic Under-Voltage
surge absorber circuit may become necessary circuit protection
depending on the application environment).
Low-side input (PWM) FO CFO
(5V line) (Note 1, 2) Fault output (5V line)
(Note 3, 5) VNC VD
(15V line)
Note1: Input logic is high-active. There is a 2.5kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the
input threshold voltage.
2: By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 8)
3: This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistance.
(see also Fig. 8)
4: The wiring between the power DC link capacitor and the PN1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these PN1 DC power input pins.
5: Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF → tFO=1.8ms (Typ.))
6: High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.

Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT

DIP-IPM
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
Drive circuit
P shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
IC (A)
SC Protection
H-side IGBTS Trip Level
U
V
W
L-side IGBTS
External protection circuit

N1 Shunt Resistor A N
(Note 1)
VNC
C R Drive circuit
CIN
B Collector current
Protection circuit waveform
C
(Note 2) 0
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs. 2 tw (µs)
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.

Jul. 2003
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21869/-A
TRANSFER-MOLD TYPE
INSULATED TYPE

MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)

INVERTER PART
Symbol Parameter Condition Ratings Unit
VCC Supply voltage Applied between P-N 450 V
VCC(surge) Supply voltage (surge) Applied between P-N 500 V
VCES Collector-emitter voltage 600 V
±IC Each IGBT collector current Tf = 25°C 50 A
±ICP Each IGBT collector current (peak) Tf = 25°C, less than 1ms 100 A
PC Collector dissipation Tf = 25°C, per 1 chip 70.4 W
Tj Junction temperature (Note 1) –20~+125 °C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ Tf ≤ 100°C) however, to en-
sure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ Tf ≤ 100°C).

CONTROL (PROTECTION) PART

Symbol Parameter Condition Ratings Unit
VD Control supply voltage Applied between VP1-VPC, VN1-VNC 20 V
VDB Control supply voltage Applied between VUFB-VUFS, VVFB-VVFS, V
20
VWFB-VWFS
Applied between UP, VP, WP-VPC, UN, VN, V
VIN Input voltage –0.5~VD+0.5
WN-VNC
VFO Fault output supply voltage Applied between FO-VNC –0.5~VD+0.5 V
IFO Fault output current Sink current at FO terminal 1 mA
VSC Current sensing input voltage Applied between CIN-VNC –0.5~VD+0.5 V

TOTAL SYSTEM
Symbol Parameter Condition Ratings Unit
VD = 13.5~16.5V, Inverter part
VCC(PROT) Self protection supply voltage limit 400 V
(short circuit protection capability) Tj = 125°C, non-repetitive, less than 2 µs
Tf Module case operation temperature (Note 2) –20~+100 °C
Tstg Storage temperature –40~+125 °C
60Hz, Sinusoidal, AC 1 minute, connection
Viso Isolation voltage 2500 Vrms
pins to heat-sink plate

Note 2 : Tf MEASUREMENT POINT

Al Board Specification :
Dimensions : 100✕100✕10mm, Finishing : 12s, Warp : –50~100µm
Control Terminals Groove DIP-IPM

18mm AI board

13.5mm

P U V W N Temp. measurement point

IGBT Chip
Power Terminals (inside the AI board)
Temp. measurement point
FWDi Chip (inside the AI board)

Silicon-grease should be applied evenly with a thickness of 100~200µm

Jul. 2003
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21869/-A
TRANSFER-MOLD TYPE
INSULATED TYPE

THERMAL RESISTANCE
Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
Rth(j-f)Q Junction to case thermal Inverter IGBT part (per 1/6 module) — — 1.42 °C/W
Rth(j-f)F resistance (Note 3) Inverter FWDi part (per 1/6 module) — — 2.00 °C/W
Note 3: Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIP-IPM
and heat-sink.

ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)

INVERTER PART
Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
Collector-emitter saturation VD = VDB = 15V IC = 50A, Tj = 25°C — 1.50 2.00
VCE(sat) V
voltage VIN = 5V IC = 50A, Tj = 125°C — 1.60 2.10
VEC FWDi forward voltage Tj = 25°C, –IC = 50A, VIN = 0V — 1.70 2.20 V
ton 0.70 1.30 1.90 µs
trr VCC = 300V, VD = VDB = 15V — 0.30 — µs
tc(on) Switching times IC = 50A, Tj = 125°C, VIN = 0 ↔ 5V — 0.40 0.60 µs
toff Inductive load (upper-lower arm) — 2.00 2.60 µs
tc(off) — 0.65 0.90 µs
Collector-emitter cut-off Tj = 25°C — — 1
ICES VCE = VCES mA
current Tj = 125°C — — 10

CONTROL (PROTECTION) PART

Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
VD = VDB = 15V Total of VP1-VPC, VN1-VNC — — 5.00 mA
VIN = 5V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS — — 0.40 mA
ID Circuit current
VD = VDB = 15V Total of VP1-VPC, VN1-VNC — — 7.00 mA
VIN = 0V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS — — 0.55 mA
VFOH VSC = 0V, FO circuit pull-up to 5V with 10kΩ 4.9 — — V
Fault output voltage
VFOL VSC = 1V, IFO = 1mA — — 0.95 V
VSC(ref) Short circuit trip level Tj = 25°C, VD = 15V (Note 4) 0.43 0.48 0.53 V
IIN Input current VIN = 5V 1.0 1.5 2.0 mA
UVDBt Trip level 10.0 — 12.0 V
UVDBr Supply circuit under-voltage Reset level 10.5 — 12.5 V
protection Tj ≤ 125°C
UVDt Trip level 10.3 — 12.5 V
UVDr Reset level 10.8 — 13.0 V
tFO Fault output pulse width CFO = 22nF (Note 5) 1.0 1.8 — ms
Vth(on) ON threshold voltage 2.1 2.3 2.6 V
Applied between UP, VP, WP-VPC, UN, VN, WN-VNC
Vth(off) OFF threshold voltage 0.8 1.4 2.1 V
Note 4 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC trip-
level is less than 85 A.
5 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulse-
width tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 ✕ 10-6 ✕ tFO [F].

Jul. 2003
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21869/-A
TRANSFER-MOLD TYPE
INSULATED TYPE

MECHANICAL CHARACTERISTICS AND RATINGS

Limits
Parameter Condition Unit
Min. Typ. Max.
Mounting torque Mounting screw : M4 Recommended 1.18 N·m 0.98 — 1.47 N·m
Weight — 65 — g
Heat-sink flatness (Note 6) –50 — 100 µm

Note 6: Measurement point of heat-sink flatness

+ – 3mm
Measurement location

Heat-sink side

–
+
Heat-sink side

RECOMMENDED OPERATION CONDITIONS

Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
VCC Supply voltage Applied between P-N 0 300 400 V
VD Control supply voltage Applied between VP1-VPC, VN1-VNC 13.5 15.0 16.5 V
VDB Control supply voltage Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS 13.0 15.0 18.5 V
∆VD, ∆VDB Control supply variation –1 — 1 V/µs
tdead Arm shoot-through blocking time For each input signal, Tf ≤ 100°C 2 — — µs
fPWM PWM input frequency Tf ≤ 100°C, Tj ≤ 125°C — 5 — kHz
VCC = 300V, VD = 15V, fc = 5kHz
IO Allowable r.m.s. current P.F = 0.8, sinusoidal — — 23 Arms
Tj ≤ 125°C, Tf ≤ 100°C (Note 7)
PWIN Minimum input pulse width ON (Note 8) 300 — — ns
VNC VNC variation between VNC-N (including surge) –5.0 — 5.0 V
Note 7 : The allowable r.m.s. current value depends on the actual application conditions.
8 : The input pulse width less than PWIN might make no response.

Jul. 2003
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21869/-A
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 4 THE DIP-IPM INTERNAL CIRCUIT

VUFB DIP-IPM
VUFS P
HVIC1
VP1 VCC VB IGBT1 Di1

UP IN HO

COM VS U
VVFB
VVFS
HVIC2
VP1 VCC VB IGBT2 Di2

VP IN HO

COM VS V
VWFB
VWFS
HVIC3
VP1 VCC VB IGBT3 Di3

WP IN HO

VPC COM VS W

LVIC IGBT4
Di4
UOUT

VN1 VCC
IGBT5
Di5
VOUT

UN UN IGBT6
Di6
VN VN WOUT
WN WN
VNO
Fo Fo
CIN
VNC GND N
CFO

CFO CIN

Jul. 2003
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21869/-A
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS

[A] Short-Circuit Protection (Lower-arms only)

(With the external shunt resistance and CR connection)

a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit current detection (SC trigger).
a3. Hard IGBT gate interrupt.
a4. IGBT turns OFF.
a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO.
a6. Input “L” : IGBT OFF state.
a7. Input “H” : IGBT ON state, but during the FO active signal period the IGBT doesn’t turn ON.
a8. IGBT OFF state.

Lower-arms control a6 a7
input

Protection circuit state SET RESET

Internal IGBT gate

a3
a2

SC a4
a1
Output current Ic a8
SC reference voltage
Sense voltage of the
shunt resistance

CR circuit time
constant DELAY
Error output Fo a5

[B] Under-Voltage Protection (Lower-arm, UVD)

b1. Control supply voltage rises : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.
b2. Normal operation : IGBT ON and carrying current.
b3. Under voltage trip (UVDt).
b4. IGBT OFF in spite of control input condition.
b5. FO operation starts.
b6. Under voltage reset (UVDr).
b7. Normal operation : IGBT ON and carrying current.

Control input

Protection circuit state RESET SET

RESET

UVDr
Control supply voltage VD b1 UVDt b6
b3

b4
b2 b7

Output current Ic

Error output Fo
b5

Jul. 2003
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21869/-A
TRANSFER-MOLD TYPE
INSULATED TYPE

[C] Under-Voltage Protection (Upper-arm, UVDB)

c1. Control supply voltage rises : After the voltage reaches UVDBr, the circuits start to operate when next input is applied.
c2. Normal operation : IGBT ON and carrying current.
c3. Under voltage trip (UVDBt).
c4. IGBT OFF in spite of control input condition, but there is no FO signal output.
c5. Under voltage reset (UVDBr).
c6. Normal operation : IGBT ON and carrying current.

Control input

Protection circuit state RESET SET RESET

UVDBr
Control supply voltage VDB c1 UVDBt c5
c3

c2 c4 c6
Output current Ic

High-level (no fault output)

Error output Fo

Fig. 6 RECOMMENDED CPU I/O INTERFACE CIRCUIT

5V line

10kΩ DIP-IPM

UP,VP,WP,UN,VN,WN

CPU
2.5kΩ (min)
Fo

VNC(Logic)

Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in
the application and the wiring impedance of the application’s printed circuit board.
The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using a external
filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement.

Fig. 7 RECOMMENDED WIRING OF SHUNT RESISTANCE

Wiring inductance should be less than 10nH.

DIP-IPM width=3mm, thickness=100µm, length=17mm

in copper pattern (rough standard)

Shunt resistor

VNC N

Please make the connection point

as close as possible to the terminal
of shunt resistor.

Jul. 2003
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21869/-A
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 8 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE

C1:Tight tolerance temp-compensated electrolytic type

C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering.
(Note: The capacitance value depends on the PWM control used in the applied system.)

C2 VUFB
DIP-IPM
C1 VUFS P
HVIC1
VP1
VCC VB
C3
UP
IN HO

COM VS U
C2 VVFB
C1 VVFS
HVIC2
VP1
VCC VB
C3
VP
IN HO
V
C2
COM VS M
VWFB
C1 VWFS
HVIC3
VP1
VCC VB
C3
CPU UNIT

WP
IN HO
VPC
COM VS W

LVIC

UOUT

VN1
VCC
C3
5V line
VOUT

UN
UN
VN VN
WOUT
WN Too long wiring here might
WN
Fo VNO cause short-circuit.
Fo
CIN N
VNC
GND CFO
C
CFO CIN

15V line C4(CFO ) B R1

Shunt
C5 Resistance
A
N1
Long GND wiring here might generate If this wiring is too long, the SC level
noise to input and cause IGBT fluctuation might be larger and cause
malfunction. SC malfunction.

Note 1 : To prevent the input signals oscillation, the wiring of each input should be as short as possible. (2cm~3cm or less)
2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler
or transformer isolation is possible.
3 : FO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately
10kΩ resistor.
4 : FO output pulse width is determined by the external capacitor between CFO and VNC terminals (CFO). (Example : CFO = 22 nF → tFO
= 1.8 ms (typ.))
5 : The logic of input signal is high-active. The DIP-IPM input signal section integrates a 2.5kΩ (min) pull-down resistor. Therefore, when
using external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement.
6 : To prevent malfunction of protection, The wiring of A, B, C should be as short as possible.
7 : Please set the R1C5 time constant in the range 1.5~2µs.
8 : Each capacitor should be located as nearby the pins of the DIP-IPM as possible.
9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 pins should be as short as possible. Approxi-
mately a 0.1~0.22µF snubber capacitor between the P&N1 pins is recommended.

Jul. 2003