TDA18219HN: 1. General Description

TDA18219HN
Silicon Tuner for terrestrial and cable digital TV reception

Rev. 5 — 9 November 2011 Product data sheet
1. General description
The TDA18219HN supports most digital TV standards and delivers a LOW IF (LIF) signal
to a channel demodulator for digital TV. Standards that are covered include DVB-T,
ISDB-T, DTMB and DVB-C.
The TDA18219HN facilitates design-ins by:
• Allowing easy on-board integration

• Drastically reducing the size of the tuner function
• Providing flexibility in system solution development
2. Features and benefits

 Fully integrated IF selectivity; eliminating the need for external SAW filters
 Fully integrated oscillators
 Alignment free
 Single 3.3 V supply voltage
 LOW power consumption
 Integrated wideband gain control
 Crystal oscillator output buffer (16 MHz) for single crystal applications
 I2C-bus interface compatible with 3.3 V microcontrollers
 Easy programming
 5 ms tuning time
 LIF channel center frequency output ranging from 3 MHz to 5 MHz
 1.7 MHz, 6 MHz, 7 MHz, 8 MHz and 10 MHz channel bandwidths
 Loop-Through (LT)
 RoHS compliant
3. Applications
 Digital TV for STB, PCTV, DVD-R and TV applications
 Digital (DVB-T/T2/C/H, DTMB, ISDB-T) standards supported
 Targeted specification (based on channel decoder or demodulator capabilities):
 NorDig cable (EU)
 C-BOOK (Cable, EU)
 NorDig 2.0 (EU TV)
 E-BOOK and D-BOOK
 ARIB STD-B21 for ISDB-T
NXP Semiconductors TDA18219HN
4. Quick reference data

Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
fRF RF frequency full range of RF input 42 - 870 MHz
NFtun tuner noise figure 75  source; maximum gain - 5.0 5.9 dB
jit phase jitter UHF; integrated from 1 kHz - 0.5 0.7 degree
to 4 MHz
image image rejection worst case for image 55 63 - dB
rejection and 4 MHz IF
frequency for levels above
50 dBm
ICP1dB 1 dB input compression at tuner input and minimum 124 - - dBV
point gain
5. Ordering information
Table 2. Ordering information
Type number Package
Name Description Version
TDA18219HN/C1 HVQFN40 plastic thermal enhanced very thin quad flat package; SOT618-1
no leads; 40 terminals; body 6  6  0.85 mm
6. Marking
Table 3. Marking codes
Type number Marking code
TDA18219HN/C1 18219HN
TDA18219HN All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 9 November 2011 2 of 50

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Product data sheet
TDA18219HN
7. Block diagram
NXP Semiconductors
CAPRFAGC
UHFHIGH
VHFHIGH
UHFLOW
VHFLOW
IR mixer
RF input LNA IF filters

42-870 MHz AGCK IF AGC IFP
RFIN
All information provided in this document is subject to legal disclaimers.
SURGE IFN
RFAGC
RF FILTER VIFAGC
Rev. 5 — 9 November 2011
AGC1 AGC2 AGC3 AGC5

LT enable AGC4
LT PLD
SURGE
LO IRQ
DIVIDERS AS_XTSEL
I2C-BUS CONTROL
AND SDA
INTERFACES
SCL
FRAC-N
DIVIDER
Xtal
LC VCO
TEMPERATURE
SENSOR
XTOUT1
XTOUT2
XTALP
XTALN
CP
VTUNE
TDA18219HN
loop
filter
001aal177
© NXP B.V. 2011. All rights reserved.
3 of 50
Fig 1. Block diagram

8. Pinning information
8.1 Pinning
37 UHFSUPPLY
31 VHFSUPPLY
40 CAPRFAGC
33 VHFSENSE
38 UHFHIGH
34 VHFHIGH
36 UHFLOW
32 VHFLOW
35 VCC(RF)
39 n.c.
terminal 1
index area
VCC(RF) 1 30 IRQ
RFIN 2 29 TEST3
LT 3 28 VIFAGC
n.c. 4 27 VCC(IF)
n.c. 5 26 GND(IF)
TDA18219HN
AS_XTSEL 6 25 IFP
GND(DIG) 7 24 IFN
n.c. 8 23 TEST2
TEST4 9 GND(RF) 22 XTOUT2
GND(DIG) 10 21 XTOUT1
SCL 11
SDA 12
TEST1 13
XTALP 14
XTALN 15
VCC(SYNTH) 16
CAPREGVCO 17
GND(SYNTH) 18
VTUNE 19
CP 20
001aal179
Transparent top view
Fig 2. Pin configuration
8.2 Pin description

Table 4. Pin description
Symbol Pin Description
VCC(RF) 1 RF supply voltage
RFIN 2 unbalanced RF input
LT 3 loop-through output
n.c. 4 not connected
AS_XTSEL 6 I2C-bus address and XTOUT level selection input
GND(DIG) 7 digital ground supply voltage
TEST4 9 test input 4; leave open
GND(DIG) 10 digital ground supply voltage
SCL 11 I2C-bus clock input
SDA 12 I2C-bus data input/output
TEST1 13 test input 1; connect to ground for operation mode
XTALP 14 crystal oscillator positive input
XTALN 15 crystal oscillator negative input

Table 4. Pin description …continued

Symbol Pin Description
VCC(SYNTH) 16 synthesizer supply voltage
CAPREGVCO 17 VCO regulator filtering input
GND(SYNTH) 18 synthesizer ground
VTUNE 19 VCO tuning voltage input
CP 20 charge pump output
XTOUT1 21 crystal oscillator buffer output 1
XTOUT2 22 crystal oscillator buffer output 2
IFN 24 IF negative output
IFP 25 IF positive output
GND(IF) 26 IF ground
VCC(IF) 27 IF supply voltage
VIFAGC 28 IF gain control input
IRQ 30 interrupt request output
VHFSUPPLY 31 RF filter VHF supply input
VHFLOW 32 RF filter VHF LOW input
VHFSENSE 33 RF filter VHF sense
VHFHIGH 34 RF filter VHF HIGH input
VCC(RF) 35 RF filter supply voltage
UHFLOW 36 RF filter UHF LOW input
UHFSUPPLY 37 RF filter UHF supply input
UHFHIGH 38 RF filter UHF HIGH input
CAPRFAGC 40 RF AGC filtering
GND(RF) die pad RF ground
9. Functional description
The silicon tuner is based on single down-conversion and LIF architecture that allows full
integration of band-pass selectivity and eliminates the need for external SAW filters.
The RF input signal is fed to the input splitter, built-out of a Low Noise Amplifier (LNA).
After the LNA, an alignment free RF tuned filter protects the rest of the tuner function
against strong unwanted signals.
The LIF concept needs complex signals that highly suppress the N + 1 image channel
thanks to image rejection calibration. A complex filter and a IF filter perform the IF
selectivity. The IF filter depends on IF frequency choice and channel bandwidth. The IF
filter is built with a IF Low-Pass Filter (LPF), a IF notch filter and a programmable IF
High-Pass Filter (HPF) for more flexibility on IF frequency selection. The IF notch filter
when activated, suppress the residual adjacent N  1 sound carrier.

Continuous gain control is performed after the RF filters and the IF selectivity. Stepped
AGC is available at all stages (LNA, RF filter, mixer and IF LPF) in order to optimize the
tuner signal-to-noise ratio. Internal broadband level detectors control gain settings of all
stepped AGC and the RF AGC amplifier. The steps in the different stages are
automatically compensated in IF with AGCK to keep a constant IF output level. The
demodulator controls the gain of the IF AGC amplifier to take advantage of the full ADC
dynamic range.
A single LC-VCO operating at 7 GHz is used within a FRAC-N phase lock-loop to

generate the LO frequency. A crystal oscillator provides the clock reference signal. This
signal can be provided to a demodulator through the crystal output buffer.
All the programming is performed via I2C-bus transceiver. An embedded test tone
generator is used for automatic calibration at Power-On-Reset (POR).
The power level indicator can be used to indicate the RF input signal strengths of the
received channel.
9.1 RF filter
The RF filter block is an alignment free tunable Band-Pass Filter (BPF). At power-up, a
self calibration is performed which compensates for external and internal components
frequency spread. The center frequency is automatically tuned to the frequency set using
the I2C-bus to suppress any undesired interferer across the broadband spectrum.
9.2 Crystal output mode

Pins XTOUT1 and XTOUT2 provide a symmetrical sine waveform which drives the
channel demodulator. The load on these outputs must be identical to ensure optimum
performance matching. If only one crystal output is used, the unused output must be
loaded by the same capacitance value. The XTOUT output level can be set to either
400 mV (p-p) or 800 mV (p-p) single ended, refer Table 29 “Pin AS_XTSEL decoding”.
9.3 AGC description

The tuner gain is composed of different variable gain stages spread according to the block
diagram (see Figure 1 “Block diagram”). Using the different detectors at different stages,
the gain is distributed to offer best trade-off between linearity and noise. Continuity gain
variation is made in 3 dB steps. The AGCK stage compensates the 3 dB steps to ensure
gain linearity. At the tuner output the gain variations appear to be continuous.
The tuner gain is externally controlled via IFAGC voltage level applied to pin VIFAGC. The
RF gain is set automatically, based on the defined AGCn_TOP values.
The different stages gain values are then a combination of the following input parameters:
• Input signal
• TOP values set via I2C-bus
• IFAGC voltage level

The programmable Take Over Points (TOP) provide the optimal noise versus linearity
trade-off during reception. The TOP values are carefully selected so that they do not
overload the following stages or have too weak signal-to-noise ratio. They correspond to
thresholds where the gain distribution changes inside the tuner.
In order to avoid instability of gain chain while working around thresholds, a hysteresis is
implemented to avoid gain toggling. This is the reason why there are different values for
TOP-up and/or TOP-down. Its main purpose is to make sure gain switch occurs to prevent
signal distortion along the gain chain.
LNA gain
(dB)
15
12 TOP = 100 dBμV
HIST = 6 dB
9
6
3
0
−3
−6
−9
−12
91 94 97 100 LNA output level (dBμV)
001aak488
Remark: to get a 0 dB gain on the LT, then only steps from 6 dB to 15 dB are available.
Fig 3. AGC1 TOP description example
The TOP values tuner settings are key for all tuner performance.
Table 5. AGC number/block correspondence

AGC number Corresponding AGC block Comment
AGC1 LNA AGC
AGC2 RF Filter AGC Not described, handled internally by tuner
AGC3 RF AGC
AGC4 Mixer AGC
AGC5 LPF AGC
9.4 Low-Pass Filter (LPF)

The programmable LPF avoids aliasing of demodulators Analog-to-Digital converters. In
addition, it suppresses the remaining signals. The programming enables signal bandwidth
of 1.7 MHz, 6 MHz, 7 MHz, 8 MHz and 10 MHz.
9.5 High-Pass Filter (HPF)

The HPF contributes to residual adjacent (N + 1) channel suppression after image
rejection removal.

9.6 Notch filter

This block is implemented in the IF filter to optionally provide additional robustness
against adjacent analog channels. It reduces the adjacent channel sound carrier level to
prevent overloading of IF output stage. The notch frequency is tracked with LPF settings.
9.7 IR mixer
The LIF concept needs complex signals that highly suppress the N + 1 image channel
thanks to image rejection calibration.
9.8 LO generation
A single LC-VCO operating at 7 GHz is used within a FRAC-N phase lock-loop to
generate the LO frequency. A crystal oscillator provides the clock reference signal. This
signal is provided to a demodulator through the crystal output buffer.
9.9 Temperature sensor

The temperature sensor indicates the junction temperature of the IC via I2C-bus for
soldering check. Refer to Section 10.1.2 for detailed description and operation.
9.10 Power Level Detector (PLD)

The power level indicator indicates the RF input signal strengths of the received channel
via I2C-bus. Refer to Section 10.1.4 for detailed description and operation.
9.11 I2C-bus transceiver

The TDA18219HN is controlled via the two-wire I2C-bus. There is one device address
(7-bit). The read or write mode is selected with the R/W bit. To be able to have more than
one tuner in an I2C-bus system, one of two possible addresses is selected depending on
the voltage applied to address selection pin AS_XTSEL (pin 6) see Table 29 “Pin
AS_XTSEL decoding”.

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Product data sheet
10. Control interface
TDA18219HN
NXP Semiconductors
10.1 Register table description
Table 6. Register table description
Addres Name[1] Bit
s (hex) 7 6 5 4 3 2 1 0
00 ID_byte_1 1 Ident[14:8]
01 ID_byte_2 Ident[7:0]
02 ID_byte_3 Major_rev[3:0] Minor_rev[3:0]
03 Thermo_byte_1 - TM_D[6:0]
04 Thermo_byte_2 - TM_ON
05 Power_state_byte_1 - POR LO_Lock

06 Power_state_byte_2 - SM 0 SM_LNA 0
07 Input_Power_Level_byte - Power_Level[6:0]
08 IRQ_status IRQ_status -

09 IRQ_enable 1 - 0
0A IRQ_clear IRQ_clear - 0
0B IRQ_set 0 - 0
0C AGC1_byte_1 LT_Enable AGC1_6_ - AGC1_TOP[3:0]
15dB
0D AGC2_byte_1 - 0 1 1 1 1
0E AGCK_byte_1 0 1 1 0 1 0
0F RF_AGC_byte_1 PD_RFAGC RFAGC_Adapt_TOP[1:0] 1 RF_Atten_ AGC3_TOP[2:0]
_Adapt 3dB
10 IR_MIXER_byte_1 - AGC4_TOP[3:0]
TDA18219HN
11 AGC5_byte_1 - 0 AGC5_TOP[3:0]
12 IF_AGC_byte - IF_Level[2:0]
13 IF_byte_1 IF_HP_Fc[1:0] IF_Notch LP_FC_Offset[1:0] LP_Fc[2:0]
14 Reference_byte 0 Digital_Clock - 0 - XTout[1:0]

15 IF_Frequency_byte IF_Freq[7:0]
16 RF_Frequency_byte_1 - RF_Freq[19:16]
17 RF_Frequency_byte_2 RF_Freq[15:8]
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Product data sheet Table 6. Register table description …continued
TDA18219HN
NXP Semiconductors
Addres Name[1] Bit
s (hex) 7 6 5 4 3 2 1 0
18 RF_Frequency_byte_3 RF_Freq[7:0]
19 MSM_byte_1 POWER_ RF_CAL_AV RF_CAL IR_CAL[1:0] 0 RC_CAL Calc_PLL
Meas
1A MSM_byte_2 - 0 MSM_Launch
1B PSM_byte_1 1 1 VHFIII 1 1 1 1 1
1C DCC_byte_1 0 -
1D FLO_Max_byte - 0
1E IR_Cal_byte_1 0
1F IR_Cal_byte_2 1 0
20 IR_Cal_byte_3 - 0
21 IR_Cal_byte_4 - 0
22 Vsync_Mgt_byte 0 1
23 IR_MIXER_byte_2 0 - HI_Pass DC_NOTCH

24 AGC1_byte_2 0 1 0 1
25 AGC5_byte_2 0 - 0 - 0 1
26 RF_Cal_byte_1 0
27 RF_Cal_byte_2 0
28 RF_Cal_byte_3 0
29 RF_Cal_byte_4 0
2A RF_Cal_byte_5 0
2B RF_Cal_byte_6 0
2C RF_Filter_byte_1 0 1 0 1 1
TDA18219HN
2D RF_Filter_byte_2 0
2E RF_Filter_byte_3 0
2F RF_Band_Pass_Filter_byte 0 - 1 1 0
30 CP_Current_byte - 1 0 1 1 1
31 AGC_Det_Out_byte X X X X X X X X
32 RF_AGC_Gain_byte_1 - RF_FILTER_GAIN[1:0] LNA_GAIN[3:0]
33 RF_AGC_Gain_byte_2 - TOP_Agc3_read[2:0]
10 of 50
34 IF_AGC_Gain_byte - LPF_GAIN[1:0] IR_MIXER[2:0]

Product data sheet Table 6. Register table description …continued
TDA18219HN
NXP Semiconductors
Addres Name[1] Bit
s (hex) 7 6 5 4 3 2 1 0
35 Power_byte_1 X X X X X X X X
36 Power_byte_2 - - 0 X 1 1 1 0
37 Misc_byte_1 1 1 0 1 0 IRQ_Polarity
38 rfcal_log_1 X X X X X X X X
3A rfcal_log_3 X X X X X X X X
3B rfcal_log_4 X X X X X X X X
3C rfcal_log_5 X X X X X X X X
3D rfcal_log_6 X X X X X X X X
3E rfcal_log_7 X X X X X X X X
3F rfcal_log_8 X X X X X X X X

50 - FORBIDDEN ACCESS
67 - FORBIDDEN ACCESS
FE - FORBIDDEN ACCESS
FF - FORBIDDEN ACCESS
[1] The settings optimization is bound to channel decoder or demodulator choice and has a high impact on the tuner performances within system environment. Refer to Application
Note AN1002 for optimal settings.
Remark:
TDA18219HN
• The values in Table 6 must be written as described for operation mode of the tuner.
• X means the tuner provides the value 0 or 1.
• - means the value is undefined. No internal bit corresponds to this address.

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10.1.1 Device type address ID

Table 7. ID byte bit descriptions
Address Register Bit Symbol Access Value Description
00 ID_byte_1 6 to 0 Ident[14:8] R 4724h type number information
01 ID_byte_2 7 to 0 Ident[7:0]
02 ID_byte_3 7 to 4 Major_rev[3:0] R 1 current major releases
3 to 0 Minor_rev[3:0] R 1 current minor releases
10.1.2 Temperature sensor

Table 8. Temperature sensor bit descriptions
03 Thermo_byte_1 6 to 0 TM_D[6:0] R - a junction temperature measurement ranging
from 22 C to 127 C is indicated through these
bits
04 Thermo_byte_2 0 TM_ON W temperature sensor ON or OFF
0 temperature sensor switched OFF
1 temperature sensor switched ON
Remark: The temperature sensor value is updated each time a read is performed on the
byte Thermo_byte_1, if TM_ON is set to 1. Otherwise, temperature sensor value is not
updated.
10.1.3 Power state

Table 9. Power state bit descriptions
05 Power_state_byte_1 1 POR R - detects when the tuner supply voltage went
below POR threshold voltage. The tuner is then
reset to its original settings (tuner not initialized).
0 once it has been read
1 the POR occurred on the tuner
0 LO_Lock R LO lock flag
0 PLL unlocked
1 PLL locked
06 Power_state_byte_2 3 SM R/W [1] Sleep mode control bits
1 SM_LNA R/W [1]
[1] See Table 10.
Table 10. Mode selection

SM[1] SM_LNA[1] Mode
0 0 Operation mode = ON
1 0 Standby mode with LT ON
1 1 Standby mode with LT OFF
[1] All others values are forbidden.

10.1.4 Power level detector

Table 11. Power level detector bit descriptions
07 Input_Power_Level_byte 6 to 0 Power_Level[6:0] R - gives the power value measured at
antenna input; Power_Level value[1] is
computed as follows:
0 to 27 power < 40 dBV (RMS)
28 to 40 dBV (RMS) 
6E[2] power  110 dBV (RMS)
6F to power > 110 dBV (RMS)
7F
[1] Power_Level value is updated only if requested via triggering of MSM_byte_1 and MSM_byte_2.
[2] The power value is read in the range from 40 dBV (RMS) to 110 dBV (RMS).
Remark: The power level measurement is not done continuously but only on request
performed by using bytes MSM_byte_1 (address: 19) and MSM_byte_2 (address: 1A):
• Set MSM_byte_1 (value: 80) to indicate a power measurement is required

• Set MSM_byte_2 (value: 01) to trig the measurement
• Then read byte Input_Power_Level_byte (address: 07) for result
Remark: This feature purpose is to ease antenna pointing when no picture is displayed on
screen only. In case a power level detection is required while displaying a picture, refer to
software procedure described in Application Note.
10.1.5 IRQ
Table 12. IRQ bit descriptions
08 IRQ_status 7 IRQ_status R/W 0 IRQ_clear is set to 1
1 all calibration sequences selected by
MSM_byte_1 and launched by
MSM_byte_2 are completed
0A IRQ_clear 7 IRQ_clear R/W 0 no action
1 drops the bit IRQ_status
Remark: A level change is generated on IRQ pin (30) that reflects the IRQ_status bit. The
polarity of the IRQ pin is set with IRQ_Polarity bit (address: 37). In operation mode, the
IRQ status raised at the end of the calibration sequence selected with MSM_byte_1 and
MSM_byte_2 and at each programming of a new channel.

10.1.6 AGC and Take Over Points (TOP)

Table 13. AGC and Take Over Points bit descriptions
0C AGC1_byte_1 7 LT_Enable R/W LT output
0 disable
1 enable
6 AGC1_6_15dB R/W limits AGC1 gain range from +6 dB to
+15 dB
0 range is from 12 dB to +15 dB
1 range is from +6 dB to +15 dB
3 to 0 AGC1_TOP[3:0] R/W [1] set the TOP of the LNA detection loop
(AGC1) according to the reception
standard or the system settings
0F RF_AGC_byte 7 PD_RFAGC_Adapt R/W RF AGC adapts algorithm power-down
_1 0 ON
1 OFF
6 to 5 RFAGC_Adapt_TOP[1:0] R/W - “AGC3 Adapt” algorithm decreases the
AGC3 TOP for low LPF gains. LPF
gain is set to low value by AGC5
detector loop in the ACI (N) and
(N  1) reception cases. Decreasing
the AGC3 TOP then limits signal
carrier to noise ratio degradation
caused by distortion in the RF stages.
At opposite, LPF gain is set to high
value by AGC5 detector loop in the
ACI (N  X) and (N + X) reception
cases. Increasing the AGC3 TOP then
limits signal carrier to noise ratio
degradation caused by noise from RF
AGC stage. PD_RFAGC_Adapt
disables this algorithm.
RFAGC_Adapt_TOP[1:0] enables the
low AGC3 TOP value, the high one is
enabled via the AGC3 TOP field.
3 RF_Atten_3dB R/W Adds 3 dB attenuation out of RF AGC
0 OFF
1 ON
2 to 0 AGC3_TOP[2:0] R/W [2] sets the RF AGC, MIXER and LPF
blocks TOP. Sets these bits according
to the required reception standard and
performances

Table 13. AGC and Take Over Points bit descriptions …continued
10 IR_MIXER_ 3 to 0 AGC4_TOP[3:0] R/W [3] sets these bits according to the
byte_1 required reception standard and
performances
11 AGC5_byte_1 3 to 0 AGC5_TOP[3:0] R/W [4] sets these bits according to the
required reception standard and
performances
12 IF_AGC_byte 2 to 0 IF_Level[2:0] R/W [5] sets the tuner required maximum
output level. This enables internal
computation of the best linearity to
noise ratio based on required output
level
[1] See Table 14.

[2] See Table 15.
[3] See Table 16.
[4] See Table 17.
[5] See Table 18.
Table 14. AGC1 TOP values

AGC1_TOP[3:0] (hex)[1] AGC1 TOP Down (dBV) AGC1 TOP Up (dBV)
0 95 89
5 99 93
A 100 94
F 101 95

AGC3_TOP[2:0] (hex) AGC3 TOP (dBV)
0 94
1 96
2 98
3 100
4 102
5 104
6 106
7 107

1 105 100
4 107 102
6 108 103

Table 16. AGC4 TOP values …continued

8 109 104
B 110 105
E 112 107

1 105 100
4 107 102
6 108 103
8 109 104
B 110 105
E 112 107
Table 18. Tuner output level

IF_Level[2:0] (hex) Output level (V (p-p) Minimum gain (dB) Maximum gain (dB)
differential)[1]
7 0.5 12 18
6 0.6 10.3 19.7
5 0.7 9 21
4 0.85 7.5 22.5
3 0.8 8 22
2 1 6 24
1 1.25 4 26
0 2 0 30
[1] Output level depends on standard and ADC headroom.

10.1.7 IF Filtering
Table 19. IF Filtering bit descriptions
13 IF_byte_1 7 to 6 IF_HP_Fc[1:0] R/W selects the IF HPF cut-off frequency. The high-pass
frequency must be set in accordance with the
desired reception standard. High-pass frequency:
00 0.4 MHz
01 0.85 MHz
10 1 MHz
11 1.5 MHz
5 IF_Notch R/W enables or disables a notch implemented for
adjacent N  1 sound carrier suppression. The notch
frequency depends on LP_Fc[2:0].
0 OFF
1 ON
4 to 3 LP_FC_Offset[1:0] R/W enables offset to LPF cut-off frequency providing
further adjacent channel rejection
00 0
01 4 %
10 8 %
11 forbidden
2 to 0 LP_Fc[2:0] R/W [1] selects the IF LPF cut-off frequency. Sets the IF LPF
cut-off frequency according to required reception
standard.
[1] See Table 20.
Table 20. Low-Pass Filter bits descriptions

LP_Fc[2:0] (hex)[1] LP cut-off frequency (MHz) IF notch frequency (MHz)
4 1.7 -
0 6 6.5
1 7 7.25
2 8 8.25
3 9 -

10.1.8 XTOUT
Table 21. XTOUT bit descriptions
14 Reference_byte 6 Digital_Clock R/W spreads digital clock power to improve
tuner EMC behavior
0 OFF
1 ON
1 to 0 XTout[1:0] R/W provides 16 MHz reference signal on the
XTOUT1 and XTOUT2 pins. XTOUT
mode:
00 no signal
01 forbidden
10 forbidden
11 16 MHz
10.1.9 IF and RF frequency

Table 22. IF and RF frequency bit descriptions
15 IF_Frequency_byte 7 to 0 IF_Freq[7:0] R/W - sets the tuner to the required IF
frequency by 50 kHz steps. For example,
to set the IF frequency to 4 MHz,
IF_Freq[7:0] value must be
4000 : 50 = 80
16 RF_Frequency_byte_1 3 to 0 RF_Freq[19:16] R/W - sets the desired RF frequency expressed
17 RF_Frequency_byte_2 7 to 0 RF_Freq[15:8] R/W - in kHz
18 RF_Frequency_byte_3 7 to 0 RF_Freq[7:0] R/W -
10.1.10 Calibration controls

Table 23. Calibration control bit descriptions
19 MSM_byte_1 7 POWER_Meas R/W - sets these bits according to the
6 RF_CAL_AV R/W - programming flowchart (see Figure 4) to
control the calibration and calculation
5 RF_CAL R/W - state machines embedded in the chip
4 to 3 IR_CAL[1:0] R/W -
1 RC_CAL R/W -
0 Calc_PLL R/W -
1A MSM_byte_2 0 MSM_Launch R/W -

10.1.11 IF filtering options

Table 24. IR Mixer bit descriptions
23 IR_Mixer_byte_2 1 HI_Pass R/W controls the high-pass frequency filter
0 OFF
1 ON
0 DC_NOTCH R/W controls a DC notch in the IR mixer
0 OFF
1 ON
10.1.12 Gain values

Table 25. AGC bit descriptions
32 RF_AGC_Gain_byte_1 5 to 4 RF_FILTER_GAIN[1:0] R RF FILTER gain value
00 11 dB
01 8 dB
10 5 dB
11 2 dB
3 to 0 LNA_GAIN[3:0] R [1] LNA gain value
0000 12 dB
0001 9 dB
0010 6 dB
0011 3 dB
0100 0 dB
0101 3 dB
0110 6 dB
0111 9 dB
1000 12 dB
1001 15 dB
33 RF_AGC_Gain_byte_2 2 to 0 TOP_Agc3_read[2:0] R gives the AGC3 TOP value
000 94 dBV (RMS)
001 96 dBV (RMS)
010 98 dBV (RMS)
011 100 dBV (RMS)
100 102 dBV (RMS)
101 104 dBV (RMS)
110 106 dBV (RMS)
111 107 dBV (RMS)

Table 25. AGC bit descriptions …continued

34 IF_AGC_Gain_byte 4 to 3 LPF_GAIN[1:0] R LPF gain value
00 0 dB
01 3 dB
10 6 dB
11 9 dB
2 to 0 IR_MIXER[2:0] R [1] IR MIXER gain value
000 2 dB
001 5 dB
010 8 dB
011 11 dB
100 14 dB
[1] Other values are forbidden.
10.1.13 IRQ polarity

Table 26. IRQ polarity bit descriptions
37 Misc_byte_1 0 IRQ_Polarity R/W selects the IRQ pin polarity. IRQ pin
output voltage when IRQ raised:
0 VCC
1 0
10.1.14 rfcal_log
These bytes provides the outcome of the RF filter calibration. It can be used as an
indicator regarding RF filter robustness implementation on PCB.
Table 27. rfcal_log bit descriptions

38 rfcal_log_1 7 to 0 R - provides RF filter calibration results
39 rfcal_log_2 7 to 0 R - according to the following convention:
Bit [7] are set to 1 in case of calibration
3A rfcal_log_3 7 to 0 R -
error
3B rfcal_log_4 7 to 0 R -
Bit [6:0] is a signed number indicating
3C rfcal_log_5 7 to 0 R - the number of switch capacitors
3D rfcal_log_6 7 to 0 R -
3E rfcal_log_7 7 to 0 R -
3F rfcal_log_8 7 to 0 R -
40 rfcal_log_9 7 to 0 R -

10.1.15 Forbidden
Table 28. Forbidden bit descriptions
50 to 67 - 7 to 0 - - - do not write or read these bytes. Any
FE - 7 to 0 - - - modification of these bits can lead to
performance degradation.
FF - 7 to 0 - - -
10.2 Tuner programming sequences with IRQ

In the Figure 4,
• Transition 0 (initialization):
– write Power_state_byte_2 (address: 06): wakes the tuner up
– write Power_byte_2 (address 36; value 0C): post POR register update
– write AGC1_byte_2 (address 24; value 49): post POR register update
– write RF_Filter_byte_3 (address 2E; value 40): post POR register update
– write AGCK_byte_1 (address 0E; value FF): post POR register update
– write AGC5_byte_1 (address 11; value 4A): post POR register update
– write IRQ_clear (address 0A; value 9F): makes sure the IRQ status is reset
– write MSM_byte_1 (address 19; value 3B): selects which calibrations and/or
calculations to perform
– write MSM_byte_2 (address 1A; value 01): launches tuner calibration and/or
calculation
– read IRQ_status (address 08; value BF): IRQ is generated once operations are
completed
– write FLO_Max_byte (address 1D; value 0A) (slave only)
– write AGC1_byte_1 (address 0C; value 09)
– write Reference_byte (address 14; value 03)
– write Reference_byte (address 14): sets clock mode
– write Power_state_byte_2 (address 06): sets the tuner in Standby mode
• Transition 1 (standard selection):
– write Power_state_byte_2 (address 06; value 00): wakes the tuner up
– write IF_Frequency_byte (address 15)
– write IF_AGC_byte (address 12)
– write IF_byte_1 (address 13)
– write IR_MIXER_byte_2 (address 23)
– write AGC1_byte_1 (address 0C)
– write AGC2_byte_1 (address 0D)
– write AGCK_byte_1 (address 0E)
– write PSM_byte_1 (address 1B; value 60)
– write RF_AGC_byte_1 (address 0F)

– write IR_MIXER_byte_1 (address 10)

– write AGC5_byte_1 (address 11)
– These settings depend on received TV standard (standard and demodulator
dependant). Register values depend on the standard received.
• Transition 2 (first frequency selection after standard change):
– write Power_state_byte_2 (address 06): wakes the tuner up
– write RF_Frequency_byte_1 (address 16)
– write RF_Frequency_byte_2 (address 17)
– write RF_Frequency_byte_3 (address 18): sets the tuner to the required RF
frequency
– write MSM_byte_1 (address 19; value 41)
– write MSM_byte_2 (address 1A; value 01): RF filters tuning, PLL locking
– Tunes the settings that depend on the RF input frequency, expressed in kHz, RF
filters tuning, PLL locking
– read IRQ_status (address 08; value BF): IRQ raised once operations are
completed
• Transition 3 (standby):
– Power_state_byte_2 (address 06)
– Sets the tuner into one of the available Standby modes, keeping the digital data
unchanged
• Transition 4 (frequency selection within same standard):
– RF_Frequency_byte_1 (address 16)
– RF_Frequency_byte_2 (address 17)
– RF_Frequency_byte_3 (address 18): sets the tuner to the required RF frequency
– MSM_byte_1 (address 19; value 41)
– MSM_byte_2 (address 1A; value 01): RF filters tuning, PLL locking
– Tunes the settings that depend on the RF input frequency, expressed in kHz, RF
filters tuning, PLL locking
– read IRQ_status (address 08; value BF): IRQ raised once operations are
completed
Remark: a transition action can be launched only after having acknowledged the IRQ of
the previous state if applicable and clear the IRQ_clear byte.
Remark: IRQ can be polled in I2C-bus register table or checked on dedicated pin.
Remark: more details are available in user programming guide.

TUNER OFF
DC supply power-up
TUNER NOT
INITIALIZED
TUNER
INITIALIZED
AND
3 STANDBY
TUNER
INITIALIZED
3 AND 1
STANDBY
MODE
1
TUNER
INITIALIZED
AND
TUNER SETTINGS
1 CONFIGURED
AND
STANDBY
2 1
TUNER
INITIALIZED
AND
TV STANDARD 1
4 CONFIGURED
AND
RF FREQUENCY
LOCKED
3
2
TUNER
INITIALIZED
AND
TV STANDARD
3 CONFIGURED
AND
STANDBY
MODE
001aak484
Fig 4. Tuner programming sequence with IRQ

10.3 Channel change programming required parameters
10.3.1 Same reception mode

The new channel to be programmed is within the same standard as the previous one
(same channel demodulator).
To be programmed:
• RF frequency
• MSM byte
10.3.2 Different reception mode

The new channel to be programmed is from a different standard compared to the previous
one (different channel demodulator).
To be programmed:
• AGC TOP
• IF Frequency
• IF output level
• IF bandwidth
• RF frequency
• MSM byte
11. Hardware settings
11.1 XTOUT output level and I2C-bus address

Table 29. Pin AS_XTSEL decoding
Pin AS_XTSEL Tuner write address (hex) Tuner read address (hex) Tuner status
0 V to 0.1VCC C0 C1 XTOUT 400 mV (p-p); single ended
0.2VCC to 0.3VCC C0 C1 XTOUT 800 mV (p-p); single ended
0.4VCC to 0.6VCC C6 C7 XTOUT 400 mV (p-p); single ended
0.9VCC to VCC C6 C7 XTOUT 800 mV (p-p); single ended

12. Internal circuitry

Table 30. Internal circuits for each pin
Symbol Pin Description[1]
RFIN 2
001aak464
LT 3
001aak492
AS_XTSEL 6
001aak456
SCL 11
11
001aak465
SDA 12
12
001aak466
XTALP 14
14
001aak472
XTALN 15
15
001aak471

Table 30. Internal circuits for each pin …continued

CAPREGVCO 17
17
001aaf841
VTUNE 19
19
001aak470
CP 20
20
001aak458
XTOUT1 21
21
001aak473
XTOUT2 22
22
001aak474
IFN 24
24
001aak460
IFP 25
25
001aak461
VIFAGC 28
28
001aak469

Table 30. Internal circuits for each pin …continued

IRQ 30
30
001aak462
VHFLOW 32
32
001aak478
VHFHIGH 34
34
001aak477
UHFLOW 36
36
001aak476
UHFHIGH 38
36
001aak476
CAPRFAGC 40
40
001aak457
[1] ESD protection components are not shown.

13. Limiting values

Table 31. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.3 +3.6 V
VI input voltage pins SDA and SCL 0.3 +3.6 V
all other pins:
VCC < 3.3 V 0.3 VCC + 0.3 V
VCC > 3.3 V 0.3 +3.6 V
Tstg storage temperature 40 +150 C
Tj junction temperature - +120 C
Tamb ambient temperature 20 [1] C
VESD electrostatic discharge voltage EIA/JESD22-A114 (human body model) 2 +2 kV
EIA/JESD22-C101-C (FCDM) class III[2] 750 - V
[1] The maximum allowed ambient temperature Tamb(max) depends on the assembly conditions of the package and especially on the design
of the Printed-Circuit Board (PCB) and die connection. The application mounting must be done in such a way that the maximum junction
temperature is never exceeded. The junction temperature can be obtained by reading the temperature sensor bit via I2C-bus as
explained in Section 9.9 “Temperature sensor”. The junction temperature: Tj = Tamb + Tj-c. where Tj-c = power  Rth.
[2] Class III: 500 V to 1000 V.
14. Thermal characteristics

Table 32. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient according to JEDEC specification 4L 31.4 K/W
board with 9 thermal vias[1][2][3]
[1] Measured in free air as defined by JEDEC standard.

[2] These values are given for information only. The thermal resistance depends strongly on the nature and design of the PCB used in the
application. The thermal resistance given corresponds to the value that can be measured on a multilayer PCB (4 layers) as defined by
JEDEC standard.
[3] The junction temperature influences strongly the reliability of an IC. The PCB used in the application contributes in a large part to the
overall thermal characteristic. It must therefore be ensured that the junction temperature of the IC never exceeds Tj(max) = 120 C at the
maximum ambient temperature.

15. Characteristics
Table 33. General characteristics for TV reception (RF input to IF output)
Tamb = 25 C; VCC = 3.3 V; IF output level option 1 V (p-p); IF output load of 1 k/1 pF; AGC1 range: from 12 dB to +15 dB;
AGC1 TOP: 95 dBV/89 dBV; AGC3 TOP: 96 dBV; AGC4 TOP: 105 dBV/100 dBV; AGC5 TOP: 105 dBV/100 dBV;
IF_Level[2:0]: 6 dB/24 dB; unless otherwise specified.
VCC supply voltage 3.13 3.30 3.47 V
VO(p-p)(max) maximum peak-to-peak output differential IF output 0.5 - 2 V
voltage
ICC supply current operation mode 210 240 270 mA
Standby mode
crystal oscillator ON, XTOUT OFF, 28 38 48 mA
LT ON
only crystal oscillator ON 8 12 16 mA
center of channel 45 - 866 MHz
flo local oscillator frequency for respective IF frequency 50 - 870.25 MHz
VSWR voltage standing wave ratio RF input; 75  nominal impedance, - 2.6 3 -
level below 95 dBV
NFtun tuner noise figure 75  source; maximum gain - 5.0 5.9 dB
75  source; 60 dBV condition [1] - - 6.6 dB
Gv(max) maximum voltage gain all bands 82 86 - dB
Gv(min) minimum voltage gain all bands - 29 24 dB
Grsd residual gain variation in case of LNA AGC gain variation [2] - - 0.8 dB
GAGC(tun) tuner AGC gain range - 115 - dB
GAGC(IF) IF AGC gain range range measured between 0 V to 2 V [3] 29 30 31 dB
ICP1dB 1 dB input compression point at tuner input and minimum gain 124 - - dBV
n phase noise UHF and VHF bands:
at 1 kHz frequency offset - 94 85 dBc/Hz
at 10 kHz frequency offset - 93 87 dBc/Hz
at 100 kHz frequency offset - 106.5 103 dBc/Hz
tstartup(tun) tuner start-up time end of hardware initialization, using a [4] - 600 1500 ms
400 kHz I2C-bus speed
tset setting time tuner channel change - - 5 ms
IP3I input third-order intercept point gain corresponding to 100 dBV [5] 120 132 - dBV
IP2I input second-order intercept gain corresponding to 100 dBV [5] 150 165 - dBV
point
jit phase jitter UHF; integrated from 1 kHz to 4 MHz - 0.5 0.7 degree
f3dB(hpf) high-pass filter cut-off 3 dB cut-off frequency: [6] - - - -
frequency

Table 33. General characteristics for TV reception (RF input to IF output) …continued
Tamb = 25 C; VCC = 3.3 V; IF output level option 1 V (p-p); IF output load of 1 k/1 pF; AGC1 range: from 12 dB to +15 dB;
f3dB(lpf) low-pass filter cut-off frequency for a 1.7 MHz channel - 1.59 - MHz
for a 6 MHz channel - 6.58 - MHz
lpf low-pass filter attenuation N  1 sound carrier [7] 10 - - dB
N1 [8] 23 - - dB
N2 60 - - dB
> 18 MHz 60 - - dB
fc(notch) notch center frequency for 6 MHz LPF - 6.5 - MHz
for 7 MHz LPF - 7.25 - MHz
for 8 MHz LPF - 8.25 - MHz
Gtlt tilt gain in band, 6 MHz, 7 MHz and 8 MHz - 1 3 dB
channels
image image rejection worst case for image rejection and 55 63 - dB
4 MHz IF frequency for levels above
50 dBm
CSO composite second-order worst interferer over RF frequency with [9] - 52 48 dBc
distortion respect to wanted carrier
CTB composite triple beat worst interferer over RF frequency with [9] - 65 60 dBc
respect to wanted carrier
[1] Single wanted channel, 60 dBV, at tuner input.

[2] If this residual gain variation is too high for the demodulator being used, refer to the associated Application Note for details of how to
overcome this.
[3] See Figure 15.
[4] Corresponding to the time needed to launch and complete “tmbslTDA18219HNInit” and “tmbslTDA18219HNReset” functions in driver
reference code.
[5] Single wanted channel, 100 dBV level, at tuner input.
[6] See Table 34.
[7] Wanted channel being N, rejection of the N + n channel sound carrier for analog reception.
[8] Adjacent channel power rejection.
[9] QAM6 reception, LNA range from 12 dB to +15 dB
Table 34. High-Pass Filter cut-off frequencies descriptions

DC_NOTCH IF_HP_Fc[1:0] HI_Pass Min Typ Max Unit
0 XX 0 - 130 - kHz
1 XX 0 - 250 - kHz
1 00 1 - 290 - kHz
1 01 1 - 610 - kHz
1 10 1 - 720 - kHz
1 11 1 - 1080 - kHz

Table 35. General characteristics for TV reception (RF input to IF output) in case of LT usage
Tamb = 25 C; VCC = 3.3 V; IF output level option 1 V (p-p); IF output load of 1 k/1 pF; AGC1 range: from +6 dB to +15 dB;
Gv(max) maximum voltage gain all bands 82 86 - dB
Gv(min) minimum voltage gain all bands - 11 6 dB
Grsd residual gain variation in case of LNA AGC gain variation [1] - - 0.8 dB
GAGC(tun) tuner AGC gain range - 100 - dB
ICP1dB 1 dB input compression point at tuner input and minimum gain 102 110 - dBV
IP3I input third-order intercept point gain corresponding to 100 dBV [2] 102 - - dBV
IP2I input second-order intercept gain corresponding to 100 dBV [2] 132 - - dBV
point
[1] If this residual gain variation is too high for the demodulator being used, refer to the associated Application Note for details of how to
overcome this.
[2] Single wanted channel, 100 dBV level, at tuner input.
Table 36. Loop-through characteristics

Tamb = 25 C; VCC = 3.3 V; unless otherwise specified.
VSWR voltage standing wave ratio 75  nominal impedance - - 3
NF noise figure - 5.5 6.5 dB
Gv voltage gain 0 - 4 dB
CSO composite second-order distortion 129 NTSC channels 75 dBV input level:
QAM6 reception LNA range from 6 dB - 60 57 dBc
to 15 dB
CTB composite triple beat 129 NTSC channels 75 dBV input level:
QAM6 reception LNA range from 6 dB - 67 63 dBc
to 15 dB
Remark: The LT function is available whatever the AGC1 gain range, nevertheless if the
level is such that AGC1 goes below +6 dB, LT output will then reproduce AGC1 gain steps
from +3 dB to 12 dB if the AGC1 gain range is not limited by AGC1_6_15dB bit.
(address: 0C, bit 6).

Table 37. Pins Characteristics

Tamb = 25 C; VCC = 3.3 V; unless otherwise specified.
IF AGC input
VAGC AGC voltage 0 - VCC V
dGAGC/dV rate of change of AGC gain with voltage - 50 65 dB/V
Crystal oscillator
fxtal crystal frequency - 16 - MHz
Crystal oscillator output buffer
Ro output resistance 16 MHz output frequency - 460 - 
Digital levels (I2C-bus)[1]
Pin SCL
VIL LOW-level input voltage VCC related input levels - - 0.3VCC V
VIH HIGH-level input voltage VCC related input levels 0.7VCC - - V
fSCL SCL clock frequency - - 400 kHz
Pin SDA
VIL LOW-level input voltage VCC related input levels - - 0.3VCC V
VIH HIGH-level input voltage VCC related input levels 0.7VCC - - V
VOL LOW-level output voltage IO = 3 mA (sink current) - - 0.4 V
[1] Devices that use non-standard supply voltages, that do not conform the intended I2C-bus system levels, must relate their input levels to
the supply voltage (VCC) to which the pull-up resistors are connected.
These performances are measured in setting the tuner in following configuration:

2.2 nH 8.2 nH
100 nF
2.4 nH 100 nH
220 nF
UHFSUPPLY
VHFSUPPLY
CAPRFAGC
VHFSENSE
UHFHIGH
VHFHIGH
UHFLOW
VHFLOW
VCC(RF)
n.c.
40
39
38
37
36
35
34
33
32
31
VCC(RF) IRQ
1 30
1 nF
RFIN TEST3
2 29
1 nF 39 Ω(2)
LT VIFAGC
3 28
n.c. VCC(IF) 4.7 nF
4 27
n.c. GND(IF)
5 26
TDA18219HN 100 nF 560 Ω(2)
AS_XTSEL IFP
6 25
100 nF 560 Ω(2)
GND(DIG) IFN
7 24
n.c. TEST2
8 23
GND(RF) 4.7 nF
TEST4 XTOUT2
9 22
4.7 nF
GND(DIG) XTOUT1
10 21
12
13
14
15
16
17
18
19
20
11
SDA
SCL
XTALP
CP
TEST1
XTALN
VCC(SYNTH)
CAPREGVCO
GND(SYNTH)
VTUNE
CONNECTOR 2
SCL
SDA 220 nF
18 pF 18 pF
CONNECTOR 1 16 MHz(1) 100 nF 6.8 nF 270 Ω 2.7 nF

VCC(RF)
VCC(SYNTH)
VCC(IF)
GND
001aal176
Remark: Decoupling capacitors are not depicted.

(1) Quartz references are: NX5032GA and NX3225GA
(2) The series resistors connected on the pins 3, 24 and 25 are used for test purpose only; not necessary for the application
Fig 5. Measurement schematic
Table 38. Used coils type 402

Band Coil reference Component size
UHF HIGH COIL LQW15AN2N2C10 402
UHF LOW COIL LQP15MN2N4W02 402
VHF HIGH COIL LQP15MN8N2B02 402
VHF LOW COIL LQG15HNR10J02 402

Table 39. Used coils type 603

Band Coil reference Component size
UHF HIGH COIL LQW18AN2N2D00 603
UHF LOW COIL LQP18MN2N2C02 603
VHF HIGH COIL LQP18MN8N2C02 603
VHF LOW COIL LQW18ANR10J00 603
100 nH
34 Ω
3Ω 37.5 nH
IFP
IFN
34 Ω
100 nH
001aam115
Fig 6. Typical IF output impedance at 8 MHz
Remark: All following curves represent typical results observed on samples.
15.1 IF filtering curves
001aak481
0
DC_NOTCH = 0 DC_NOTCH = 1
level
(dB)
−20
−40
−60
−80
−15 −5 5 15
IF (MHz)
Fig 7. DC notch

001aak515
0
level
(dB)
DC_NOTCH = 0 DC_NOTCH = 1
−10
−20
−30
−40
−50
−1.0 −0.5 0 0.5 1.0
IF (MHz)
Fig 8. DC notch zoom
001aak489
0
level LPF = 1.7 MHz 6 MHz

(dB) 7 MHz
8 MHz
−20 9 MHz
−40
−60
−80
0 4 8 12 16 20
IF (MHz)
Fig 9. Low-Pass Filter

001aak485
0
level
(dB)
−10
0.4 MHz
−20 0.85 MHz
1 MHz
1.5 MHz
−30
−40
−50
0 1 2 3
IF (MHz)
Fig 10. High-Pass Filter
001aak480
0
level
(dB)
−10 IF notch = 6.5 MHz
7.25 MHz
8.25 MHz
−20
−30
−40
−50
0 4 8 12
IF (MHz)
Fig 11. IF notches

001aak487
0
level
(dB)
LPF = 1.7 MHz 6 MHz
−20 7 MHz
8 MHz
9 MHz
−40
−60
−80
−5 0 5 10 15 20
IF (MHz)
Fig 12. IF selectivity without notch
001aak486
0
level
(dB)
LPF = 1.7 MHz 6 MHz
−20 7 MHz
8 MHz
9 MHz
−40
−60
−80
−5 0 5 10 15 20
IF (MHz)
Fig 13. IF selectivity with notch

15.2 Phase noise curves
001aal178
−80
phase noise
(4)
(dBc/Hz)
(5)
−90
(2)
(3)
−100
(6)
(1)
−110
−120
0 200 400 600 800 1000
RF (MHz)
(1) 100 kHz

(2) 10 kHz
(3) 1 kHz
(4) Spec_1 kHz
(5) Spec_10 kHz
(6) Spec_100 kHz
Fig 14. Phase noise
15.3 IF AGC gain versus IF AGC voltage
001aak453
35
GAGC(IF)
(dB) GAGC(IF) level = 0 dB
−4 dB
25
−6 dB
−7.5 dB
−8 dB
15 −9 dB
−10.3 dB
−12 dB
-5
-15
0 0.4 0.8 1.2 1.6 2.0
VIFAGC (V)
Fig 15. IF AGC gain versus IF AGC voltage

15.4 NF curves
001aal533
8
noise figure
(dB)
0
0 200 400 600 800 1000
RF (MHz)
Fig 16. Noise figure

16. Application information
XTAL
VIFAGC
XTALN
XTALP
14 15 28
IFP TS
SILICON 25 DEMODULATOR
SURGE RFIN
2 TUNER IFN
DVB-C
CVBS
PROTECTION
TDA18219HN 24 DVB-T
21 22
XTOUT1
XTOUT2
001aal180
Fig 17. Tuner application diagram

17. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm SOT618-1
D B A
terminal 1
index area
A
E A1
c
detail X
e1 C
e 1/2 e b v M C A B y1 C y
11 20 w M C
L
21
10
Eh e2
1/2 e
1
30
terminal 1
index area 40 31
Dh X
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
A(1)
UNIT
max.
A1 b c D(1) Dh E(1) Eh e e1 e2 L v w y y1
mm 0.05 0.30 6.1 4.25 6.1 4.25 0.5

1 0.2 0.5 4.5 4.5 0.1 0.05 0.05 0.1
0.00 0.18 5.9 3.95 5.9 3.95 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
01-08-08
SOT618-1 --- MO-220 ---
02-10-22
Fig 18. Package outline SOT618-1 (HVQFN40)


18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
18.3 Wave soldering

Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities

18.4 Reflow soldering

Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 40 and 41
Table 40. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350  350
< 2.5 235 220
 2.5 220 220
Table 41. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 19.

maximum peak temperature

temperature = MSL limit, damage level
minimum peak temperature

= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level

Fig 19. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.
19. Abbreviations
Table 42. Abbreviations
Acronym Description
ACI Adjacent Channel Interferer
ADC Analog-to-Digital Converter
AGC Automatic Gain Control
AGCK Automatic Gain Control step Killer
D-BOOK Digital Terrestrial Television Requirements for Interoperability issued by the
Digital Television Group in UK
DTMB Digital Terrestrial Multimedia Broadcast
DVB Digital Video Broadcasting
DVB-T/C/H DVB-Terrestrial/Cable/Handheld
DVD-R DVD-Recorder
EMC ElectroMagnetic Compatibility
ESD ElectroStatic Discharge
EU European Union
FCDM Field-induced Charged-Device Model
FRAC-N FRACtional-N
HPF High-Pass Filter
IC Integrated Circuit
IF Intermediate Frequency
IR Image Rejection
IRQ Interrupt ReQuest

Table 42. Abbreviations …continued

Acronym Description
ISDB-T Integrated Services Digital Broadcasting - Terrestrial
LC-VCO Inductors and Capacitors - Voltage Controlled Oscillator
LNA Low-Noise Amplifier
LO Local Oscillator
LPF Low-Pass Filter
LT Loop-Through
MSM Main State Machine
NTSC National Television System Committee
PCTV Personal Computer Television
PLD Power Level Detector
PLL Phase-Locked Loop
POR Power-On Reset
RC CAL Resistors and Capacitors CALibrations
RF Radio Frequency
RoHS Restriction on Hazardous Substances
SAW Surface Acoustic Wave
STB Set Top Box
TOP Take Over Point
UHF Ultra High Frequency
VCO Voltage Controlled Oscillator
VHF Very High Frequency
20. Revision history

Table 43. Revision history
Document ID Release date Data sheet status Change notice Supersedes
TDA18219HN v.5 20111109 Product data sheet - TDA18219HN v.4
Modifications: • Table 4: updated description pin 9
• Figure 5: removed the ground pin 9
• Table 38: updated
TDA18219HN v.2 20100706 Preliminary data sheet - TDA18219HN_1
TDA18219HN_1 20100203 Objective data sheet - -

21. Legal information
21.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
Draft — The document is a draft version only. The content is still under
NXP Semiconductors products in such equipment or applications and
internal review and subject to formal approval, which may result in
therefore such inclusion and/or use is at the customer’s own risk.
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of Applications — Applications that are described herein for any of these
information included herein and shall have no liability for the consequences of products are for illustrative purposes only. NXP Semiconductors makes no
use of such information. representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended Customers are responsible for the design and operation of their applications
for quick reference only and should not be relied upon to contain detailed and and products using NXP Semiconductors products, and NXP Semiconductors
full information. For detailed and full information see the relevant full data accepts no liability for any assistance with applications or customer product
sheet, which is available on request via the local NXP Semiconductors sales design. It is customer’s sole responsibility to determine whether the NXP
office. In case of any inconsistency or conflict with the short data sheet, the Semiconductors product is suitable and fit for the customer’s applications and
full data sheet shall prevail. products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
Product specification — The information and data provided in a Product design and operating safeguards to minimize the risks associated with their
data sheet shall define the specification of the product as agreed between applications and products.
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however, NXP Semiconductors does not accept any liability related to any default,
shall an agreement be valid in which the NXP Semiconductors product is damage, costs or problem which is based on any weakness or default in the
deemed to offer functions and qualities beyond those described in the customer’s applications or products, or the application or use by customer’s
Product data sheet. third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
21.3 Disclaimers the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limited warranty and liability — Information in this document is believed to Limiting values — Stress above one or more limiting values (as defined in
be accurate and reliable. However, NXP Semiconductors does not give any the Absolute Maximum Ratings System of IEC 60134) will cause permanent
representations or warranties, expressed or implied, as to the accuracy or damage to the device. Limiting values are stress ratings only and (proper)
completeness of such information and shall have no liability for the operation of the device at these or any other conditions above those given in
consequences of use of such information. the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
In no event shall NXP Semiconductors be liable for any indirect, incidental,
repeated exposure to limiting values will permanently and irreversibly affect
punitive, special or consequential damages (including - without limitation - lost
the quality and reliability of the device.
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such Terms and conditions of commercial sale — NXP Semiconductors
damages are based on tort (including negligence), warranty, breach of products are sold subject to the general terms and conditions of commercial
contract or any other legal theory. sale, as published at http://www.nxp.com/profile/terms, unless otherwise
Notwithstanding any damages that customer might incur for any reason agreed in a valid written individual agreement. In case an individual
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards agreement is concluded only the terms and conditions of the respective
customer for the products described herein shall be limited in accordance agreement shall apply. NXP Semiconductors hereby expressly objects to
with the Terms and conditions of commercial sale of NXP Semiconductors. applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without No offer to sell or license — Nothing in this document may be interpreted or
limitation specifications and product descriptions, at any time and without construed as an offer to sell products that is open for acceptance or the grant,
notice. This document supersedes and replaces all information supplied prior conveyance or implication of any license under any copyrights, patents or
to the publication hereof. other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed, Export control — This document as well as the item(s) described herein
authorized or warranted to be suitable for use in life support, life-critical or may be subject to export control regulations. Export might require a prior
safety-critical systems or equipment, nor in applications where failure or authorization from competent authorities.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this
21.4 Licenses
document, and as such is not complete, exhaustive or legally binding.
ICs with DVB-T or DVB-T2 functionality
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified, Use of this product in any manner that complies with the DVB-T or the
the product is not suitable for automotive use. It is neither qualified nor tested DVB-T2 standard may require licenses under applicable patents of the
in accordance with automotive testing or application requirements. NXP DVB-T respectively the DVB-T2 patent portfolio, which license is available
Semiconductors accepts no liability for inclusion and/or use of from Sisvel S.p.A., Via Sestriere 100, 10060 None (TO), Italy, and under
non-automotive qualified products in automotive equipment or applications. applicable patents of other parties.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
21.5 Trademarks
product for such automotive applications, use and specifications, and (b) Notice: All referenced brands, product names, service names and trademarks
whenever customer uses the product for automotive applications beyond are the property of their respective owners.
NXP Semiconductors’ specifications such use shall be solely at customer’s
I2C-bus — logo is a trademark of NXP B.V.
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
22. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

23. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 5. AGC number/block correspondence . . . . . . . . .7
Table 6. Register table description . . . . . . . . . . . . . . . . .9
Table 7. ID byte bit descriptions . . . . . . . . . . . . . . . . . .12
Table 8. Temperature sensor bit descriptions . . . . . . . .12
Table 9. Power state bit descriptions . . . . . . . . . . . . . . .12
Table 10. Mode selection . . . . . . . . . . . . . . . . . . . . . . . .12
Table 11. Power level detector bit descriptions . . . . . . . .13
Table 12. IRQ bit descriptions . . . . . . . . . . . . . . . . . . . . .13
Table 13. AGC and Take Over Points bit descriptions . . .14
Table 14. AGC1 TOP values . . . . . . . . . . . . . . . . . . . . . .15
Table 18. Tuner output level . . . . . . . . . . . . . . . . . . . . . .16
Table 19. IF Filtering bit descriptions . . . . . . . . . . . . . . . .17
Table 20. Low-Pass Filter bits descriptions . . . . . . . . . . .17
Table 21. XTOUT bit descriptions . . . . . . . . . . . . . . . . . .18
Table 22. IF and RF frequency bit descriptions . . . . . . . .18
Table 23. Calibration control bit descriptions . . . . . . . . . .18
Table 24. IR Mixer bit descriptions . . . . . . . . . . . . . . . . .19
Table 25. AGC bit descriptions . . . . . . . . . . . . . . . . . . . .19
Table 26. IRQ polarity bit descriptions . . . . . . . . . . . . . . .20
Table 27. rfcal_log bit descriptions . . . . . . . . . . . . . . . . .20
Table 28. Forbidden bit descriptions . . . . . . . . . . . . . . . .21
Table 29. Pin AS_XTSEL decoding . . . . . . . . . . . . . . . . .24
Table 30. Internal circuits for each pin . . . . . . . . . . . . . . .25
Table 31. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 32. Thermal characteristics . . . . . . . . . . . . . . . . . .28
Table 33. General characteristics for TV reception
(RF input to IF output) . . . . . . . . . . . . . . . . . . .29
Table 34. High-Pass Filter cut-off frequencies
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 35. General characteristics for TV reception
(RF input to IF output) in case of LT usage . . .31
Table 36. Loop-through characteristics . . . . . . . . . . . . . .31
Table 37. Pins Characteristics . . . . . . . . . . . . . . . . . . . . .32
Table 38. Used coils type 402 . . . . . . . . . . . . . . . . . . . . .33
Table 39. Used coils type 603 . . . . . . . . . . . . . . . . . . . . .34
Table 40. SnPb eutectic process (from J-STD-020C) . . .43
Table 41. Lead-free process (from J-STD-020C) . . . . . .43
Table 42. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 43. Revision history . . . . . . . . . . . . . . . . . . . . . . . .45

24. Figures
Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Fig 2. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4
Fig 3. AGC1 TOP description example . . . . . . . . . . . . . .7
Fig 4. Tuner programming sequence with IRQ . . . . . . .23
Fig 5. Measurement schematic . . . . . . . . . . . . . . . . . . .33
Fig 6. Typical IF output impedance at 8 MHz. . . . . . . . .34
Fig 7. DC notch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Fig 8. DC notch zoom . . . . . . . . . . . . . . . . . . . . . . . . . .35
Fig 9. Low-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . .35
Fig 10. High-Pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . .36
Fig 11. IF notches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Fig 12. IF selectivity without notch . . . . . . . . . . . . . . . . . .37
Fig 13. IF selectivity with notch . . . . . . . . . . . . . . . . . . . .37
Fig 14. Phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Fig 15. IF AGC gain versus IF AGC voltage . . . . . . . . . .38
Fig 16. Noise figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Fig 17. Tuner application diagram . . . . . . . . . . . . . . . . . .40
Fig 18. Package outline SOT618-1 (HVQFN40) . . . . . . .41
Fig 19. Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

25. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 12 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 25
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 13 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 28
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 14 Thermal characteristics . . . . . . . . . . . . . . . . . 28
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 15 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 15.1 IF filtering curves . . . . . . . . . . . . . . . . . . . . . . 34
6 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 15.2 Phase noise curves . . . . . . . . . . . . . . . . . . . . 38
15.3 IF AGC gain versus IF AGC voltage . . . . . . . 38
7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
15.4 NF curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
16 Application information . . . . . . . . . . . . . . . . . 40
8.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
8.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 17 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 41
9 Functional description . . . . . . . . . . . . . . . . . . . 5 18 Soldering of SMD packages . . . . . . . . . . . . . . 42
9.1 RF filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 18.1 Introduction to soldering. . . . . . . . . . . . . . . . . 42
9.2 Crystal output mode . . . . . . . . . . . . . . . . . . . . . 6 18.2 Wave and reflow soldering. . . . . . . . . . . . . . . 42
9.3 AGC description . . . . . . . . . . . . . . . . . . . . . . . . 6 18.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 42
9.4 Low-Pass Filter (LPF) . . . . . . . . . . . . . . . . . . . . 7 18.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 43
9.5 High-Pass Filter (HPF) . . . . . . . . . . . . . . . . . . . 7 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.6 Notch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . 45
9.7 IR mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 21 Legal information . . . . . . . . . . . . . . . . . . . . . . 46
9.8 LO generation . . . . . . . . . . . . . . . . . . . . . . . . . . 8 21.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 46
9.9 Temperature sensor . . . . . . . . . . . . . . . . . . . . . 8 21.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.10 Power Level Detector (PLD) . . . . . . . . . . . . . . . 8 21.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.11 I2C-bus transceiver . . . . . . . . . . . . . . . . . . . . . . 8 21.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10 Control interface . . . . . . . . . . . . . . . . . . . . . . . . 9 21.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1 Register table description . . . . . . . . . . . . . . . . . 9 22 Contact information . . . . . . . . . . . . . . . . . . . . 47
10.1.1 Device type address ID . . . . . . . . . . . . . . . . . 12 23 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.1.2 Temperature sensor . . . . . . . . . . . . . . . . . . . . 12
24 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1.3 Power state. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10.1.4 Power level detector . . . . . . . . . . . . . . . . . . . . 13 25 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.1.5 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10.1.6 AGC and Take Over Points (TOP) . . . . . . . . . 14
10.1.7 IF Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10.1.8 XTOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.1.9 IF and RF frequency . . . . . . . . . . . . . . . . . . . . 18
10.1.10 Calibration controls . . . . . . . . . . . . . . . . . . . . . 18
10.1.11 IF filtering options . . . . . . . . . . . . . . . . . . . . . . 19
10.1.12 Gain values. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10.1.13 IRQ polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10.1.14 rfcal_log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10.1.15 Forbidden . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.2 Tuner programming sequences with IRQ . . . . 21
10.3 Channel change programming required
parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10.3.1 Same reception mode . . . . . . . . . . . . . . . . . . 24
10.3.2 Different reception mode . . . . . . . . . . . . . . . . 24
11 Hardware settings . . . . . . . . . . . . . . . . . . . . . . 24
11.1 XTOUT output level and I2C-bus address . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 November 2011
Document identifier: TDA18219HN

TDA18219HN: 1. General Description

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TDA18219HN

Silicon Tuner for terrestrial and cable digital TV reception

The TDA18219HN facilitates design-ins by:

• Allowing easy on-board integration

2. Features and benefits

4. Quick reference data

Product data sheet Rev. 5 — 9 November 2011 2 of 50

RF input LNA IF filters

AGC1 AGC2 AGC3 AGC5

Silicon Tuner for terrestrial and cable digital TV reception

Fig 1. Block diagram

Transparent top view

Fig 2. Pin configuration

8.2 Pin description

Product data sheet Rev. 5 — 9 November 2011 4 of 50

Table 4. Pin description …continued

Product data sheet Rev. 5 — 9 November 2011 5 of 50

A single LC-VCO operating at 7 GHz is used within a FRAC-N phase lock-loop to

9.2 Crystal output mode

9.3 AGC description

Product data sheet Rev. 5 — 9 November 2011 6 of 50

Table 5. AGC number/block correspondence

9.4 Low-Pass Filter (LPF)

9.5 High-Pass Filter (HPF)

Product data sheet Rev. 5 — 9 November 2011 7 of 50

9.6 Notch filter

9.9 Temperature sensor

9.10 Power Level Detector (PLD)

9.11 I2C-bus transceiver

Product data sheet Rev. 5 — 9 November 2011 8 of 50

05 Power_state_byte_1 - POR LO_Lock

Silicon Tuner for terrestrial and cable digital TV reception

14 Reference_byte 0 Digital_Clock - 0 - XTout[1:0]

Silicon Tuner for terrestrial and cable digital TV reception

34 IF_AGC_Gain_byte - LPF_GAIN[1:0] IR_MIXER[2:0]

Silicon Tuner for terrestrial and cable digital TV reception

• - means the value is undefined. No internal bit corresponds to this address.

10.1.1 Device type address ID

10.1.2 Temperature sensor

10.1.3 Power state

[1] See Table 10.

Table 10. Mode selection

[1] All others values are forbidden.

Product data sheet Rev. 5 — 9 November 2011 12 of 50

10.1.4 Power level detector

• Set MSM_byte_1 (value: 80) to indicate a power measurement is required

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10.1.6 AGC and Take Over Points (TOP)

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[1] See Table 14.

Table 14. AGC1 TOP values

[1] All others values are forbidden.

Table 15. AGC3 TOP values

Table 16. AGC4 TOP values

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Table 16. AGC4 TOP values …continued

[1] All others values are forbidden.

Table 17. AGC5 TOP values

[1] All others values are forbidden.