What is the difference between new () and new []?

- A new() is used for constructing object whereas new[] is used to declare a dynamic array.
- A constructor function does not have a return type. When you use a constructor, the left
hand side of the assignment determines the return type.

Myths and misconception surrounding constructors are abound. We will try to disspell some of
them here.

 "I must have a constructor for each class that I define."

It is not illegal not to have a constructor for each class, though having one will be a good
practice for your peace of mind.

As a matter of fact, whether you have a class-specific constructor or not, by default,

every class has a built-in constructor. This built-in constructor assigns each member to
its uninitialized value (e.g., x for a wire, 0 for a real etc.).

 "I must name my constructor as 'new'."

Although it is customary to name a constructor as 'new', any other name is fine too.

Triangle t = my_new();

 "I cannot pass any argument to new()."

On the contrary, it is always a good idea to make your constructor flexible by passing
arguments to it. For example, we can customize our own new() defined
within Triangle as:

Triangle t = new(first_arg, second_arg, last_arg);

Corresponding to this, the definition of new() within the class Triangle will look like (with
arbitrarily chosen types for first_arg, second_arg, etc.):

function new (int first_arg, time second_arg, bit third_arg);

... // rest of the definition goes here
Endfunction
Whenever the use of a variable (or object) ends, the System Verilog compiler automatically de-
allocates the memory for that variable.

What happened if don’t define new function in UVM?

- If you don’t use constructor for your class, it won’t give any compilation or simulation error
but few simulation reports will not get generated.

Refer https://pcisig.com/faq?field_category_value%5B%5D=pci_express_3.0&keys=
For PCIe question answers

What is PCLK in PCIe?

- This clock synchronizes the parallel interface between the PHY and the MAC . PLL generates
clock is called PCLK which is output from physical coding sub layer to Media access control
layer. PCLK 125MHz for 16-bit and 250MHz for 8-bit data width. For more detail please refer
PIPE architecture.
- The PCIe3.0 is providing 985 Mb/s of speed for each lane.
- Giga transfers per second GT/s are the same thing (in this case) as gigabits per second Gb/s
is called bandwidth, speed as well as bit rate.

The PLL generates the PCLK used in synchronizing the parallel PHY/MAC Interface based on the CLK
input. The PCLK frequency is 125 MHz for 16-bit implementations and 250 MHz for 8-bit
implementations. The PLL will produce a 250 MHz clock used as an input to the 8B/10B encoder and
decoder and the elastic buffer. The PLL will produce a 2.5 GHz clock that is used as an input to the
SERDES and the clock recovery circuitry.

How does the PCIe 3.0 8GT/s "double" the PCIe 2.0 5GT/s bit rate?

- The PCIe 2.0 bit rate is specified at 5GT/s, but with the 20 percent performance overhead of
the 8b/10b encoding scheme, the delivered bandwidth is actually 4Gbps. PCIe 3.0 removes
the requirement for 8b/10b encoding and uses a more efficient 128b/130b encoding
scheme instead. By removing this overhead, the interconnect bandwidth can be doubled to
8Gbps with the implementation of the PCIe 3.0 specification. This bandwidth is the same as
an interconnect running at 10GT/s with the 8b/10b encoding overhead. In this way, the
PCIe 3.0 specifications deliver the same effective bandwidth, but without the prohibitive
penalties associated with 10GT/s signaling, such as PHY design complexity and increased
silicon die size and power. The following table summarizes the bit rate and approximate
bandwidths for the various generations of the PCIe architecture: PCIe architecture Raw bit
rate Interconnect bandwidth Bandwidth per lane per direction Total bandwidth for x16 link

PCIe 1.x 2.5GT/s 2Gbps ~250MB/s ~8GB/s

PCIe 2.x 5.0GT/s 4Gbps ~500MB/s ~16GB/s
PCIe 3.0 8.0GT/s 8Gbps ~1GB/s ~32GB/s

Total bandwidth represents the aggregate interconnect bandwidth in both directions.

Refer http://www.hardwaresecrets.com/everything-you-need-to-know-about-the-pci-
express/3/

Operating frequency of gen3.0 PCIe?

2.5 GHz

Base Clock Speed: PCIe 3.0 = 8.0GHz, PCIe 2.0 = 5.0GHz, PCIe 1.1 = 2.5GHz
Data Rate: PCIe 3.0 = 1000MB/s, PCIe 2.0 = 500MB/s, PCIe 1.1 = 250MB/s
Total Bandwidth: (x16 link): PCIe 3.0 = 32GB/s, PCIe 2.0 = 16GB/s, PCIe 1.1 = 8GB/s
Data Transfer Rate: PCIe 3.0 = 8.0GT/s, PCIe 2.0= 5.0GT/s, PCIe 1.1 = 2.5GT/s
What is the data width in PCIe?

Data width is 8 bit or 16 bit between MAC layer and PCS layer as per PIPE specification.

Why do we need 8 to 10 encoding?

- To easily discriminate data and control at receiver as well as it ensures that encoded data
stream has certain amount of 0’s and 1’s transition to avoid long stream of continuous 1’s
and 0’s(DC).

What is ACK/NAK in PCIe?

- If data is received properly and buffer space is available at the Rx to accept that data
ACK(acknowledgement) is given to Tx else NAK(not acknowledgement) is given to Tx.

Difference between mailbox and queue?

How to start sequence from test?

- With sequesce.start(sequencer);
- With `uvm_do

Can we start two sequences simultaneously on same or on different sequencer?

- No.

Brief about LTSSM states?

How speed changes in PCIe?

- In recovery state speed changes. Read PCIe QA document for this answer.

How memory read or write takes place?

- PCIe runs big endian.

- When CS is low and R / W is low, the memory chip writes the data on the data bus into the
location indicated by the address bus. This allows the microprocessor to store data into
memory.

- When CS is low and R / W are high, the memory chip drives the data bus with the data
from the location indicated by the address bus. This allows the microprocessor to load data
out of memory into registers.

How you implemented design in your project.

- Read PCIe QA document for this answer.

Wafer space telephonic and F2F

What is the difference between uvm_object_utils and uvm_component_utils?

- The uvm_object_utils is dynamic means it doesn’t attached during entire simulation

whereas uvm_component_utils is static means it remains attached throughout the
simulation.

Why we can’t use uvm_component_utils in place of uvm_object_utils?

- Because if we use uvm_component_utils everywhere our objects get connected statically

due to which we cannot override them dynamically.

What is dynamic array? How to delete its 5th element?

- Int dyna_arr[];
Dyna_arr = new[5];
Dyna_arr = dyna_arr({0,2},4); // 3rd element deleted(not sure need to find solution)

What is factory method in uvm?

- Factory is used to register and create components and objects. If we don’t use factory we
cannot override them.

How to find the lowest value index from array?

- The min and max functions find the smallest and largest elements in an array. Note that
these functions return a queue, not a scalar as you might expect.(Page-43 chris spear)

What kind of responses in AXI?

What is virtual keyword in task and function?

- To override the functionality of task or function, virtual keyword is used.

Logic to sum 3, 6, 9, …, 50. Find the even numbers from this.(LSB= 0/1 its even/odd)

- For(int i = 1; i<50; i++) // 3+6+9+12…up to 50

Begin
Int sum = 0;
Sum = sum + (i*3); // 0+(1*3) = 3, 3+(2*3) = 9, 9+(3*3) = 18
If(sum==50) break;
End
What is copy method in system verilog. Any $cast is needed if yes then why?

What is uvm_config_db in UVM? Can we set uvm component in it?

What is associative array?

- Associative array is used if we want to create an array with elements at random locations. In
it if assign any value to any location then only memory will get allocated, otherwise memory
won’t get allocated.

Write logic for array to change its values in reverse order keep first and last values same.

- Dyn_arr[5] = `{1,2,3,4,5}; // desired output = 1,4,3,2,5

For(int i=0;i<dyn_arr.size();i++)
If(dyn_arr[0] || dyn_arr[$])
Else if
Dyn_arr = dyn_arr[1:$-1];
Dyn_arr = dyn_arr.reverse();

How build phase is executed in UVM? Why its top down?

- Ex – in Test below is written – explain the flow.

Virtual function build_phase(uvm_phase phase)
Display…
Env.build;
Component.build;
Display…
endfunction

Write a transaction class in SV. How to give few conditions to data fields in this class?

- Using inline constraints. Use randomize() with { ..; ..;};

Why do we need to assign lane numbers successively? Who assigns it in pcie?

- When the lane reversal is set incorrectly on an analyzer the user will only be able to record
ordered sets. Ordered sets such as Training or Skip sequences transmit the same symbol
simultaneously on all active lanes, and consequently they are not affected by lane ordering.
However DLLP and TLP packets are sensitive to lane ordering and must start with an SDP
or STP symbol in Logical lane#0. If these symbols are being transmitted on physical lane#3
with respect to the analyzer input and lane reversal has not been configured, an analyzer
will detect no valid packet start.
What is raise_objection and drop_objection?

- To stop simulation at the end of test when all phases have got executed.
- We can also use drain_time to stop simulation.

Driver and sequencer communication.

- Sequencer
Start_item(tx);
Assert(Tx.randomize);
Finish_item(tx);
- Driver
Seq_item_port.get_next_item(tx);
Seq_item_port.item_done();

Monitor and scoreboard communication.

- Mon.analysis_port -> agent.analysis_port -> scoreboard.analysis_import

What is virtual sequencer? When needed.

- Virtual Sequence decides which Agent’s (multiple agents and multiple interfaces with DUT)
Sequence will start first and the order of Sub-Sequences execution.
- A virtual sequence does not itself interact with a sequencer, it can be started without a
sequencer.
- Virtual sequences are typically used to coordinate the behavior of multiple agents (though
strictly speaking a sequence that coordinates multiple agents need not be a virtual
sequence.
- In UVM, Virtual Sequence can be implemented using 2 approaches.
- In the 1st approach, Virtual Sequence will contain itself the handles of the Agent’s
Sequencers on which the Sub-Sequences are to be executed.
- In the 2nd approach, Virtual Sequence will run on a Virtual Sequencer which is of type
uvm_sequencer. In this approach, Virtual Sequencer will contain the target Agent
Sequencer’s handle.

http://www.learnuvmverification.com/index.php/2016/02/23/how-virtual-sequence-works-
part-1/

How many phases in UVM? What is main phase in uvm?

- Main phase executes transaction and start sequences

Write (method) — a method that is called through an analysis port and implemented within a
component that has an analysis imp. The implementation of the method write typically
performs checking or functional coverage collection.

PVIP questions

How to off copy and compare or methods in uvm?

- Using uvm_field_* macros define transaction required methods. So use UVM_NOPACK for
excluding atomic creation of packing and unpacking method.
- `uvm_field_int(length, UVM_ALL_ON|UVM_NOPACK)

The `uvm_field_* macros are invoked inside of the `uvm_*_utils_begin and `uvm_*_utils_end
(`uvm_object_utils_begin or `uvm_component_utils_begin) macro blocks to form “automatic”
implementations of the core data methods: copy, compare, pack, unpack, record, print, and
sprint.

`uvm_field_int(ARG,FLAG)

ARG is an integral property of the class, and FLAG is a bitwise OR of one or more flag settings as
described in Field Macros above.

UVM_ALL_ON Set all operations on (default).

UVM_DEFAULT Use the default flag settings.

UVM_NOCOPY Do not copy this field.

UVM_NOCOMPAR Do not compare this field.

E

UVM_NOPRINT Do not print this field.

UVM_NOPACK Do not pack or unpack this field.

How to override constraints?

- U can extend constraint class and rewrite new constraints Or you can assert constraint off
and specify inline constraints while randomizing transaction object.

What us $bits?

pack_field_int

virtual function void pack_field_int (logic[63:0] value,

 int  size )

- Packs the integral value (less than or equal to 64 bits) into the pack array.  The size is the
number of bits to pack, usually obtained by $bits.  
- packer.pack_field_int(da,$bits(da));

 `uvm_sequence_utils is used to tie the sequence with sequencer.

Mobiveil questions
SGL in NVMe

Different ways to start sequence.

Difference between `uvm_do and `uvm_do_on_with

- `uvm_do we simply pass the sequence or item whereas in `uvm_do_on_with we need to

pass sequence, sequencer and constraints.

Handshake mechanism between sequencer and driver

How to get response from driver

Is it possible to connect sequencer and driver with analysis ports and scoreboard and monitor
with seq_item_port/export ?
- No. The seq_item_port is used exclusively for the sequencer/driver. The methods contained
within the seq_item_port are usable only by sequences and not meant for any other use.
- The seq_item_port is a specific type of port which allows bi-directional communication
between the sequencer and driver. There are several additional methods provided by it
which enable sequences to function.
Types of responses in AXI

How many numbers of completion queues in NVMe and how many entries in one completion
queue?