EXP1
EXP1
EXP1
EDU
VLSI Lab
Introduction :
SPICE (Simulation Program with Integrated Circuit Emphasis) is a very powerful and probably the most
widely used software for electrical and electronic circuits simulation. In this experiment our aim is to
introduce SPICE capabilities applied to CMOS VLSI circuits design. In SPICE we can do dc, ac, transient
and other types of analysis. Some common statements that will be needed in this experiment are given
below.
Resistor: R<name> <pos. node> <neg. node> <value>
Capacitor: C<name> <pos. node> <neg. node> <value>
Inductor: L<name> <pos. node> <neg. node> <value>
DC voltage source: V<name> <pos. node> <neg. node> <value>
Pulse voltage source: V<name> <pos. node> <neg. node> PULSE (V1 V2 TD TR TF PW PER) where V1 =
voltage level for logic 0, V2 = voltage level for logic 1, TD = time delay, TR = rise time, TF = fall time, PW =
pulse width, PER= pulse period.
Sinusoidal voltage source: V<name> <pos. node> <neg. node> SIN(dc_offset amplitude frequency).
Output :
To observe output in graphic mode we will use .PROBE statement. To observe output in printed form we
will use .PRINT <analysis type> <variable to be printed>
1
V1
MP
U
2 3
MP CL
V2
D
V1 1 0 DC 5V
V2 2 0 PULSE (0 5 3ns 3ns 3ns 20ns 40ns)
CL 3 0 0.15PF
MPU 3 2 1 1 IRF150
MPD 3 2 0 0 IRF250
.MODEL IRF250 NMOS (level=3 w=4u l= 3u vto=1.0 tox=470e-10 nsub=38e14
+ cj=160e-6 cjsw=430e-12 mj=0.5 mjsw=0.33 kp=30e-6 )
.MODEL IRF150 PMOS (level=3 w=10u l=3u vto=-1.0 tox=470e-10 nsub=8.7e14
+ cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 kp=12e-6)
.DC V2 0 5 0.1
.TRAN 1ns 80ns
.PROBE V(2,0) V(CL) ID(MPD) ID(MPU)
.END
Procedure :
1) Write the above code for CMOS inverter in PSPICE and test the functionality of the gate by transient
analysis.
2) Run the above program in dc analysis mode and observe output voltage. This is the transfer
characteristic of the inverter. From the curve measure the inversion voltage.
3) From the transient analysis determine the values of rise time and fall time of the output voltage.
Observe the transistor currents along with input and output voltages. The smaller current spikes
during logic transition cause switching power loss.
4) Change the width (w) of NMOS to 10u and run the program. Observe the dc transfer characteristic
and measure the inversion voltage and from the transient analysis determine the values of rise time
and fall time of the output voltage. You do not need to observe transistor currents in this step.
5) Change the width (w) of NMOS back to 4u and that of PMOS to 20u and run the program. Observe
the dc transfer characteristic and measure the inversion voltage and from the transient analysis
determine the values of rise time and fall time of the output voltage. Notice the change in three
cases.
Report :
1) Include the results and figures obtained in procedure.
2) Write the PSPICE program for 2-input CMOS NAND gate using the transistors used in above code.
Check its functionality by transient analysis and provide figures, code and circuit diagram.
3) Do the same as mentioned in 2 for a 2-input CMOS NOR gate.