William Stallings Computer Organization and Architecture
William Stallings Computer Organization and Architecture
William Stallings Computer Organization and Architecture
Computer Organization
and Architecture
Chapter 5
Internal Memory
Semiconductor Memory Types
Semiconductor Memory
• RAM
—Misnamed as all semiconductor memory is random
access
—Read/Write
—Volatile
—Temporary storage
—Static or dynamic
Memory Cell Operation
Dynamic RAM
• Bits stored as charge in capacitors
• Charges leak
• Need refreshing even when powered
• Simpler construction
• Smaller per bit
• Less expensive
• Need refresh circuits
• Slower
• Main memory
Dynamic RAM Structure
DRAM Operation
• Address line active when bit read or written
—Transistor switch closed (current flows)
• Write
—Voltage to bit line
– High for 1 low for 0
—Then signal address line
– Transfers charge to capacitor
• Read
—Address line selected
– transistor turns on
—Charge from capacitor fed via bit line to sense
amplifier
– Compares with reference value to determine 0 or 1
—Capacitor charge must be restored
Static RAM
• Bits stored as on/off switches
• No charges to leak
• No refreshing needed when powered
• More complex construction
• Larger per bit
• More expensive
• Does not need refresh circuits
• Faster
• Cache
• Digital
—Uses flip-flops
Logic state 1, C1 is high
and C2 is lowlow; in this
state T1 & T4 are off and
T2 & T3 are on
Stating RAM Structure
Static RAM Operation
• Transistor arrangement gives stable logic state
• State 1
—C1 high, C2 low
—T1 T4 off, T2 T3 on
• State 0
—C2 high, C1 low
—T2 T3 off, T1 T4 on
• Address line transistors T5 T6 is switch
• Write – apply value to B & compliment to B
• Read – value is on line B
SRAM v DRAM
• Both volatile
—Power needed to preserve data
• Dynamic cell
—Simpler to build, smaller
—More dense
—Less expensive
—Needs refresh
—Larger memory units
• Static
—Faster
—Cache
Read Only Memory (ROM)
• Permanent storage
—Nonvolatile
• Microprogramming (see later)
• Library subroutines
• Systems programs (BIOS)
• Function tables
Types of ROM
• Written during manufacture
—Very expensive for small runs
• Programmable (once)
—PROM
—Needs special equipment to program
• Read “mostly”
—Erasable Programmable (EPROM)
– Erased by UV
—Electrically Erasable (EEPROM)
– Takes much longer to write than read
—Flash memory
– Erase whole memory electrically
Organisation in detail
• A 16Mbit chip can be organised as 1M of 16 bit
words
• A bit per chip system has 16 lots of 1Mbit chip
with bit 1 of each word in chip 1 and so on
• A 16Mbit chip can be organised as a 2048 x
2048 x 4bit array
—Reduces number of address pins
– Multiplex row address and column address
– 11 pins to address (211=2048)
– Adding one more pin doubles range of values so x4 capacity
Refreshing
• Refresh circuit included on chip
• Disable chip
• Count through rows
• Read & Write back
• Takes time
• Slows down apparent performance
Typical 16 Mb DRAM (4M x 4)
Packaging
Module Organisation
• Contains only 1 bit per word
—Number of chips equal to the number of bits per
word
• A memory module consisting of 256K 8-bit
words could be organized
—18-bit address is needed that supplied to the module
from external source
—Address lines of a bus
• Address is presented to 8256K x 1-bit chips
—Provides the input/output of 1-bit
Module
Organisation (2)
Error Correction
• Hard Failure
—Permanent physical defect
—Harsh environmental abuse, manufacturing defect
• Soft Error
—Random, non-destructive
—No permanent damage to memory
—Power supply problem, alpha particle
—Radio active decay
• Includes logic for both detecting and correcting
errors
Error Correcting Code Function
Error Correcting Code Function (2)
• No errors are detected
—Fetched data bits are sent out
• An error is detected and possible to correct the
error
—Data bits + error correction bits fed into a corrector
and produced a corrected M bits to be sent out
• An error is detected, but not possible to correct
it
—Reported