STM32F100x4 STM32F100x6 STM32F100x8 STM32F100xB

STM32F100x4 STM32F100x6
STM32F100x8 STM32F100xB
Low & medium-density value line, advanced ARM-based 32-bit MCU
with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces
Features
■ Core: ARM 32-bit Cortex™-M3 CPU FBGA
– 24 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1) LQFP100 14 × 14 mm
performance LQFP64 10 × 10 mm TFBGA64 (5 × 5 mm)
LQFP48 7 × 7 mm
– Single-cycle multiplication and hardware
■ Up to 12 timers
division
– Up to three 16-bit timers, each with up to 4
■ Memories
IC/OC/PWM or pulse counter
– 16 to 128 Kbytes of Flash memory
– 16-bit, 6-channel advanced-control timer:
– 4 to 8 Kbytes of SRAM up to 6 channels for PWM output, dead
■ Clock, reset and supply management time generation and emergency stop
– 2.0 to 3.6 V application supply and I/Os – One 16-bit timer, with 2 IC/OC, 1
– POR, PDR and programmable voltage OCN/PWM, dead-time generation and
detector (PVD) emergency stop
– 4-to-24 MHz crystal oscillator – Two 16-bit timers, each with
– Internal 8 MHz factory-trimmed RC IC/OC/OCN/PWM, dead-time generation
– Internal 40 kHz RC and emergency stop
– PLL for CPU clock – 2 watchdog timers (Independent and
– 32 kHz oscillator for RTC with calibration Window)
– SysTick timer: 24-bit downcounter
■ Low power
– Two 16-bit basic timers to drive the DAC
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers ■ Up to 8 communications interfaces
– Up to two I2C interfaces (SMBus/PMBus)
■ Debug mode
– Up to 3 USARTs (ISO 7816 interface, LIN,
– Serial wire debug (SWD) and JTAG
IrDA capability, modem control)
interfaces
– Up to 2 SPIs (12 Mbit/s)
■ DMA
– Consumer electronics control (CEC)
– 7-channel DMA controller interface
– Peripherals supported: timers, ADC, SPIs,
■ CRC calculation unit, 96-bit unique ID
I2Cs, USARTs and DACs
■ ECOPACK® packages
■ 1 × 12-bit, 1.2 µs A/D converter (up to 16
channels)
Table 1. Device summary
– Conversion range: 0 to 3.6 V
Reference Part number
– Temperature sensor
STM32F100x4 STM32F100C4, STM32F100R4
■ 2 × 12-bit D/A converters
STM32F100x6 STM32F100C6, STM32F100R6
■ Up to 80 fast I/O ports STM32F100C8, STM32F100R8,
STM32F100x8
– 37/51/80 I/Os, all mappable on 16 external STM32F100V8
interrupt vectors and almost all 5 V-tolerant STM32F100xB
STM32F100CB, STM32F100RB,
STM32F100VB
July 2010 Doc ID 16455 Rev 5 1/86

www.st.com 1
Contents STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 14
2.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 14
2.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 15
2.7 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.11 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.12 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.13 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.14 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.15 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . . 17
2.16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.16.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.16.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16 & TIM17) . 18
2.16.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.16.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.16.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.16.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
²
2.17 I C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.18 Universal synchronous/asynchronous receiver transmitter (USART) . . . 20
2.19 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.20 HDMI (high-definition multimedia interface) consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/86 Doc ID 16455 Rev 5

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Contents
2.22 Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.23 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.24 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.25 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.26 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 35
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 35
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 54
5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.14 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Doc ID 16455 Rev 5 3/86

Contents STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
5.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 81
7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4/86 Doc ID 16455 Rev 5

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F100xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. STM32F100xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 6. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 8. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 9. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 11. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 12. Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. STM32F100xxB maximum current consumption in Sleep mode, code
running from Flash or RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 40
Table 16. Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 17. Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 44
Table 18. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 19. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 20. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 21. HSE 4-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 23. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 24. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 26. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 27. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 28. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 29. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 30. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 31. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 32. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 33. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 35. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 36. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 37. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 38. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 39. SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 40. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 41. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 42. RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 43. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 44. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Doc ID 16455 Rev 5 5/86

List of tables STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Table 45. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 46. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 47. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 75
Table 48. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 76
Table 49. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 77
Table 50. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 79
Table 51. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 52. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 53. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6/86 Doc ID 16455 Rev 5

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB List of figures
List of figures
Figure 1. STM32F100xx value line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. STM32F100xx value line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. STM32F100xx value line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. STM32F100xx value line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. STM32F100xx value line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 7. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 8. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. Maximum current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 39
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 39
Figure 14. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values
40
Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 17. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and
3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 19. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 20. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 22. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 23. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 24. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 25. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 26. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 28. I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 29. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 30. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 31. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 32. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 33. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 34. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 70
Figure 35. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 70
Figure 36. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 37. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 75
Figure 38. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 39. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 76
Figure 41. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 77
Figure 42. Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 78
Doc ID 16455 Rev 5 7/86

List of figures STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Figure 43. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 45. LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8/86 Doc ID 16455 Rev 5

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Introduction
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F100x4, STM32F100x6, STM32F100x8 and STM32F100xB value line
microcontrollers. In the rest of the document, the STM32F100x4 and STM32F100x6 are
referred to as low-density devices while the STM32F100x8 and STM32F100xB are
identified as medium-density devices.
The STM32F100xx datasheet should be read in conjunction with the low- and medium-
density STM32F100xx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F100xx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
Doc ID 16455 Rev 5 9/86

Description STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
2 Description
The STM32F100xx value line family incorporates the high-performance ARM Cortex™-M3
32-bit RISC core operating at a 24 MHz frequency, high-speed embedded memories (Flash
memory up to 128 Kbytes and SRAM up to 8 Kbytes), and an extensive range of enhanced
peripherals and I/Os connected to two APB buses. All devices offer standard communication
interfaces (up to two I2Cs, two SPIs, one HDMI CEC, and up to three USARTs), one 12-bit
ADC, two 12-bit DACs, up to six general-purpose 16-bit timers and an advanced-control
PWM timer.
The STM32F100xx low- and medium-density value line family operates in the –40 to +85 °C
and –40 to +105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive
set of power-saving mode allows the design of low-power applications.
The STM32F100xx value line family includes devices in three different packages ranging
from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are
included.
These features make the STM32F100xx value line microcontroller family suitable for a wide
range of applications such as application control and user interfaces, medical and handheld
equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs,
inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
10/86 Doc ID 16455 Rev 5

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Description
2.1 Device overview

The description below gives an overview of the complete range of peripherals proposed in
this family.
Figure 1 shows the general block diagram of the device family.
Table 2. STM32F100xx features and peripheral counts

Peripheral STM32F100Cx STM32F100Rx STM32F100Vx
Flash - Kbytes 16 32 64 128 16 32 64 128 64 128
SRAM - Kbytes 4 4 8 8 4 4 8 8 8 8
Advanced-control 1 1 1 1 1
Timers
General-purpose 5(1) 6 5(1) 6 6
SPI 1(2) 2 1(2) 2 2
2C
Communication I 1(3) 2 1(3) 2 2
interfaces USART 2(4) 3 2(4) 3 3
CEC 1
12-bit synchronized ADC 1 1 1
number of channels 10 channels 16 channels 16 channels
GPIOs 37 51 80
12-bit DAC 2
Number of channels 2
CPU frequency 24 MHz
Operating voltage 2.0 to 3.6 V
Ambient operating temperature: –40 to +85 °C /–40 to +105 °C (see Table 8)
Operating temperatures
Junction temperature: –40 to +125 °C (see Table 8)
Packages LQFP48 LQFP64, TFBGA64 LQFP100
1. TIM4 not present.
2. SPI2 is not present.
3. I2C2 is not present.
4. USART3 is not present.
Doc ID 16455 Rev 5 11/86

Figure 1. STM32F100xx value line block diagram
42!#%#,+
4RACE
42!#%$;= 40)* PBUS 0OWER
%4- CONTROLLER 6$$
AS!& 6$$6TO6
TRACETRIGGER 6OLTAGEREG
37*4!' 633
.*4234 6TO6
&LASH OBL
INTERFACE
*4$) )BUS &LASH+"
*4#+37#,+ #ORTEX -#05 BIT
6$$
*4-337$)/
*4$/ $BUS
FMAX -(Z 0/2 3UPPLY
AS!& SUPERVISION .234
32!- 2ESET
6$$!
+" 6$$! )NT 0/20$2
"USMATRIX
3YSTEM 633!
.6)# 2#(3 06$
2#,3
'0$-! 6$$!
6$$
/3#?).
CHANNELS
84!,/3# /3#?/54
0,, -(Z
0#,+ )7$'
2ESET
0#,+
!("& MAX -(Z
CLOCK 3TANDBY
CONTROL (#,+ INTERFACE 6"! 46TO6
&#,+
%84) 4 6"!4
!&
7+50
/3#?).
84!, K(Z
'0)/PORT! /3#?/54
0!;=
24# "ACKUP
REGISTER 4!- 0%2 24#
0";= '0)/PORT" !75
!,!2-/54
"ACKUPINTERFACE
0#;= '0)/PORT#
CHANNELS
!(" 4)-
!(" AS!&
0$;= '0)/PORT$ !0" !0"
CHANNELS
4)- AS!&
0%;= '0)/PORT%
CHANNELS
!0" & MAX -(Z 4)-
CHANNELSCOMPL AS!&
CHANNELAND"+). 4)- 2848#43243
AS!& 53!24
#+AS!&
CHANNELCOMPL 2848#43243
CHANNELAND"+). 4)- 53!24
#+AS!&
AS!&
CHANNELCOMPL -/3)-)3/
30)
!0"& MAX -(Z
CHANNELAND"+). 4)- 3#+.33AS!&

AS!&
($-)#%# ($-)#%#AS!&
CHANNELSCOMPL
CHANNELS%42AND 4)-
"+).AS!&
)# 3#,3$!3-"!AS!&
-/3)-)3/
3#+.33AS!& 30) 3#,3$!3-"!AS!&
)#
77$'
2848#43243
53!24
#+AS!&
4EMP SENSOR 4)- )& BIT$!# $!#?/54AS!&

)&
!$#CHANNELS BIT!$# )& 4)- BIT$!# $!# ?/54AS!&
!$#?).X
6
2%&
6 6$$!
2%&n 6$$!
AIB
1. Peripherals not present in low-density value line devices.

2. AF = alternate function on I/O port pin.
3. TA = –40 °C to +85 °C (junction temperature up to 105 °C) or TA = –40 °C to +105 °C (junction temperature up to 125 °C).
12/86 Doc ID 16455 Rev 5

Figure 2. Clock tree
-(Z
(3)2# (3)

(#,+
-(ZMAX TO!("BUSCORE
#LOCK MEMORYAND$-!
%NABLE
TO#ORTEX3YSTEMTIMER
0,,32# 37
0,,-5, &#,+#ORTEX
(3) FREERUNNINGCLOCK
X 393#,+ !(" !0"
-(ZMAX 0#,+
XXX 0,,#,+ -(Z
0RESCALER 0RESCALER
TO!0"
0,, MAX PERIPHERALS
0ERIPHERAL#LOCK
(3%
%NABLE
4)-
)F!0"PRESCALER X TO4)-AND
#33 ELSEX 4)-X#,+
0ERIPHERAL#LOCK
%NABLE
02%$)6 !0"
-(ZMAX 0#,+
0RESCALER
/3#?/54 PERIPHERALSTO!0"
-(Z 0ERIPHERAL#LOCK
(3%/3# %NABLE
/3#?). TO4)-4)-
4)-TIMERS 4)-AND4)-
)F!0"PRESCALER X
ELSEX 4)-X#,+
0ERIPHERAL#LOCK
%NABLE
!$# TO!$#
/3#?). TO24#
,3%/3# ,3% 0RESCALER
!$##,+-(ZMAX
K(Z 24##,+
/3#?/54
24#3%,;=
TOINDEPENDENTWATCHDOG)7$'
,3)2# ,3)
K(Z )7$'#,+
-AIN ,EGEND
0,,#,+
CLOC KOUT PUT (3%(IGH SPEEDEXTERNALCLOCKSIGNAL
-#/ (3) (3) (IGH SPEEDINTERNALCLOCKSIGNAL
(3% ,3),OW SPEEDINTERNALCLOCKSIGNAL
393#,+ ,3%,OW SPEEDEXTERNALCLOCKSIGNAL
-#/
AI
4. To have an ADC conversion time of 1.2 µs, APB2 must be at 24 MHz.
Doc ID 16455 Rev 5 13/86

2.2 Overview
2.2.1 ARM® Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F100xx value line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
2.3 Embedded Flash memory

Up to 128 Kbytes of embedded Flash memory is available for storing programs and data.
2.4 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
2.5 Embedded SRAM

Up to 8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
14/86 Doc ID 16455 Rev 5

2.6 Nested vectored interrupt controller (NVIC)

The STM32F100xx value line embeds a nested vectored interrupt controller able to handle
up to 41 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)
and 16 priority levels.
● Closely coupled NVIC gives low latency interrupt processing
● Interrupt entry vector table address passed directly to the core
● Closely coupled NVIC core interface
● Allows early processing of interrupts
● Processing of late arriving higher priority interrupts
● Support for tail-chaining
● Processor state automatically saved
● Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.7 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 18 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
2.8 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 24 MHz.
2.9 Boot modes

At startup, boot pins are used to select one of three boot options:
● Boot from user Flash
● Boot from system memory
● Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Doc ID 16455 Rev 5 15/86

2.10 Power supply schemes

● VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
● VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used).
VDDA and VSSA must be connected to VDD and VSS, respectively.
● VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
2.11 Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher
than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.12 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.
● MR is used in the nominal regulation mode (Run)
● LPR is used in the Stop mode
● Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
2.13 Low-power modes

The STM32F100xx value line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
● Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
● Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
16/86 Doc ID 16455 Rev 5

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
● Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
2.14 DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, DAC, I2C, USART, all timers and
ADC.
2.15 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit
registers used to store 20 bytes of user application data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.16 Timers and watchdogs

The STM32F100xx devices include an advanced-control timer, six general-purpose timers,
two basic timers and two watchdog timers.
Table 3 compares the features of the advanced-control, general-purpose and basic timers.
Doc ID 16455 Rev 5 17/86

Table 3. Timer feature comparison

Counter Counter Prescaler DMA request Capture/compare Complementary
Timer
resolution type factor generation channels outputs
Up, Any integer

TIM1 16-bit down, between 1 Yes 4 Yes
up/down and 65536
TIM2, Up, Any integer
TIM3, 16-bit down, between 1 Yes 4 No
TIM4 up/down and 65536
Any integer
TIM15 16-bit Up between 1 Yes 2 Yes
and 65536
Any integer
TIM16,
16-bit Up between 1 Yes 1 Yes
TIM17
and 65536
Any integer
TIM6,
16-bit Up between 1 Yes 0 No
TIM7
and 65536
2.16.1 Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:
● Input capture
● Output compare
● PWM generation (edge or center-aligned modes)
● One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard TIM timers which have the same
architecture. The advanced control timer can therefore work together with the TIM timers via
the Timer Link feature for synchronization or event chaining.
2.16.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16 & TIM17)
There are six synchronizable general-purpose timers embedded in the STM32F100xx
devices (see Table 3 for differences). Each general-purpose timers can be used to generate
PWM outputs, or as simple time base.
TIM2, TIM3, TIM4
STM32F100xx devices feature three synchronizable 4-channels general-purpose timers.

These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.
They feature 4 independent channels each for input capture/output compare, PWM or one-
18/86 Doc ID 16455 Rev 5

pulse mode output. This gives up to 12 input captures/output compares/PWMs on the

largest packages.
The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM1
advanced-control timer via the Timer Link feature for synchronization or event chaining.
TIM2, TIM3, TIM4 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM15, TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with
TIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and
independent DMA request generation
Their counters can be frozen in debug mode.
2.16.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
2.16.4 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
2.16.5 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
Doc ID 16455 Rev 5 19/86

2.16.6 SysTick timer

This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
● A 24-bit down counter
● Autoreload capability
● Maskable system interrupt generation when the counter reaches 0.
● Programmable clock source
2.17 I²C bus

The I²C bus interface can operate in multimaster and slave modes. It can support standard
and fast modes.
It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.
A hardware CRC generation/verification is embedded.
The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.
2.18 Universal synchronous/asynchronous receiver transmitter

(USART)
The STM32F100xx value line embeds three universal synchronous/asynchronous receiver
transmitters (USART1, USART2 and USART3).
The available USART interfaces communicate at up to 3 Mbit/s. They provide hardware
management of the CTS and RTS signals, they support IrDA SIR ENDEC, the
multiprocessor communication mode, the single-wire half-duplex communication mode and
have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
2.19 Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 12 Mbit/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits.
Both SPIs can be served by the DMA controller.
2.20 HDMI (high-definition multimedia interface) consumer

electronics control (CEC)
The STM32F100xx value line embeds a HDMI-CEC controller that provides hardware
support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI
standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead.
20/86 Doc ID 16455 Rev 5

2.21 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
2.22 Remap capability

This feature allows the use of a maximum number of peripherals in a given application.
Indeed, alternate functions are available not only on the default pins but also on other
specific pins onto which they are remappable. This has the advantage of making board
design and port usage much more flexible.
For details refer to Table 4: STM32F100xx pin definitions; it shows the list of remappable
alternate functions and the pins onto which they can be remapped. See the STM32F10xxx
reference manual for software considerations.
2.23 ADC (analog-to-digital converter)

The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
2.24 DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in noninverting configuration.
This dual digital Interface supports the following features:
● two DAC converters: one for each output channel
● up to 10-bit output
● left or right data alignment in 12-bit mode
● synchronized update capability
● noise-wave generation
● triangular-wave generation
● dual DAC channels’ independent or simultaneous conversions
● DMA capability for each channel
● external triggers for conversion
● input voltage reference VREF+
Doc ID 16455 Rev 5 21/86

Eight DAC trigger inputs are used in the STM32F100xx. The DAC channels are triggered
through the timer update outputs that are also connected to different DMA channels.
2.25 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC1_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
2.26 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
22/86 Doc ID 16455 Rev 5

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Pinouts and pin description
3 Pinouts and pin description
Figure 3. STM32F100xx value line LQFP100 pinout
BOOT0
VDD_3
VSS_3
PC12
PC11
PC10
PA15
PA14
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD_2
PE3 2 74 VSS_2
PE4 3 73 NC
PE5 4 72 PA 13
PE6 5 71 PA 12
VBAT 6 70 PA 11
PC13-TAMPER-RTC 7 69 PA 10
PC14-OSC32_IN 8 68 PA 9
PC15-OSC32_OUT 9 67 PA 8
VSS_5 10 66 PC9
VDD_5 11 65 PC8
OSC_IN 12
LQFP100 64 PC7
OSC_OUT 13 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0-WKUP 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
ai14386b
Doc ID 16455 Rev 5 23/86

Pinouts and pin description STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
BOOT0
VDD_3
VSS_3
PC12
PC11
PC10
PA15
PA14
PD2
PB9
PB8
PB7
PB6
PB5
PB4
PB3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT 1 48 VDD_2
PC13-TAMPER-RTC 2 47 VSS_2
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PD0 OSC_IN 5 44 PA11
PD1 OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9
LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0-WKUP 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
ai14387b

BOOT0
VDD_3
VSS_3
PA15
PA14
PB9
PB8
PB7
PB6
PB5
PB4
PB3
48 47 46 45 44 43 42 41 40 39 38 37
VBAT 1 36 VDD_2
PC13-TAMPER-RTC 2 35 VSS_2
PC14-OSC32_IN 3 34 PA13
PC15-OSC32_OUT 4 33 PA12
PD0-OSC_IN 5 32 PA11
PD1-OSC_OUT 6 31 PA10
NRST 7
LQFP48 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0-WKUP 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13 14 15 16 17 18 19 20 21 22 23 24
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
ai14378d
24/86 Doc ID 16455 Rev 5

Figure 6. STM32F100xx value line TFBGA64 ballout

1 2 3 4 5 6 7 8
PC14- PC13-
A OSC32_IN TAMPER-RTC PB9 PB4 PB3 PA15 PA14 PA13
PC15-
B OSC32_OUT VBAT PB8 BOOT0 PD2 PC11 PC10 PA12
C OSC_IN VSS_4 PB7 PB5 PC12 PA10 PA9 PA11
D OSC_OUT VDD_4 PB6 VSS_3 VSS_2 VSS_1 PA8 PC9
E NRST PC1 PC0 VDD_3 VDD_2 VDD_1 PC7 PC8
F VSSA PC2 PA2 PA5 PB0 PC6 PB15 PB14
G VREF+ PA0-WKUP PA3 PA6 PB1 PB2 PB10 PB13
H VDDA PA1 PA4 PA7 PC4 PC5 PB11 PB12
AI15494
Table 4. STM32F100xx pin definitions

Pins Alternate functions(3)(4)
I / O level(2)
Type(1)
Main
TFBGA64
LQFP100
LQFP64
LQFP48
Pin name function(3)

(after reset) Default Remap
1 - - - PE2 I/O FT PE2 TRACECLK

2 - - - PE3 I/O FT PE3 TRACED0
6 1 B2 1 VBAT S VBAT
PC13-TAMPER-
7 2 A2 2 I/O PC13(6) TAMPER-RTC
RTC(5)
Doc ID 16455 Rev 5 25/86

Table 4. STM32F100xx pin definitions (continued)

I / O level(2)
Type(1)
Main
TFBGA64
LQFP100
LQFP64
LQFP48 Pin name function(3)

PC14-
8 3 A1 3 I/O PC14(6) OSC32_IN
OSC32_IN(5)
PC15-
9 4 B1 4 I/O PC15(6) OSC32_OUT
OSC32_OUT(5)
10 - - - VSS_5 S VSS_5
11 - - - VDD_5 S VDD_5
12 5 C1 5 OSC_IN I OSC_IN
13 6 D1 6 OSC_OUT O OSC_OUT
14 7 E1 7 NRST I/O NRST
15 8 E3 - PC0 I/O PC0 ADC1_IN10
16 9 E2 - PC1 I/O PC1 ADC1_IN11
17 10 F2 - PC2 I/O PC2 ADC1_IN12
18 11 -(7) - PC3 I/O PC3 ADC1_IN13
19 12 F1 8 VSSA S VSSA
20 - - - VREF- S VREF-
21 - G1 - VREF+ S VREF+
22 13 H1 9 VDDA S VDDA
WKUP / USART2_CTS(12)/
23 14 G2 10 PA0-WKUP I/O PA0
ADC1_IN0 / TIM2_CH1_ETR(12)
USART2_RTS(12)/ ADC1_IN1 /
24 15 H2 11 PA1 I/O PA1
TIM2_CH2(12)
USART2_TX(12)/ ADC1_IN2 /
25 16 F3 12 PA2 I/O PA2
TIM2_CH3(12)/ TIM15_CH1(12)
USART2_RX(12)/ ADC1_IN3 /
26 17 G3 13 PA3 I/O PA3
TIM2_CH4(12) / TIM15_CH2(12)
27 18 C2 - VSS_4 S VSS_4
28 19 D2 - VDD_4 S VDD_4
SPI1_NSS(12)/ADC1_IN4
29 20 H3 14 PA4 I/O PA4
USART2_CK(12) / DAC1_OUT
SPI1_SCK(12)/ADC1_IN5 /
30 21 F4 15 PA5 I/O PA5
DAC2_OUT
SPI1_MISO(12)/ADC1_IN6 / TIM1_BKIN /
31 22 G4 16 PA6 I/O PA6
TIM3_CH1(12) TIM16_CH1
SPI1_MOSI(12)/ADC1_IN7 / TIM1_CH1N /
32 23 H4 17 PA7 I/O PA7
TIM3_CH2(12) TIM17_CH1
33 24 H5 - PC4 I/O PC4 ADC1_IN14
26/86 Doc ID 16455 Rev 5


I / O level(2)
Type(1)
Main
TFBGA64
LQFP100
LQFP64

34 25 H6 - PC5 I/O PC5 ADC1_IN15

35 26 F5 18 PB0 I/O PB0 ADC1_IN8/TIM3_CH3(12) TIM1_CH2N
(12)
36 27 G5 19 PB1 I/O PB1 ADC1_IN9/TIM3_CH4 TIM1_CH3N
37 28 G6 20 PB2 I/O FT PB2/BOOT1
38 - - - PE7 I/O FT PE7 TIM1_ETR
39 - - - PE8 I/O FT PE8 TIM1_CH1N
40 - - - PE9 I/O FT PE9 TIM1_CH1
42 - - - PE11 I/O FT PE11 TIM1_CH2
44 - - - PE13 I/O FT PE13 TIM1_CH3
45 - - - PE14 I/O FT PE14 TIM1_CH4
46 - - - PE15 I/O FT PE15 TIM1_BKIN
TIM2_CH3 /
47 29 G7 21 PB10 I/O FT PB10 I2C2_SCL(8)/USART3_TX (12)
CEC
48 30 H7 22 PB11 I/O FT PB11 I2C2_SDA(8)/USART3_RX(12) TIM2_CH4
49 31 D6 23 VSS_1 S VSS_1
50 32 E6 24 VDD_1 S VDD_1
SPI2_NSS(9)/ I2C2_SMBA(8)/
51 33 H8 25 PB12 I/O FT PB12
TIM1_BKIN(12)/USART3_CK(12)
SPI2_SCK(9) /TIM1_CH1N(12)
52 34 G8 26 PB13 I/O FT PB13
USART3_CTS(12)
SPI2_MISO(9)/ TIM1_CH2N(12) /
53 35 F8 27 PB14 I/O FT PB14 TIM15_CH1
USART3_RTS(12)
SPI2_MOSI(9) / TIM1_CH3N /
54 36 F7 28 PB15 I/O FT PB15 TIM15_CH2
TIM15_CH1N(12)
55 - - - PD8 I/O FT PD8 USART3_TX
56 - - - PD9 I/O FT PD9 USART3_RX
57 - - - PD10 I/O FT PD10 USART3_CK
58 - - - PD11 I/O FT PD11 USART3_CTS
TIM4_CH1(10) /
59 - - - PD12 I/O FT PD12
USART3_RTS
60 - - - PD13 I/O FT PD13 TIM4_CH2(10)
61 - - - PD14 I/O FT PD14 TIM4_CH3(10)
Doc ID 16455 Rev 5 27/86


I / O level(2)
Type(1)
Main
TFBGA64
LQFP100
LQFP64

62 - - - PD15 I/O FT PD15 TIM4_CH4(10)

63 37 F6 - PC6 I/O FT PC6 TIM3_CH1
64 38 E7 PC7 I/O FT PC7 TIM3_CH2
65 39 E8 PC8 I/O FT PC8 TIM3_CH3
66 40 D8 - PC9 I/O FT PC9 TIM3_CH4
USART1_CK / MCO /
67 41 D7 29 PA8 I/O FT PA8
TIM1_CH1
68 42 C7 30 PA9 I/O FT PA9 USART1_TX(12) / TIM1_CH2 TIM15_BKIN
(12)
69 43 C6 31 PA10 I/O FT PA10 USART1_RX / TIM1_CH3 TIM17_BKIN
70 44 C8 32 PA11 I/O FT PA11 USART1_CTS / TIM1_CH4
71 45 B8 33 PA12 I/O FT PA12 USART1_RTS / TIM1_ETR
JTMS-
72 46 A8 34 PA13 I/O FT PA13
SWDIO
73 - - - Not connected
74 47 D5 35 VSS_2 S VSS_2
75 48 E5 36 VDD_2 S VDD_2
JTCK/SWCL
76 49 A7 37 PA14 I/O FT PA14
K
TIM2_CH1_ETR
77 50 A6 38 PA15 I/O FT JTDI / PA15/
SPI1_NSS
78 51 B7 - PC10 I/O FT PC10 USART3_TX
79 52 B6 - PC11 I/O FT PC11 USART3_RX
80 53 C5 - PC12 I/O FT PC12 USART3_CK
(11)
81 5 C1 5 PD0 I/O FT OSC_IN
82 6 D1 6 PD1 I/O FT OSC_OUT(11)
83 54 B5 PD2 I/O FT PD2 TIM3_ETR
84 - - - PD3 I/O FT PD3 USART2_CTS
85 - - - PD4 I/O FT PD4 USART2_RTS
86 - - - PD5 I/O FT PD5 USART2_TX
87 - - - PD6 I/O FT PD6 USART2_RX
88 - - - PD7 I/O FT PD7 USART2_CK
TIM2_CH2 / PB3
89 55 A5 39 PB3 I/O FT JTDO TRACESWO
SPI1_SCK
28/86 Doc ID 16455 Rev 5


I / O level(2)
Type(1)
Main
TFBGA64
LQFP100
LQFP64

PB4 / TIM3_CH1
90 56 A4 40 PB4 I/O FT NJTRST
SPI1_MISO
TIM3_CH2 /
91 57 C4 41 PB5 I/O PB5 I2C1_SMBA / TIM16_BKIN
SPI1_MOSI
I2C1_SCL(12)/ TIM4_CH1(10)(12)
92 58 D3 42 PB6 I/O FT PB6 USART1_TX
TIM16_CH1N
I2C1_SDA(12)/ TIM17_CH1N
93 59 C3 43 PB7 I/O FT PB7 USART1_RX
TIM4_CH2(10)(12)
94 60 B4 44 BOOT0 I BOOT0
TIM4_CH3(10)(12) /
95 61 B3 45 PB8 I/O FT PB8 I2C1_SCL
TIM16_CH1(12) / CEC(12)
TIM4_CH4(10)(12) /
96 62 A3 46 PB9 I/O FT PB9 I2C1_SDA
TIM17_CH1(12)
97 - - - PE0 I/O FT PE0 TIM4_ETR(10)
98 - - - PE1 I/O FT PE1
99 63 D4 47 VSS_3 S VSS_3
100 64 E4 48 VDD_3 S VDD_3
1. I = input, O = output, S = supply, HiZ= high impedance.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch and since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.
8. I2C2 is not present on low-density value line devices.
9. SPI2 is not present on low-density value line devices.
10. TIM4 is not present on low-density value line devices.
11. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages and C1 and C2 in the
TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be
remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in
the STM32F10xxx reference manual.
12. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
Doc ID 16455 Rev 5 29/86

Memory mapping STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
4 Memory mapping
The memory map is shown in Figure 7.
Figure 7. Memory map

APB memory space
0xFFFF FFFF
reserved
0x4002 3400
CRC
0x4002 3000
reserved
0x4002 2400
0xFFFF FFFF 0x4002 2000 Flash interface
0x4002 1400 reserved
0x4002 1000 RCC

7 reserved
0x4002 0400
0xE010 0000 0x4002 0000 DMA
Cortex-M3 internal
0xE000 0000 peripherals reserved
0x4001 4C00
TIM17
0x4001 4800
TIM16
0x4001 4400
6 TIM15
0x4001 4000
reserved
0xC000 0000 0x4001 3C00
USART1
0x4001 3800
reserved
0x4001 3400
SPI1
5 0x4001 3000
TIM1
0x4001 2C00
0xA000 0000 reserved
0x4001 2800
ADC1
0x4001 2400
reserved
0x4001 1C00
0x4001 1800 Port E
4 0x1FFF FFFF
reserved Port D
0x1FFF F80F 0x4001 1400
0x4001 1000 Port C
0x8000 0000 Option Bytes
0x1FFF F800 0x4001 0C00 Port B
0x4001 0800 Port A

3 System memory 0x4001 0400 EXTI
0x4001 0000 AFIO

0x1FFF F000 reserved
0x6000 0000 0x4000 7C00
0x4000 7800 CEC
DAC
0x4000 7400
2 PWR
0x4000 7000
BKP
reserved 0x4000 6C00
Peripherals I2C2
0x4000 0000 0x4000 5C00
reserved
0x4000 5800
0x4000 5400 I2C1
1
reserved
0x4000 4C00
USART3
SRAM 0x4000 4800
0x2000 0000 USART2
0x0801 FFFF 0x4000 4400
reserved
0x4000 3C00
SPI2
0 Flash memory 0x4000 3800
0x4000 3400 reserved
0x0800 0000
0x4000 3000 IWDG
0x0000 0000 Aliased to Flash or
system memory 0x4000 2C00 WWDG
depending on 0x4000 2800 RTC
0x0000 0000 BOOT pins
Reserved reserved
0x4000 1800
TIM7
0x4000 1400
TIM6
0x4000 1000
reserved
0x4000 0C00
0x4000 0800 TIM4
0x4000 0400 TIM3
0x4000 0000 TIM2

ai17156
30/86 Doc ID 16455 Rev 5

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Electrical characteristics
5 Electrical characteristics
5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3).
5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2 V  VDD  3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2).
5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 8.
5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9.
Doc ID 16455 Rev 5 31/86

Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Figure 8. Pin loading conditions Figure 9. Pin input voltage
STM32F10xxx pin STM32F10xxx pin
C = 50 pF VIN
ai14124b
ai14123b
5.1.6 Power supply scheme
Figure 10. Power supply scheme
VBAT
Backup circuitry
Po wer swi tch (OSC32K,RTC,
1.8-3.6V
Wake-up logic
Backup registers)
Level shifter
OUT
IO
GP I/Os Logic
IN Kernel logic
(CPU,
Digital
VDD
VDD & Memories)
1/2/3/4/5 Regulator
5 × 100 nF VSS
+ 1 × 4.7 µF 1/2/3/4/5
VDD
VDDA
VREF
VREF+
10 nF Analog:
10 nF VREF- ADC
+ 1 µF RCs, PLL,
+ 1 µF
...
VSSA
ai14125d
Caution: In Figure 10, the 4.7 µF capacitor must be connected to VDD3.
32/86 Doc ID 16455 Rev 5

5.1.7 Current consumption measurement
Figure 11. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics,
Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 5. Voltage characteristics

Symbol Ratings Min Max Unit
External main supply voltage (including

VDD VSS –0.3 4.0
VDDA and VDD)(1)
V
Input voltage on five volt tolerant pin(2) VSS  0.3 +5.5
VIN
Input voltage on any other pin(2) VSS 0.3 VDD+0.3
|VDDx| Variations between different VDD power pins 50
Variations between all the different ground mV
|VSSX VSS| 50
pins
see Section 5.3.11: Absolute
Electrostatic discharge voltage (human body
VESD(HBM) maximum ratings (electrical
model)
sensitivity)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. IINJ(PIN) must never be exceeded (see Table 6: Current characteristics). This is implicitly insured if VIN
maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is
induced by VIN<VSS.
Doc ID 16455 Rev 5 33/86

Table 6. Current characteristics

Symbol Ratings Max. Unit
IVDD Total current into VDD/VDDA power lines (source)(1) 150

(1)
IVSS Total current out of VSS ground lines (sink) 150
Output current sunk by any I/O and control pin 25
IIO
Output current source by any I/Os and control pin 25
Injected current on NRST pin ±5
mA
Injected current on High-speed external OSC_IN and Low-
±5
IINJ(PIN) (2)(3) speed external OSC_IN pins
Injected current on the PA5, PA6 and PA7 pins(4) +5 / –0
(4)
Injected current on any other pin ±5
IINJ(PIN)(2) Total injected current (sum of all I/O and control pins)(4) ± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.16: 12-bit ADC
characteristics.
4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 7. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C
5.3 Operating conditions
5.3.1 General operating conditions
Table 8. General operating conditions

Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency 0 24

fPCLK1 Internal APB1 clock frequency 0 24 MHz
fPCLK2 Internal APB2 clock frequency 0 24
VDD Standard operating voltage 2 3.6 V
Analog operating voltage
2 3.6
(ADC not used) Must be the same potential
VDDA(1) V
Analog operating voltage as VDD
2.4 3.6
(ADC used)
34/86 Doc ID 16455 Rev 5

Table 8. General operating conditions (continued)

VBAT Backup operating voltage 1.8 3.6 V

LQFP100 434
Power dissipation at TA = LQFP64 444
PD 85 °C for suffix 6 or TA = mW
105 °C for suffix 7(2) TFBGA64 308
LQFP48 363
Ambient temperature for 6 Maximum power dissipation –40 85

°C
suffix version Low power dissipation (3)
–40 105
TA
Ambient temperature for 7 Maximum power dissipation –40 105
°C
suffix version Low power dissipation (3)
–40 125
6 suffix version –40 105
TJ Junction temperature range °C
7 suffix version –40 125
1. When the ADC is used, refer to Table 41: ADC characteristics.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 80).
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 6.2: Thermal characteristics on page 80).
5.3.2 Operating conditions at power-up / power-down

Subject to general operating conditions for TA.
Table 9. Operating conditions at power-up / power-down

Symbol Parameter Min Max Unit
VDD rise time rate 0 

tVDD µs/V
VDD fall time rate 20 
5.3.3 Embedded reset and power control block characteristics

The parameters given in Table 10 are derived from tests performed under the ambient
temperature and VDD supply voltage conditions summarized in Table 8.
Doc ID 16455 Rev 5 35/86

.
Table 10. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V

PLS[2:0]=000 (falling edge) 2 2.08 2.16 V
PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V
PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V
PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V
PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V
Programmable voltage PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V

VPVD
detector level selection PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V
PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V
PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V
PLS[2:0]=111 (rising edge) 2.76 2.88 3 V
(2)
VPVDhyst PVD hysteresis 100 mV
Power on/power down Falling edge 1.8(1) 1.88 1.96 V

VPOR/PDR
reset threshold Rising edge 1.84 1.92 2.0 V
(2)
VPDRhyst PDR hysteresis 40 mV
tRSTTEMPO(2) Reset temporization 1.5 2.5 4.5 ms
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
36/86 Doc ID 16455 Rev 5

5.3.4 Embedded reference voltage

Table 11. Embedded internal reference voltage

–40 °C < TA < +105 °C 1.16 1.20 1.26 V

VREFINT Internal reference voltage
–40 °C < TA < +85 °C 1.16 1.20 1.24 V
ADC sampling time when
TS_vrefint(1) reading the internal 5.1 17.1(2) µs
reference voltage
Internal reference voltage
VRERINT(2) spread over the temperature VDD = 3 V ±10 mV 10 mV
range
TCoeff(2) Temperature coefficient 100 ppm/°C
1. Shortest sampling time can be determined in the application by multiple iterations.
5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption

The MCU is placed under the following conditions:
● All I/O pins are in input mode with a static value at VDD or VSS (no load)
● All peripherals are disabled except if it is explicitly mentioned
● Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
● When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
Doc ID 16455 Rev 5 37/86

running from Flash
Max(1)
Symbol Parameter Conditions fHCLK Unit
TA = 85 °C TA = 105 °C
24 MHz 15.4 15.7

External clock (2), all
16 MHz 11 11.5
peripherals enabled
Supply 8 MHz 6.7 6.9
IDD current in mA
Run mode 24 MHz 10.3 10.5
External clock(2), all
16 MHz 7.8 8.1
peripherals disabled
8 MHz 5.1 5.3
1. Based on characterization, not tested in production.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
running from RAM
Max(1)
TA = 85 °C TA = 105 °C
24 MHz 14.5 15
External clock (2), all
16 MHz 10 10.5
peripherals enabled
Supply current 8 MHz 6 6.3
IDD mA
in Run mode 24MHz 9.3 9.7
External clock(2) all
16 MHz 6.8 7.2
8 MHz 4.4 4.7
1. Based on characterization, tested in production at VDD max, fHCLK max.
38/86 Doc ID 16455 Rev 5

code with data processing running from RAM, peripherals enabled

#ONSUMPTIONM!
-(Z
-(Z
-(Z

n # # # #
4EMPERATURE #
AI
code with data processing running from RAM, peripherals disabled

#ONSUMPTIONM!
-(Z
-(Z
-(Z

n # # # #
4EMPERATURE # AI
Table 14. STM32F100xxB maximum current consumption in Sleep mode, code

running from Flash or RAM
Max(1)
TA = 85 °C TA = 105 °C
24 MHz 9.6 10
External clock(2) all
16 MHz 7.1 7.5
peripherals enabled
Supply current 8 MHz 4.5 4.8
IDD mA
in Sleep mode 24 MHz 3.8 4
External clock(2), all
16 MHz 3.3 3.5
8 MHz 2.7 3
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
Doc ID 16455 Rev 5 39/86

Table 15. Typical and maximum current consumptions in Stop and Standby modes
Typ(1) Max
Symbol Parameter Conditions Unit
VDD/VBAT VDD/ VBAT VDD/VBAT TA = TA =
= 2.0 V = 2.4 V = 3.3 V 85 °C 105 °C
Regulator in Run mode,

Low-speed and high-speed
internal RC oscillators and high- 23.5 24 190 350
speed oscillator OFF (no
Supply current independent watchdog)
in Stop mode Regulator in Low-Power mode,
Low-speed and high-speed
internal RC oscillators and high- 13.5 14 170 330
speed oscillator OFF (no
IDD independent watchdog)
Low-speed internal RC oscillator µA
2.6 3.4 - -
and independent watchdog ON
Low-speed internal RC oscillator
Supply current 2.4 3.2 - -
ON, independent watchdog OFF
in Standby
mode Low-speed internal RC oscillator
and independent watchdog OFF,
1.7 2 4 5
low-speed oscillator and RTC
OFF
Backup
Low-speed oscillator and RTC
IDD_VBAT domain supply 0.9 1.1 1.4 1.9 2.2
ON
current
1. Typical values are measured at TA = 25 °C.
Figure 14. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT
values
2.00
1.50
3.6 V
IDD_VBAT (µA)
3.3 V
1.00
2.4 V
2V
0.50
0.00
-45°C 25°C 85°C 105°C
Temperature (°C) ai15792
40/86 Doc ID 16455 Rev 5

Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V

#ONSUMPTION!

6

6

n # # # #
4EMPERATURE # AI
Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus

#ONSUMPTION!

6

6

n # # # #
4EMPERATURE # AI
Doc ID 16455 Rev 5 41/86

Figure 17. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and
3.6 V

#ONSUMPTION!

6
6

n # # # #
4EMPERATURE # AI
Typical current consumption

The MCU is placed under the following conditions:
● All I/O pins are in input mode with a static value at VDD or VSS (no load)
● All peripherals are disabled except if it is explicitly mentioned
● When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK =
fPCLK2/4
42/86 Doc ID 16455 Rev 5

Table 16. Typical current consumption in Run mode, code with data processing
running from Flash
Typical values(1)
All peripherals All peripherals
enabled(2) disabled
24 MHz 12.8 9.3

16 MHz 9.3 6.6
8 MHz 5.1 3.9
Running on high-speed 4 MHz 3.2 2.5
external clock with an
8 MHz crystal(3) 2 MHz 2.1 1.75
1 MHz 1.55 1.4
500 kHz 1.3 1.2
Supply 125 kHz 1.1 1.05
IDD current in mA
Run mode 24 MHz 12.2 8.6
16 MHz 8.5 6
8 MHz 4.6 3.3

internal RC (HSI) 2 MHz 1.5 1.15
1 MHz 0.9 0.8
500 kHz 0.65 0.6
125 kHz 0.45 0.43
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In
applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency
when fHCLK < 8 MHz, the PLL is used when fHCLK > 8 MHz.
Doc ID 16455 Rev 5 43/86

Table 17. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typical values(1)
All peripherals All peripherals
enabled(2) disabled
24 MHz 7.3 2.6

16 MHz 5.2 2
8 MHz 2.8 1.3
Running on high-speed 4 MHz 2 1.1
external clock with an
8 MHz crystal(3) 2 MHz 1.5 1.1
1 MHz 1.25 1
500 kHz 1.1 1
Supply
current in 125 kHz 1.05 0.95
IDD mA
Sleep 24 MHz 6.65 1.9
mode
16 MHz 4.5 1.4
8 MHz 2.2 0.7

internal RC (HSI) 2 MHz 0.85 0.45
1 MHz 0.6 0.41
500 kHz 0.5 0.39
125 kHz 0.4 0.37
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In
applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency
when fHCLK > 8 MHz, the PLL is used when fHCLK > 8 MHz.
On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 18. The MCU is placed
under the following conditions:
● all I/O pins are in input mode with a static value at VDD or VSS (no load)
● all peripherals are disabled unless otherwise mentioned
● the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
● ambient operating temperature and VDD supply voltage conditions summarized in
Table 5.
44/86 Doc ID 16455 Rev 5

Table 18. Peripheral current consumption

Peripheral Typical consumption at 25 °C(1) Unit
TIM2 0.52
TIM3 0.46
TIM4 0.5
TIM6 0.125
TIM7 0.19
DAC 0.5(2)
APB1 WWDG 0.13
SPI2 0.2
USART2 0.38
USART3 0.32
I2C1 0.27
I2C2 0.28
HDMI CEC 0.16 mA
GPIO A 0.25
GPIO B 0.12
GPIO C 0.18
GPIO D 0.15
GPIO E 0.15
(3)
ADC1 1.15
APB2
SPI1 0.12
USART1 0.27
TIM1 0.63
TIM15 0.33
TIM16 0.26
TIM17 0.25
1. fHCLK = fAPB1 = fAPB2 = 24 MHz, default prescaler value for each peripheral.
2. Specific conditions for DAC: EN1 bit in DAC_CR register set to 1.
3. Specific conditions for ADC: fHCLK = 24 MHz, fAPB1 = fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADON bit in the
ADC_CR2 register is set to 1.
5.3.6 External clock source characteristics

High-speed external user clock generated from an external source
The characteristics given in Table 19 result from tests performed using an high-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 8.
Doc ID 16455 Rev 5 45/86

Table 19. High-speed external user clock characteristics

User external clock source

fHSE_ext 1 8 24 MHz
frequency(1)
OSC_IN input pin high level
VHSEH 0.7VDD VDD
voltage(1)
V
OSC_IN input pin low level
VHSEL VSS 0.3VDD
voltage(1)
tw(HSE)
OSC_IN high or low time(1) 16
tw(HSE)
ns
tr(HSE)
OSC_IN rise or fall time(1) 20
tf(HSE)
Cin(HSE) OSC_IN input capacitance(1) 5 pF
DuCy(HSE) Duty cycle(1) 45 55 %
IL OSC_IN Input leakage current VSS  VIN  VDD ±1 µA
Low-speed external user clock generated from an external source

The characteristics given in Table 20 result from tests performed using an low-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 8.
Table 20. Low-speed external user clock characteristics

User external clock source

fLSE_ext 32.768 1000 kHz
frequency(1)
OSC32_IN input pin high level
VLSEH 0.7VDD VDD
voltage(1)
V
OSC32_IN input pin low level
VLSEL VSS 0.3VDD
voltage(1)
tw(LSE)
OSC32_IN high or low time(1) 450
tw(LSE)
ns
tr(LSE)
OSC32_IN rise or fall time(1) 50
tf(LSE)
Cin(LSE) OSC32_IN input capacitance(1) 5 pF
DuCy(LSE) Duty cycle(1) 30 70 %
IL OSC32_IN Input leakage current VSS  VIN  VDD ±1 µA
46/86 Doc ID 16455 Rev 5

Figure 18. High-speed external clock source AC timing diagram
VHSEH
90%
10%
VHSEL
tr(HSE) tW(HSE) t
tf(HSE) tW(HSE)
THSE
External fHSE_ext
IL
clock source OSC _IN
STM32F10xxx
ai14127b
Figure 19. Low-speed external clock source AC timing diagram
VLSEH
90%
10%
VLSEL
tr(LSE) tW(LSE) t
tf(LSE) tW(LSE)
TLSE
External fLSE_ext
OSC32_IN IL
clock source
STM32F10xxx
ai14140c
High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 21. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Doc ID 16455 Rev 5 47/86

Table 21. HSE 4-24 MHz oscillator characteristics(1)(2)

fOSC_IN Oscillator frequency 4 8 24 MHz

RF Feedback resistor 200 k
Recommended load capacitance
CL1
versus equivalent serial RS = 30 30 pF
CL2(3)
resistance of the crystal (RS)(4)
VDD = 3.3 V
i2 HSE driving current VIN = VSS with 30 pF 1 mA
load
gm Oscillator transconductance Startup 25 mA/V
tSU(HSE)
(5) Startup time VDD is stabilized 2 ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. It is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.),
designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be
included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Figure 20. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MH z controlled
RF
resonator gain
OSC_OU T STM32F10xxx
CL2 REXT(1)
ai14128b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 22. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
48/86 Doc ID 16455 Rev 5

Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL  7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

RF Feedback resistor 5 M
CL1 Recommended load capacitance

versus equivalent serial RS = 30 K 15 pF
CL2(2)
resistance of the crystal (RS)(3)
VDD = 3.3 V
I2 LSE driving current 1.4 µA
VIN = VSS
gm Oscillator transconductance 5 µA/V
(4)
tSU(LSE) Startup time VDD is stabilized 3 s
2. Refer to the note and caution paragraphs above the table.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
Figure 21. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
OSC32_IN fLSE
Bias
32.768 KH z controlled
RF
resonator gain
OSC32_OU T STM32F10xxx
CL2
ai14129b
Doc ID 16455 Rev 5 49/86

5.3.7 Internal clock source characteristics

High-speed internal (HSI) RC oscillator
Table 23. HSI oscillator characteristics(1)

fHSI Frequency 8 MHz

TA = –40 to 105 °C –2.7 3 %
TA = –10 to 85 °C –2 2.5 %
ACCHSI Accuracy of HSI oscillator(2)
TA = 0 to 70 °C –2 2.5 %
TA = 25 °C –0.7 1 %
tsu(HSI) HSI oscillator startup time 1 2 µs
IDD(HSI) HSI oscillator power consumption 80 100 µA
1. VDD = 3.3 V, TA = –40 to 105 °C °C unless otherwise specified.
Low-speed internal (LSI) RC oscillator
Table 24. LSI oscillator characteristics (1)

Symbol Parameter Min Typ Max Unit
fLSI Frequency 30 40 60 kHz

fLSI(T) Temperature-related frequency drift(2) -9 9 %
tsu(LSI) (3) LSI oscillator startup time 85 µs
IDD(LSI)(3) LSI oscillator power consumption 0.65 1.2 µA
1. VDD = 3 V, TA = –40 to 105 °C °C unless otherwise specified.
Wakeup time from low-power mode

The wakeup times given in Table 25 are measured on a wakeup phase with an 8-MHz HSI
RC oscillator. The clock source used to wake up the device depends from the current
operating mode:
● Stop or Standby mode: the clock source is the RC oscillator
● Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under the ambient temperature and VDD supply
voltage conditions summarized in Table 8.
50/86 Doc ID 16455 Rev 5

Table 25. Low-power mode wakeup timings

Symbol Parameter Typ Unit
tWUSLEEP(1) Wakeup from Sleep mode 1.8 µs
Wakeup from Stop mode (regulator in run mode) 3.6

tWUSTOP(1) µs
Wakeup from Stop mode (regulator in low-power mode) 5.4
tWUSTDBY(1) Wakeup from Standby mode 50 µs
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
5.3.8 PLL characteristics

Table 26. PLL characteristics

Value
Symbol Parameter Unit
Min(1) Typ Max(1)
PLL input clock(2) 1 8.0 24 MHz

fPLL_IN
PLL input clock duty cycle 40 60 %
fPLL_OUT PLL multiplier output clock 16 24 MHz
tLOCK PLL lock time 200 µs
Jitter Cycle-to-cycle jitter 300 ps
1. Based on device characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
Doc ID 16455 Rev 5 51/86

5.3.9 Memory characteristics

Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 27. Flash memory characteristics

Symbol Parameter Conditions Min(1) Typ Max(1) Unit
tprog 16-bit programming time TA–40 to +105 °C 40 52.5 70 µs

tERASE Page (1 KB) erase time TA –40 to +105 °C 20 40 ms
tME Mass erase time TA –40 to +105 °C 20 40 ms
Read mode
20 mA
fHCLK = 24 MHz, VDD = 3.3 V
Write / Erase modes
IDD Supply current 5 mA
fHCLK = 24 MHz, VDD = 3.3 V
Power-down mode / Halt,
50 µA
VDD = 3.0 to 3.6 V
Vprog Programming voltage 2 3.6 V
Table 28. Flash memory endurance and data retention

Value
Min(1) Typ Max
TA = –40 to +85 °C (6 suffix versions)
NEND Endurance 10 kcycles
TA = –40 to +105 °C (7 suffix versions)
1 kcycle(2) at TA = 85 °C 30
tRET Data retention 1 kcycle(2) at TA = 105 °C 10 Years
10 kcycles(2) at TA = 55 °C 20
1. Based on characterization not tested in production.
2. Cycling performed over the whole temperature range.
52/86 Doc ID 16455 Rev 5

5.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (Electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 29. They are based on the EMS levels and classes
defined in application note AN1709.
Table 29. EMS characteristics

Symbol Parameter Conditions Level/Class
VDD 3.3 V, TA +25 °C,

Voltage limits to be applied on any I/O pin to fHCLK 24 MHz, LQFP100
VFESD 2B
induce a functional disturbance package, conforms to
IEC 61000-4-2
VDD3.3 V, TA +25 °C,
Fast transient voltage burst limits to be
fHCLK 24 MHz, LQFP100
VEFTB applied through 100 pF on VDD and VSS pins 4A
package, conforms to
to induce a functional disturbance
IEC 61000-4-4
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
● Corrupted program counter
● Unexpected reset
● Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
Doc ID 16455 Rev 5 53/86

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 30. EMI characteristics

Max vs. [fHSE/fHCLK]
Monitored
frequency band
8/24 MHz
0.1 MHz to 30 MHz 9

VDD 3.6 V, TA 25°C,
LQFP100 package 30 MHz to 130 MHz 16 dBµV
SEMI Peak level
compliant with SAE 130 MHz to 1GHz 19
J1752/3
SAE EMI Level 4 -
5.3.11 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 31. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)
Electrostatic discharge TA +25 °C

VESD(HBM) 2 2000
voltage (human body model) conforming to JESD22-A114
V
Electrostatic discharge TA +25 °C
VESD(CDM) II 500
voltage (charge device model) conforming to JESD22-C101
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
● A supply overvoltage is applied to each power supply pin
● A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD78 IC latch-up standard.
Table 32. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latch-up class TA +105 °C conforming to JESD78 II level A
54/86 Doc ID 16455 Rev 5

5.3.12 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 33 are derived from tests
performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL
compliant.
Table 33. I/O static characteristics

0.28 (VDD–2)
Standard I/O input low level voltage –0.5
+0.8
VIL
0.32 (VDD–2)
I/O FT(1) input low level voltage –0.5
+0.75
V
0.41 (VDD–2)
Standard I/O input high level voltage VDD+0.5
+1.3
VIH
0.42 (VDD–2)
I/O FT(1) input high level voltage 5.5
+1
Standard I/O Schmitt trigger voltage
200 mV
hysteresis(2)
Vhys
I/O FT Schmitt trigger voltage
5% VDD(3) mV
hysteresis(2)
VSS  VIN  VDD
1
Standard I/Os
Ilkg Input leakage current(4) µA
VIN = 5 V
3
I/O FT
RPU Weak pull-up equivalent resistor(5) VIN VSS 30 40 50 k
Weak pull-down equivalent
RPD VIN VDD 30 40 50 k
resistor(5)
CIO I/O pin capacitance 5 pF
1. FT = 5V tolerant. To sustain a voltage higher than VDD+0.5 the internal pull-up/pull-down resistors must be disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by design, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 22 and Figure 23 for standard I/Os, and
in Figure 24 and Figure 25 for 5 V tolerant I/Os.
Doc ID 16455 Rev 5 55/86

Figure 22. Standard I/O input characteristics - CMOS port
6)(6),6

6 $$
6
MENT6 )( 6 )( $$
QUIRE
TANDARDRE
#-/3S
)NPUTRANGE
7)(MIN
NOTGUARANTEED

7),MAX
6 $$ 6
RDREQU IREMENT6 ), 6), $$
#-/3STANDA
6$$6

AIB
Figure 23. Standard I/O input characteristics - TTL port
6)(6),6
44,REQUIREMENTS 6)( 6

7)(MIN

)NPUTRANGE
6
6 )( $$ NOTGUARANTEED

7),MAX 6 ),6 $$

44,REQUIREMENTS 6),6
6$$6

AI
56/86 Doc ID 16455 Rev 5

Figure 24. 5 V tolerant I/O input characteristics - CMOS port
6)(6),6
6 $$
TS6 )(
REQUIREMEN 6 )(6 $$

TANDARD
#-/3S
)NPUTRANGE

NOTGUARANTEED

T6 ),6 $$ 6 ),6 $$
REQUIRMEN
#- /3STANDARD
6$$6

6$$
AIB
Figure 25. 5 V tolerant I/O input characteristics - TTL port
6)(6),6
44,REQUIREMENT6 )(6

6
6 )(
$$ )NPUTRANGE
NOTGUARANTEED
7)(MIN

6 ),
6 $$
7),MAX
44,REQUIREMENTS6 ),6
6$$6

AI
Output driving current

The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 6).
● The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 6).
Doc ID 16455 Rev 5 57/86

Output voltage levels

performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 8. All I/Os are CMOS and TTL compliant.
Table 34. Output voltage characteristics

Output Low level voltage for an I/O pin

VOL(1) TTL port, 0.4
when 8 pins are sunk at the same time
IIO = +8 mA, V
(2) Output High level voltage for an I/O pin 2.7 V < VDD < 3.6 V
VOH VDD–0.4
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
VOL(1) CMOS port 0.4
when 8 pins are sunk at the same time
IIO = +8 mA V
(2) Output high level voltage for an I/O pin
VOH 2.7 V < VDD < 3.6 V 2.4
VOL(1) 1.3
when 8 pins are sunk at the same time IIO = +20 mA(3)
V
(2) Output high level voltage for an I/O pin 2.7 V < VDD < 3.6 V
VOH VDD–1.3
VOL(1) 0.4
when 8 pins are sunk at the same time IIO = +6 mA(3)
V
(2) Output high level voltage for an I/O pin 2 V < VDD < 2.7 V
VOH VDD–0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
3. Based on characterization data, not tested in production.
58/86 Doc ID 16455 Rev 5

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 26 and
Table 35, respectively.
in Table 8.
Table 35. I/O AC characteristics(1)

MODEx
[1:0] bit Symbol Parameter Conditions Max Unit
value(1)
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 2(3) MHz

Output high to low level fall
tf(IO)out 125(3)
10 time
CL = 50 pF, VDD = 2 V to 3.6 V ns
Output low to high level rise (3)
tr(IO)out 125
time
fmax(IO)out Maximum frequency(2) CL= 50 pF, VDD = 2 V to 3.6 V 10(3) MHz
tf(IO)out 25(3)
01 time
CL= 50 pF, VDD = 2 V to 3.6 V ns
Output low to high level rise
tr(IO)out 25(3)
time
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 24 MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
time
11 CL = 50 pF, VDD = 2 V to 2.7 V 12(3)
ns
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
Output low to high level rise
tr(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
time
CL = 50 pF, VDD = 2 V to 2.7 V 12(3)
Pulse width of external
- tEXTIpw signals detected by the 10(3) ns
EXTI controller
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 26.
Doc ID 16455 Rev 5 59/86

Figure 26. I/O AC characteristics definition
90% 10%
50% 50%
10% 90%
EXT ERNAL tr(I O)out tr(I O)out

OUTPUT
ON 50pF T
Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131
5.3.13 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 33).
in Table 8.
Table 36. NRST pin characteristics

VIL(NRST)(1) NRST Input low level voltage –0.5 0.8

V
(1)
VIH(NRST) NRST Input high level voltage 2 VDD+0.5
NRST Schmitt trigger voltage
Vhys(NRST) 200 mV
hysteresis
RPU Weak pull-up equivalent resistor(2) VIN VSS 30 40 50 k
VF(NRST)(1) NRST Input filtered pulse 100 ns
VNF(NRST)(1) NRST Input not filtered pulse 300 ns
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).
Figure 27. Recommended NRST pin protection
6$$
%XTERNAL
RESETCIRCUIT
205 )NTERNALRESET
.234
&ILTER
&
34-&X
AID
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 36. Otherwise the reset will not be taken into account by the device.
60/86 Doc ID 16455 Rev 5

5.3.14 TIMx characteristics

The parameters given in Table 37 are guaranteed by design.
Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 37. TIMx characteristics

Symbol Parameter Conditions(1) Min Max Unit
1 tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 24 MHz 41.7 ns
Timer external clock 0 fTIMxCLK/2 MHz

fEXT
frequency on CHx(2) fTIMxCLK = 24 MHz 0 12 MHz
ResTIM Timer resolution 16 bit
16-bit counter clock period 1 65536 tTIMxCLK
tCOUNTER when the internal clock is
selected fTIMxCLK = 24 MHz 2730 µs
65536 × 65536 tTIMxCLK

tMAX_COUNT Maximum possible count
fTIMxCLK = 24 MHz 178 s
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM15, TIM16 and TIM17 timers.
2. CHx is used as a general term to refer to CH1 to CH4 for TIM1, TIM2, TIM3 and TIM4, to the CH1 to CH2
for TIM15, and to CH1 for TIM16 and TIM17.
5.3.15 Communications interfaces

I2C interface characteristics
performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage
conditions summarized in Table 8.
The STM32F100xx value line I2C interface meets the requirements of the standard I2C
communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 38. Refer also to Section 5.3.12: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Doc ID 16455 Rev 5 61/86

Table 38. I2C characteristics

Standard mode I2C(1) Fast mode I2C(1)(2)
Symbol Parameter Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.7 1.3

µs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100
(3)
th(SDA) SDA data hold time 0 0(4) 900(3)
tr(SDA) ns
SDA and SCL rise time 1000 300
tr(SCL)
tf(SDA)
SDA and SCL fall time 300 300
tf(SCL)
th(STA) Start condition hold time 4.0 0.6
Repeated Start condition setup µs
tsu(STA) 4.7 0.6
time
tsu(STO) Stop condition setup time 4.0 0.6 µs
Stop to Start condition time (bus
tw(STO:STA) 4.7 1.3 µs
free)
Cb Capacitive load for each bus line 400 400 pF
2. fPCLK1 must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than
4 MHz to achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz
maximum I2C fast mode clock.
3. The maximum hold time of the Start condition only has to be met if the interface does not stretch the low
period of SCL signal.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
62/86 Doc ID 16455 Rev 5

Figure 28. I2C bus AC waveforms and measurement circuit(1)

6$$ 6$$
KΩ KΩ 34-&X
Ω
3$!
)£#BUS Ω
3#,
3TARTREPEATED
3TART
3TART
TSU34!
3$!
TF3$! TR3$! TSU3$!
3TOP TSU34/34!
TH34! TW3#,, TH3$!
3#,
TW3#,( TR3#, TF3#, TSU34/
AID
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 39. SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V)(1)(2)

I2C_CCR value
fSCL (kHz)(3)
RP = 4.7 k
400 0x8011
300 0x8016
200 0x8021
100 0x0064
50 0x00C8
20 0x01F4
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 400 kHz, the tolerance on the achieved speed is of 2%. For other speed ranges, the
tolerance on the achieved speed 1%. These variations depend on the accuracy of the external
components used to design the application.
Doc ID 16455 Rev 5 63/86

SPI interface characteristics

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 40. SPI characteristics(1)

fSCK Master mode 12

SPI clock frequency MHz
1/tc(SCK) Slave mode 12
tr(SCK) SPI clock rise and fall
Capacitive load: C = 30 pF 8 ns
tf(SCK) time
SPI slave input clock
DuCy(SCK) Slave mode 30 70 %
duty cycle
tsu(NSS)(2) NSS setup time Slave mode 4tPCLK
th(NSS)(2) NSS hold time Slave mode 2tPCLK
tw(SCKH)(2) Master mode, fPCLK = 24 MHz,
SCK high and low time 50 60
tw(SCKL)(2) presc = 4
tsu(MI) (2) Master mode 5

Data input setup time
tsu(SI)(2) Slave mode 5
th(MI) (2) Master mode 5
Data input hold time
th(SI)(2) Slave mode 4
ns
ta(SO) (2)(3) Data output access time Slave mode, fPCLK = 24 MHz 0 3tPCLK
tdis(SO)(2)(4) Data output disable time Slave mode 2 10
(2)(1)
tv(SO) Data output valid time Slave mode (after enable edge) 25
Master mode (after enable
tv(MO)(2)(1) Data output valid time 5
edge)
th(SO)(2) Slave mode (after enable edge) 15
Data output hold time Master mode (after enable
th(MO)(2) 2
edge)
1. Remapped SPI1 characteristics to be determined.
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
64/86 Doc ID 16455 Rev 5

Figure 29. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
tSU(NSS) th(NSS)
CPHA= 0
SCK Input
CPOL=0
tw(SCKH)
CPHA= 0 tw(SCKL)
CPOL=1
ta(SO) tv(SO) th(SO) tr(SCK) tdis(SO)

tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT
th(SI)
ai14134c
Figure 30. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tSU(NSS) tc(SCK) th(NSS)
CPHA=1
SCK Input
CPOL=0
tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1
tv(SO) th(SO) tr(SCK) tdis(SO)

ta(SO) tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI) th(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT
ai14135
Doc ID 16455 Rev 5 65/86

Figure 31. SPI timing diagram - master mode(1)
High
NSS input
tc(SCK)
CPHA= 0
SCK Input
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
SCK Input
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MS BIN BI T6 IN LSB IN
th(MI)
MOSI
M SB OUT B I T1 OUT LSB OUT
OUTUT
tv(MO) th(MO)
ai14136
HDMI consumer electronics control (CEC)

Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics.
5.3.16 12-bit ADC characteristics

performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
Note: It is recommended to perform a calibration after each power-up.
66/86 Doc ID 16455 Rev 5

Table 41. ADC characteristics

VDDA Power supply 2.4 3.6 V

VREF+ Positive reference voltage 2.4 VDDA V
Current on the VREF input
IVREF 160(1) 220(1) µA
pin
fADC ADC clock frequency 0.6 12 MHz
fS(2) Sampling rate 0.05 1 MHz
fADC = 12 MHz 823 kHz

fTRIG(2) External trigger frequency
17 1/fADC
0 (VSSA tied to
VAIN(3) Conversion voltage range VREF+ V
ground)
See Equation 1 and
RAIN(2) External input impedance 50 k
Table 42 for details
RADC(2) Sampling switch resistance 1 k
Internal sample and hold

CADC(2) 8 pF
capacitor
fADC = 12 MHz 5.9 µs
tCAL(2) Calibration time
83 1/fADC
Injection trigger conversion fADC = 12 MHz 0.214 µs

tlat(2)
latency 3(4)
1/fADC
Regular trigger conversion fADC = 12 MHz 0.143 µs

tlatr(2)
latency 2(4) 1/fADC
0.125 17.1 µs
tS(2) Sampling time fADC = 12 MHz
1.5 239.5 1/fADC
tSTAB(2) Power-up time 0 0 1 µs
fADC = 12 MHz 1.17 21 µs
Total conversion time
tCONV(2) 14 to 252 (tS for sampling +12.5 for
(including sampling time) 1/fADC
successive approximation)
1. Based on characterization results, not tested in production.
3. In devices delivered in LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally connected to VSSA),
see Table 4: STM32F100xx pin definitions and Figure 6.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 41.
Equation 1: RAIN max formula:

TS
R AIN  -------------------------------------------------------------
- – R ADC
N+2
f ADC  C ADC  ln  2 
Doc ID 16455 Rev 5 67/86

The above formula (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 42. RAIN max for fADC = 12 MHz(1)

Ts (cycles) tS (µs) RAIN max (k)
1.5 0.125 0.4

7.5 0.625 5.9
13.5 1.125 11.4
28.5 2.375 25.2
41.5 3.45 37.2
55.5 4.625 50
71.5 5.96 NA
239.5 20 NA
Table 43. ADC accuracy - limited test conditions(1)(2)

Symbol Parameter Test conditions Typ Max Unit
ET Total unadjusted error fPCLK2 = 24 MHz, ±1.3 ±2.2

fADC = 12 MHz, RAIN < 10 k,
EO Offset error ±1 ±1.5
VDDA = 3 V to 3.6 V
EG Gain error VREF+ = VDDA ±0.5 ±1.5 LSB
ED Differential linearity error TA = 25 °C ±0.7 ±1
Measurements made after
EL Integral linearity error ADC calibration ±0.8 ±1.5
1. ADC DC accuracy values are measured after internal calibration.

Table 44. ADC accuracy(1) (2) (3)

Symbol Parameter Test conditions Typ Max Unit
ET Total unadjusted error fPCLK2 = 24 MHz, ±2 ±5

EO Offset error fADC = 12 MHz, RAIN < 10 k, ±1.5 ±2.5
VDDA = 2.4 V to 3.6 V
EG Gain error ±1.5 ±3 LSB
TA = Full operating range
ED Differential linearity error Measurements made after ±1 ±2
EL Integral linearity error ADC calibration ±1.5 ±3
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency, VREF and temperature ranges.
Note: ADC accuracy vs. negative injection current: Injecting a negative current on any of the
standard (non-robust) analog input pins should be avoided as this significantly reduces the
accuracy of the conversion being performed on another analog input. It is recommended to
68/86 Doc ID 16455 Rev 5

add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in
Section 5.3.12 does not affect the ADC accuracy.
Figure 32. ADC accuracy characteristics

V V
[1LSBIDEAL = REF+ (or DDA depending on package)]
4096 4096
EG
(1) Example of an actual transfer curve
4095
(2) The ideal transfer curve
4094 (3) End point correlation line
4093
(2)
ET=Total Unadjusted Error: maximum deviation
ET between the actual and the ideal transfer curves.
7 (3) EO=Offset Error: deviation between the first actual
(1) transition and the first ideal one.
6
EG=Gain Error: deviation between the last ideal
5 transition and the last actual one.
EO EL ED=Differential Linearity Error: maximum deviation
4 between actual steps and the ideal one.
3 EL=Integral Linearity Error: maximum deviation
ED between any actual transition and the end point
2 correlation line.
1 LSBIDEAL
1
0 1 2 3 4 5 6 7 4093 4094 4095 4096

VSSA VDDA ai14395b
Figure 33. Typical connection diagram using the ADC
VDD STM32F10xxx
Sample and hold ADC

VT converter
0.6 V
RAIN(1) AINx RADC(1)
12-bit
converter
VT
VAIN 0.6 V
Cparasitic CADC(1)
IL±1 µA
ai14139d
1. Refer to Table 41 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 34 or Figure 35,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Doc ID 16455 Rev 5 69/86

Figure 34. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F10xxx
V REF+
1 µF // 10 nF V DDA
1 µF // 10 nF
V SSA/V REF-
ai14380b
1. VREF+ is available on 100-pin packages and on TFBGA64 packages. VREF- is available on 100-pin
packages only.
Figure 35. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F10xxx
VREF+/VDDA
1 µF // 10 nF
VREF–/VSSA
ai14381b
1. VREF+ and VREF- inputs are available only on 100-pin packages.
70/86 Doc ID 16455 Rev 5

5.3.17 DAC electrical specifications
Table 45. DAC characteristics

Symbol Parameter Min Typ Max(1) Unit Comments
VDDA Analog supply voltage 2.4 3.6 V
VREF+ must always be below

VREF+ Reference supply voltage 2.4 3.6 V
VDDA
VSSA Ground 0 0 V
(2)
RLOAD Resistive load with buffer ON 5 k
When the buffer is OFF, the
Minimum resistive load between
RO(1) Impedance output with buffer OFF 15 k
DAC_OUT and VSS to have a
1% accuracy is 1.5 M
Maximum capacitive load at
CLOAD(1) Capacitive load 50 pF DAC_OUT pin (when the buffer
is ON).
It gives the maximum output
DAC_OUT Lower DAC_OUT voltage with buffer excursion of the DAC.
0.2 V
min(1) ON
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
DAC_OUT Higher DAC_OUT voltage with buffer VDDA – VREF+ = 3.6 V and (0x155) and
V
max(1) ON 0.2 (0xEAB) at VREF+ = 2.4 V
DAC_OUT Lower DAC_OUT voltage with buffer
0.5 mV
min(1) OFF It gives the maximum output
DAC_OUT Higher DAC_OUT voltage with buffer VREF+ excursion of the DAC.
V
max(1) OFF – 1LSB
With no load, worst code
DAC DC current consumption in (0xF1C) at VREF+ = 3.6 V in
IDDVREF+ 220 µA
quiescent mode (Standby mode) terms of DC consumption on the
inputs
With no load, middle code
380 µA
(0x800) on the inputs
DAC DC current consumption in With no load, worst code
IDDA
quiescent mode (Standby mode) (0xF1C) at VREF+ = 3.6 V in
480 µA
terms of DC consumption on the
inputs
Given for the DAC in 10-bit

±0.5 LSB
Differential non linearity Difference configuration
DNL(3)
between two consecutive code-1LSB)
±2 LSB
configuration
Integral non linearity (difference Given for the DAC in 10-bit
±1 LSB
between measured value at Code i configuration
INL(3) and the value at Code i on a line
drawn between Code 0 and last Code Given for the DAC in 12-bit
±4 LSB
1023) configuration
Doc ID 16455 Rev 5 71/86

Table 45. DAC characteristics (continued)

Symbol Parameter Min Typ Max(1) Unit Comments

±10 mV
configuration
Offset error
(difference between measured value Given for the DAC in 10-bit at
Offset(3) ±3 LSB
at Code (0x800) and the ideal value = VREF+ = 3.6 V
VREF+/2)
Given for the DAC in 12-bit at
±12 LSB
VREF+ = 3.6 V
Gain Given for the DAC in 12bit
Gain error ±0.5 %
error(3) configuration
Settling time (full scale: for a 10-bit
input code transition between the
tSETTLING(
3) lowest and the highest input codes 3 4 µs CLOAD  50 pF, RLOAD  5 k
when DAC_OUT reaches final value
±1LSB
Max frequency for a correct
Update DAC_OUT change when small
1 MS/s CLOAD  50 pF, RLOAD  5 k
rate(3) variation in the input code (from code i
to i+1LSB)
Wakeup time from off state (Setting CLOAD  50 pF, RLOAD  5 k
tWAKEUP(3) the ENx bit in the DAC Control 6.5 10 µs input code between lowest and
register) highest possible ones.
Power supply rejection ratio (to VDDA)
PSRR+ (1) –67 –40 dB No RLOAD, CLOAD = 50 pF
(static DC measurement
1. Guaranteed by characterization, not tested in production.
Figure 36. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC
Buffer(1)
R LOAD
12-bit DACx_OUT
digital to
analog
converter
C LOAD
ai17157
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
72/86 Doc ID 16455 Rev 5

5.3.18 Temperature sensor characteristics
Table 46. TS characteristics

Symbol Parameter Min Typ Max Unit
TL(1) VSENSE linearity with temperature 1 2 °C

(1)
Avg_Slope Average slope 4.0 4.3 4.6 mV/°C
V25(1) Voltage at 25°C 1.32 1.41 1.50 V
tSTART(2) Startup time 4 10 µs
TS_temp(3)(2) ADC sampling time when reading the temperature 17.1 µs
3. Shortest sampling time can be determined in the application by multiple iterations.
Doc ID 16455 Rev 5 73/86

Package characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
6 Package characteristics
6.1 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
74/86 Doc ID 16455 Rev 5

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Package characteristics
Figure 37. LQFP100, 14 x 14 mm, 100-pin low-profile Figure 38. Recommended footprint(1)(2)
quad flat package outline(1)
0.25 mm
0.10 inch
GAGE PLANE
k 75 51
D
L 76 50
D1
0.5
D3 L1
75 51 C
0.3
76 50
16.7 14.3
E3 E1 E
100 26
1.2
1 25
100 26
Pin 1 1 25
12.3
ccc C
identification
16.7
e
A1
ai14906
A2
A
SEATING PLANE C
1L_ME
1. Drawing is not to scale.

2. Dimensions are in millimeters.
Table 47. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 0.2 0.0035 0.0079
D 15.80 16.00 16.2 0.622 0.6299 0.6378
D1 13.80 14.00 14.2 0.5433 0.5512 0.5591
D3 12.00 0.4724
E 15.80 16.00 16.2 0.622 0.6299 0.6378
E1 13.80 14.00 14.2 0.5433 0.5512 0.5591
E3 12.00 0.4724
e 0.50 0.0197
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 0.0394
k 0° 3.5° 7° 0.0° 3.5° 7.0°
ccc 0.08 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 16455 Rev 5 75/86

Figure 39. LQFP64 – 10 x 10 mm, 64 pin low-profile quad Figure 40. Recommended
flat package outline(1) footprint(1)(2)
D 48 33
D1 ccc C
0.3
D3 A
A2 49 0.5 32
48 33
49 32
12.7
10.3
b
L1
10.3
E3 E1 E
64 17
1.2
L
A1 K
1 16
64 7.8
17
Pin 1
identification 1 16
12.7
c
5W_ME
ai14909

Table 48. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data
Symbol
A 1.60 0.0630
A1 0.05 0.15 0.0020 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 0.20 0.0035 0.0079
D 12.00 0.4724
D1 10.00 0.3937
E 12.00 0.4724
E1 10.00 0.3937
e 0.50 0.0197
 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 0.0394
Number of pins
N 64
76/86 Doc ID 16455 Rev 5

Figure 41. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline
B D
A D1
A
A1 e F
H
F
G
F
E
E1 E
D
C
B
A
e
1 2 3 4 5 6 7 8
A3 A1 ball pad corner Øb (64 balls)
A4
A2
Seating
plane C Bottom view
ME_R8
Table 49. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package
mechanical data
Symbol
A 1.200 0.0472
A1 0.150 0.0059
A2 0.785 0.0309
A3 0.200 0.0079
A4 0.600 0.0236
b 0.250 0.300 0.350 0.0098 0.0118 0.0138
D 4.850 5.000 5.150 0.1909 0.1969 0.2028
D1 3.500 0.1378
E 4.850 5.000 5.150 0.1909 0.1969 0.2028
E1 3.500 0.1378
e 0.500 0.0197
F 0.750 0.0295
ddd 0.080 0.0031
eee 0.150 0.0059
fff 0.050 0.0020
Doc ID 16455 Rev 5 77/86

Figure 42. Recommended PCB design rules for pads (0.5 mm pitch BGA)
Pitch 0.5 mm
D pad 0.27 mm
Dsm 0.35 mm typ (depends on

the soldermask registration
tolerance)
Solder paste 0.27 mm aperture diameter

Dpad
Dsm
ai15495
1. Non solder mask defined (NSMD) pads are recommended

2. 4 to 6 mils solder paste screen printing process
78/86 Doc ID 16455 Rev 5

Figure 43. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat Figure 44. Recommended
package outline(1) footprint(1)(2)
Seating plane
C
A A2
A1 c 0.50
b
1.20
0.25 mm
ccc C Gage plane
0.30
36 25
D 37 24
D1
k
0.20
D3 7.30
A1 L 9.70 5.80
36 25
L1
7.30
24 48 13
37 1 12
1.20
5.80
E3 E1 E
9.70
ai14911b
48
13
Pin 1 1 12
identification
5B_ME

Table 50. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
Symbol
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 0.200 0.0035 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 5.500 0.2165
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 5.500 0.2165
e 0.500 0.0197
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0° 3.5° 7° 0° 3.5° 7°
ccc 0.080 0.0031
Doc ID 16455 Rev 5 79/86

6.2 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 8: General operating conditions on page 34.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x JA)
Where:
● TA max is the maximum ambient temperature in C,
● JA is the package junction-to-ambient thermal resistance, in C/W,
● PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
● PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 51. Package thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient

46
LQFP 100 - 14 × 14 mm / 0.5 mm pitch
45
LQFP 64 - 10 × 10 mm / 0.5 mm pitch
JA °C/W
65
TFBGA64 - 5 × 5 mm / 0.5 mm pitch
55
LQFP 48 - 7 × 7 mm / 0.5 mm pitch
6.2.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
80/86 Doc ID 16455 Rev 5

6.2.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 52: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F10xxx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example: high-performance application

Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
mode at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Table 51 TJmax is calculated as follows:
– For LQFP64, 45 °C/W
TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 52: Ordering information scheme).
Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Doc ID 16455 Rev 5 81/86

Using the values obtained in Table 51 TJmax is calculated as follows:

– For LQFP100, 46 °C/W
TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C
This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Table 52: Ordering information scheme).
Figure 45. LQFP100 PD max vs. TA
700
600
500
PD (mW)
400 Suffix 6
Suffix 7
300
200
100
0
65 75 85 95 105 115 125 135
TA (°C)
82/86 Doc ID 16455 Rev 5

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Ordering information scheme
7 Ordering information scheme
Table 52. Ordering information scheme
Example: STM32 F 100 C 6 T 6 B xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Device subfamily
100 = value line
Pin count
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size

4 = 16 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
Package
T = LQFP
H = BGA
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Internal code
B
Options
xxx = programmed parts
TR = tape and real
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 16455 Rev 5 83/86

Revision history STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
8 Revision history
Table 53. Document revision history

Date Revision Changes
12-Oct-2009 1 Initial release.

TFBGA64 package added (see Table 49 and Table 41).
Note 5 modified in Table 4: STM32F100xx pin definitions.
IINJ(PIN) modified in Table 6: Current characteristics. Conditions
removed from Table 25: Low-power mode wakeup timings.
Notes modified in Table 33: I/O static characteristics.
Figure 27: Recommended NRST pin protection modified.
Note modified in Table 38: I2C characteristics. Figure 28: I2C bus AC
waveforms and measurement circuit(1) modified.
Table 45: DAC characteristics modified. Figure 36: 12-bit buffered
/non-buffered DAC added.
TIM2, TIM3, TIM4 and TIM15, TIM16 and TIM17 updated.
HDMI-CEC electrical characteristics added.
Values added to:
– Table 12: Maximum current consumption in Run mode, code with
data processing running from Flash
– Table 13: Maximum current consumption in Run mode, code with
data processing running from RAM
– Table 14: STM32F100xxB maximum current consumption in Sleep
mode, code running from Flash or RAM
26-Feb-2010 2 – Table 15: Typical and maximum current consumptions in Stop and
Standby modes
– Table 18: Peripheral current consumption
– Table 29: EMS characteristics
– Table 30: EMI characteristics
– Table 46: TS characteristics
Section 5.3.12: I/O port characteristics modified.
Added figures:
– Figure 12: Maximum current consumption in Run mode versus
frequency (at 3.6 V) - code with data processing running from RAM,
peripherals enabled
– Figure 13: Maximum current consumption in Run mode versus
frequency (at 3.6 V) - code with data processing running from RAM,
– Figure 15: Typical current consumption in Stop mode with regulator
in Run mode versus temperature at VDD = 3.3 V and 3.6 V
– Figure 16: Typical current consumption in Stop mode with regulator
in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V
– Figure 17: Typical current consumption in Standby mode versus
84/86 Doc ID 16455 Rev 5

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB Revision history
Table 53. Document revision history (continued)

Date Revision Changes
Revision history corrected.

Updated Table 6: Current characteristics
Values and note updated in Table 16: Typical current consumption in
Run mode, code with data processing running from Flash and
Table 17: Typical current consumption in Sleep mode, code running
from Flash or RAM.
Updated Table 15: Typical and maximum current consumptions in Stop
and Standby modes
30-Mar-2010 3 Added Figure 14: Typical current consumption on VBAT with RTC on
vs. temperature at different VBAT values
Typical consumption for ADC1 corrected in Table 18: Peripheral
current consumption.
Maximum current consumption and Typical current consumption:
frequency conditions corrected. Output driving current corrected.
Updated Table 30: EMI characteristics
fADC max corrected in Table 41: ADC characteristics.
Small text changes.
Updated Table 31: ESD absolute maximum ratings on page 54 and
Table 32: Electrical sensitivities on page 54
06-May-2010 4
Updated Table 43: ADC accuracy - limited test conditions on page 68
and Table 44: ADC accuracy on page 68
Updated Table 24: LSI oscillator characteristics on page 50
12-Jul-2010 5 Updated Table 43: ADC accuracy - limited test conditions on page 68
and Table 44: ADC accuracy on page 68
Doc ID 16455 Rev 5 85/86

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2010 STMicroelectronics - All rights reserved
STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
86/86 Doc ID 16455 Rev 5

STM32F100x4 STM32F100x6 STM32F100x8 STM32F100xB

Uploaded by

Copyright:

Available Formats

STM32F100x4 STM32F100x6 STM32F100x8 STM32F100xB

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

STM32F100x4 STM32F100x6 STM32F100x8 STM32F100xB

Uploaded by

Copyright:

Available Formats

STM32F100x4 STM32F100x6

– 24 MHz maximum frequency,

July 2010 Doc ID 16455 Rev 5 1/86

2/86 Doc ID 16455 Rev 5

2.22 Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Doc ID 16455 Rev 5 3/86

5.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4/86 Doc ID 16455 Rev 5

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Doc ID 16455 Rev 5 5/86

Table 45. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6/86 Doc ID 16455 Rev 5

Figure 1. STM32F100xx value line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Doc ID 16455 Rev 5 7/86

Figure 43. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat

8/86 Doc ID 16455 Rev 5

Doc ID 16455 Rev 5 9/86

10/86 Doc ID 16455 Rev 5

2.1 Device overview

Table 2. STM32F100xx features and peripheral counts

Doc ID 16455 Rev 5 11/86

Figure 1. STM32F100xx value line block diagram

CHANNELAND"+). 4)- 3#+ .33AS!&

4EMP SENSOR 4)- )&  BIT$!# $!#?/54AS!&

1. Peripherals not present in low-density value line devices.

12/86 Doc ID 16455 Rev 5

Figure 2. Clock tree

4. To have an ADC conversion time of 1.2 µs, APB2 must be at 24 MHz.

Doc ID 16455 Rev 5 13/86

2.2.1 ARM® Cortex™-M3 core with embedded Flash and SRAM

2.3 Embedded Flash memory

2.4 CRC (cyclic redundancy check) calculation unit

2.5 Embedded SRAM

14/86 Doc ID 16455 Rev 5

2.6 Nested vectored interrupt controller (NVIC)

2.7 External interrupt/event controller (EXTI)

2.8 Clocks and startup

2.9 Boot modes

Doc ID 16455 Rev 5 15/86

2.10 Power supply schemes

2.11 Power supply supervisor

2.12 Voltage regulator

2.13 Low-power modes

16/86 Doc ID 16455 Rev 5

2.15 RTC (real-time clock) and backup registers

2.16 Timers and watchdogs

Doc ID 16455 Rev 5 17/86

Table 3. Timer feature comparison

Up, Any integer

2.16.1 Advanced-control timer (TIM1)

TIM2, TIM3, TIM4

STM32F100xx devices feature three synchronizable 4-channels general-purpose timers.

18/86 Doc ID 16455 Rev 5

pulse mode output. This gives up to 12 input captures/output compares/PWMs on the

TIM15, TIM16 and TIM17

2.16.3 Basic timers TIM6 and TIM7

2.16.4 Independent watchdog

CHANNELAND"+). 4)- 3#+.33AS!&

4EMP SENSOR 4)- )& BIT$!# $!#?/54AS!&