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Uvm TB Flow

The document summarizes the key components in a UVM verification environment and their responsibilities: 1. Agents contain drivers, monitors, and sequencers, and connect them. The agent configures these components during build and connects them during connect. 2. The agent_top declares arrays of agent handles and constructs multiple agents during build based on a configuration parameter. 3. The env extends uvm_env, contains the agent_top, scoreboard, and virtual sequencer, and configures and connects these during the build and connect phases. 4. The test extends uvm_test, creates and configures the env, starts sequences on the virtual sequencer, and handles test flow and object

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Meghana Veggalam
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185 views2 pages

Uvm TB Flow

The document summarizes the key components in a UVM verification environment and their responsibilities: 1. Agents contain drivers, monitors, and sequencers, and connect them. The agent configures these components during build and connects them during connect. 2. The agent_top declares arrays of agent handles and constructs multiple agents during build based on a configuration parameter. 3. The env extends uvm_env, contains the agent_top, scoreboard, and virtual sequencer, and configures and connects these during the build and connect phases. 4. The test extends uvm_test, creates and configures the env, starts sequences on the virtual sequencer, and handles test flow and object

Uploaded by

Meghana Veggalam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as TXT, PDF, TXT or read online on Scribd
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seqr : `uvm_component_utils and the function new definition with 2

arguments
except function new, nothing else is required

driver : `uvm_component_utils and the function new definition with 2 arguments


build - get the config_db
connect - to establish the connections b/w dut & driver through
interfaces.
run - forever block to do get_next_item, drive_2_dut, item_done

monitor : `uvm_component_utils and the function new definition with 2 arguments


declare a handle analysis port
build - get the config_db
connect - to establish the connections b/w dut & monitor through
interfaces.
run - collect the data from the interfaces and broadcast the info
to sb & other components
with write method of analysis port.

agent : extends from uvm_agent


`uvm_component_utils and the function new definition with 2
arguments
declare the handles for drv, mon, seqr
build - get the config_db to use the is_active information
we will decide whether to construct active agent or
passive agent.
connect - establish the connections b/w drv & seqr
no need of any run phase

agent_top : extends from uvm_env or uvm_agent


`uvm_component_utils and the function new definition with 2
arguments
declare dynamic array of handles for the agents
build - get the cfg_db to get the no_of_agents information
use this no_of_agents information to decide,
how many no. of agents are going to be constructed.
no connect phase
no run phase

env : extends uvm_env


`uvm_component_utils and the function new definition with 2 arguments
handles for agent_top, sb, vseqr
build - get the env_config_db
- set the agent_cfg_db seperately, by restricting the access.
- creation of the components like sb, vseqr, ref_mod based on
the config parameters.
conenct - sb and mon - connections
- vseqr handle assignments
no run phase is required

test : extends uvm_test


`uvm_component_utils and the function new definition with 2 arguments
declare a handle for env & config_db
build - get the virtual interface information and put those
informations in the agent_cfg_db
- adjust the is_active parameter depending on the user
requirement.
- adjust the configuration parameters like has_sb, has_vseqr,
no_of_agents and store them in env_cfg_db
- set the env_cfg_db to the lower components by providing
global visibility.
- creating the env
end_of_eloboration - uvm_top.print_topology();
run - phase.raise_objection(this);
vseq.start(env_h.vseqr_h);
phase.drop_objection(this);

top module : declare an instance for interfaces


instantiate the design with the interface instance that is
already declared.
initial forever block to generate the clock required for
the design.
initial
- set the virtual interface information into the
config_db
- run_test("test_1");

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