DR - Chao Tan, Carnegie Mellon University
DR - Chao Tan, Carnegie Mellon University
DR - Chao Tan, Carnegie Mellon University
Chao Tan,
Carnegie Mellon University
Chap. 1: Digital Logic Circuits
• Characteristics of Multiprocessors
• Interconnection Structures
• Interprocessor Arbitration
• Interprocessor Communication/Synchronization
• Cache Coherence
Register Transfer & μ-operations
• Typically,
• What operations are performed on the data in the registers
• What information is passed between registers
Register Transfer & μ-operations
• Register Transfer
• Arithmetic Microoperations
• Logic Microoperations
• Shift Microoperations
MICROOPERATIONS (1)
- Microoperations set
MICROOPERATION (2)
R ← f(R, R)
• For any function of the computer, the register transfer language can be
used to describe the (sequence of) microoperations
DESIGNATION OF REGISTERS
MAR
• Registers may also be represented showing the bits of data they contain
Register Transfer & μ-operations Register Transfer Language
DESIGNATION OF REGISTERS
• Designation of a register
- a register
- portion of a register
- a bit of a register
15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields
Register Transfer & μ-operations Register Transfer
REGISTER TRANSFER
R2 ← R1
REGISTER TRANSFER
R3 ← R5
CONTROL FUNCTIONS
P: R2 ← R1
Load
Transfer occurs here
• The same clock controls the circuits that generate the control function
and the destination register
• Registers are assumed to use positive-edge-triggered flip-flops
Register Transfer & μ-operations Register Transfer
SIMULTANEOUS OPERATIONS
P: R3 ← R5, MAR ← IR
CONNECTING REGISTRS
Bus lines
B1 C1 D 1 B2 C2 D 2 B3 C3 D 3 B4 C4 D 4
0 0 0 0
4 x1 4 x1 4 x1 4 x1
MUX MUX MUX MUX
x
select
y
4-line bus
Register Transfer & μ-operations Bus and Memory Transfers
Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3
D 0 D1 D2 D 3
z E (enable)
Select 2x4
w
Decoder
S0 0
Select 1
S1 2
Enable 3
Register Transfer & μ-operations Bus and Memory Transfers
R2 ← R1
or
• In the former case the bus is implicit, but in the latter, it is explicitly
indicated
Register Transfer & μ-operations Bus and Memory Transfers
MEMORY (RAM)
• Memory (RAM) can be thought as a sequential circuits containing
some number of registers
• These registers hold the words of memory
• Each of the r registers is indicated by an address
• These addresses range from 0 to r-1
• Each register (word) can hold n bits of data
• Assume the RAM contains r = 2k words. It needs the following
• n data input lines
data input lines
• n data output lines
• k address lines n
• A Read control line
address lines
• A Write control line
k
RAM
Read
unit
Write
n
data output lines
Register Transfer & μ-operations Bus and Memory Transfers
MEMORY TRANSFER
• Collectively, the memory is viewed at the register level as a device,
M.
• Since it contains multiple locations, we must specify which address in
memory we will be using
• This is done by indexing memory references
MEMORY READ
R1 ← M[MAR]
MEMORY WRITE
M[MAR] ← R1
MICROOPERATIONS
ARITHMETIC MICROOPERATIONS
• The basic arithmetic microoperations are
• Addition
• Subtraction
• Increment
• Decrement
Binary Adder
Binary Adder-Subtractor
Binary Incrementer
Register Transfer & μ-operations Arithmetic Microoperations
ARITHMETIC CIRCUIT
Cin
S1
S0
A0 X0 C0
S1 D0
S0 FA
B0 0 4x1 Y0 C1
1 MUX
2
3
A1 X1 C1
S1 FA D1
S0
B1 0 4x1 Y1 C2
1 MUX
2
3
A2 X2 C2
S1 FA D2
S0
B2 0 4x1 Y2 C3
1 MUX
2
3
A3 X3 C3
S1 FA D3
S0
B3 0 4x1 Y3 C4
1 MUX
2
3 Cout
0 1
LOGIC MICROOPERATIONS
• Specify binary operations on the strings of bits in registers
• Logic microoperations are bit-wise operations, i.e., they work on the individual bits
of data
• useful for bit manipulations on binary data
• useful for making logical decisions based on the bit value
• There are, in principle, 16 different logic functions that can be defined
over two binary input variables
Ai
0
Bi
1
4X1 Fi
MUX
2
3 Select
S1
S0
Function table
S1 S0 Output μ-operation
0 0 F=A∧B AND
0 1 F=A∨B OR
1 0 F=A⊕B XOR
1 1 F = A’ Complement
Register Transfer & μ-operations Logic Microoperations
• Selective-set A←A+B
• Selective-complement A ← A ⊕ B
• Selective-clear A ← A • B’
• Mask (Delete) A←A•B
• Clear A←A⊕B
• Insert A ← (A • B) + C
• Compare A←A⊕B
• ...
Register Transfer & μ-operations Logic Microoperations
SELECTIVE SET
• In a selective set operation, the bit pattern in B is used to set certain bits
in A
1 1 0 0 At
1010 B
1 1 1 0 At+1 (A ← A + B)
SELECTIVE COMPLEMENT
1 1 0 0 At
1010 B
0 1 1 0 At+1 (A ← A ⊕ B)
SELECTIVE CLEAR
1 1 0 0 At
1010 B
0 1 0 0 At+1 (A ← A ⋅ B’)
MASK OPERATION
1 1 0 0 At
1010 B
1 0 0 0 At+1 (A ← A ⋅ B)
CLEAR OPERATION
• In a clear operation, if the bits in the same position in A and B are the
same, they are cleared in A, otherwise they are set in A
1 1 0 0 At
1010 B
0 1 1 0 At+1 (A ← A ⊕ B)
Register Transfer & μ-operations Logic Microoperations
INSERT OPERATION
• An insert operation is used to introduce a specific bit pattern into A register,
leaving the other bit positions unchanged
• This is done as
• A mask operation to clear the desired bit positions, followed
by
• An OR operation to introduce the new bits into the desired
positions
• Example
• Suppose you wanted to introduce 1010 into the low order four bits
of A: 1101 1000 1011 0001 A (Original)
1101 1000 1011 1010 A (Desired)
SHIFT MICROOPERATIONS
• There are three types of shifts
• Logical shift
• Circular shift
• Arithmetic shift
• What differentiates them is the information that goes into the
serial input
LOGICAL SHIFT
• In a logical shift the serial input to the shift is a 0.
CIRCULAR SHIFT
• In a circular shift the serial input is the bit that is shifted out of the other
end of the register.
ARITHMETIC SHIFT
• An arithmetic shift is meant for signed binary numbers (integer)
• An arithmetic left shift multiplies a signed number by two
• An arithmetic right shift divides a signed number by two
• The main distinction of an arithmetic shift is that it must keep the sign of
the number the same as it performs the multiplication or division
sign
bit
ARITHMETIC SHIFT
• An left arithmetic shift operation must be checked for the overflow
0
sign
bit
S
MUX H0
0
1
A0
A1 S
MUX H1
0
A2 1
A3
S
MUX H2
0
1
S
MUX H3
0
1
Serial
input (IL)
Register Transfer & μ-operations Shift Microoperations
Arithmetic D i
Circuit
Select
Ci+1
0 4x1 Fi
1 MUX
2
3
Ei
Logic
Bi Circuit
Ai
Ai-1 shr
Ai+1 shl