10fhy RSM1 Gan TF (LF) (SN)
10fhy RSM1 Gan TF (LF) (SN)
10fhy RSM1 Gan TF (LF) (SN)
IRLR3110ZPbF
IRLU3110ZPbF
Features
l Advanced Process Technology HEXFET® Power MOSFET
l Ultra Low On-Resistance D
l 175°C Operating Temperature
l Fast Switching VDSS = 100V
l Repetitive Avalanche Allowed up to Tjmax
Description G RDS(on) = 14mΩ
Specifically designed for Industrial applications,
this HEXFET® Power MOSFET utilizes the latest S
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating . These features com-
bine to make this design an extremely efficient and
reliable device for use in Industrial applications
and a wide variety of other applications. D-Pak I-Pak
IRLR3110ZPbF IRLU3110ZPbF
nH 6mm (0.25in.)
LS Internal Source Inductance ––– 7.5 ––– from package
G
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 38A, VGS = 0V e
trr Reverse Recovery Time ––– 34 51 ns TJ = 25°C, IF = 38A, VDD = 50V
Qrr Reverse Recovery Charge ––– 42 63 nC di/dt = 100A/µs e
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRLR/U3110ZPbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
100
4.5V 4.5V
3.5V 3.5V
3.0V 3.0V
2.7V 100 2.7V
BOTTOM 2.5V BOTTOM 2.5V
10
1
10
2.5V
0.1 2.5V
≤60µs PULSE WIDTH ≤60µs PULSE WIDTH
Tj = 25°C Tj = 175°C
0.01 1
0.1 1 10 100 1000 0.1 1 10 100 1000
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)
1000 150
T J = 25°C
Gfs, Forward Transconductance (S)
125
ID, Drain-to-Source Current (Α)
100 T J = 175°C
100
10 75 T J = 175°C
50
T J = 25°C
1
25 V DS = 10V
VDS = 25V
≤60µs PULSE WIDTH 300µs PULSE WIDTH
0.1 0
0 2 4 6 8 10 12 14 16 0 25 50 75
ID,Drain-to-Source Current (A)
VGS, Gate-to-Source Voltage (V)
100000 5.0
VGS = 0V, f = 1 MHZ
ID= 38A
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
Ciss
3.0
1000
Coss
2.0
Crss
100
1.0
10 0.0
1 10 100 0 10 20 30 40
VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC)
1000 1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
T J = 175°C
100
100 100µsec
T J = 25°C 1msec
10
10msec
10 DC
1
Tc = 25°C
Tj = 175°C
VGS = 0V
Single Pulse
0.1 1
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)
70 3.0
ID = 63A
2.0
(Normalized)
40
30
1.5
20
1.0
10
0 0.5
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C) T J , Junction Temperature (°C)
10
Thermal Response ( Z thJC )
1
D = 0.50
0.20
0.10 R1 R2
0.1 R1 R2 Ri (°C/W) τi (sec)
0.05 τJ
τJ
τC
0.383 0.000267
τ
τ1 τ2
0.02 τ1 τ2 0.667 0.003916
0.01
0.01 Ci= τi/Ri
Ci i/Ri
SINGLE PULSE Notes:
( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1
www.irf.com 5
IRLR/U3110ZPbF
300
15V
100
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
50
tp
0
25 50 75 100 125 150 175
Starting T J , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
vs. Drain Current
QG
10 V
QGS QGD 3.0
VGS(th) Gate threshold Voltage (V)
VG 2.5
2.0
Charge
Fig 13a. Basic Gate Charge Waveform 1.5 ID = 100µA
ID = 250µA
1.0 ID = 1.0mA
ID = 1.0A
L 0.5
VCC
DUT
0 0.0
1K -75 -50 -25 0 25 50 75 100 125 150 175 200
T J , Temperature ( °C )
Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage vs. Temperature
6 www.irf.com
IRLR/U3110ZPbF
100
10
0.05
0.10
0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
*
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
Recovery Body Diode Forward
- + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD
Ripple ≤ 5% ISD
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
RD
V DS
VGS
D.U.T.
RG
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
VDS
90%
10%
VGS
td(on) tr t d(off) tf
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IRLR/U3110ZPbF
D-Pak (TO-252AA) Package Outline
25
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
www.irf.com 9
IRLR/U3110ZPbF
I-Pak (TO-251AA) Package Outline
25
3$57180%(5
,17(51$7,21$/
5(&7,),(5 ,5)8 '$7(&2'(
/2*2 3 '(6,*1$7(6/($')5((
352'8&7237,21$/
<($5
$66(0%/<
/27&2'( :((.
$ $66(0%/<6,7(&2'(
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10 www.irf.com
IRLR/U3110ZPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
max. junction temperature. (See fig. 11). avalanche performance.
Limited by TJmax, starting TJ = 25°C, L = 0.16mH This value determined from sample failure population. 100%
RG = 25Ω, IAS = 38A, VGS =10V. Part not tested to this value in production.
recommended for use above this value. When mounted on 1" square PCB (FR-4 or G-10 Material).
Pulse width ≤ 1.0ms; duty cycle ≤ 2%. Rθ is measured at TJ approximately 90°C.
Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to
80% VDSS .
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.11/09
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