CE001

Using dsPIC30F A/D Converters and the DSP library for

Signal Filtering
signal analysis and filtering will benefit from the
Author: Hrushikesh “Rishi” Vasuki dsPIC30F product family. Key features in the dsPIC30F
Microchip Technology Inc. architecture that enable such applications are briefly
described to help you understand the example source
OVERVIEW code. We will summarize how the example source
code demonstrates these capabilities. We will also
This Code Example document briefly describes and provide a list of the software and hardware
demonstrates the capabilities of the dsPIC30F Digital development tools and libraries used in building the
Signal Controller product family for performing signal example project.
analysis and filtering. The accompanying MPLAB® IDE
workspace exemplifies why applications that require

FIGURE 1: SIGNAL ANALYSIS AND FILTERING WITH dsPIC® DSC

+2.5V

dsPIC® DSC

4 kHz 2.5 VDC High Pass

A/D Further D/A
Anti-aliasing Level Converter Processing Converter
Filter Shifter Filter

-2.5V

Note: Check the schematics for the development board you are using to determine if analog circuitry,
level shifting and D/A conversion are provided on that board. You may need to provide some of
this circuitry externally.

BENEFITS digital result to an Infinite Impulse Response (IIR) filter.

IIR filters can be used to attenuate or amplify a range
The dsPIC® DSC devices feature a DSP engine that is of frequencies from an incoming signal.
seamlessly integrated into the CPU. They also provide
The Digital IIR filter used in this example is a C-callable
an on-chip 10-bit (1M SPS) or 12-bit (200K SPS) A/D
function provided in the dsPIC30F DSP library
Converter peripheral module. This combination of the
software. Such digital filters are typically implemented
A/D converter peripheral module and DSP engine
in software using Multiply-Accumulate (MAC) class of
allows applications to perform complex operations like
DSP instructions, featured in the dsPIC DSC
signal filtering and frequency estimation with the dsPIC
architecture. The MAC-class of instructions requires
DSC. This capability reduces on-board analog circuitry,
input data to be presented in 1.15 signed-fractional
saves space on the board and provides the additional
number format. The 1.15 format is described in detail in
benefits of field re-programmability and improving
the dsPIC30F Programmer's Reference Manual
temperature characteristics of your circuit.
(DS70030). The dsPIC30F A/D converters provide
conversion results in many number formats, including
OPERATION the 1.15 signed fractional format. Further details on the
dsPIC30F A/D converters may be found in the
The example dsPIC30F project in the attached MPLAB dsPIC30F Family Reference Manual (DS70046).
IDE workspace demonstrates how the dsPIC30F A/D
converter can be configured for converting an analog Figure 1 illustrates the operation of the dsPIC30F
signal and providing a signed fractional (1.15 format) device demonstrated by the example project.

© 2005 Microchip Technology Inc. DS92001A-page 1

CE001
The example dsPIC30F project configures the The project/workspace assumes that a 7.37 MHz
dsPIC30F A/D converter for a sampling analog input crystal provides device clocking. Such crystals are
pin, AN7, at a rate of 8 kHz. Any single-ended input provided on several dsPIC30F development boards,
signal band-limited to 4 kHz may be applied on the for example dsPICDEM™ 64-Pin Starter Development
input pin. A single-ended input signal (not differential) Board, dsPICDEM 1.1, dsPICDEM 2,
is one that has a DC bias that is half the reference dsPICDEM.net™, and dsPICDEM MC1. Additional
voltage. oscillator and PLL options have been configured in
The A/D converter is set up for interrupting the CPU source code to operate the device at a throughput of
after converting 16 samples. At each interrupt, a High- 29.4 MIPS. All Microchip software tools and dsPIC30F
Pass Elliptic IIR filter function is invoked. The high- documentation described in this document can be
pass filter heavily attenuates any signals in the downloaded from http://www.microchip.com.
frequency range, 0 to 500 Hz. The filtering is performed
on a block of 16 samples using a cascade of SUMMARY
transposed biquadratic (Direct Form II) IIR filter
sections provided by the DSP library. The biquadratic The example project lets you set up the dsPIC30F
filter section is a commonly used filter topology that 12-bit A/D converter for sampling an analog input
implements the difference equations required for signal at 8 KHz in an interrupt-driven fashion using C
filtering a digital signal. language. The example also demonstrates how you
can invoke an IIR filter function provided in the
dsPIC30F DSP library software, as well as, how
DEVELOPMENT TOOLS AND coefficients generated by the dsPIC DSC Filter
LIBRARIES Design software can be incorporated into the project.
dsPICworks™ tool and dsPIC DSC Filter Design
The example workspace was created using MPLAB
screen shots and simulation files are also provided in
IDE v7.11. All source code in the project is written
the Zip file. Refer to the Readme.txt file for a sum-
in C. Source-level comments have been provided to
mary description of the various files and folders pro-
aid understanding. The project also uses an IIR
vided in the project. Operational aspects are
filtering function from the DSP Library archive file,
described in source-level comments in each file.
libdsp-coff.a, which is provided in the MPLAB
C30 v1.32 C compiler tools suite. The IIR filter uses
filter coefficients generated by dsPIC DSC Filter
Design, a graphical tool that designs digital filters
for the dsPIC30F device. The example MPLAB IDE
workspace is configured for a dsPIC30F6014
device, but it is easily re-configured for any
dsPIC30F device with a 10-bit or 12-bit A/D
converter. Analog input pin, AN7, used in this
project is available for use on all dsPIC DSC
development boards and many dsPIC DSC devices.

DS92001A-page 2 © 2005 Microchip Technology Inc.

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© 2005 Microchip Technology Inc. DS92001A-page 3

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DS92001A-page 4 © 2005 Microchip Technology Inc.