UNIT – III

Sequential Logic Circuits

Objectives:
 To familiarize with the concepts of different sequential circuits.
Syllabus:

Design procedure, Flip-flops, Truth tables and excitation tables, Conversion of flip-flops, Design
of counters, Ripple counters, Synchronous counters, Ring counter, Johnson counter, Registers,
Shift registers, Universal shift register.
Outcomes:
Students will be able to
 understand the functionality of different latches and flip-flops..
 distinguish the working of latch and flip-flop.
 convert from one flip-flop to another flip-flop
 classify various types of registers.
 design synchronous and asynchronous counters.
Learning Material
INTRODUCTION:

 Combinational circuits are those whose output at any instant of time is entirely dependent
on the input present at that time.

 On the other hand Sequential circuits are those in which output at any given time is not
only dependent on the present input but also on previous outputs. Naturally, such circuits
must record the previous outputs which give rise to memory.

 Often, there are requirements of digital circuits whose output remain unchanged, once
set, even if the inputs are removed. Such devices are referred as “memory elements”,
each of which can hold 1-bit of information. These binary bits can be retained in the

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 memory indefinitely (as long as power is delivered) or until new information is feeded to
the circuit.

Fig 1: Block diagram of a sequential circuit

 Block diagram of a sequential circuit, which can be regarded as a collection of memory

 A feedback path is formed by using memory elements, input to which is the output of
combinational circuit.

 The binary information stored in memory element at any given time is defined as the
state of sequential circuit at that time. Present contents of memory elements are referred
as the present state.

 The combinational circuit receives the signals from external input and from the memory
output and determines the external output.

 They also determine the condition and binary values to change the state of memory. The
new contents of the memory elements are referred as next state and depend upon the
external input and present state.

 Hence, a sequential circuit can be completely specified by a time sequence of inputs,

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 CLASSIFICATION OF SEQUENTIAL CIRCUITS:

There exist two main categories of sequential circuits, namely synchronous and asynchronous
sequential circuits.

i. Asynchronous Sequential Circuits:

 Sequential circuits whose behavior depends upon the sequence, in which the inputs are
applied, are called Asynchronous Sequential Circuits.

 In these circuits, outputs are affected whenever a change in inputs is detected. Memory
elements used in asynchronous circuits mostly are time delay devices.

 The memory capability of time delay devices is due to the propagation delay of the devices.
Propagation delay produced by the logic gates is sufficient for this purpose.

 Hence “An Synchronous sequential circuit can be regarded as a combinational circuit with
feedback”. However feedback among logic gates makes the asynchronous sequential
circuits, often susceptible to instability.

 As a result they may become unstable. This makes the design of asynchronous circuits very
tedious and difficult.

ii. Synchronous Sequential Circuit:

 It may be defined as a sequential circuit, whose state can be affected only at the discrete
instants of time.

 The synchronization is achieved by using a timing device, termed as System Clock

 The clock pulses are feed to entire system in such a way that internal states (i.e. memory
contents) are affected only when the clock pulses hit the circuit.

STORAGE ELEMENTS:

 Latches

 A storage element in a digital circuit can maintain a binary state indefinitely (as long as
power is delivered to the circuit), until directed by an input signal to switch states.
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  The major differences among various types of storage elements are in the number of inputs
they possess and in the manner in which the inputs affect the binary state.

 Storage elements that operate with signal levels (rather than signal transitions) are referred
to as latches; those controlled by a clock transition are flip-flops. Latches are said to be level
sensitive devices; flip-flops are edge sensitive devices.

 The two types of storage elements are related because latches are the basic circuits from
which all flip-flops are constructed. Although latches are useful for storing binary
information and for the design of asynchronous sequential circuits, they are not practical for
use as storage elements in synchronous sequential circuits.

i. SR Latch

 The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND
gates, and two inputs labeled S for set and R for reset.

 Both the versions are shown in Fig 2(a) & Fig 2(b). The latch has two useful states. When
output Q = 1 and Q’ = 0, the latch is said to be in the set state. When Q = 0 and Q’ = 1, it is
in the reset state. SR

SR Latch with Control Input

 The operation of the basic SR latch can be modified by providing an additional input signal
that determines (controls) when the state of the latch can be changed by determining
whether S and R (or S’ and R’) can affect the circuit.

 An SR latch with a control input is shown in Fig 2(c) which consists of the basic SR latch
and two additional NAND gates. The control input En acts as an enable signal for the other
two inputs.

 The outputs of the NAND gates stay at the logic-1 level as long as the enable signal
remains at 0. This is the quiescent condition for the SR latch. When the enable input goes
to 1, information from the S or R input is allowed to affect the latch.

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 The set state is reached with S = 1, R = 0, and En = 1 (active-high enabled). To change to the
reset state, the inputs must be S = 0, R = 1, and En = 1. In either case, when En returns to 0,
the circuit remains in its current state.

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  The control input disables the circuit by applying 0 to En, so that the state of the output does
not change regardless of the values of S and R. Moreover, when En = 1 and both the S and R
inputs are equal to 0, the state of the circuit does not change.

 These conditions are listed in the function table accompanying the diagram. An
indeterminate condition occurs when all three inputs are equal to 1. This condition places
0’s on both inputs of the basic SR latch, which puts it in the undefined state.

ii. D Latch (Transparent latch)

 One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to
ensure that inputs S and R are never equal to 1 at the same time.

 This is done in the D latch, shown in Fig.3. This latch has only two inputs: D (data) and En
(enable). The D input goes directly to the S input, and its complement is applied to the R
input.

 As long as the enable input is at 0, the cross-coupled SR latch has both inputs at the 1 level
and the circuit cannot change state regardless of the value of D. The D input is sampled when
En = 1.

 If D = 1, the Q output goes to 1, placing the circuit in the set state. If D = 0, output Q goes to
0, placing the circuit in the reset state.

Fig. 3 D-latch

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 The graphical representration of S-R and D-latch is as shown below

FLIPFLOPS

 The synchronous sequential circuit which uses clock at the input of memory element is
referred as Clocked Sequential circuit and the memory element in this circuit known as
Flip-Flop that can store 1-bit of information, and thus forms a 1-bit memory cell.

 These circuits have two outputs, one giving the value of binary bit stored in it and the other
gives the complemented value.

 The real differences among various flip-flops are the number of inputs and the manner in
which binary information can be entered into it

 The flip-flops are 1-bit memory cells that can maintain the stored bit for desired period of
time which consists of two stable stages so it is called as Bi-stable device and states are 0V
and + 5V corresponding to Logic 0 and Logic 1 respectively

i. RS Flip-Flop

 A flip-flop circuit can be constructed either by using two 2-input OR gate or NAND gates.
These circuits consists of a cross coupled connection from output of one gate to the input of
the other gate constitutes a feedback path. Each flip-flop has two outputs, Q and Q ’, and two
inputs, set, reset.

 The operation of basic flip-flop can be modified by proving an additional control input that
determines when the state of the circuit is to be changed.

 An RS flip-flop with a clock pulse (CP) input, which consists of a basic flip-flop circuit and
two additional NAND gates, is as shown in Fig. 4.

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 Fig. 4. RS flip-flop with NAND gates

ii. D-Flip-flop

 The SR latch, which has two inputs S and R. At any time to store a bit, must activate both the
inputs simultaneously. This may be troubling in some applications. Use of only one data line
is convenient in such applications.

 Moreover the forbidden input combination S = R = 1 may occur unintentionally, thus leading
the flip-flop to indeterminate state. In order to deal such issues, SR flip-flop is further
modified as shown in Fig 5.

 The resultant is referred as D flip-flop which has only one input labelled D (called as Data
input). An external NAND gate (connected as inverter) is used to ensure that S and R inputs
are always complement to each other. Thus to store information in this latch, only one signal
has to be generated.

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 Fig 5: D flip-flop or D latch

 Operation of this flip-flop is straight forward. At any instant of time the output Q is same as
D (i.e. Q = D). Since output is exactly same as the input, the latch may be viewed as a delay
unit.

 The flip-flop always takes some time to produce output, after the input is applied. This is
called propagation delay.

 Thus it is said that the information present at point D (i.e. at input) will take a time equal to
the propagation delay to reach to Q. Hence the information is delayed. For this reason it is
often called as Delay (D) Flip-Flop.

iii. JK FLIPFLOP

 A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type
is defined in the JK type.

 Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-
flop, the letter J is for set and the letter K is for clear).

 When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its
complement state, ie., if Q=1, it switches to Q=0 and vice versa. A clocked JK flip-flop is
shown in Fig. 6.

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  Output Q is ANDed with K and CP inputs so that the flip-flop is cleared during a clock pulse
only if Q was previously 1.

 Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop is set with a clock
pulse only if Q' was previously 1.

Fig.6 JK Flip-flop

 Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a
1 (while J=K=1) after the outputs have been complemented once will cause repeated and
continuous transitions of the outputs.

 To avoid this, the clock pulses must have a time duration less than the propagation delay
through the flip-flop.

 The restriction on the pulse width can be eliminated with a master-slave or edge-triggered
construction. The same reasoning also applies to the T flip-flop presented next.

iv. T Flip-Flop

 The T flip-flop is a single input version of the JK flip-flop which is shown, in Fig.7and it is
obtained from the JK type if both inputs are tied together. The output of the T flip-flop
"toggles" with each clock pulse.

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 Fig. 7 Clocked T flip-flop

Race around Condition and Solution

 Whenever the width of the trigger pulse is greater than the propagation time of the flip-flop,
then flip-flop continues to toggle 1-0-1-0 until the pulse turns 0.

 When the pulse turns 0, unpredictable output may result i.e. the state and output not known.
This is called race around condition.

 In level-triggered flip-flop circuits, the circuit is always active when the clock signal is high,
and consequently unpredictable output may result. For example, during this active clock
period, the output of a T-FF may toggle continuously.

 The output at the end of the active period is therefore unpredictable. To overcome this
problem, edge triggered circuits can be used whose output is determined by the edge, instead
of the level, of the clock signal, for example, the rising (or trailing) edge.

 Another way to resolve the problem is the Master-Slave circuit shown in Fig 8.

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 Fig 8: Master slave circuit
The operation of a Master-Slave FF has two phases as shown in Fig.8

• During the high period of the clock, the master FF is active, taking both inputs and feedback
from the slave FF. The slave FF is de-activated during this period by the negation of the clock
so that the new output of the master FF won’t affect it.

• During the low period of the clock, the master FF is deactivated while the slave FF is active.
The output of the master FF can now trigger the slave FF to properly set its output. However,
this output will not affect the master FF through the feedback as it is not active.

Fig 9: Master slave operation

 It is seen that the trailing edge of the clock signal will trigger the change of the output of the
Master-Slave FF. The master-slave combination can be constructed for any type of flip-flop
by adding a clocked RS flip-flop with an inverted clock to form the slave. A master-slave JK
flip-flop constructed with NAND gates is shown in Fig.10.

 It consists of two flip-flops; gates1 through 4 form the master flip-flop, and gates 5 through 8
form the slave flip-flop. The information presented at the J and K inputs is transmitted to the
master flip-flop on the positive edge of the clock pulse and is held there until the negative
edge of the clock pulse occurs, after which it is allowed to pass through to the slave flip-flop.

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 The clock input is normally 0, which keeps the outputs of gates 1 and 2 at the 1 level. This
prevents the J and K inputs from affecting the master flip-flop.

 The slave flip-flop is a clocked RS type, with the master flip-flop supplying the inputs and the
clock input being inverted by gate 9. When the clock is 0, the output of gate 9 is 1, so that
output Q is equal to Y, and Q’ is equal to Y’.

 When the positive edge of a clock pulse occurs, the master flip-flop is affected and may
switch states. The slave flip-flop is isolated as long as the clock is at the level1, because the
output of gate 9 provides a 1 to both inputs of the NAND basic flip-flop of gates 7 and 8.

 When the clock input returns to 0, the master flip-flop is isolated from J and K inputs and the
slave flip-flop goes to the same state as the master flip-flop.

Fig.10 Clocked master-slave JK flip-flop

Operating Characteristics of Flip-flops

The operation characteristics specify the performance, operating requirements, and operating
limitations of the circuits. The operation characteristics mentions here apply to all flip-flops
regardless of the particular form of the circuit.

Propagation Delay Time—is the interval of time required after an input signal has been applied
for the resulting output change to occur.

Set-up Time—is the minimum interval required for the logic levels to be maintained constantly
on the inputs (J and K, or S and R, or D) prior to the triggering edge of the clock pulse in order
for the levels to be reliably clocked into the flip-flop.
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Hold Time—is the minimum interval required for the logic levels to remain on the inputs after
the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-
flop.

Maximum Clock Frequency—is the highest rate that a flip-flop can be reliably triggered.

Power Dissipation—is the total power consumption of the device.

Pulse Widths—are the minimum pulse widths specified by the manufacturer for the Clock, SET
and CLEAR inputs.

Flip-Flop Applications

 Frequency Division
 Parallel Data Storage
FLIP-FLOP EXCITATION TABLE

 The characteristic table is useful during the analysis of sequential circuits when the value of
flip-flop inputs is known and if the value of the flip-flop output Q after the rising edge of the
clock signal. As with any other truth table, the map method is used to derive the characteristic
equation for each flip-flop.

 During the design process the transition from present state to the next state s usually known
and flip-flop input conditions are found that will cause the required transition. For this reason
a table that lists the required inputs for a given change of state is needed. Such a list is called
the excitation table.

 There are four possible transitions from present state to the next state. The required input
conditions are derived from the information available in the characteristic table.

 The symbol X in the table represents a “don’t care” condition, that is, it does not matter
whether the input is 1 or 0.

 The different types of flip flops (RS, JK, D, T) can also be described by their excitation, table
as shown in Fig. The left side shows the desired transition from Qn to Qn+1, the right side
gives the triggering signals of various types of FFs needed for the transitions.

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 Table 1:Excitation table

FLIP-FLOP CONVERSIONS

 To convert a given type A FF to a desired type B FF some conversion logic is used and the
key here is to use the excitation table specified in Table 1 which shows the necessary
triggering signal (S, R, J, K, D and T) for a desired flip flop state transition Qn →Qn+1 is
reproduced here.

Example 1. Convert a D-FF to a T-FF:

A circuit is to be designed which is used to generate the triggering signal D as a function of T

Consider the excitation table:

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Treating D as a function of T and current FF state Q Qn we have D = T'Q + TQ = T⊕Q

Fig. 11 Convert a D-FF to a T-FF

Example 2. Convert a RS-FF to a D-FF:

A circuit is to be designed which can generate the triggering signals S and R as functions of D
and Q. Consider the excitation table:

The desired signal S and R can be obtained as functions of T and current FF state Q from the
Karnaugh maps:

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 Fg.12 Convert a RS-FF to a D-FF

Example 3. Convert a RS-FF to a JK-FF.

We need to design the circuit to generate the triggering signals S and R as functions of J, K and
Q. Consider the excitation table.

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The desired signals S and R as function J, K and current FF state Q can be obtained from the
Karnaugh maps:

Fig.13 Convert a RS-FF to a JK-FF

RIPPLE COUNTER

 A register that goes through a prescribed sequence of states upon the application of input
pulses is called a counter.

 The input pulses may be clock pulses, or they may originate from some external source and
may occur at a fixed interval of time or at random.

 The sequence of states may follow the binary number sequence or any other sequence of
states.

 A counter that follows the binary number sequence is called a binary counter. An n ‐bit binary
counter consists of n flip‐flops and can count in binary from 0 through 2n - 1.

 Counters are available in two categories: ripple counters and synchronous counters.

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 In a ripple counter, a flip‐flop output transition serves as a source for triggering other flip‐
flops. In other words, the C (clock)input of some or all flip‐flops are triggered, not by the
common clock pulses, but rather by the transition that occurs in other flip‐flop outputs.

 In a synchronous counter, the C inputs of all flip‐flops receive the common clock.

Binary Ripple Counter

 A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an
external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop.

 Asynchronous counters are also called ripple-counters because of the way the clock pulse
ripples it way through the flip-flops.

 The MOD of the ripple counter or asynchronous counter is 2 n if n flip-flops are used. For a 4-
bit counter, the range of the count is 0000 to 1111.

 A counter may count up or count down or count up and down depending on the input control.
The count sequence usually repeats itself. When counting up, the count sequence goes from
0000, 0001, 0010, ... 1110 , 1111 , 0000, 0001, ... etc.

 When counting down the count sequence goes in the opposite manner: 1111, 1110, ... 0010,
0001, 0000, 1111, 1110, ... etc.

 The complement of the count sequence counts in reverse direction. If the uncomplemented
output counts up, the complemented output counts down. If the uncomplemented output
counts down, the complemented output counts up.

 There are many ways to implement the ripple counter depending on the characteristics of the
flip flops used and the requirements of the count sequence.

 Clock Trigger: Positive edged or Negative edged

 JK or D flip-flops

 Count Direction: Up, Down, or Up/Down

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 Asynchronous counters are slower than synchronous counters because of the delay in the
transmission of the pulses from flip-flop to flip-flop.

 With a synchronous circuit, all the bits in the count change synchronously with the assertion
of the clock. Examples of synchronous counters are the Ring and Johnson counter.

 It can be implemented using D-type flip-flops or JK-type flip-flops. The circuit below uses 2
D flip-flops to implement a divide-by-4 ripple counter (2n = 22 = 4). It counts down.

Fig. 13 Two bit Ripple Conter

 Click on CLK (Red) switch and observe the changes in the outputs of the flip flops. The
CLK switch is a momentary switch (similar to a door bell switch - normally off).
 PR and CLR are both connected to VCC (set to 1)
 The D flip flop clock has a rising edge CLK input. For example Q0 behaves as follows
 The D input value just before the CLK rising edge is noted (Q00).
 When CLK rising edge occurs, Q0 is assigned the previously noted D value
(Q00).
 Thus, whenever a rising edge appears at the CLK of the D flip flop, the
output Q changes state (or toggles).

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 The MOD or number of unique states of this 2 flip flop ripple counter is 4 (22).
 Simulate and Breadboard the Ripple Counter circuit.
 A Truncated Ripple Counter is used if a MOD of less than 2n is required. For example, if
you want to change the sequence from 3,2,1,0,3,2,1,0 ... to 3,2,0,3,2,0 ...

BCD Ripple Counter

 A decimal counter follows a sequence of 10 states and returns to 0 after the count of 9. Such a
counter must have at least four flip‐flops to represent each decimal digit, since a decimal digit
is represented by a binary code with at least four bits.

 The sequence of states in a decimal counter is dictated by the binary code used to represent a
decimal digit. If BCD is used, the sequence of states is as shown in the state diagram of Fig14.
A decimal counter is similar to a binary counter, except that the state after 1001 (the code for
decimal digit 9) is 0000 (the code for decimal digit 0).

Fig.14 State Diagram of BCD counter

 The logic diagram of a BCD ripple counter using JK flip‐flops is shown in Fig.15, the four
outputs are designated by the letter symbol Q, with a numeric subscript equal to the binary
weight of the corresponding bit in the BCD code.

 Note that the output of Q1 is applied to the C inputs of both Q2 and Q8 and the output of Q2
is applied to the C input of Q4. The J and K inputs are connected either to a permanent 1
signal or to outputs of other flip‐flops.

 A ripple counter is an asynchronous sequential circuit. Signals that affect the flip‐flop
transition depend on the way they change from 1 to 0. The operation of the counter can be

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 explained by a list of conditions for flip‐flop transitions. These conditions are derived from
the logic diagram and from knowledge of how a JK flip‐flop operates.

 Remember that when the C input goes from 1 to 0, the flip‐flop is set if J = 1, is cleared if K
= 1, is complemented if J = K = 1, and is left unchanged if J = K = 0.

Fig.15 BCD counter

SYNCHRONOUS COUNTERS

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 Synchronous counters are different from ripple counters in that clock pulses are applied to the
inputs of all flip‐flops. A common clock triggers all flip‐flops simultaneously, rather than one
at a time in succession as in a ripple counter.

 The decision whether a flip‐flop is to be complemented is determined from the values of the
data inputs, such as T or J and K at the time of the clock edge. If T = 0 or J = K = 0, the flip‐
flop does not change state. If T = 1 or J = K = 1, the flip‐flop complements.

Binary Counter

 The design of a synchronous binary counter is so simple that there is no need to go through a
sequential logic design process. In a synchronous binary counter, the flip‐flop in the least
significant position is complemented with every pulse.

 A flip-flop in any other position is complemented when all the bits in the lower significant
positions are equal to 1. For example, if the present state of a four‐bit counter is A3A2A1A0 =
0011, the next count is 0100. A0 is always complemented.

 A1 is complemented because the present state of A0 = 1. A2 is complemented because the

 Synchronous binary counters have a regular pattern and can be constructed with
complementing flip‐flops and gates. The regular pattern can be seen from the four‐bit counter
depicted in Fig. 16 below.

 The C inputs of all flip‐flops are connected to a common clock. The counter is enabled by
Count Enable. If the enable input is 0, all J and K inputs are equal to 0 and the clock does not
change the state of the counter.

 The first stage, A0, has its J and K equal to 1 if the counter is enabled. The other J and K
inputs are equal to 1 if all previous least significant stages are equal to 1 and the count is
enabled.

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 The chain of AND gates generates the required logic for the J and K inputs in each stage. The
counter can be extended to any number of stages, with each stage having an additional flip‐
flop and an AND gate that gives an output of 1 if all previous flip‐flop outputs are 1.

Fig.16 Four Bit Synchrounous Binary Counter

Binary Up/Down Counter

 A synchronous countdown binary counter goes through the binary states in reverse order,
from 1111 down to 0000 and back to 1111 to repeat the count.

 It is possible to design a countdown counter in the usual manner, but the result is predictable
by inspection of the downward binary count. The bit in the least significant position is
complemented with each pulse.

 A bit in any other position is complemented if all lower significant bits are equal to 0. For
example, the next state after the present state of 0100 is 0011. The least significant bit is
always complemented.

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 The second significant bit is complemented because the first bit is 0. The third significant bit
is complemented because the first two bits are equal to 0. But the fourth bit does not change,
because not all lower significant bits are equal to 0.

 A countdown binary counter can be constructed as shown in Fig.17 below, except that the
inputs to the AND gates must come from the complemented outputs, instead of the normal
outputs, of the previous flip‐flops.

 The two operations can be combined in one circuit to form a counter capable of counting
either up or down. The circuit of an up–down binary counter using T flip‐flops is shown in
Fig.17 It has an up control input and a down control input.

 When the up input is 1, the circuit counts up, since the T inputs receive their signals from the
values of the previous normal outputs of the flip‐flops.

 When the down input is 1 and the up input is 0, the circuit counts down, since the
complemented outputs of the previous flip‐flops are applied to the T inputs. When the up and
down inputs are both 0, the circuit does not change state and remains in the same count.

 When the up and down inputs are both 1, the circuit counts up. This set of conditions ensures
that only one operation is performed at any given time. Note that the up input has priority over
the down input.

Fig 17: Four-bit up-down binary counter

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Ring Counter

 A ring counter is a Shift Register (a cascade connection of flip-flops) with the output of the
last flip flop connected to the input of the first. It is initialized such that only one of the flip
flop output is 1 while the remainder is 0.

 The 1 bit is circulated so the state repeats every n clock cycles if n flip-flops are used. The
"MOD" or "MODULUS" of a counter is the number of unique states. The MOD of the n flip
flop ring counter is n. It can be implemented using D-type flip-flops (or JK-type flip-flops).

Fig 18: Ring Counter

Notes:

· Enable the flips flops by clicking on the RESET (Green) switch. The RESET switch is a

on/off switch (similar to a room light switch)

· Click on CLK (Red) switch and observe the changes in the outputs of the flip flops. The

CLK switch is a momentary switch (similar to a door bell switch - normally off).

· The D flip flop clock has a rising edge CLK input. For example Q1 behaves as follows:

-The D input value just before the CLK rising edge is noted (Q0).

-When CLK rising edge occurs, Q1 is assigned the previously noted D value (Q0).

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 The MOD or number of unique states of this 3 flip flop ring counter is 3.

Johnson Counter

 A Johnson counter is a modified ring counter, where the inverted output from the last flip flop
is connected to the input to the first.

 The register cycles through a sequence of bit-patterns. The MOD of the Johnson counter is 2n
if n flip-flops are used.

 The main advantage of the Johnson counter is that it only needs half the number of flip-flops
compared to the standard ring counter for the same MOD.

 It can be implemented using D-type flip-flops (or JK-type flip-flops).

Fig 19: Johnson Counter

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Notes:

 Enable the flips flops by clicking on the RESET (Green) switch. The RESET switch is a
on/off switch (similar to a room light switch)

 Click on CLK (Red) switch and observe the changes in the outputs of the flip flops. The
 CLK switch is a momentary switch (similar to a door bell switch - normally off).
o The D flip flop clock has a rising edge CLK input. For example Q1 behaves as
follows:
 The D input value just before the CLK rising edge is noted (Q0).
 When CLK rising edge occurs, Q1 is assigned the previously noted D value (Q0).

The MOD or number of unique states of this 3 flip flop Johnson counter is 6.

REGISTER:

 A clocked sequential circuit consists of a group of flip‐flops and combinational gates. The
flip‐flops are essential because, in their absence, the circuit reduces to a purely combinational
circuit (provided that there is no feedback among the gates).

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 A circuit with flip‐flops is considered a sequential circuit even in the absence of
combinational gates. Circuits that include flip‐flops are usually classified by the function they
perform rather than by the name of the sequential circuit. Two such circuits are registers and
counters.

 A register is a group of flip‐flops, each one of which shares a common clock and is capable of
storing one bit of information. An n ‐bit register consists of a group of n flip‐flops capable of
storing n bits of binary information.

 In addition to the flip‐flops, a register may have combinational gates that perform certain data‐
processing tasks. In its broadest definition, a register consists of a group of flip‐flops together
with gates that affect their operation.

 The flip‐flops hold the binary information, and the gates determine how the information is
transferred into the register.

 A counter is essentially a register that goes through a predetermined sequence of binary states.
The gates in the counter are connected in such a way as to produce the prescribed sequence of
states.

 Although counters are a special type of register, it is common to differentiate them by giving
them a different name.

 Various types of registers are available commercially. The simplest register is one that
consists of only flip‐flops, without any gates.

 A register constructed with four D ‐type flip‐flops to form a four‐bit data storage register is
shown in figure below.

 The common clock input triggers all flip‐flops on the positive edge of each pulse, and the
binary data available at the four inputs are transferred into the register.

 The value of ( I 3 , I 2 , I 1 , I 0 ) immediately before the clock edge determines the value of (
A 3 , A 2 , A 1 , A 0 ) after the clock edge.

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 The four outputs can be sampled at any time to obtain the binary information stored in the
register.

 The input Clear_b goes to the active‐low R (reset) input of all four flip‐flops. When this input
goes to 0, all flip‐flops are reset asynchronously.

 The Clear_b input is useful for clearing the register to all 0’s prior to its clocked operation.
The R inputs must be maintained at logic 1 (i.e., de-asserted) during normal clocked
operation.

 Note that, depending on the flip‐flop, either Clear, Clear_b, reset, or reset_b can be used to
indicate the transfer of the register to an all 0’s state.

SHIFT REGISTERS:

 A register capable of shifting the binary information held in each cell to its neighboring cell,
in a selected direction, is called a shift register.

 The logical configuration of a shift register consists of a chain of flip‐flops in cascade, with
the output of one flip‐flop connected to the input of the next flip‐flop.

 All flip‐flops receive common clock pulses, which activate the shift of data from one stage to
the next. The simplest possible shift register is one that uses only flip‐flops, as shown in
Fig.20

 The output of a given flip‐flop is connected to the D input of the flip‐flop at its right. This
shift register is unidirectional (left‐to‐right).

 Each clock pulse shifts the contents of the register one bit position to the right. The
configuration does not support a left shift.

 The serial input determines what goes into the leftmost flip‐flop during the shift. The serial
output is taken from the output of the rightmost flip‐flop.

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 Fig 20: 4 –Bit Register

Fig 21: Four bit Shift register

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 Sometimes it is necessary to control the shift so that it occurs only with certain pulses, but not
with others. As with the data register discussed in the previous section, the clock’s signal can
be suppressed by gating the clock signal to prevent the register from shifting.

 A preferred alternative in high speed circuits is to suppress the clock action, rather than gate
the clock signal, by leaving the clock path unchanged, but recirculating the output of each
register cell back through a two‐channel mux whose output is connected to the input of the
cell.

 When the clock action is not suppressed, the other channel of the mux provides a data path to
the cell.

 Shift registers have found considerable application in arithmatic operations. Since, moving a
binary number one bit to the left is equivalent to multiplying the number by 2 and moving the
number one bit position to the right amounts to dividing the number by 2.

 Thus, multiplications and divisions can be accomplished by shifting data bits. Shift registers
find considerable application in generating a sequence of control pulses.

Fig 22: Data Transmission in Shift Register

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Bidirectional Shift Registers (Universal Shift Register)

 The registers discussed so far involved only right shift operations. Each right shift operation
has the effect of successively dividing the binary number by two.

 If the operation is reversed (left shift), this has the effect of multiplying the number by two.
With suitable gating arrangement a serial shift register can perform both operations.

A bi-directional, or reversible shift register is one in which the data can be shift either left or
right. A four-bit bi-directional shift register using D-flip-flops is shown in Fig 23.

Here a set of NAND gates are configured as OR gates to select data inputs from the right or left
adjacent bistables, as selected by the LEFT_/RIGHT control line.

Fig 23: 4 Bit Universal Shift Register

APPLICATIONS OF SHIFT REGISTERS

Shift registers can be found in many applications. Here is a list of a few.

 To Produce Time Delay

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