electronics

Article
Article
An
An Ultra-Low Quiescent Current
Ultra-Low Quiescent Current Under-Voltage
Under-Voltage
Lockout
Lockout Circuit
Circuit for
for aa High-Voltage Gate Driver
High-Voltage Gate Driver IC
IC
Kunhee Cho 1,2
Kunhee Cho 1,2
1
1 School of Electronics Engineering, Kyungpook National University, Daegu 41566, Korea;
School of Electronics Engineering, Kyungpook National University, Daegu 41566, Korea; kunhee@knu.ac.kr
2 kunhee@knu.ac.kr
School of Electronic and Electrical Engineering, Kyungpook National University, Daegu 41566, Korea
2 School of Electronic and Electrical Engineering, Kyungpook National University, Daegu 41566, Korea




Received: 28
28 September
September 2020;
2020; Accepted:
Accepted: 19
19October
October 2020;
2020; Published:
Published: 20
20October
October2020
2020


ultra-low quiescent
Abstract: An ultra-low quiescent current
current under-voltage
under-voltage lockout
lockout (UVLO)
(UVLO) circuit
circuit for a high-voltage
gate driver integrated
gate integrated circuit (HVIC) is described for application in portable devices. The The UVLO
circuit consumes the static current in the high-side circuitry and the resistive divider used to detect
Hence, aa supply-voltage
the supply-voltage was the major consumer of power in the circuit. Hence, supply-voltage sensor
sensor
based
based on a diode-connected metal–oxide–semiconductor field-effect transistor (MOSFET) with a
metal–oxide–semiconductor field-effect transistor (MOSFET) with
voltage limiter design is proposed to ensure
voltage ensure low
low power
power consumption. Unlike the conventional
consumption. Unlike
UVLO design,
UVLO design, where
where a resistive divider
divider is used, the proposed structure dissipates the negligible
current at a low supply-voltage and significantly reduces the static current at the nominal and high
supply-voltage. The
supply-voltage. The high-side
high-side quiescent
quiescent current
current using
using the
the proposed
proposed design
design and
and the conventional
designs at various supply-voltage
designs supply-voltage levels
levels are analyzed. InIn the
the proposed
proposed structure,
structure, the
the size
size of
of the
the
voltage sensor is considerably smaller when compared with those in conventional designs.designs.

high-voltage gate
Keywords: high-voltage gate driver;
driver; HVIC;
HVIC; supply-voltage
supply-voltage sensing;
sensing; under-voltage
under-voltage lockout
lockout circuit;
circuit;
UVLO; voltage limiter

1. Introduction
1. Introduction
The high-voltage
The high-voltage gategate driver
driver integrated
integrated circuits
circuits (HVICs)
(HVICs) are
are gaining
gaining popularity
popularity because
because ofof the
the
fast-growing demand for portable home appliances and tablet computers. Portable
fast-growing demand for portable home appliances and tablet computers. Portable devices are devices are powered
by batteries.
powered The boostThe
by batteries. converter generatesgenerates
boost converter a high-voltage signal from
a high-voltage thesefrom
signal batteries
thesesuch as signals
batteries such
with voltages of 50–200 V (Figure 1). An HVIC is used to switch high-voltage signals and
as signals with voltages of 50–200 V (Figure 1). An HVIC is used to switch high-voltage signals and drive the coil
or specific load conditions [1–4]. In such applications, the driver spends majority of the time
drive the coil or specific load conditions [1–4]. In such applications, the driver spends majority of the in the
sleep in
time mode
the and
sleepwakes
modeupandoccasionally
wakes upfor switching operations.
occasionally for switchingTheoperations.
average powerThe consumption
average power of
the HVICs is determined based on the sleep mode operation, which should consume
consumption of the HVICs is determined based on the sleep mode operation, which should consume very low power
to achieve
very long battery
low power lifetimes.
to achieve long battery lifetimes.

VDRV (50-200V)
VDD (10-25V) RBOOT DBOOT 50-200V
Boost converter

HVIC
CBOOT
MCU CVDD VDD VB
Control SD HO
PWM IC
IN VS

DT LO
Battery RDT
VSS COM
0V

Figure 1. System block diagram of the high-voltage gate driver.

Electronics 2020, 9, x; doi: FOR PEER REVIEW www.mdpi.com/journal/electronics
Electronics 2020, 9, 1729; doi:10.3390/electronics9101729 www.mdpi.com/journal/electronics
Electronics 2020, 9, x FOR PEER REVIEW 2 of 9
Electronics 2020, 9, 1729 2 of 9

Figure 1. System block diagram of the high-voltage gate driver.

The HVIC consists of high-side circuitry, low-side circuitry, and a high-voltage level shifter
The HVIC consists of high-side circuitry, low-side circuitry, and a high-voltage level shifter
(Figure 2a). To reduce the power consumption of the HVICs, a shut-down (SD) pin is added to
(Figure 2a). To reduce the power consumption of the HVICs, a shut-down (SD) pin is added to
indicate the sleep mode of an HVIC. Although the SD signal can reduce the power consumption of the
indicate the sleep mode of an HVIC. Although the SD signal can reduce the power consumption of
low-side circuitry and high-voltage level shifter [4–7], the power consumption of the high-side circuitry
the low-side circuitry and high-voltage level shifter [4–7], the power consumption of the high-side
cannot be decreased because the high-side region is isolated from the low-side region. Furthermore,
circuitry cannot be decreased because the high-side region is isolated from the low-side region.
an additional high-voltage level shifter is required to send the SD signal to the high-side region,
Furthermore, an additional high-voltage level shifter is required to send the SD signal to the high-
which is undesirable from the cost perspective.
side region, which is undesirable from the cost perspective.

Low-side (LS)
High-side (HS) Static current
HV LDMOS for HV level shifter
VB
HS
SET UVLO
SHORT-PULSE

DRIVER
CANCELLER
GENERATOR
HO

NOISE
INHS S
IN R
Q

SCHMITT
TRIGGER INPUT RESET VS
SHOOT
THROUGH VDD
PREVENTION
VDD
DEAD-TIME LS
DT UVLO

DRIVER
GENERATOR
INLS
VSS/COM
LO
VSS DELAY
LEVEL SHIFT

SHUTDOWN
SD LOGIC COM

(a)
Supply-voltage Reference
Power-on-reset Current bias sensor Comparator voltage
VB

R1
UVLO

R2

RS R3
VS
(b)
Figure2.
Figure 2. High-voltage
High-voltage gate
gate driver.
driver. (a)
(a) Full
Full block
block diagram.
diagram. (b)
(b) Conventional
Conventional high-side
high-side under-voltage
under-voltage
lockoutcircuit.
lockout circuit.

The
Theunder-voltage
under-voltagelockoutlockout (UVLO)
(UVLO) protection
protection is anis essential part part
an essential of theofHVIC to disable
the HVIC the driver
to disable the
at low supply-voltage
driver at low supply-voltageand protect
and the device
protect thefrom
devicedamage
from [8–11].
damageThe UVLO
[8–11]. Thecircuits
UVLOare required
circuits are
for the low-side
required for the and high-side
low-side region separately
and high-side since the since
region separately supply-voltages of both sides
the supply-voltages are sides
of both isolated
are
from each
isolated other.
from eachAlthough a low-side
other. Although UVLO UVLO
a low-side can be can fully beturned off byoff
fully turned thebySD signal,
the a high-side
SD signal, a high-
UVLO still consumes
side UVLO the quiescent
still consumes currentcurrent
the quiescent which iswhich
a majority of the quiescent
is a majority current incurrent
of the quiescent the high-side
in the
region [10,11].
high-side regionTherefore, minimizing
[10,11]. Therefore, the powerthe
minimizing consumption
power consumptionof the UVLOof theinUVLO
the high-side region
in the high-side
is an important
region approach
is an important to improve
approach the battery
to improve the lifetime. Figure 2b
battery lifetime. shows
Figure 2bthe conventional
shows UVLO
the conventional
structure. The power-on-reset
UVLO structure. (POR) circuit
The power-on-reset (POR) can be reconfigured
circuit as a coarseasUVLO
can be reconfigured to reduce
a coarse UVLOthe power
to reduce
consumption of the UVLOof[10].
the power consumption theThe
UVLO supply-voltage sensor is disconnected
[10]. The supply-voltage sensor isfrom the supply-voltage
disconnected from the
when the outputwhen
supply-voltage of thethe
POR circuit
output is high.
of the POR Thus,
circuitthe static Thus,
is high. current theatstatic
a lowcurrent
supply-voltage can be
at a low supply-
eliminated
voltage canwhile dissipating
be eliminated the same
while currentthe
dissipating at asame
nominal supply-voltage.
current The power consumption
at a nominal supply-voltage. The power of
the UVLO can also
consumption of the beUVLO
reduced canusing
alsoa be
slope-based POR circuit
reduced using [11]. Although
a slope-based the current
POR circuit consumption
[11]. Although the
can be reduced
current by removing
consumption the staticby
can be reduced current in the
removing POR
the circuit,
static currentonly
in athe
minor
PORimprovement
circuit, only acan be
minor
observed because the POR circuit is not a major factor associated with the UVLO power consumption.
Electronics 2020, 9, 1729 3 of 9

In this paper, a low quiescent current UVLO circuit is described that can reduce the power
consumption of the HVIC in the sleep mode and enhance the battery lifetime. The proposed
supply-voltage sensor dissipates the negligible current at a low supply-voltage and significantly
reduces the static current at the nominal and high supply-voltage. In addition, the size of the UVLO can
be considerably reduced by preventing the resistive divider from detecting the supply-voltage level.
This paper is organized as follows. Section 2 describes the architecture of HVIC. Section 3
introduces the proposed low-quiescent current UVLO structure. Section 4 describes the simulation
results and the conclusion follows in Section 5.

2. High-Voltage Gate Driver IC

2.1. Architecture
Figure 2a shows the full block diagram of a half-bridge type HVIC comprising a high-side and
low-side gate driver. The input signal is received through the Schmitt trigger block, and the dead-time
generator generates input signals for both high-side and low-side drivers with the dead-time to prevent
shoot-through current between VB and COM in the output stage [4,12]. A short-pulse generator is used
to drive the high-voltage laterally diffused MOSFET (LDMOS) in the high-voltage level shifter to reduce
the power consumption at the level shifter. The short-pulse generator generates the SET and RESET
short pulses synchronized at the rising and falling edges of the INHS signal, respectively. The input
signal can be restored from these short pulses using the SR latch in the high-side region [13–19].
However, the parasitic capacitance of the LDMOS and dV/dt arises from VB rising, which will introduce
common-mode noise in the level shifter. This noise may lead the incorrect pulses into the SR latch.
Therefore, a noise canceller can be employed to remove the common-mode noise during transitions [14].
In addition, the low-side and high-side circuitries contain UVLO protection circuits to perform the
switching operation at a sufficiently high supply-voltage.

2.2. Under-Voltage Lockout Circuit

In case of the high-side circuitry, the static current only flows through the high-side UVLO
protection circuit. Figure 2b describes the circuit diagram of the conventional high-side UVLO [10,11].
The reference current independent of the supply-voltage (VBS ) is generated by the current bias
circuit, and the POR circuit generates the reset pulse to prevent any latch-on state during power-up.
The comparator compares the VBS level with the reference voltage to ensure that the VBS level is greater
than the minimum operating voltage. The VBS level is detected using the resistive divider and the
Zener diode generates the reference voltage. The hysteresis can be added by controlling the ratio of the
resistive divider. When the supply-voltage is rising, R1 and R2 sense the supply-voltage, while R3 is
added if the supply-voltage is falling. Hence, the positive and negative UVLO levels can be determined
as follows:
R + R2
VUVLO+ = VREF 1 (1)
R2
R1 + R2 + R3
VUVLO− = VREF (2)
R2 + R3
where VREF is the reference voltage generated by the Zener diode.
In the conventional UVLO circuit, the resistive divider always draws the static current, which is
proportional to the supply-voltage. Furthermore, it is the dominant quiescent current source, especially
at a high supply-voltage. The current can be reduced by increasing the size of the resistor. However,
this requires a large area and increases the cost.
Electronics
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3. Low-Quiescent Current High-Side UVLO

3. Low-Quiescent Current High-Side UVLO
An active resistor using the diode-connected MOSFET (MOS-diode) can be employed for
An activea resistor
implementing using the
supply-voltage diode-connected
sensor MOSFET
to reduce the current (MOS-diode)
at the can be
resistive divider employed
(Figure for
3a). The
implementing a supply-voltage sensor to reduce
resistance of the MOS-diode can be represented as follows: the current at the resistive divider (Figure 3a).
The resistance of the MOS-diode can be represented as follows:
1 r 1 𝐿
𝑅𝑑𝑖𝑜𝑑𝑒 =1 = √ 1 L 𝐼𝐷 (3)
Rdiode = 𝑔𝑚 = 2𝑘′ 𝑊I
D (3)
gm 2k0 W
where k′ is the process transconductance parameter. The resistance of the MOS-diode is controlled by
where k0 isthe
adjusting the process
aspect transconductance parameter.
ratio (W/L). Because The resistance
the resistance of theof the MOS-diode is
smaller-sized controlled by
MOS-diode is
adjusting the aspect ratio (W/L). Because the resistance of the smaller-sized MOS-diode
considerably greater than that of the general-purpose poly or diffusion resistor, exploiting is considerably
the MOS-
greatercan
diode than that of
reduce the the
both general-purpose poly or diffusion
current consumption and sizeresistor, exploiting
associated with thethesupply-voltage
MOS-diode cansensor.
reduce
both the current consumption and size associated with the supply-voltage sensor.

VB VB VB

MP1 MP1
R1 VSEN VSEN
VSEN MP2 MP2

R2 MP3 VREF MN
MP3
MP4
MP4
R3
MP5 MP5

VS VS VS

(a) (b) (c)

Figure
Figure 3. Supply-voltage
Supply-voltagesensor.
sensor.(a)(a)Resistive
Resistive divider.
divider. (b)(b) MOS-diode
MOS-diode divider.
divider. (c) Proposed
(c) Proposed MOS-
MOS-diode
divider
diode with awith
divider voltage limiter.limiter.
a voltage

Figure 3b
Figure 3b shows
showsthe thesupply-voltage
supply-voltage sensor
sensorbasedbasedon on
the the
MOS-diode.
MOS-diode. By assuming
By assuming that same sized
that same
MOSFETs
sized are used
MOSFETs aretoused
implement the MOS-diode,
to implement the MOS-diode,the supply-voltage (VBS ) can
the supply-voltage (Vbe
BS) expressed as follows:
can be expressed as
follows:
VBS = nVGS = n(VT + Vov ) (4)
𝑉𝐵𝑆 = 𝑛𝑉𝐺𝑆 = 𝑛(𝑉𝑇 + 𝑉𝑜𝑣 ) (4)
where n is the number of stacked MOS-diode, and V and V are the threshold and overdrive
where n is the number of stacked MOS-diode, and VT andT VOV areOV the threshold and overdrive voltage
voltage of the MOSFET, respectively. Therefore, the current at the MOS-diode divider can be expressed
of the MOSFET, respectively. Therefore, the current at the MOS-diode divider can be expressed as
as follows:
follows: 2
k0 W VBS

ID = − VT 2 (5)
𝑘′𝑊 n
2L 𝑉𝐵𝑆
𝐼𝐷 = ( − 𝑉𝑇 ) (5)
Unlike the typical resistive divider, the 2𝐿 current 𝑛 consumption of the MOS-diode divider is
proportional to the
Unlike the square
typical of supply-voltage.
resistive divider, theHence, current theconsumption
static current ofcanthe
be significantly
MOS-diode reduced
divider is at
a low supply-voltage.
proportional to the square However, this can alsoHence,
of supply-voltage. result in theconsiderably
static current high
cancurrent consumption
be significantly at a
reduced
high supply-voltage.
at a low supply-voltage. However, this can also result in considerably high current consumption at a
To reduce the current of the supply-voltage sensor at a high supply-voltage, a MOS-diode divider
high supply-voltage.
withTo a voltage
reduce limiter is proposed
the current (Figure 3c). Thesensor
of the supply-voltage voltage at limiter
a highissupply-voltage,
implemented by a introducing
MOS-diode
an additional NMOS transistor (M ) observed under one MOS-diode
divider with a voltage limiter is Nproposed (Figure 3c). The voltage limiter is SEN below the V node,
implemented and the
by
gate voltage is connected
introducing an additional NMOS to V . When
REF transistorSEN V is less than
(MN) observed under V REF , Mone is fully turned
N MOS-diode below the Von which isSEN
at
the triode
node, region
and the gateand the proposed
voltage is connected structure
to VREFworks
. When the same
VSEN as the
is less MOS-diode
than VREF, MN isdivider structure.
fully turned on
The resistance of M increases if the supply-voltage
which is at the triodeN region and the proposed structure works the same increases and V decreases. Once
as the MOS-diode divider
GS.MN V SEN
becomes greater
structure. than VREF
The resistance of −MVNSG.MP2
increases + VGS.MN MN enters the saturation
if the ,supply-voltage increases andregion and decreases.
VGS.MN limits the source
Once
VSEN becomes greater than VREF − VSG.MP2 + VGS.MN, MN enters the saturation region and limits the source
Electronics 2020, 9, 1729 5 of 9
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FOR PEER
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REVIEW 55 of
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voltage of
voltage
voltage of MMN N. V
N.. V
GS.MN should
VGS.MN
GS.MN should
should bebe
be higher
higher
higher than
than
than VSG.MP2
V VSG.MP2
SG.MP2 to ensure
to ensure
to ensure thatthat
that MNN can
M can
M limitlimit
can
N limit
the voltage
the voltage when
the voltage
when VSEN
when
V SEN

Vbecomes
SEN becomes
becomes greater
greater than V
greater
than VREF
REF. V
than Even though
REF . though
. Even the supply-voltage
Even though
the supply-voltage
the supply-voltage is increasing,
is increasing, the source
is increasing,
the source voltage
the source
voltage of M
MNNof
voltage
of is
is
Mmaintained
N is maintained
maintained as V
as VSEN as V
SEN − V
− SENGS.MN
VGS.MN , and
− V, GS.MN a
and a, and constant current
a constant
constant current is
current dissipated
is dissipated
is dissipated by
byby the
the supply-voltage
thesupply-voltage sensor.
supply-voltagesensor.
sensor.
Therefore, the
Therefore,
Therefore, the proposed
the proposed structure
proposed structure can
structure can notnot only
not only reduce
only reduce the
reduce the current
the current at
current at aaa low
at low supply-voltage
low supply-voltage but
supply-voltage but also
but also
also
preventhigh
prevent
prevent highcurrent
high currentconsumption
current consumptionat
consumption ataaahigh
at highsupply-voltage.
high supply-voltage.
supply-voltage.
Figure
Figure 4
Figure 44shows shows
showsthe the proposed
proposed
the proposed high-side
high-side
high-side UVLO UVLO
UVLO circuit
circuit using
usingusing
circuit the MOS-diode
the MOS-diode
the MOS-diode divider
dividerdivider with aa
with a voltage
with
voltage The
limiter.
voltage limiter. The hysteresis
hysteresis
limiter. The hysteresis
comparator comparator
is employed
comparator is employed
is employed
to ensure to to ensure
theensure the stable
stable the stable operation
switching switching instead
switching operation
operationof
instead
controllingof controlling
the number
instead of controlling the number
theofnumber
MOS-diodeof MOS-diode
devices in
of MOS-diode devices in the
the supply-voltage
devices supply-voltage sensor.
sensor. sensor.
in the supply-voltage Thus,
Thus, the
Thus, the
same same
the static
same
static current
current
static current
can becan can be maintained
maintained
be maintained with respect
with respect
with respect to the
the supply-voltage
supply-voltage
to the supply-voltage
to sensorVwhen
sensor when
sensor when V VBS
BS is increased
BS is increased to trigger
is increased to
to
Vtrigger
trigger
UVLO+ V
Vand
UVLO+
UVLO+
and Vdecreased
Vand
BS isV
BS is decreased to trigger
to trigger
BS is decreased to trigger
VUVLO−VVUVLO−
. ..
UVLO−

Voltage
Voltage Reference
Reference
sensor Hysteresis comparator
Hysteresis comparator voltage
sensor voltage
VB
V B
Power-on-reset
Power-on-reset

Current
Currentbias

VREF
VREF
UVLO
UVLO
VREF
VREF
bias

VS
V S

Figure 4.
Figure 4. Proposed high-side
high-side under-voltage
under-voltage lockout
lockout circuit.
circuit.
Figure 4. Proposed
Proposed high-side under-voltage lockout circuit.

4. Simulation
4.
4. Simulation Results
Simulation Results
Results
A
AA proposed
proposed UVLO
proposed UVLOis
UVLO is designed
is designedin
designed in 3.8
in μm25
3.8 µm
3.8 μm 25 V
25 V CMOS
V CMOS devices
CMOS devices to
devices to provide
to providethe
provide theV
the VVBS level up
BS level up to to 25
BS level up to 25 V.
25 V.
V.
Cadence
CadenceSpectre
Cadence Spectretool
Spectre toolisis
tool isused
usedfor
used forthe
for thesimulation.
the simulation.Figure
simulation. Figure
Figure 5 5shows
5 shows
shows the simulated
the
the simulated
simulated current
current
current consumption
consumption
consumption of
different
of types
different typesof voltage
of voltage sensors
sensors in high-side
in high-sideUVLO.UVLO. The total
The resistance
total
of different types of voltage sensors in high-side UVLO. The total resistance of the resistive dividerresistance of the
of resistive
the resistivedivider
divideris
set to to
is set
is set 650
to 650
650kΩkΩkΩ (R=11 100
(R1(R == 100
100kΩ,kΩ,
kΩ,R2R R=2 = 400
400kΩ, kΩ,and
2 = 400 kΩ, and R
andRR 3 33==
=150
150kΩ),
150 kΩ), which
kΩ), which is
which is aaa practical
is practical value
practical value obtained
value obtained by
obtained by
by
considering
considering the
the tradeoff
tradeoff between
between the size
the and
size current
and consumption.
current
considering the tradeoff between the size and current consumption. A MOS-diode divider isconsumption. A MOS-diodeA divider
MOS-diode is designed
divider is
to dissipate
designed to1 at
dissipate
µA a supply-voltage
1 µ A at a of 8 V
supply-voltagethat is sufficiently
of 8 V that fast
is to detect
sufficiently
designed to dissipate 1 µ A at a supply-voltage of 8 V that is sufficiently fast to detect the supply- the supply-voltage
fast to detect the through
supply-
the MOS-diode
voltage
voltage through
through structure.
the Although structure.
the MOS-diode
MOS-diode the currentAlthough
structure. of the MOS-diode
Although the current
the divider
current of is
of the
the considerably
MOS-diode
MOS-diode smaller
divider
divider thanis
is
that of the
considerably resistive
smaller divider,
than especially
that of the at low
resistive and nominal
divider, supply-voltages,
especially at low
considerably smaller than that of the resistive divider, especially at low and nominal supply-voltages, and high
nominalcurrent is consumed
supply-voltages,
high
at
high current
a high
current is consumed
consumed because
supply-voltage
is at aa high
at highthe supply-voltage because the
current is proportional
supply-voltage because theto current
the square
current is proportional
is proportional to the
the square
of the supply-voltage.
to square
of the
However, supply-voltage.
even at a high However, even
supply-voltage, at a high
the supply-voltage,
MOS-diode divider the
of the supply-voltage. However, even at a high supply-voltage, the MOS-diode divider with a voltage MOS-diode
with a voltage divider
limiter with
can a voltage
maintain
limiter
very
limiterlow can
can maintain
current very low
consumption
maintain very low current
current consumption
becauseconsumption because
the current is because
limited whenthe current
the current
VSEN is isgreater
is limitedthan
limited when
when VSEN
VREF
V SEN isVgreater
−is greater
SG.MP2
+than
than VREF
VGS.MN
V REF. − VSG.MP2 + VGS.MN.
− VSG.MP2 + VGS.MN.

Resistive divider
divider (conventional)
(conventional) 41.7 µA
41.7 µA
Resistive
MOS-diode divider
MOS-diode divider 36.8 µA
36.8 µA
MOS-diode divider
MOS-diode divider with
with voltage
voltage
limiter (proposed)
limiter (proposed)

96.3%
96.3%
saving
saving
16.7 µA
16.7 µA

10 µA
10 µA
90.8%
90.8%
saving
saving
~100%
~100% 2.46 µA
µA 1.56 µA
µA
saving 2.46 1.56
saving
1.54 µA
1.54 µA
0.1 nA
0.1 nA

Figure
Figure 5. Current
5. Current consumption
consumption of
Current consumption of different
different types
types of
of supply-voltage
supply-voltagesensors.
sensors.
Figure 5. of different types of supply-voltage sensors.
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Electronics 2020,9,9,1729
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The size of the resistive divider is 5136 µ m2 (L = 44.9 µ m, W = 4.4 µ m, and mul = 26) for a given
technology. The MOS-diode divider which uses 3.8 µ m 25 V CMOS devices can be implemented with
The size of2 the resistive divider is 5136 µ m2 (L = 44.9 µ m, W = 4.4 µ m, and mul = 26) for a given
a sizeThe
of 170
sizeµThe
technology.
m the
of (L ×resistive
W), which is 30istimes
MOS-diodedivider 5136 smaller
divider which
2
µm 3.8
uses =µ m
(L than44.9
25µm, W = 4.4
the resistive
V CMOS
divider.
µm, and
devices can mul = 26) for a given
be implemented with
Figure 6The
technology. shows the
MOS-diode transient response
divider which of the
uses proposed
3.8 µm 25 V UVLO
CMOS circuit
devicesat different
can be temperatures.
implemented with
a size of 170 µ m (L × W), which is 30 times smaller than the resistive divider.
2
The VUVLO+
a size /VUVLO−
of 170 2 levels
(L ×thearewhich
W), 8.38/7.82,
308.64/8.08, and 9.03/8.43 V at −40,divider.
25, and 125 °C, respectively.
Figure 6µmshows transientisresponse
times smaller than the UVLO
of the proposed resistivecircuit at different temperatures.
The temperature variation is mainly caused ofbythe
theproposed
referenceUVLO
voltagecircuit
level variation from the Zener
The Figure
VUVLO+/V 6UVLO−
shows the transient
levels response
are 8.38/7.82, 8.64/8.08, and 9.03/8.43 V at −40, 25,atanddifferent
125 °C,temperatures.
respectively.
diode.
The V UVLO+ /V UVLO− levels are 8.38/7.82, 8.64/8.08, and 9.03/8.43 V at −40, 25, and
The temperature variation is mainly caused by the reference voltage level variation from the Zener 125 ◦ C, respectively.

The temperature variation is mainly caused by the reference voltage level variation from the Zener diode.
diode.
VBS
UVLO at -40°C
UVLO
VBS at 25°C
UVLO
UVLOatat125°CC
-40°
UVLO at 25°C
9.03 V UVLO at 125°C
8.64 V 8.43 V
8.08 V
8.38 V
9.03 V 7.82 V
8.64 V 8.43 V
8.08 V
8.38 V
7.82 V

Figure 6. Proposed under-voltage lockout (UVLO) operation at different temperatures.

Figure 6. Proposed
Figure 6. Proposed under-voltage
under-voltage lockout
lockout (UVLO)
(UVLO) operation
operation at
at different
differenttemperatures.
temperatures.
Figures 7 and 8 show the Monte-Carlo simulation results of the quiescent current consumption
of theFigures
conventional
7 and 8high-side
show theUVLO and proposed
Monte-Carlo high-side
simulation resultsUVLO, respectively.
of the quiescent The conventional
current consumption
Figures 7 and 8 show the Monte-Carlo simulation results of the quiescent current consumption
UVLO design consumes
of the conventional 13.1 and
high-side UVLO 37.3and
µ Aproposed
at VBS of high-side
5 and 20 UVLO,
V, whilerespectively.
the proposed TheUVLO design
conventional
of the conventional high-side UVLO and proposed high-side UVLO, respectively. The conventional
consumes
UVLO design2.6 and 6.1 µ A at
consumes VBSand
13.1 of 537.3
and µA
20 V,
at respectively.
VBS of 5 andThe
20 V,quiescent current
while the can be
proposed reduced
UVLO by
design
UVLO design consumes 13.1 and 37.3 µ A at VBS of 5 and 20 V, while the proposed UVLO design
80.2% and 83.6%
consumes 2.6 andat6.1
VBSµA
of 5atand
V 20 ofV, respectively,
5 and by employing
20 V, respectively. the proposed
The quiescent design.
current can be reduced by
consumes 2.6 and 6.1 µ A at VBS BS of 5 and 20 V, respectively. The quiescent current can be reduced by
80.2% and 83.6% at VBS of 5 and 20 V, respectively, by employing the proposed design.
80.2% and 83.6% at VBS of 5 and 20 V, respectively, by employing the proposed design.
35 35
300 samples 300 samples
3035 Mean : 13.1μA 3035 Mean : 37.3μA
density

density

Std Dev : 0.8μA Std Dev : 2.4μA

300 samples 300 samples
2530 Mean : 13.1μA 2530 Mean : 37.3μA
density

density

Std Dev : 0.8μA Std Dev : 2.4μA

2025 2025
Probability

Probability

1520 1520
Probability

Probability

1015 1015
510 510
05 05
8 10 12 14 16 18 25 30 35 40 45 50
0 IQBS (μA) 0 IQBS (μA)
8 10 12 14 16 18 25 30 35 40 45 50
IQBS (μA) IQBS (μA)
(a) (b)
Figure
Figure7.7.Monte-Carlo simulation
(a)
Monte-Carlo simulationresults of the
results of quiescent current
the quiescent consumption
current of conventional
(b)
consumption high-
of conventional
side UVLOUVLO
high-side based based
on theon
resistive divider
the resistive (Figure
divider 2b). (a)
(Figure VBS(a)
2b). = 5VV.
BS =
(b)5VV.
BS =
(b)20
V V.
BS = 20 V.
Figure 7. Monte-Carlo simulation results of the quiescent current consumption of conventional high-
side UVLO based on the resistive divider (Figure 2b). (a) VBS = 5 V. (b) VBS = 20 V.
Electronics 2020, 9, x FOR PEER REVIEW 7 of 9
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Electronics 2020, 9,
9, 1729
x FOR PEER REVIEW 7 of 99
7 of

35
35 35
35
300 samples 300 samples
300 samples 300 samples
30
30
Mean : 2.6μA 30
30
Mean : 6.1μA
density
Mean : 2.6μA Mean : 6.1μA

density
Std Dev : 0.2μA Std Dev : 0.6μA
Probabilitydensity

Probabilitydensity
Std Dev : 0.2μA Std Dev : 0.6μA
25
25 25
25
20 20
20
20

Probability
Probability

15 15
15
15
10 10
10
10
55 55
001.5 00
1.5 22 2.5
2.5 33 3.5
3.5 44 44 55 66 77 88 99
IIQBS (μA)
QBS (μA) IIQBS (μA)
QBS (μA)

(a)
(a) (b)
(b)
Figure 8. Monte-Carlo simulation
simulation results of the quiescentcurrent
current consumption
consumption of of proposed
proposed high-side
high-side
Figure 8. Monte-Carlo
Monte-Carlo simulation results of the quiescent
quiescent
UVLO based onon the
the MOS-diode
MOS-diode divider
divider with
with aa voltage
voltage limiter
limiter (Figure
(Figure 4).
4). (a)
(a) VVBS
BS = 5 V. (b) VBS = 20 V.
UVLO based on the MOS-diode divider with a voltage limiter (Figure 4). (a) VBS = = 5 V.
V. (b)
(b) V
VBS =20
BS = 20V.
V.

Figure 99 shows
Figure shows the
the quiescent
quiescent current
current of
of the
the high-side
high-side UVLO
UVLO circuits
circuits at
at different
different supply-voltage
supply-voltage
levels for
levels for different
different types
different types of
types ofsupply-voltage
of supply-voltage sensors.
supply-voltage sensors. The
sensors. The quiescent
The quiescent current
quiescent current consumption
consumption can
consumption can bebe
significantly reduced at low as well as high supply-voltages because of the quiescent
significantly reduced at low as well as high supply-voltages because of the quiescent current of the current of the
supply-voltagesensor
supply-voltage sensoris is significantly
significantlyreduced
reducedoveroverthe
the entire
entire supply-voltage
supply-voltagerange
rangebyby employing
employing the
the
proposeddesign.
proposed design.

50
50
45
45 IQBS (w/ R-div)
IQBS (w/ R-div)
40
40
IQBS (w/ MOS-div)
IQBS (w/ MOS-div)
IQBS (w/ MOS-div + V-lim, proposed)
35
35 IQBS (w/ MOS-div + V-lim, proposed)
(µA)

30
IQBS(µA)

30
25
25 85.1%
85.1%
IQBS

saving
20
20 saving

15
15 70.5%
70.5%
saving
10
10 saving
80.2%
80.2%
55
saving
saving

00
00 55 10
10 15
15 20
20 25
25
VVBS (V)
BS (V)

Figure 9.
Figure 9. Quiescent
9. Quiescent current
Quiescent current consumption
current consumption of
consumption of high-side
of high-side UVLO
high-side UVLO circuits.
UVLO circuits.
circuits.
Figure

Figure
Figure10 10shows
showsthe thequiescent
quiescent current
currentof the proposed
of the
the proposed structure by varying
structure the temperature
by varying
varying the temperature from
temperature
Figure ◦ 10 shows the quiescent current of proposed structure by the
−40
fromto−40
125toC125
−40 at V°C of 5BSand
BS at of 5520and
V. Although the quiescent currentcurrent
of the proposed supply-voltage
from to 125 °C at VVBS of and 20 V.
20 V. Although
Although the quiescent
the quiescent current of of the
the proposed
proposed supply-
supply-
sensor is increased
voltage sensor
sensor is when
is increased the
increased whentemperature
when the rises,
the temperature the increased
temperature rises,rises, the amount
the increased is sufficiently
increased amount
amount is small compared
is sufficiently
sufficiently small
small
voltage
to total quiescent
compared to totalcurrent.
quiescentMoreover,
current. the temperature
Moreover, the coefficient ofcoefficient
temperature the bias current
of the isbias
second order
current is
compared to total quiescent current. Moreover, the temperature coefficient of the bias current is
compensated
second order by applying the
compensated by appropriate
applying the temperature
appropriate coefficient
temperature at coefficient
RS in the current
at R S in bias
the circuit
current
second order compensated by applying the appropriate temperature coefficient at RS in the current
(Figure 2b). The
bias circuit
circuit temperature
(Figure Thecoefficient
2b). The temperature of Rcoefficient
S can be adjusted by combining
of RRSS can
can be adjusted
adjusted diffusion resistors diffusion
by combining
combining and poly
bias (Figure 2b). temperature coefficient of be by diffusion
resistors
resistors that
andhavepolyaresistors
positive temperature
resistors have aa coefficient
that have and a complementary
positive temperature
temperature coefficienttemperature coefficient,
and aa complementary
complementary
resistors and poly that positive coefficient and
respectively.
temperature Hence the quiescent
coefficient, respectively.current
Henceof the
the proposed
quiescent structure
current shows
of the an almoststructure
proposed constant shows
value
temperature coefficient, respectively. Hence the quiescent current of the proposed structure shows
over the
an almost temperature
almost constant
constant value variation.
value over
over thethe temperature
temperature variation.
variation.
an
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Electronics 2020, 9, x FOR PEER REVIEW 8 of 9

10
VBS = 5V
8
VBS = 20V

IQBS (µA)
4

0
-40 -20 0 20 40 60 80 100 120
Temperature (°
C)
Figure 10. Quiescent current consumption of proposed high-side UVLO circuit at temperature variation.
Figure 10. Quiescent current consumption of proposed high-side UVLO circuit at temperature
variation.
The quiescent current of the high-side circuitry without UVLO consumes approximately 1 nA [10],
which is negligible when compared with that consumed by the circuitry with UVLO. Therefore,
The quiescent current of the high-side circuitry without UVLO consumes approximately 1 nA
the quiescent current of high-side UVLO can be considered as the quiescent current of high-side
[10], which is negligible when compared with that consumed by the circuitry with UVLO. Therefore,
circuitry. Table 1 summarizes the quiescent current of proposed structure and provides a comparison
the quiescent current of high-side UVLO can be considered as the quiescent current of high-side
with prior works that contain the high-side UVLO circuit. A considerably low quiescent current
circuitry. Table 1 summarizes the quiescent current of proposed structure and provides a comparison
consumption can be achieved using the proposed structure by preventing the resistive divider from
with prior works that contain the high-side UVLO circuit. A considerably low quiescent current
detecting the supply-voltage in the high-side UVLO circuit.
consumption can be achieved using the proposed structure by preventing the resistive divider from
detecting the supply-voltage in the high-side UVLO circuit.
Table 1. Performance comparison of high-side quiescent current.

Table 1. Performance comparison of high-side quiescentThis

current.
Work
VBS [11] [5] [6] [7]
ConventionalThis Work
Proposed MOS-Diode
Resistive Divider Divider with Voltage-Limiter
VBS [11] [5] [6] [7] Conventional Proposed MOS-Diode Divider
5V 20 µA N/A N/A N/A 13 µA
Resistive Divider 2.6 µA
with Voltage-Limiter
20 V 30 µA 50 µA 80 µA 35 µA 37 µA 6.1 µA
5V 20 µ A N/A N/A N/A 13 µ A 2.6 µ A
20 V 30 µ A 50 µ A 80 µ A 35 µ A 37 µ A 6.1 µ A
5. Conclusions
5. Conclusions
An ultra-low quiescent current UVLO for the HVIC is described for portable devices. The proposed
supply-voltage
An ultra-lowsensor based on
quiescent the MOS-diode
current UVLO fordivider withisa voltage
the HVIC describedlimiter consumes
for portable negligible
devices. The
current
proposedat asupply-voltage
low supply-voltage and
sensor significantly
based reduces the
on the MOS-diode static current
divider at the nominal
with a voltage limiter and high
consumes
supply-voltage.
negligible currentTherefore,
at a lowthe quiescent current
supply-voltage and of the proposed
significantly UVLOthe
reduces canstatic
be reduced
currentover the
at the entire
nominal
supply-voltage range compared
and high supply-voltage. to the conventional
Therefore, the quiescentUVLO design,
current of thewhere the resistive
proposed UVLO divider is used.
can be reduced
Furthermore,
over the entirethe proposed structure
supply-voltage range significantly
compared to reduces the sensorUVLO
the conventional size by avoiding
design, thethe
where usage of a
resistive
resistive divider.
divider is used. Furthermore, the proposed structure significantly reduces the sensor size by avoiding
the usage of a resistive divider.
Funding: This work was supported by the National Research Foundation of Korea (NRF), grant funded by the
Korea government (MSIT) (No. 2020R1G1A1100085).
Funding: This work was supported by the National Research Foundation of Korea (NRF), grant funded by the
Acknowledgments: The EDA
Korea government (MSIT) tool
(No. was supported by the IC Design Education Center (IDEC), Korea.
2020R1G1A1100085).
Conflicts of Interest: The
Acknowledgments: The authors
EDA tooldeclare no conflictbyofthe
was supported interest.
IC Design Education Center (IDEC), Korea.

Conflicts of Interest: The authors declare no conflict of interest.

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