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EE-410
FPGA Based System Design
VERILOG PROGRAMMING
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Hardware Description Language
A hardware description language is a computer language
that is used to describe hardware.
Currently, almost all integrated circuits are designed with
using HDL. Two HDLs are widely used
Verilog HDL
VHDL (Very High Speed Integrated Circuit Hardware Description
Language)
Schematic design entry can be replaced by writing HDL
code that CAD tools understand.
CAD tools can verify the HDL codes, and create the
circuits automatically from HDL codes.
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Facts About Verilog
We use Verilog, not VHDL for FPGA programming
Verilog is more popular in industry than VHDL
They offer similar features
History of Verilog
In 1980s, originally developed by Gateway Design Automation.
In 1990, was put in public domain.
In 1995, adopted as an IEEE standard 1364-1995
In 2001, an enhanced version, Verilog 2001
Functions of Verilog
Design entry, like schematic
Simulation and verification of your design
Synthesis
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Verilog Usage
Verilog may be used to model circuits and behaviors at
various levels of abstraction:
Transistor/Switch Level Modeling. LOW LEVEL
Gate Level Modeling.
Data Flow Modeling.
Behavioral or algorithmic Modeling. HIGH LEVEL
For design with FPGA devices, transistor and gate level
modeling is not appropriate.
Register Transfer Level (RTL) is a combination of
behavioral and dataflow Modeling.
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Switch Level Modeling
//Define inverter
module my_not(out, in);
output out;
input in;
// declare power
// and ground
supply1 pwr;
supply0 gnd;
//instantiate nmos
// and pmos switches
pmos (out, pwr, in);
nmos (out, gnd, in);
endmodule
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A Simple Verilog Example
// A simple example comment line
module gate1 (a,b,c); module name
input a,b; port list
port declarations
output c; gate1
and (c,a,b); a
c
endmodule end module b
Modules are the basic building blocks in Verilog.
A logic circuit module, Its ports: inputs and outputs
Begins with module, ends with endmodule
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Gate Level Modeling vs Data Flow Modeling
module eg1 (a,b,c,f);
input a,b,c;
a g
output f; f
wire g,h,i; b
F = AB + B'C
and (g,a,b);
h i
not (h,b);
c
and (i,h,c);
or (f,g,i);
// Data Flow Modeling
endmodule
module ex1 (a,b,c,f);
input a,b,c;
output f;
assign f = (a&b) | (~b&c);
endmodule
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Writing Test Bench /* testbench for ex1 block */
module ex1 (a,b,c,f); module ex1_tb ; print to a console
wire f1;
input a,b,c; reg a1, b1, c1;
output f;
assign f=(a&b)|(!b&c); ex1 my_module(a1, b1, c1, f1);
endmodule initial
begin
Each signal in Verilog belongs $monitor($time," ", a1, b1, c1,
to either a net or a register ," ", f1);
a1 = 1'b0; b1 = 1'b1; c1 = 1'b0;
A net (wire) represents a
physical wire. Its signal value is #5
determined by its driver. a1 = 1'b1; b1 = 1'b1; c1 = 1'b1;
If it is not driven by any driver,
its value is high impedance (Z). #5
A register is like a variable in a1 = 1'b1; b1 = 1'b0; c1 = 1'b1;
programming languages. It keeps
#5
its value until a new value is a1 = 1'b1; b1 = 1'b1; c1 = 1'b1;
assigned to it. #10 $finish;
Unlike registers, nets do not end
have storage capacity. endmodule
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Basic Gates
Verilog supports basic logic gates as predefined primitives.
There are two classes of basic gates: and/or gates and buf/not gates.
And/or gates have one scalar output and multiple scalar inputs
The first terminal in the list of gate terminals is an output and the
other terminals are inputs.
Example 1: Gate Instantiation of And/Or Gates
wire OUT, IN1, IN2;
and a1(OUT, IN1, IN2);
xnor (OUT, IN1, IN2);
// More than two inputs;
// 3 input nand gate
nand (OUT, IN1, IN2, IN3);
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Truth Tables for And/Or Gates
and 0 1 x z or 0 1 x z xor 0 1 x z
0 0 0 0 0 0 0 1 x x 0 0 1 x x
1 0 1 x x 1 1 1 1 1 1 1 0 x x
x 0 x x x x x 1 x x x x x x x
z 0 x x x z x 1 x x z x x x x
nand 0 1 x z nor 0 1 x z xnor 0 1 x z
0 1 1 1 1 0 1 0 x x 0 1 0 x x
1 1 0 x x 1 0 0 0 0 1 0 1 x x
x 1 x x x x x 0 x x x x x x x
z 1 x x x z x 0 x x z x x x X
1=True , 0=False, X=Unknown, Z=High impedance
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Buf/Not Gates
Buf/not gates have one scalar input and one or more scalar outputs
The last terminal in the port list is connected to the input. Other
terminals are connected to the outputs
Basic buf/not gate primitives in verilog are buf not
Buf/not gates with additional
control signal are
bufif1, notif1, bufif0, notif0
buf not
input output input output
0 0 0 1
1 1 1 0
x x x x
z x z x
www.iiu.edu.pk 11 Wednesday, March 25, 2020
Truth Table for bufif/notif Gates
Ctrl Ctrl
The L and H symbols have a bufif1 notif1
0 1 x z 0 1 x z
special meaning. The L symbol
means the output has 0 or z value. 0 z 0 L L 0 z 1 H H
The H symbol means the output in
1 z 1 H H
in
1 z 0 L L
has 1 or z value. x z x x x x z x x x
Any transition to H or L is treated z z x x x z z x x x
as a transition to x.
Ctrl Ctrl
Examples bufif0 notif0
0 1 x z 0 1 x z
//Instantiation of bufif gates.
0 0 z L L 0 1 z H H
bufif1 b1 (out, in, ctrl);
1 1 z H H 1 0 z L L
bufif0 b0 (out, in, ctrl); in in
x x z x x x x z x x
//Instantiation of notif gates
z x z x x z x z x x
notif1 n1 (out, in, ctrl);
notif0 n0 (out, in, ctrl); x={0,1,z} L={0,z} H={1,z}
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