Switched Capacitor Converter

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S.
Ben-Yaakov 2009 [1]
Switched Capacitors Converters
Sam Ben-Yaakov
Power Electronics Laboratory
Department of Electrical and Computer Engineering
Ben-Gurion University of the Negev
P.O. Box 653, Beer-Sheva 84105, ISRAEL
Phone: +972-8-646-1561; Fax: +972-8-647-2949;
Email: sby@ee. bgu.ac.il; Website: www.ee.bgu.ac.il/~pel
APEC09, February 2009
Full set of slides:

http://www.ee.bgu.ac.il/~pel/seminars/APEC09.pdf
Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [2]
OUTLINE
1. Introduction (30min)
Switched capacitors versus switched inductors converters
Charge Pumps and Switched Capacitors converters
Losses in switched capacitors converters – overview
Examples of SCC and charge pump topologies
2. Losses in Hard Switched SCC (50 min)
Target voltages
Equivalent resistance
Efficiency
Inherent power loss
Effect of switch resistances
Equivalent-circuit based average models – New Approach
Regulation
Examples
OUTLINE
3 Losses in Soft Switched SCC - New Results (50 min)
Topologies
Waveforms of resonant networks
Losses in resonant networks
Parasitic
Equivalent-circuit based average models
Regulation
Examples
4 Self-Adjusting Binary SCC (50 min) - New Concept
The concept
The Extended Binary (EXB) numbers representation
Features of the EXB
Translating the EXB to SCC topologies
Proof of solution
Examples –simulation – experimental results
Efficiency – output resistance
Regulation
Examples
5. Q&A
Power Conversion Objective
y Needed in all modern systems

y Except: incandescent lamps, heaters…
Linear Voltage Regulator
Pout Vout ⋅ I out

η= =
Pin Vin ⋅ I in
since I out ≅ I in
Vout
η=
Vin
Types of Switching DC-DC Converters
Switched inductor
Lossless process
Switched capacitor
Lossy process
Inherent Energy Loss due to ΔV

For complete charge/discharge
Sw Rp
V1 ≠ V2 C1 C2
V1 V2
ΔV = V2 − V1
CV12 C1V12 C2V22

E0 = + QV1 E0 = +
2 2 2
Q = C( V2 − V1) V1 Lossy
(C1V1 + C2V2 )2
process E1 =
E1 =
CV22 2 (C1 + C2 )
2
C (ΔV )2 C1C2 (ΔV )
2
E1 − E0 = ΔE = 1 E1 − E0 = ΔE =
2 C1 + C2 2
Independent of parasitic resistances
Types of the Switching DC-DC Converters

Lossless Switching Lossy switching
Relevancy of the Switched Capacitor

Converters (SCC)
Advantages
☺ No magnetic elements
☺ Minimal EM interferences
☺ Can be fabricated as IC
Disadvantages
Inherent power losses
Relatively large number of switches
High inrush current at start-up
The concept of Equivalent Circuit

y The input voltage is divided or multiplied by k
y The losses are emulated by equivalent resistor Req
Target voltage
TR
Vout = kVin
⇓
Vout
η= TR
Vout
Output Resistance in Charge Transfer

(The switched capacitor approximate approach)
y The output capacitor is sufficiently large
y The output voltage is averaged to DC
y The charge/discharge process is completed
Vin − Vout C1 ΔV
Iavg = C1 =
T T
ΔV T 1
R eq = = =
Iavg C1 f ⋅ C1
Peq =
(ΔV )2 = f ⋅ C1 (ΔV )
2
R eq
Independent of parasitic resistances
Output Resistance- Doubler

Output Resistance- Doubler
What is going on???

To be completely deciphered in this seminar
Target Voltages
No-Load No-Loss
Vc1 = Vc 2 = Vc3
Target Voltages
Vout = Vin − Vc1 − Vc 2 − Vc3
Vout = Vc1
1
Vout = Vin
4
1
TargetVoltage = Vin
4
Vc1 = Vc 2 = Vc3
Vout = Vc1 + Vc 2 + Vc3
Vout = Vc1
3
Vout = Vin
4
3
TargetVoltage = Vin
Solution of algebraic equations 4
Multiple Target Voltage Ratios

y Number of target voltage ratios is limited
y Target voltage ratios are spread apart Vout 1
N = 1; =
Vin 2
Vout 1
N = 2; =
Vin 3
Vout 2
N = 2; =
Vin 3
Vout 1
N = 3; =
Vin 4
Vout 3
N = 3; =
Vin 4
N=number of capacitors
Commercial SC Converters
y Maximum efficiency at the fixed voltage ratios:

2/3 and 1/2
Can it be improved ?
Soft Switched SCC
Sinusoidal rather than exponential currents

Claimed to be of low loss
Soft switching – does it help reduce losses?
Classic Dickson’s charge pump
Using diodes
Dickson’s charge pump
Using MOSFETs as diodes
Using MOSFETs
as switches
Operational
modes
Charge-pump/Switched-capacitor
The same operation principle

Charge-pump/Switched-capacitor
Many other modern charge pump topologies
2. Losses in Hard Switched SCC
Features of the new model presented here:
Average model
Relating the losses to the output current
Generic – applicable to practically any SCC
Can take into account output capacitor
Takes into account diode losses
Unified – applicable to hard and soft switched SCC
Has it’s own limitations….
The Generic Charging/Discharging Process

1:1 converter
ΔV≡ Voltage difference before
switch closure
t
ΔV − RC
i(t) = ⋅e ; τ = RC
R
ΔV 2 ⋅ e −2t/τ
PR = i(t) 2 ⋅ R =
R
t1 t
ΔV 2 1 − 2t/τ
E R = ∫ PR dt = ⋅ ∫ e dt
0 R 0
R = R S1 + R ESR
ER =
ΔV 2 ⋅ C
2
(
1 − e − 2β ) t
β= 1
τ
ER= Energy dissipated during switch closure time t1

Energy Dissipated in each switching period
ER =
ΔV 2 ⋅ C
2
(
1 − e − 2β ) t
;β = 1
τ
ΔV 2 ⋅ C
For β >> 1 → E R =
2
ex = 1 + x ...
x →0
ΔV 2
ER β→0 = t1
R

Relating the losses to capacitor’s current
Average current through capacitor
t t
ΔV 1 − RC ΔV iC
Qc = ⋅ ∫ e dt R
R 0
Qc ⋅ fs = IC1(avg)
Iout(avg) = fs ΔV ⋅ C ⋅ 1 − e −β ( ) 0 τ t1 t
ΔV iC
R
IC1(avg)
ΔV =
fsC ⋅ (1 − e −β )
ΔV 2 ⋅ C
ER = ⋅ (1 − e − 2β )
2
0 t1 t

Energy lost per switching period
2
⎛ IC(avg) ⎞ C
ER = ⎜ ⎟ ⋅ ⋅ (1 − e − 2β )
⎜ f C ⋅ (1 − e −β ) ⎟ 2
⎝ s ⎠
(1 − e −2β ) (1 − e −β )(1 + e −β ) (1 + e −β ) ⎛ x ⎞ 1+ e
−x
= = coth⎜ ⎟ =
−β 2 −β −β −β −
(1 − e ) (1 − e )(1 − e ) (1 − e ) ⎝ 2 ⎠ 1− e x
2 2
⎛ IC (avg) ⎞ C (1 + e −β ) ⎛ IC1(avg) ⎞ C β
ER = ⎜⎜ 1 ⎟ ⋅ ⋅
⎟ 2 = ⎜⎜ ⎟ ⋅ coth( )
⎟ 2
f C −β f C 2
⎝ s ⎠ (1 − e ) ⎝ s ⎠
⎛ 1 ⎞ 1
Taking into account deadtime β = ⎜⎜ − DeadTime ⎟⎟ ⋅
2f
⎝ s ⎠ RC

Relating the losses to capacitor’s current
2 2
⎛ IC (avg) ⎞ C (1 + e −β ) ⎛ IC1(avg) ⎞ C β
ER = ⎜⎜ 1 ⎟ ⋅ ⋅
⎟ = ⎜⎜ ⎟ ⋅ coth( )
⎟
−β
⎝ fsC ⎠ 2 (1 − e ) ⎝ fsC ⎠ 2 2
E charging + E discharging
P=
TS
t1 t2
β1 = β2 =
R1C R 2C
R1 = Rs1 + RESR IC1(avg) = IC2 (avg) = IC(avg)

R 2 = Rs2 + RESR
⎧⎪ 1 ⎡ (1 + e−β1 ) (1 + e−β2 ) ⎤ ⎫⎪
Energy lost per 2
PR(avg) = IC(avg) ⋅⎨ ⋅⎢ + ⎥⎬
−β −β
switching cycle ⎪⎩ 2Cfs ⎢⎣ (1 − e 1 ) (1 − e 2 ) ⎥⎦ ⎪⎭
SCC Equivalent Resistance

1:1 converter
Assuming β1 = β1 = β
V TRG
out = Vin 2 ⎡ 1 ⎛ β ⎞⎤
PR(avg) = I out(avg) ⋅⎢ ⋅ coth⎜ ⎟⎥
⎣ fsC ⎝ 2 ⎠⎦
1 ⎛β ⎞ 1 (1 + e −β )
R eq = ⋅ coth⎜ ⎟ = ⋅
fsC ⎝ 2 ⎠ f s C (1 − e − β )

Limits β→ ∞
Complete charge/discharge RC<<Ts
D2Ts D1Ts
β2 = β1 =
RC RC
⎧⎪ 1 ⎡ (1 + e − β1 ) (1 + e − β2 ) ⎤ ⎫⎪
Req = ⎨ ⋅⎢ − β1
+ − β2 ⎥ ⎬
⎪⎩ 2Cf s ⎣ (1 − e ) (1 − e ) ⎦ ⎪⎭
1
Re β>>1 = 0 τ t1 t
fsC
Independent of R
High losses (large rms currents)
The classical solution

Incomplete charge/discharge RC>>Ts; β→0
Ts
For t1= t2=Ts/2 β=
2 RC
⎧⎪ 1 ⎡ (1 + e − β1 ) (1 + e − β2 ) ⎤ ⎫⎪
Req = ⎨ ⋅⎢ − β1
+ − β2 ⎥⎬
⎪⎩ 2Cf s ⎣ (1 − e ) (1 − e ) ⎦ ⎪⎭
⎡ 1 + e −β ⎤
1 (1 + e −β ) β⎢ ⎥
R eq = ⋅ ⎢ 1 − e −β ⎥
f sC (1 − e −β ) ⎣ ⎦
⎧⎪ 2R (1 + e −β ) ⎫⎪ (1 + e −β )
Re = ⎨ ⋅ ⎬ = 2Rβ ⋅
−β
⎪⎩ 2fsCR (1 − e ) ⎪⎭ (1 − e −β )
Re β→0 = 4R Why??

Behavior
Re β→0 = 4R Ts
For t1 = t2=Ts/2 β=
2 RC
(2I out )2 ⋅ Ts + (2I out )2 Ts

PR = 2 2 R
Ts
(2 * Io )2 R = (I0 )2 ⋅ 4R
Re β →0 = 4 R

Frequency dependence
⎧⎪ 1 ⎡ (1 + e − β1 ) (1 + e − β2 ) ⎤ ⎪⎫
Req = ⎨ ⋅⎢ −β
+ − β ⎥⎬
⎪⎩ 2Cf s ⎣ (1 − e 1 ) (1 − e 2 ) ⎦ ⎪⎭
10
⎡ 1 + e(−1 fs ) ⎤
⎧ 1 ⎡ (1 + e −β ) ⎤ ⎫ Re
R eq = ⎨ ⋅⎢ −β ⎥ ⎬
⎩ Cfs ⎣ (1 − e ) ⎦ ⎭ 1 ⎢ ⎥
1 fs ⎢ 1 − e(−1 fs ) ⎥
β = ⎣ ⎦
2 RCf s 1
=1
2 RC
2
1
0.1 1 10
f

Incomplete charge/discharge RC>>Ts; β→0
Ts
For t1= t2=Ts/2 β=
−β
⎧⎪ 2R (1 + e ) ⎪⎫ −β
(1 + e ) 2 RC
Re = ⎨ ⋅ ⎬ = 2Rβ ⋅
⎪⎩ 2fsCR (1 − e −β ) ⎪⎭ (1 − e −β )
⎡ 1 + e −β ⎤
Sizing C β⎢ ⎥
⎢ 1 − e −β ⎥
⎣ ⎦
Ts
β= <1
2RC
1
C>
2Rfs

Effect of Duty Cycle
⎧⎪ 1 ⎡ (1 + e − β1 ) (1 + e − β2 ) ⎤ ⎪⎫
Req = ⎨ ⋅⎢ −β
+ − β ⎥⎬
⎪⎩ 2Cf s ⎣ (1 − e 1 ) (1 − e 2 ) ⎦ ⎪⎭
Re ⎡ −
D
−
1- D
⎤
1 ⎢1 + e fs
1 + e fs ⎥
+
1 ⎧ ⎛β ⎞ ⎛ β ⎞⎫
20
fs ⎢ −
D
−
1- D ⎥
R eq = ⋅ ⎨coth⎜ 1 ⎟ + coth⎜ 1 ⎟ ⎬
2fsC ⎩ ⎝2⎠ ⎝ 2 ⎠⎭
⎢⎣1 − e fs
1 − e fs ⎥⎦ 1
=1
D=0.2
2 RC
D=0.3
10
D=0.4
D=0.5
0.1 1 10
f

Effect of duty cycle β→0
⎧⎪ 1 ⎡ (1 + e − β1 ) (1 + e − β2 ) ⎤ ⎫⎪
Req = ⎨ ⋅⎢ + ⎥⎬ 1 ⎧2 2⎫
⎪⎩ 2Cf s
− β1
⎣ (1 − e ) (1 − e
− β2
) ⎦ ⎪⎭ R eq = ⋅⎨ + ⎬
2fsC ⎩ β1 β 2 ⎭
1 ⎧ ⎛β ⎞ ⎛ β ⎞⎫ D 1− D
R eq = ⋅ ⎨coth⎜ 1 ⎟ + coth⎜ 1 ⎟ ⎬ β1 = β2 =
2fsC ⎩ 2
⎝ ⎠ ⎝ 2 ⎠⎭ f s RC f s RC
⎧R R ⎫
R eq = ⎨ + ⎬
⎩D 1− D ⎭
R
Req =
β →0 (1 − D)D
Re as a function of Duty Cycle

Explanation
2 2
⎛I ⎞ ⎛I ⎞
PR = ⎜ out ⎟ ⋅ D ⋅ R + ⎜ out ⎟ ⋅ (1 − D) ⋅ R
⎝ D ⎠ ⎝ 1 − D ⎠
2 ⎛R R ⎞ 2
PR = Iout ⎜ + ⎟ = IoutRe
⎝ D 1 − D⎠
R R R
Re = + =
D 1 − D D(1 − D)
Simulation/Experimental Demonstartion
Mosfets S1, S2: IRF840, Rdson = 0.85Ω, C = 1μF

Vin = 24V; Vout_theoretical = 24V;
RL = 100Ω || 1K Ω ~ 91Ω or 1KΩ; Duty Cycle = 0.5;
Power Level: 6.3 Watts (max)
200KHz 20KHz
RL =91 Ω
Vout= 22.58V
Vout= 15.49V
94% Efficiency
64% Efficiency
D = 0.5; Vout = 20.58V;
Vin = 24V; Vout_target = 24V

RL ~ 91Ω;
Rs = 3.35Ω; fs = 200KHz;
Simulation/Experimental Demonstration
D = 0.7; Vout = 19.94V; D = 0.9; Vout = 14.456V;

Generalization
⎧⎪ 1 ⎡ (1 + e −β1 ) ⎤ ⎡ (1 + e −β 2 ) ⎤ ⎫⎪ t1, 2
2
PCi (avg) = IC ⋅ ⎨ ⋅⎢ ⎥+⎢ ⎥⎬ β1, 2 =
i (avg) −β −β
⎪⎩ 2Cfs ⎣⎢ (1 − e 1 ) ⎦⎥ ⎣⎢ (1 − e 2 ) ⎦⎥ ⎪⎭ τ 1, 2
I Ci = ki I out (avg )
⎧⎪ 1 ⎡ (1 + e −β1 ) ⎤ ⎡ (1 + e −β 2 ) ⎤ ⎫⎪
R eC = k 2 ⋅ ⎨ PCi = (I o ) ⋅ ReCi
2
⋅⎢ ⎥+⎢ ⎥⎬
−β −β
i
⎪⎩ 2Cfs ⎢⎣ (1 − e 1 ) ⎥⎦ ⎢⎣ (1 − e 2 ) ⎥⎦ ⎪⎭
n
Re = ∑ ReCi
i=1
Ci = flying capacitor i
τ = time constant of charge/discharge loop

1/2 converter
C
VIn COut IOut
l o ut ( avg ) = lC1( avg ) + lC2 ( avg ) l o ut ( avg )

lC ( avg ) = → k = 1/ 2
2
⎧⎪ 1 (1 + e −β ) ⎫⎪ 1 1
Re = k 2 ⎨ ⋅ ⎬ =
⎪⎩ fsC (1 − e −β ) ⎪⎭ R1C1 R2C2
1 ⎧⎪ 1 (1 + e −β ) ⎫⎪
Re = ⎨ ⋅ ⎬
4 ⎪⎩ fsC (1 − e −β ) ⎪⎭

Example
I C + 3I C = I out
k = 1/ 4
In general τ 1 ≠ τ 1
In practice τ 1 = τ 1
1 ⎧ 1 (1 + e − β ) ⎫ ⎡ 1 ⎧⎪ 1 (1 + e −β ) ⎫⎪⎤
ReC i = ⎨ ⋅ ⎬ ReT = 3 ⎢ ⎨ ⋅
16 ⎩ f sC (1 − e − β ) ⎭ ⎬⎥
⎢⎣ 16 ⎪⎩ fsC (1 − e −β ) ⎪⎭⎥⎦
Assuming equal size capacitors
Including Finite Output Capacitor

RS1 S1 i(t) RS2 S2
C1 Co
Vin R ESR(out) Ro Vo
R ESR
t1,2 ⎧⎪ 1 ⎡ (1 + e −β1 ) ⎤ ⎡ (1 + e −β 2 ) ⎤ ⎫⎪
β1,2 = R eC = k 2 ⋅ ⎨ ⋅⎢ ⎥+⎢ ⎥⎬
τ 1,2 i −β −β
⎪⎩ 2Cfs ⎣⎢ (1 − e 1 ) ⎦⎥ ⎣⎢ (1 − e 2 ) ⎦⎥ ⎪⎭
τ1 = (RS2 + RESR )C1
⎧ CC ⎫
τ2 = (RS1 + RESR + RESRo )⎨ 1 o ⎬
⎩ C1 + Co ⎭
n
Re = ∑ ReCi Including Co (could be neglected in practical cases)
i=1
Including diodes
Step up X3
IC=ID =Iout(avg)
Including diodes
Step up X3
VTRG = 3 × Vin
1 ⎡ ⎛ β ⎞ C +C ⎛β ⎞ ⎛β ⎞ ⎛ β ⎞⎤
Req = ⋅ ⎢2 ⋅ coth⎜⎜ (1) ⎟⎟ + out ⋅ coth⎜⎜ (2) ⎟⎟ + coth⎜⎜ (3) ⎟⎟ + 2 ⋅ coth⎜⎜ (4) ⎟⎟⎥
2f S ⋅ C ⎣ ⎝ 2 ⎠ C out ⎝ 2 ⎠ ⎝ 2 ⎠ ⎝ 2 ⎠⎦
t2 t2
β (1) = β (2) =
(R1 + 2ESR) ⋅ C/2 ⎛ C ⋅C ⎞
(R1 + ESR + ESR out ) ⋅ ⎜⎜ out ⎟⎟
⎝ C out + C ⎠
t1 t1
β (3) = β (4) =
(R1 + ESR) ⋅ C (R1 + 2ESR) ⋅ C/2
Including diodes/Simulation
Step up X3
PSIM Parameters file
Rout = 1000
Cout = 100u
C_init = 23.22
Vin = 10
C_fly = 1uF
R1 = 1m
ESR = 10m
ESR_out = 100m
V_forward = 1
DeadTime = 10n
f_s = 100k
k_2 = ((Cout + C_fly) / Cout)
beta _1 = (1 / (2 * f_s) - DeadTime) * (1 / ((R1+ 2*ESR) * (C_fly/2)))
beta _2 = (1 / (2 * f_s) - DeadTime) * (1 / ((R1 + ESR + ESR_out) * (Cout * C_fly /(C_fly + Cout)) ))
beta _3 = (1 / (2 * f_s) - DeadTime) * (1 / ((R1+ ESR) * C_fly))
beta _4 = (1 / (2 * f_s) - DeadTime) * (1 / ((R1+ 2*ESR) * (C_fly/2)))
coth_1 = (1 + exp(-beta_1)) / (1- exp(-beta_1))
Req = ((1 / (2 * f_s * C_fly)) * (2 * coth_1+ k_2 * coth_2 + coth_3 + 2 * coth_4))
Including diodes
Step up X3
Rout Cout Vin Cfly R1 ESR ESRout Vforward Dead fS
[Ω] [F] [V] [F] [Ω] [Ω] [Ω] [V] Time [Hz]
[sec]
1000 100μ 10 1μ 100m 10m 10m 1 10n 100k
time
Complications
Rout Cout Vin Cfly R1 ESR ESRo Vforwa Dead fS
[Ω] [F] [V] [F] [Ω] [Ω] ut rd Time [Hz]
[Ω] [V] [sec]
1000 100μ 10 1μ 10 10m 10m 1 10n 100k
Coupled Loops
R1 is shared by two loops

Small effect in practical cases
Output Voltage Regulation
D1Ts D2Ts
β1 = β2 =
RC RC
⎧⎪ 1 ⎡ (1 + e −β1 ) ⎤ ⎡ (1 + e −β 2 ) ⎤ ⎫⎪
R eC = k 2 ⋅ ⎨ ⋅⎢ ⎥+⎢ ⎥
−β1 −β 2 ⎬
i
⎪⎩ 2Cfs ⎣⎢ (1 − e ) ⎦⎥ ⎣⎢ (1 − e ) ⎦⎥ ⎪⎭
Variable frequency control (increases output voltage ripple)

Frequency dithering (increases output voltage ripple)
Variable loop resistance
Duty Cycle control (high operating frequency)
Global PWM (increases output voltage ripple)
Switching VTRG (increases complexity)

Up converter: x2, x1.5
Interim Summary
Expressing losses as a function of capacitor's current

Generic average model
Limits
Duty cycle effect
Generalization
Regulation
3. Losses in Soft Switched SCC
Model building approach

Analysis follows that of hard switched SCC
Expressing losses as a function of output current
Generalizing
Comparison to hard switched SCC
Generic Resonant Charging/Discharging Process

ΔV≡ Voltage difference before switch closure
ΔV 1
i(t) = ⋅ e − α ⋅ t ⋅ sin(ω d t) Q>
ωd ⋅ L 2
2
⎛ ΔV ⎞
PR = i(t) 2 ⋅ R = ⎜⎜ ⎟⎟ ⋅ e − 2α ⋅ t ⋅ sin 2 (ωd t) ⋅ R
⎝ ωd L ⎠
π/ω d π/ω d
ΔV 2 ⋅ R
E R(res) = ∫ PR dt = ∫ ⋅ e − 2α ⋅ t ⋅ sin 2 (ω d t)dt
0 0 ω d2 ⋅ L2
⎛ − 2π
α ⎞ R 1
ΔV 2 ⋅ C ⎜ ωd ⎟ α= ω0 =
E R(res) = ⋅ ⎜1 − e ⎟ 2L LC
2 ⎜ ⎟
⎝ ⎠
ω d2 = ω 02 − α 2
R = R S1 + R ESR + R Ind
ER(res)= Energy dissipated per switch closure

Energy Dissipated in each switching period
R 1
⎛ − 2π
α ⎞ α= ω0 =
ΔV 2 ⋅ C ⎜ ωd ⎟ 2L LC
E R(res) = ⋅ ⎜1 − e ⎟
2 ⎜ ⎟
⎝ ⎠ ω d2 = ω 02 − α 2
ωd L
Qd =
R
ΔV 2 ⋅ C 1 R
E R(res) = ⋅ (1 − e − 2π⋅ζ d ) ζd = =
2 2Q d 2ω d L

Relating the losses to the output current
Average current through a capacitor

ΔV π/ω d − α ⋅ t
Qc = ∫ e ⋅ sin(ω d t)dt
ωd ⋅ L 0
ΔVQc = ΔVC ⋅ (1 + e − πζ d )
Qc Q c ⋅ f s = I C1 (avg)
ΔV =
C ⋅ (1 + e − πζ d )
I out(avg) = f s ⋅ ΔV ⋅ C ⋅ (1 + e − πζ d )
I C1 (avg)
ΔV =
f s C ⋅ (1 + e − πζ d )
ΔV 2 ⋅ C
E R(res) = ⋅ (1 − e − 2π⋅ζ d )
2

2
⎛ I C1 (avg) ⎞ C
E R(res) = ⎜ ⎟ ⋅ ⋅ (1 − e − 2πζ d )
⎜ f C ⋅ (1 + e − πζ d ) ⎟ 2
⎝ s ⎠
(1 − e −2 πζ d ) (1 − e − πζ d )(1 + e − πζ d ) (1 − e − πζ d ) −x
= = ⎛ x ⎞ (1 − e )
tanh ⎜ ⎟ =
(1 + e − πζ d ) 2 (1 + e − πζ d )(1 + e − πζ d ) (1 + e − πζ d ) −
⎝ 2 ⎠ (1 + e x )
2 2
⎛ I out(avg) ⎞ C (1 − e − πζ d ) ⎛ I out(avg) ⎞ C
⎟ ⋅ ⋅ tanh⎛⎜ d ⎞⎟
πζ
E R = ⎜⎜ ⎟ ⋅ ⋅
⎟ 2 = ⎜⎜ ⎟ 2
f C − πζ d f C ⎝ 2 ⎠
⎝ s ⎠ (1 + e ) ⎝ s ⎠

2
⎛ I out(avg) ⎞ C
⎟ ⋅ ⋅ tanh⎛⎜ d ⎞⎟
πζ
E R = ⎜⎜ ⎟ 2
⎝ f s C ⎠ ⎝ 2 ⎠
E charging + E discharging
P=
TS
R1 R2
ζ d(1) = ζ d(2) =
2ωd1L 2ω d2 L
R 1 = R S1 + R ESR + R Ind
I C1 (avg ) = I C 2 (avg ) = I C(avg )
R 2 = R S 2 + R ESR + R Ind
2 ⎧ ⎡ (1 − e −πζ d (1) ) (1 − e −πζ d ( 2) ) ⎤ ⎫⎪

1 ⎛ R(1,2) ⎞ 2
PR(avg) = I C(avg)
⎪ 1
⋅⎨ ⋅⎢ + ⎥⎬
ω d(1,2) = −⎜ ⎟
LC ⎜⎝ 2 L ⎟
⎠ ⎪⎩ 2Cf s ⎢ (1 + e −πζ d (1) ) (1 + e −πζ d ( 2) ) ⎥ ⎪
⎣ ⎦⎭
Resonant SCC Equivalent Resistance
1:1 converter
In steady state
Q charging = Q discharging
IC1(avg) = IC2 (avg) = Iout(avg)

2 ⎧ 1 ⎛ πζ ⎞⎫
PR(avg) = I out(avg) ⋅⎨ ⋅ tanh⎜ d ⎟⎬
⎩fsC ⎝ 2 ⎠⎭
V TRG
out = Vin
For ζ d(1) = ζ d(2)
1 ⎛ πζ ⎞ 1 (1 − e −πζ d )
R eq = ⋅ tanh⎜ d ⎟ = ⋅
fsC ⎝ 2 ⎠ f s C (1 + e − πζ d )

1:1 converter Dependence on fs
1 ⎛ πζ ⎞ 1 (1 − e −πζ d )
R eq = ⋅ tanh⎜ d ⎟ = ⋅
fsC ⎝ 2 ⎠ f s C (1 + e − πζ d )
Losses decrease as 1/fs up to the limit: fs=ωd/2 π
Comparing Hard and Soft SCC Losses

R2
Soft ζ d(1) =
R1 ζ d(2) =
2ω d2 L
2ωd1L
1 (1 − e − πζ d ) 1 ⎛ πζ ⎞
Req = ⋅ = ⋅ tanh⎜ d ⎟ 2
fsC (1 + e − πζ d ) fsC ⎝ 2 ⎠ ω 1 ⎛ R(1,2) ⎞
fs ≤ d ω d(1,2) = −⎜ ⎟
2π LC ⎜⎝ 2 L ⎟
⎠
Hard
1 (1 + e −β ) 1 ⎛β⎞ 1
Req = ⋅ = ⋅ coth⎜ ⎟ β=
fsC (1 − e −β ) fsC ⎝ 2⎠ 2fsRC
Unified
1 ⎛ α ⎞ R
R eq = tanh⎜⎜ ⎟⎟ Soft → α =
soft fsC 4L
⎝ 2fs ⎠
1 ⎛ α ⎞ 1
Req = coth⎜⎜ ⎟⎟ Hard → α =
hard fsC ⎝ 2fs ⎠ 2RC
Comparing Hard and Soft SCC Losses

Limits
For high Q soft switched SCC (ζd >> 1)
R π2R
Req = = ≈ 5R
soft 8(fs )2 LC 2
R→ 0
Req →0 1
→
5
Req
soft hard fsC 4
( 1+e− β )
fs→ ∞ ( 1−e− β )
3
π2R
2
Req = 4R Req = ≈ 5R
hard soft 2 1
0 2 4 6
β
RS1 S1 i(t) RS2 S2
L
RInd
Vin Co Ro Vo
C
R ESR
Mosfets S1, S2: IRF840, Rdson = 0.85Ω, C = 1μF

Vin = 24V; Vout_theoretical = 24V;
RL = 100Ω || 1K Ω ~ 91Ω; Duty Cycle = 0.5;
Power Level: 5.5 Watts (max)
100 KHz 20 KHz
RL = 91Ω
L = 2.3 μHy
Q = 1.8
Vout = 22V Vout = 16.1V
Efficiency = 91.7% Efficiency = 67%
100 KHz 20 KHz
RL = 91Ω
L = 0.5 μHy
Q = 0.9
Vout = 21.2V Vout = 15.4V
Efficiency = 88.3% Efficiency = 64.2%


Generalization
2
1 ⎛ R(1, 2) ⎞
⎧ ⎡ (1 − e− πζ d(1) − πζ d(2) ⎫ ω d(1,2) = −⎜ ⎟
2 ⎪ 1 ) (1 − e ) ⎤⎪ LC ⎜⎝ 2 L ⎟
⎠
PC i (avg) = I C ⋅⎨ ⋅⎢ + ⎥⎬
i (avg) ⎢ (1 + e − πζ d(1) ) (1 + e − πζ d(2) ) ⎥ ⎪
⎪⎩ 2Cf s ⎣ ⎦⎭ R
ζ d(1,2) =
2ω d(1,2) L
⎧ ⎡ (1 − e − πζ d(1) ) (1 − e − πζ d(2) ) ⎤ ⎫⎪
⎪ 1
R eC i = k 2 ⋅ ⎨ ⋅⎢ + ⎥⎬ 2
PC i = I out ⋅ R eC i
⎪⎩ 2Cf s ⎢ (1 + e − πζ d(1) ) (1 + e − πζ d(2) ) ⎥ ⎪
⎣ ⎦⎭
n
Re = ∑ ReCi
i=1
Ci = flying capacitor i
ζd = damping ratio of charge/discharge loop
Including Finite Output Capacitor

RS1 S1 i(t) RS2 S2
L
RInd Co
Vin RESR(out) Ro Vo
C
R ESR
R ⎧ ⎡ (1 − e − πζ d(1) ) (1 − e − πζ d(2) ) ⎤ ⎫⎪
ζ d(1,2) = ⎪ 1
2ω d(1,2) L R eC i = k 2 ⋅ ⎨ ⋅⎢ + ⎥⎬
⎪⎩ 2Cf s ⎢ (1 + e − πζ d(1) ) (1 + e − πζ d(2) ) ⎥ ⎪
⎣ ⎦⎭
R S1 + R ESR + R Ind R S 2 + R ESR + R ESR(out) + R Ind

ζ (2) =
ζ (1) = R S 2 + R ESR + R ESR(out) + R Ind
1
1 R S1 + R ESR + R Ind 2L −
2L − C out ⋅ C 2L
LC 2L L⋅
C out + C
Including Co (could be neglected in practical cases)

Including Diodes
Step up x3
IC=ID =Iout(avg)
Including Diodes
Step up x3
VTRG = 3 × Vin
1 ⎡ ⎛ πζ (1) ⎞ C out + C ⎛ πζ (2) ⎞ ⎛ πζ ⎞ ⎛ πζ ⎞⎤

Re = ⋅ ⎢2 ⋅ tanh⎜⎜ ⎟+ ⋅ tanh⎜⎜ ⎟ + tanh⎜ (3) ⎟ + 2 ⋅ tanh⎜ (4) ⎟⎥
2f s ⋅ C ⎣⎢ ⎟ ⎟ ⎜ 2 ⎟ ⎜ 2 ⎟
⎝ 2 ⎠ C out ⎝ 2 ⎠ ⎝ ⎠ ⎝ ⎠⎦⎥
R S1 + 2R ESR + R Ind R S1 + R ESR + R ESR(out) + R ind
ζ (1) = ζ (2) =
1 R S + R ESR + R ESR(out) + R Ind
1 R S + 2R ESR + R Ind 2L − 1
2L − 1 C ⋅C 2L
L(C/2) 2L L ⋅ out
C out + C
R S 2 + R ESR + R Ind R S 2 + 2R ESR + R Ind

ζ (3) = ζ (4) =
1 R S 2 + R ESR + R Ind 1 R S 2 + 2R ESR + R Ind
IC=ID =Iout(avg) 2L
LC
−
2L
2L
L(C/2)
−
2L
Including Diodes
Step up x3
Rout Cout Vin Cr Rr Vforward ESR ESRout Lr Dead fS
[Ω] [F] [V] [F] [Ω] [V] [Ω] [Ω] [Hy] Time [Hz]
[sec]
1K 100μ 10 1μ 3m 0 1m 1m 1μ 10n 100k
Q ~ 200
Including Diodes
Step up x3
Rout Cout Vin Cr Rr Vforward ES ESRout Lr Dead fS
[Ω] [F] [V] [F] [Ω] [V] R [Ω] [Hy] Time [Hz]
[Ω] [sec]
1K 100μ 10 2μ 150m 0 10m 1m 1μ 10n 100k
Q~5
The case of Coupled Loops

Rout Cout Vin C R1 Vforward ESR ESRou Lr Dead fS
[Ω] [F] [V] [F] [Ω] [V] [Ω] t [Hy] Time [Hz]
[Ω] [sec]
1K 100μ 10 1μ 1 0 1m 1m 1μ 10n 100k
Q~1

Regulation → Losses
R
ζ d(1,2) =
2ω d(1,2) L
⎧ ⎡ (1 − e − πζ d(1) ) (1 − e − πζ d(2) ) ⎤ ⎫⎪
⎪ 1
R eC i = k 2 ⋅ ⎨ ⋅⎢ + ⎥⎬
⎪⎩ 2Cf s ⎢ (1 + e − πζ d(1) ) (1 + e − πζ d(2) ) ⎥ ⎪
⎣ ⎦⎭
Variable frequency control

Frequency dithering
Variable loop resistance
Global PWM (increases output voltage ripple)
2nd Interim Summary
Expressing losses as a function of capacitor's current

Generic average model
Limits
Generalization
Regulation
Self Adjusting Binary SCC

Objective: To increase the number of target voltage ratios
y More target voltage ratios with same number of capacitors

y Small ΔV between adjacent target voltage ratios
The Approach
y Developing a novel Extended Binary

(EXB) number representation for
increased resolution
y Translating the EXB sequences into
switched capacitor topologies
Theoretical Foundation of novel SCC

Binary Fractions
y Negative powers of two are used

y Resolution is defined by the LSB 1·2-n
n
3 Aj = {0, 1}
Bn = ∑ A j 2 − j
j= 0 3 n – is the resolution
For example Bn = 5/8
5 8 = 0 ⋅ 20 + 1 ⋅ 2−1 + 0 ⋅ 2−2 + 1 ⋅ 2 −3 → {0 1 0 1}
Signed Binary Number Representation
n
3 Aj = {-1, 0, 1}
Zn = ∑ A j 2 j
j= 0 3 n – is the resolution
y More than one code for a given ZN
For example:
5 = 0 + 4 + 0 + 1 → {0 1 0 1}
5 = 0 + 4 + 2 − 1 → {0 1 1-1}
5 = 8 + 0 − 2 − 1 → {1 0-1-1}
5 = 8 − 4 + 0 + 1 → {1-1 0 1}
5 = 8 − 4 + 2 − 1 → {1-1 1-1}
Extended Binary (EXB) Representation

developed in this study
y For numbers Mn in the range from 0 to 1
n
3 A0 = {0, 1}
Mn = A 0 + ∑ A j 2 −j
3 Aj = {-1, 0, 1}
j=1
3 n – is the resolution
y More than one code for a given Mn
Number EXB code

For example 5 8 = 0 + 2-1 + 2-2 − 2-3 → {0 1 1 -1}
5/8 = {0 1 0 1}, 5 8 = 1 − 2-1 + 0 + 2-3 → {1 -1 0 1}
so that n = 3 5 8 = 1 + 0 − 2-2 − 2-3 → {1 0 -1 - 1}
Spawning the EXB Representation Sequences

The proposed algorithm
y Adding and subtracting 2-j keeps Mn unchanged
↓ Example: 5/8 ⇒ {0 1 0 1}, ↓

-3 -3
20 2-1 2-2 2 j=3 2 2 2-2 2
0 -1
0 1 0 1 0 1 1 -1
+ binary addition +
0 0 0 1 0 0 1 0
0 1 1 0 1 0 0 -1
+ replace the original 1 with -1 +
0 0 0 -1 0 0 -1 0
0 1 1 -1 {0 1 0 1} 1 0 -1 -1
0 1 1 -1
Result: 1 0 -1 -1
1 -1 1 -1
1 -1 0 1
Properties of the EXB representations

Corollary 1:
For any EXB number Mn in the range of 0 to 1 of
resolution n, the minimum number of EXB representations is
n+1.
This is because each of the Aj =1 (j>0) in the original binary
representation will generate a new representation.
Furthermore, each Aj =0 will turn into Aj =1 that can spawn
a new representation. {0 1 0 1}
0 1 1 -1
1 0 -1 -1
Example: n= 3, Mn= 5/8
1 -1 1 -1
1 -1 0 1
Properties of the EXB representations
Corollary 2:
For each Aj=1 (j>0) in an EXB representations of a
given number Mn , there will be at least one Aj=-1 in another
sequence of same Mn.
This is because the generation process involves
replacing “1” by a “-1”. {0 1 0 1}
0 1 1 -1
1 0 -1 -1
Example: n= 3, Mn= 5/8 1 -1 1 -1
1 -1 0 1
Sequences of the EXB representations
y Example for n = 3
y The number of the EXB representations is at least n+1

y There are “1” and “-1” placed in the same columns
Back to Switched Capacitor DC-DC Converter
y The EXB representation attributes were used to develop

a new family of SC converters
y Capacitors’ interconnections follow the EXB codes
Translating the EXB to Capacitor Connections
n
Mn = A 0 + ∑ A j 2 − j
j
y Mn represents the desired output target voltage

ratio
y Each EXB sequence of Mn is associated with a
switched capacitors topology
y A0 is associated with the input voltage
y Each Aj (j>0) is associated with a flying capacitor Cj
y Polarity of Aj (j>0) indicates polarity of Cj connection
Translating the EXB to Capacitor Connections
n
Mn = A 0 + ∑ A j 2 − j
j
y The capacitors are always serially connected to the load

y The source is connected in series with the load (and
capacitors) in opposite polarity
3 A0 – the voltage source 3 Aj – capacitor connection

1: connected -1: charging
0: disabled
0: disconnected
1: discharging
All Topological Constraints for Vout = 3/8·Vin
y For VC1=1/2Vin, VC2=1/4Vin, VC3=1/8Vin, the system is in

steady state
All Topological Constraints for Vout = 3/8·Vin
n=3
n
Mn = A 0 + ∑ A j 2 − j
j
y There are at least n+1 topologies for each ratio Mn.

(Corollary 1)
y The capacitors are charged and discharged (Corollary 2)
The Self-Adjusting Property
The perpetual EXB sequences of the converter
But…
y Is there an unique steady state solution?
y Convergence from start up (zero voltage across the
capacitors)?
y Recovery from load step transient?
The EXB as a System of Linear Equations

⎧ Vin - V1 + 0 - V3 = Vo
n
⎪
Mn = A 0 + ∑ A j 2 −j
⎪⎪ 0 + V1 + 0 - V3 = Vo
j
⎨ Vin - V1 - V2 + V3 = Vo
⎪ 0 + V1 - V2 + V3 = Vo
For Mn= 3/8 ⎪
⎪⎩ 0 + 0 + V2 + V3 = Vo
Solution of linear equation by hardware!

From Corollary 1: ⎧ - V1 - V2 + V3 - Vo = -Vin
Number of equations at least n+1 ⎪ V1 - V2 + V3 - Vo = 0
Number of unknowns n+1 ⎪⎪
⎨ - V1 + 0 - V3 - Vo = -Vin
For n=3 ⎪ V1 + 0 - V3 - Vo = 0
⎪
4 unknowns: V0, V1, V2, V3 ⎩⎪ 0 + V2 + V3 - Vo = 0
Divide the system by Vin:

⎧ - 1 ⋅ x1 - 1 ⋅ x2 + 1 ⋅ x3 - 1 ⋅ x 4 = -1
x1 = V1 Vin ⎪
x2 = V2 Vin ⎪ 1 ⋅ x1 - 1 ⋅ x2 + 1 ⋅ x3 - 1 ⋅ x 4 = 0
⎪
x3 = V3 Vin ⎨ - 1 ⋅ x1 + 0 ⋅ x2 - 1 ⋅ x3 - 1 ⋅ x 4 = -1
⎪ 1⋅ x + 0 ⋅ x -1⋅ x -1⋅ x = 0
x 4 = Vo Vin ⎪ 1 2 3 4
⎪ 0 ⋅ x1 + 1 ⋅ x2 + 1 ⋅ x3 - 1 ⋅ x 4 = 0
⎩

⎧ - 1 ⋅ x1 - 1 ⋅ x2 + 1 ⋅ x3 - 1 ⋅ x 4 = -1
⎪
⎪ 1 ⋅ x1 - 1 ⋅ x2 + 1 ⋅ x3 - 1 ⋅ x 4 = 0
⎪
⎨ - 1 ⋅ x1 + 0 ⋅ x2 - 1 ⋅ x3 - 1 ⋅ x 4 = -1
⎪ 1⋅ x + 0 ⋅ x -1⋅ x -1⋅ x = 0
⎪ 1 2 3 4
⎪ 0 ⋅ x1 + 1 ⋅ x2 + 1 ⋅ x3 - 1 ⋅ x 4 = 0
⎩
In the matrix form, vector X is the unknown weighted
voltages
AX = B, where ⎡- 1 - 1 1 - 1 ⎤ ⎡- 1⎤
⎢ 1 -1 1 -1 ⎥ ⎡ x1 ⎤ ⎢ 0⎥
⎢ ⎥ ⎢x ⎥ ⎢ ⎥
A = ⎢- 1 0 - 1 - 1 ⎥ X = ⎢ ⎥ B = ⎢- 1⎥
2
⎢ ⎥ ⎢x3 ⎥ ⎢ ⎥
⎢ 1 0 -1 -1 ⎥ ⎢⎣ x 4 ⎥⎦ ⎢ 0⎥
⎢⎣ 0 1 1 - 1 ⎥⎦ ⎢⎣ 0⎥⎦
Solvability of the EXB Linear Equations

yThe Kronecker-Capelli theorem:
A system has at least one solution
if and only if rank(A) = rank(A1)
A solution is unique if and only if
rank(A) = rank(A1) = the number of unknowns
For the voltage ratio Mn= 3/8

the augmented matrix 3 Number of unknowns is 4
⎡- 1 - 1 1 - 1 -1 ⎤ 3 rank(A) = rank(A1) = 4
⎢ 1 -1 1 -1 0
⎥
⎢ ⎥ ⎡1 2 ⎤
A1 = ⎢- 1 0 - 1 - 1 - 1⎥ ⎢1 4 ⎥
⎢ ⎥ X = A -1B = ⎢ ⎥
⎢ 1 0 -1 -1 0⎥
⎢1 8 ⎥
⎢⎣ 0 1 1 - 1 0⎥⎦ ⎢⎣3 8⎥⎦
Explicating of the Obtained Solution
y At the steady state the capacitors keep the binary

weighted voltages:
VC1 = 1/2∙Vin
VC2 = 1/4∙Vin
VC3 = 1/8∙Vin
Vout = 3/8∙Vin
y The steady state solution follows the EXB sequence
Step up conversion
⎧ Vin - V1 + 0 - V3 = Vo
⎪ 0 + V1 + 0 - V3 = Vo
⎪⎪
The step-down case: ⎨ Vin - V1 - V2 + V3 = Vo
⎪ 0 + V1 - V2 + V3 = Vo
⎪
⎩⎪ 0 + 0 + V2 + V3 = Vo
⎧ Vo - V1 + 0 - V3 = Vin
⎪ 0 + V1 + 0 - V3 = Vin
⎪⎪
The step-up case: ⎨ Vo - V1 - V2 + V3 = Vin
⎪ 0 + V1 - V2 + V3 = Vin
⎪
⎩⎪ 0 + 0 + V2 + V3 = Vin
y Step up by replacing the functions of input and output

Implementation
y The capacitors need to have

3 types of connections -1, 0, 1
Experimental evaluation board
Microcontroller PIC18F452 (MICROCHIP)

Quad bilateral CMOS switches MAX4678 (MAXIM)
Ceramic Z5U dielectric capacitors 4.7μF (KEMET)
Simulation and Experimental Results

for Starting Up Circuit, Vout = 3/8·Vin
Simulation Experiment
Ch.1: Output voltage

Ch.2: Input voltage
Vertical scale: 1 V/div
Horizontal scale: 10 ms/div
Vin=8V, Load resistor: 3.9 kΩ
Efficiency at different Mn vs. Load resistor
Mn= 3/8
Mn= 5/8
Î
Efficiency at target voltage
yThe losses are determined by an equivalent resistor Req
T
Vout = Target voltage
Vout
η= T
Vout
Testing the Req concept
RoVS
Vo =
Req + Ro
VS
VS Ro = Ro + Req
Ro Vo
Vo
y = x+b
Req = − x y =0
− Req
Experimental results for Mn=3/8
y Req= 7.35 Ω
Zoom in
Rds(on)=1.2 Ω (each switch)
y Supported by theoretical analysis
Voltage Ripple Reduction

Output voltage Regulation
y Voltage ratios outside the target voltages

y Two approaches examined
y Dithering
y Linear regulator (increasing Req)
Output voltage Regulation by Dithering
y Repetitive change of target voltage ratios

y The output voltage is given by a “duty cycle” of dither
Vout 4 3 1 4 2
= ⋅ + ⋅ = = 0.4
Vin 5 8 5 8 5
Output voltage ripple

Dithering between
Constant 3/8 ratio
3/8 and 4/8 in 2:1 ratio
Output ripple for Vin = 8V, Load resistor = 437 Ω

Vertical scale: 10 mV/div, Horizontal scale: 100 μS/div
Using a Linear Regulator for the LSB

y Small power loss due to close target voltage ratios
y Lower output voltage ripple
Generalization to Other Number Systems

n
Nn (r ) = A0r 0 + ∑ A jr − j r= radix
j=1
Aj = jth digit
Digit values= {-(r-1)…-1, 0, 1,…(r-1)}
r-1 capacitors per digit
Example radix 3, 3 bits

N3 (3) = 1⋅ 3 −0 + 0 ⋅ 3 −1 − 2 ⋅ 3 −2 + 1⋅ 3 −3 = 22 ⋅ 3 −3 = 22 / 27

N1( 4)
r= 4, one digit
1/ 4 = 0 ⋅ 4−0 + 1⋅ 4−1 {0 1}
1/ 4 = 1 ⋅ 4 −0 − 3 ⋅ 4 −1 {1 − 3}
3 / 4 = 0 ⋅ 4 −0 + 3 ⋅ 4 −1 {0 3}
3 / 4 = 1 ⋅ 4 −0 − 1 ⋅ 4 −1 {1 − 1}
Applying r=2 (binary) and 2 bits, only 2 capacitors are

required (instead of 3)
Last printed slide
3rd Interim Summary
Binary SCC
High efficiency in wide range of output to input
voltage ratios
2n-1 target voltage ratios with n capacitors
Binary resolution for the adjacent voltage ratios
Relatively large number of switches
Proposed representation by number system

Could help optimizing SCC topologies
Thanks for your attention

Losses in hard-switched SCC
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Switched Capacitor Converter

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Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S.

Ben-Yaakov 2009 [1]

Switched Capacitors Converters

Full set of slides:

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [2]

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [4]

Power Conversion Objective

y Needed in all modern systems

Linear Voltage Regulator

Pout Vout ⋅ I out

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [6]

Types of Switching DC-DC Converters

Inherent Energy Loss due to ΔV

CV12 C1V12 C2V22

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [8]

Types of the Switching DC-DC Converters

Relevancy of the Switched Capacitor

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [10]

The concept of Equivalent Circuit

Output Resistance in Charge Transfer

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [12]

Output Resistance- Doubler

Output Resistance- Doubler

What is going on???

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [14]

Multiple Target Voltage Ratios

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [16]

y Maximum efficiency at the fixed voltage ratios:

Soft Switched SCC

Sinusoidal rather than exponential currents

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [18]

Classic Dickson’s charge pump

Dickson’s charge pump

Using MOSFETs as diodes

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [20]

Dickson’s charge pump

Dickson’s charge pump

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [22]

The same operation principle

Many other modern charge pump topologies

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [24]

2. Losses in Hard Switched SCC

Features of the new model presented here:

The Generic Charging/Discharging Process

ER= Energy dissipated during switch closure time t1

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [26]

The Generic Charging/Discharging Process

The Generic Charging/Discharging Process

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [28]

The Generic Charging/Discharging Process

The Generic Charging/Discharging Process

R1 = Rs1 + RESR IC1(avg) = IC2 (avg) = IC(avg)

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [30]

SCC Equivalent Resistance

SCC Equivalent Resistance

Prof. Sam Ben-Yaakov, Switched Capacitors Converters, © S. Ben-Yaakov 2009 [32]

SCC Equivalent Resistance

SCC Equivalent Resistance

(2I out )2 ⋅ Ts + (2I out )2 Ts