DDR SDRAM Controller

ABSTRACT :

Synchronous DRAM (SDRAM) has become a mainstream memory of choice in design due to its
speed, burst access and pipeline features. For high-end applications using processors, the
interface to the SDRAM is supported by the processor’s built-in peripheral module. However, for
other applications, the system designer must design a controller to provide proper commands
forSDRAM initialization, read/write accesses and memory refresh. This SDRAM controller
reference design, located between the SDRAM and the bus master, reduces the user’s effort to
deal with the SDRAM command interface by providing a simple generic system interface to the
bus master.

Figure 1 shows the relationship of the controller between the bus master and SDRAM. The
bus master can be either a microprocessor or a user’s proprietary module interface.

Features
• Simplifies SDRAM command interface to standard system read/write interface.
• Internal state machine built for SDRAM power-on initialization.
• Read/write cycle access time optimized automatically according to the SDRAM timing spec and
the mode it’s configured to.
• Dedicated auto-refresh request input and acknowledge output for SDRAM refresh.
• Easily configurable to support different CAS latency and burst length.
Functional Description
The functional block diagram of the SDRAM controller is shown in Figure 2. It consists of three
modules: the main control module, the signal generation module and the data path module. The
main control module, containing two state machines and a counter, is the primary module of the
design which generates proper iState and cState outputs according to the system interface
control signals. The signal generation module generates the address and command signals
required for SDRAM based on iState and cState. The data path module performs the data
latching and dispatching of the data between the bus master and SDRAM.

The ispMACH 5000VG reference design illustrates the use of the sysCLOCK PLL and sysIO
features. All modules derive internal timing from the ispMACH 5000VG’s PLL clock output. This
PLL clock also outputs through a dedicated ispMACH 5000VG pin (PLL_OUT0 or PLL_OUT1)
and can be connected to the SDRAM directly. A separate onboard SDRAM clock may not be
required. With the ispMACH 5000VG sysIO feature, the bus master I/O can be
LVCMOS1.8/2.5/3.3, LVTTL, PCI, PCI-X or GTL+. The sysCLOCK PLL and sysIO are also
supported by the LatticeXP, LatticeECP/EC and ispXPLD device families.

When targeting to other Lattice CPLD devices, instead of generating SDRAM clock with the
CPLD, the system needs an on-board clock source such as a clock oscillator to generate the
clocks for both the CPLD and the SDRAM.
4
SDRAM Initialization
Before normal memory accesses can be performed, the SDRAM needs to be initialized by a
sequence of commands.The INIT_FSM state machine handles this initialization. Figure 3 shows
the state diagram of the INIT_FSM state machine. During reset, the INIT_FSM is forced to the
i_NOP state. After reset, the sys_100 is signal will be sampled at the rising edge of every PLL
clock cycle to determine if the 100 is power/clock stabilization delay is completed. After the
power/clock stabilization is complete, the SDRAM initialization sequence will begin and the
INIT_FSM will switch from i_NOP to i_PRE state. The initialization starts with the PRECHARGE
command, followed by two AUTO REFRESH commands, and then the LOAD MODE REGISTER
command to configure SDRAM to a specific mode of operation. The i_PRE, i_AR1, i_AR2 and
i_MRS states are used for issuing these commands.After each of these commands is issued, a
corresponding timing delay needs to be satisfied before any command other than NOP can be
issued. These timing delays are tRP,RFC and tMRD for command PRECHARGE,AUTO REFRESH
and LOAD MODE REGISTER respectively. After issuing the LOAD MODE REGISTER command
andthe tMRD timing delay is satisfied, INIT_FSM goes to i_ready state and remains there for the
normal memory access cycles unless sys_RESET is asserted. Also, signal sys_INIT_DONE is
set to high to indicate the SDRAM initialization is completed.

The LOAD MODE REGISTER command configures the SDRAM by loading data into the mode
register through the address bus. The data present on the address bus during the LOAD MODE
REGISTER command is loaded to the mode register. The mode register contents specify the
burst length, burst type, CAS latency, etc. Refer to the SDRAM vendor’s data sheet for more
detailed information about the mode register field definitions. As long as all banks of the SDRAM
are put into idle state by the PRECHARGE or AUTO PRECHARGE, the mode register can be
reloaded with different values, thereby changing the mode of operation. However, in most
applications, the mode register value will not be changed after the initialization. This design
assumes the mode register stays the same after initialization and a fixed mode register content is
implemented in the HDL code. The mode register content in the HDL code may need to be
modified to suit the user’s needs.

As mentioned above, certain timing delays (tRP, tRFC, tMRD) need to be satisfied before another
non-NOP command can be issued. These SDRAM delays vary from speed grade to speed grade
and sometimes from vendor to vendor.To accommodate this without sacrificing performance, the
designer needs to modify the HDL code for the specific delays and clock period (tCK). According
to these timing values, the number of clocks the state machine will stay at i_tRP, i_tRFC1,
i_tRFC2, i_tMRD states will be determined after the code is synthesized. In cases where tCK is
larger than the timing delay, the state machine doesn’t need to switch to the timing delay states
and can go directly to the command states. The dashed lines in Figure 3 show the possible state
switching paths.

Read/Write Cycle
Figure 4 shows the state diagram of CMD_FSM which handles the read, write and refresh of the
SDRAM. The CMD_FSM state machine is initialized to c_idle during reset. After reset,
CMD_FSM stays in c_idle as long as sys_INIT_DONE is low which indicates the SDRAM
initialization sequence is not yet completed.

Once the initialization is done, sys_ADSn and sys_REF_REQ will be sampled at the rising edge
of every clock cycle. A logic high sampled on sys_REF_REQ will start a SDRAM refresh cycle.
This is described in the following section. If logic low is sampled on both sys_REF_REQ and
sys_ADSn, a system read cycle or system write cycle will begin. These system cycles are made
up of a sequence of SDRAM commands.
Similar to the FP and EDO DRAM, row address and column address are required to pinpoint the
memory cell location of the SDRAM access. Since SDRAM is composed of four banks, bank
address needs to be provided as well.

The SDRAM can be considered as a four by N array of rows. All rows are in the “closed” status
after the SDRAM initialization. The rows need to be “opened” before they can be accessed.
However, only one row in the same bank can be opened at a time. Since there are four banks,
there can be at most four rows opened at the same time. If a row in one bank is currently opened,
it must be closed before another row in the same bank can be opened.ACTIVE command is used
to open the rows and PRECHARGE (or the AUTO PRECHARGE hidden in the WRITE and
READ commands, as used in this design) is used to close the rows. When issuing the commands
for opening or closing the rows, both row address and bank address need to be provided.

For sequential access applications and those with page memory management, the proper
address assignments and the use of the SDRAM pipeline feature deliver the highest performance
SDRAM controller. However, this type of controller design is highly associated with the bus
master cycle specification and will not fit the general applications.Therefore, this SDRAM
controller design does not implement these custom features to achieve the highest performance
through these techniques.
In this design, the ACTIVE command will be issued for each read or write access to open
the row. After a tRCD delay is satisfied, READ or WRITE commands will be issued with a
high sdr_A[10] to enable the AUTO REFRESH for closing the row after access. So, the
clocks required for read/write cycle are fixed and the access can be random over the full
address range.

Read or write is determined by the sys_R_Wn status sampled at the rising edge of the
clock before tRCD delay is satisfied. If a logic high is sampled, the state machine
switches to c_READA. If a logic low is sampled, the state machine switches to
c_WRITEA.

For read cycles, the state machine switches from c_READA to c_cl for CAS latency, then
switches to c_rdata for transferring data from SDRAM to bus master. The number of
clocks the state machine stays in c_rdata state is determined by the burst length. After the
data is transferred, it switches back to c_idle.

For write cycles, the state machine switches from c_WRITEA to c_wdata for
transferring data from bus master to SDRAM, then switches to c_tDAL. Similar to read,
the number of clocks the state machine stays in c_wdata state is determined by the burst
length. The time delay tDAL is the sum of WRITE recovery time tWR and the AUTO PRECHARGE
timing delay tRP. After the clock rising edge of the last data in the burst sequence, no commands
otherthan NOP can be issued to SDRAM before tDAL is satisfied.

As mentioned in the INIT_FSM section above, the dash lines indicates possible state switching
paths when tCK period is larger than timing delay spec.

Implementation
This design is implemented in VHDL language.