Jedec Standard: Western Digital

JEDEC
STANDARD
Stress-Test-Driven Qualification of
Integrated Circuits
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JESD47K
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(Revision of JESD47J.01, September 2017)

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AUGUST 2018
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
Downloaded by Niharica Sohal (Niharica.sohal@wdc.com) on Jul 18, 2021, 6:53 am PDT

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JEDEC Standard No. 47K
STRESS DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
Contents
Page
1 Scope .................................................................................................................................................................. 1
2 Reference documents ........................................................................................................................................ 2
2.1 Military ............................................................................................................................................................... 2
2.2 Industrial ............................................................................................................................................................. 2
3 General requirements ....................................................................................................................................... 3
3.1 Objective ............................................................................................................................................................. 3
3.2 Qualification family ............................................................................................................................................ 3
3.3 Lot requirements ................................................................................................................................................. 3
3.4 Production requirements ..................................................................................................................................... 3
3.5 Reusability of test samples ................................................................................................................................ 3
3.6 Definition of electrical test failure after stressing .............................................................................................. 4
3.7 Required stress tests for qualification ................................................................................................................. 4
3.8 Pass/Fail criteria.................................................................................................................................................. 4
4 Qualification and requalification..................................................................................................................... 5
4.1 Qualification of a new device ............................................................................................................................ 5
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4.2 Requalification of a changed device .................................................................................................................. 5
5 Qualification tests ............................................................................................................................................ 6
5.1
5.2
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General test ......................................................................................................................................................... 6
Device specific tests............................................................................................................................................ 6
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5.3 Wearout reliability tests ...................................................................................................................................... 6
5.4 Flammability/oxygen index ............................................................................................................................... 7
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5.5 Device qualification requirements ..................................................................................................................... 7

5.6 Nonhermetic package qualification test requirements ..................................................................................... 13
5.7 Hermetic package qualification tests ............................................................................................................... 15
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6 Explanatory comments regarding process/product changes ..................................................................... 16

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6.1 To conform to J-STD-046 ................................................................................................................................ 16

6.2 Changes that may not require re-qualification ................................................................................................. 17
6.3 Multiple family qualifications .......................................................................................................................... 17
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6.4 Guidelines for stress tests for product/process changes ................................................................................... 18

7 Wire bond qualification requirements ......................................................................................................... 19
7.1 Failure criteria for wire bond shear test method (JESD22-B116) of unencapsulated and unstressed bonds .... 19
7.2 Failure criteria for wire bond shear test method (JESD22-B116) for encapsulated and stressed bonds ........... 19
7.3 Failure criteria for wire bond pull testing (Mil-Std 883, Method 2011) ........................................................... 20
Annex A (informative) Nonhermetic package temperature cycling variations for solder joint ................................... 21
Annex B (informative) Sampling options with nonzero failures ................................................................................. 22
Annex C (informative) Differences between revisions ............................................................................................... 23
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Page 1
STRESS DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS
(From JEDEC Board Ballot, JCB-18-25, formulated under the cognizance of the JC14.3 Subcommittee
on Silicon Devices Reliability Qualification and Monitoring.)
1 Scope
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as
new products, a product family, or as products in a process which is being changed.
These tests are capable of stimulating and precipitating semiconductor device and packaging failure
modes on free-standing components not soldered to a printed wired board (PWB), or the like (base
component reliability). The objective is to precipitate failures in an accelerated manner compared to use
conditions. Failure Rate projections usually require larger sample sizes than are called out in qualification
testing. For guidance on projecting failure rates, refer to JESD85 Methods for Calculating Failure Rates
in Units of FITs.
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This qualification standard is aimed at a generic qualification for a range of use conditions, but
 may not be applicable at extreme use conditions such as military applications, automotive under-the-
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hood applications, or uncontrolled avionics environments

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does not cover components assembled onto a PWB, or the like, which may affect the component
reliability under assembled state. This is addressed in JEP150 and e.g., typically applies to TC on
WLCSP devices
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Additional qualification testing tailored to meet specific requirements such as solder joint interconnect
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reliability can be developed by applying JESD94.

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This set of tests should not be used indiscriminately. Each qualification project should be examined for:
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a) Any potential new and unique failure mechanisms.

b) Any situations where these tests/conditions may induce invalid or overstress failures.
If it is known or suspected that failures either are due to new mechanisms or are uniquely induced by the
severity of the test conditions, then the application of the test condition as stated is not recommended.
Alternatively, new mechanisms or uniquely problematic stress levels should be addressed by building an
understanding of the mechanism and its behavior with respect to accelerated stress conditions (Ref.
JESD91, “Method for Developing Acceleration Models for Electronic Component Failure Mechanisms”
and JESD94, “Application Specific Qualification using Knowledge Based Test Methodology”).
Consideration of PC board assembly-level effects may also be necessary. For guidance on this, refer to
JEP150, Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid
State Surface-Mount Components.
This document does not relieve the supplier of the responsibility to assure that a product meets the
complete set of its requirements.

Page 2
2 Reference documents
The revision of the referenced documents shall be that which is in effect on the date of the qualification
plan.
2.1 Military
MIL-STD-883, Test Methods and Procedures for Microelectronics.

MIL-PRF 38535, General Specification for Integrated Circuit Manufacturing.
2.2 Industrial
UL94, Tests for Flammability of Plastic Materials for Parts in Devices and Appliances.
ASTM D2863, Flammability of Plastic Using the Oxygen Index Method.
IEC Publication 695, Fire Hazard Testing.
J-STD-020, Joint IPC/JEDEC Standard, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid
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State Surface-Mount Devices.
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JP-001, Foundry Process Qualification Guidelines (Wafer Fabrication Manufacturing Sites).
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JS-001, Joint JEDEC/ESDA Standard for Electrical Discharge Sensitivity Test - Human Body Model
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(HBM) – Component Level
JS-002, ESDA/JEDEC Joint Standard for Electrostatic Discharge Sensitivity Testing – Charged Device
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Model (CDM) – Device Level

J-STD-002, Solderability Tests for Component Leads, Terminations, Lugs, Terminals and Wires
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JESD22 Series, Reliability Test Methods for Packaged Devices

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JESD46, Guidelines for User Notification of Product/process Changes by Semiconductor Suppliers.

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JESD69, Information Requirements for the Qualification of Silicon Devices.

JESD74, Early Life Failure Rate Calculation Procedure for Electronic Components.
JESD78, IC Latch-Up Test.
JESD85, Methods for Calculating Failure Rates in Units of FITs.
JESD86, Electrical Parameters Assessment.
JESD91, Methods for Developing Acceleration Models for Electronic Component Failure Mechanisms.
JESD94, Application Specific Qualification using Knowledge Based Test Methodology.
JEP122, Failure Mechanisms and Models for Semiconductor Devices.
JEP143, Solid State Reliability Assessment Qualification Methodologies.
JEP150, Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid
State Surface-Mount Components.
JEP156, Chip-Package interaction Understanding, Identification and Evaluation.
JESD201, Environmental Acceptance Requirements for Tin Whisker Susceptibility of Tin and Tin Alloy
Surface Finishes.

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3 General requirements
3.1 Objective
The objective of this procedure is to ensure that the device to be qualified meets a generally accepted set
of stress test driven qualification requirements. Qualification is aimed at components predominantly used
in commercial or industrial operating environments. For other applications, such as automotive, avionics,
medical, etc., adjustments to these requirements may be necessary per supplier and customer agreements.
3.2 Qualification family
While this specification may be used to qualify an individual component, it is designed to also qualify a
family of similar components utilizing the same fabrication process, design rules, and similar circuits.
The family qualification may also be applied to a package family where the construction is the same and
only the size and number of leads differs. Interactive effects of the silicon and package per JEP156 shall
be considered in applying family designations.
3.3 Lot requirements
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Test samples shall comprise representative samples from the qualification family. Manufacturing
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variability and its impact on reliability shall be assessed. Where applicable, the test samples will be
composed of approximately equal numbers from at least three (3) nonconsecutive lots. Other appropriate
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means may be used to evaluate manufacturing variability. Sample size and pass/fail requirements are
listed in Table 1, Table 2, and Table 3. Table A and Table B give guidance on translating pass/fail
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requirements to larger sample sizes.

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Generic data and larger sample sizes may be employed based upon a Chi Squared distribution using a
total percent defective at a 90% confidence limit for the total required lot and sample size. ELFR
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requirements shall be assessed at a 60% confidence level as shown in Table 5-2. If a single unique and
expensive component is to be qualified, a reduced sample size qualification may be performed using 1/3
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the sample size listed in the qualification tables.
3.4 Production requirements
All test samples shall be fabricated and assembled in the same production site and with the same
production process for which the device and qualification family will be manufactured in production.
Samples need to be processed through the full production process including burn-in, handling, test, and
screening.
3.5 Reusability of test samples
Devices that have been used for nondestructive qualification tests may be used to populate other
qualification tests. Devices that have been used in destructive qualification tests may not be used in
subsequent qualification stresses except for engineering analysis. Non-destructive qualification tests are:
Early Life Failure Rate, Electrical Parameters Assessment, External Visual, System Soft Error, and
Physical Dimensions.

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3.6 Definition of electrical test failure after stressing
Post-stress electrical failures are defined as those devices not meeting the individual device specification
or other criteria specific to the environmental stress. If the cause of failure is due to causes unrelated to
the test conditions, the failure shall be discounted.
3.7 Required stress tests for qualification
Table 5-1, Table 5-3, and Table 5-4 list the qualification requirements for new components. Table 5-3
and Table 5-4 are differentiated by package type, but these are not exclusively packaging tests. As
outlined in JEP156, interactive effects of the packaging on the silicon also drive the need for tests in
Table 5-3 and Table 5-4. Power supply voltage for biased reliability stresses should be Vcc max or Vdd
max as defined in the device datasheet as the maximum specified power supply operating voltage, usually
the maximum power supply voltage is 5% to 10% higher than the nominal voltage. Some tests such as
HTOL may allow for higher voltages to gain additional acceleration of stress time. JEP122 can provide
guidance for accelerating common failure mechanisms.
Table 6-1 lists the stresses that should be considered for a qualification family or category of change.
Interactive effects from the unchanged aspects of both the silicon and packaging must be assessed.
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3.8 Pass/Fail criteria
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Passing all appropriate qualification tests specified in Table 5-1, Table 5-3, and Table 5-4, either by
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performing the test, showing equivalent data with a larger sample size, or demonstrating acceptable
generic data (using an equivalent total percent defective at a 90% confidence limit for the total required
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lot and sample size), qualifies the device per this document. When submitting test data from generic
products or larger sample sizes to satisfy the Table 5-1, Table 5-3, and Table 5-4 qualification
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requirements of this document, the number of samples and the total number of defective devices
occurring during those tests must satisfy 90% confidence level of a Poisson exponential binomial
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distribution, as defined in MIL-PRF 38535. MIL-PRF 38535 is available for free from
http://www.dscc.dla.mil/Programs/MilSpec/listdocs.asp?BasicDoc=MIL-PRF-38535. The minimum
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number or samples for a given defect level can be approximated by the formula:
N >= 0.5 [Χ2 (2C+2, 0.1)] [1/LTPD – 0.5] + C
where C = accept #, N=Minimum Sample Size, Χ 2 is the Chi Squared distribution value for a 90% CL,
and LTPD is the desired 90% confidence defect level. Table 3-1 is based upon this formula, but in some
cases the sample sizes are slightly smaller than MIL-PRF-38535.

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3.8 Pass/Fail criteria (cont’d)
Table 3-1 — Zero Defect Sample Sizes for Stress Tests

Zero Defect Sampling should be set based on
defect type and process maturity and specific application
Confidence Level (defect rate)
Samples No. of Total 40% 50% 60% 75% 90%
per batch batches Sample
77 3 231 ≤0.2% ≤0.3% ≤0.4% ≤0.6% ≤1.0% *
45 3 135 ≤0.4% ≤0.5% ≤0.7% ≤1.0% * ≤1.7%
30 3 90 ≤0.6% ≤0.8% ≤1.0% * ≤1.5% ≤2.6%
25 3 75 ≤ 0.7% ≤ 0.9% * ≤1.2% ≤1.8% ≤3.1%
15 3 45 ≤1.1% * ≤ 1.5% ≤ 2.0% ≤ 3.1% ≤5.1%
* Suggested sampling per confidence level.
Specific sample plan can be established according to a desired defect rate, and consider the defect type,
process maturity and understanding of device application. Agreement between suppliers and customers is
recommended.
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The confidence levels in Table 3-1 reflect a zero defect sampling response. For instance, reaching 0
defects for 231 samples would demonstrate ≤1.0% defect rate at 90% confidence level. Conversely, for 0
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defects at 90 samples, ≤1.0% defect rate would only carry at 60% confidence.
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However, other equivalent defect rates and confidence levels can also be considered using larger sample
sizes and nonzero fail counts in accordance with the same non-parametric binomial probability. Please
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refer to Annex B for different sampling plan.

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4 Qualification and requalification

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4.1 Qualification of a new device
New or redesigned products (die revisions) manufactured in a currently qualified qualification family may
be qualified using one (1) wafer/assembly lot. Electrical parameter assessment to accompany each test
should be conducted.
4.2 Requalification of a changed device
Requalification of a device will be required when the supplier makes a change to the product and/or
process that could potentially impact the form, fit, function, quality and/or reliability of the device. A list
of changes that may require requalification is shown in clause 6.1.
4.2.1 Process change notification
Supplier should follow the guidelines of J-STD-046 "Guidelines for User Notification of Product/Process
Changes by Semiconductor Suppliers" for product/process notification changes to consider whether
requalification of a device is warranted.

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4.2.2 Changes requiring requalification

All product/process changes should be evaluated against the guidelines listed in Table 6-1.
4.2.3 Criteria for passing requalification

Table 6-1 lists qualification plan guidelines for performing the appropriate Table 5-1, Table 5-3, and
Table 5-4 stresses. Failed devices should be analyzed for root cause and correction; only a representative
sample needs to be analyzed. Acceptable resolution of root cause and successful demonstration of
corrective and preventive actions will constitute successful requalification of the device(s) affected by the
change. The part and/or the qualification family can be qualified as long as containment of the problem is
demonstrated until corrective and preventive actions are in place.
5 Qualification tests
5.1 General tests

Test details are given in Table 5-1, Table 5-3, and Table 5-4. Not all tests apply to all devices. Table 5-1
tests generally apply to design and fabrication process changes. Table 5-3 tests are for non-hermetic
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packaged devices, and Table 5-4 is for hermetic packaged devices. Table 5-2 lists the pass/fail
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requirements for common infant mortality levels. Table 6-1 gives guidance as to which tests are required
for a given process change. Some of the data required may be substituted by generic process or package
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data.
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5.2 Device specific tests
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The following tests must be performed on the specific device to be qualified for all hermetic and plastic
packages. Passing or failing these tests qualifies or disqualifies only the device under qualification and not
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the associated qualification family:

1) Electrostatic Discharge (ESD) - All products. See Table 5-1.
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2) Latch-up (LU) – Required for CMOS, BiCMOS, and Bipolar technologies. See Table 5-1.
3) Electrical Parameters Assessment - The supplier shall be capable of demonstrating, over the
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application temperature range, that the part is capable of meeting parametric limits in the individual
device specification or data sheet.
5.3 Wearout reliability tests

Qualification family testing for the failure mechanisms listed below must be available upon request when
a new wafer fabrication technology or a material relevant to the appropriate wearout failure mechanism is
to be qualified. JP001 lists requirements for Fabrication Process Qualification. JEP122 explains how to
project wearout lifetime for these failure mechanisms. The following mechanisms need to be considered,
but there may be other mechanisms to consider based upon technology details.
 Electromigration; EM
 Time-Dependent Dielectric Breakdown; TDDB or Gate Oxide Integrity Test such as Charge to
Breakdown.
 Hot Carrier Injection; HCI
 Bias Temperature Instability; BTI
 Stress Migration; SM, may be performed on an actual product.
The data, test method, calculations, and internal criteria need not be demonstrated or performed on the
qualification of every new device.

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5.4 Flammability/oxygen index
Certificates of compliance to UL94-0 or ASTM D2863 must be available upon request.
5.5 Device qualification requirements
Table 5-1 — Device qualification tests

Requirements
Stress Ref. Abbv. Conditions
# Lots / SS per lot Duration/Accept
High Temperature JESD22-A108, TJ  125 °C
HTOL 3 Lots/77 units 1000 hrs/ 0 Fail
Operating Life JESD85 Vcc  Vcc max
Early Life Failure JESD22-A108, TJ  125 °C
ELFR See ELFR Table 48  t  168 hrs
Rate JESD74 Vcc  Vcc max
Low Temperature TJ  50 °C
JESD22-A108 LTOL 1 Lot/32 units 1000 hrs/0 Fail
Operating Life Vcc  Vcc max
High Temperature
JESD22-A103 HTSL TA  150 °C 3 Lots/25 units 1000 hrs/0 Fail
Storage Life
Class I or
Latch-Up JESD78 LU 1 Lot/3 units 0 Fail
Class II
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Electrical Parameter
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JESD86 ED Datasheet 3 Lots/10 units TA per datasheet
Assessment
Human Body Model
ESD
JS-001
ESD-
HBM
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TA = 25 °C 3 units Classification
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Charged Device ESD-
JS-002 TA = 25 °C 3 units Classification
Model ESD CDM
Accelerated Soft 3 units
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JESD89-2 and ASER

Error Testing
JESD89-3
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OR TA = 25 °C OR Classification
OR
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System Soft Error Minimum of 1E+06

JESD89-1 SSER
Testing Device Hrs or 10 fails.
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a) HTOL – The duration listed here is generally acceptable to qualify for the given Application Level.
However, it does not necessarily imply the demonstration of the lifetime requirement for a particular use
condition. It depends on failure mechanisms and application environments. For example, with apparent
activation energy of 0.7 eV, 125 °C stress temperature and 55 °C use temperature, the acceleration factor
(Arrhenius equation) is 78.6. This means 1000h stress duration is equivalent to 9 years of use. This might
be shorter than the application requirement. The equivalent life can be even lower for products or
technologies where activation energies are less (e.g., 0.4 eV yields an acceleration factor of ~12 or 1.4
years of equivalent life). In order to assure adequate lifetime requirement, it would be necessary to include
Wafer Level Reliability Test information. Wafer Level Reliability can provide information about long
term or intrinsic reliability of specific die-level wearout mechanisms, the onset to failure time and design
rule (e.g., maximum current density). For many failure mechanisms, such as dielectric breakdown,
elevated voltage will provide additional acceleration and can be used to increase effective device hours or
achieve an equivalent life point with a shorter stress duration. Refer to JEP122 for voltage acceleration
models. Nonvolatile memory devices must be tested for proper operation after HTOL, but testing for data
retention is optional (see Table 5-1a for nonvolatile memory data retention tests).

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5.5 Device qualification requirements (cont’d)
b) ELFR – Several methods can be used to calculate the Early Life Failure Rate (ref. JESD74). The
objective of ELFR is to measure the failure rate in the first several months or year of operation.
Knowledge of the life distribution is generally required to accurately predict ELFR. Equivalently, Table
5-2 can be used to determine sample sizes to satisfy a particular FPM (cumulative failures) target. Voltage
and temperature acceleration may be used to further accelerate effective unit hours. Nonvolatile memory
devices must be tested for proper operation after ELFR, but testing for data retention is optional (see Table
5-1a for nonvolatile memory data retention tests).
c) LTOL – This requirement is aimed at Hot Carrier Degradation and may be satisfied by appropriate wafer
level data as specified in JP001. This test is particularly useful when the wafer level data cannot
demonstrate adequate life. This test should be run at the maximum frequency of the device with speed
parameters data logged. Nonvolatile memory devices must be tested for proper operation after LTOL, but
testing for data retention is optional (see Table 5-1a for nonvolatile memory data retention tests).
d) HTSL – High temperature storage may be accelerated by utilizing a higher temperature; however care
must be taken that failure mechanisms are not introduced such as Kirkendal Voiding occurring at very
high a temperature or suppressing failure mechanisms such as stress migration at temperatures above
180 °C. Alternatively, this test may be performed at the wafer level if packaged device reliability has been
addressed with generic data. Nonvolatile memory devices must be tested for proper operation after HTSL,
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but testing for data retention is optional (see Table 5-1a for nonvolatile memory data retention tests).
e) LU – Verify Vcc overvoltage and I/O trigger current resistance to latch-up per JESD78.
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f) ED – This study is to be performed on key device parameters, it is not aimed at all datasheet
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parameters.
g) ESD-HBM – Classification of Human body Model ESD sensitivity.
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h) ESD-CDM – Classification of Charge Device model ESD sensitivity.

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i) ASER  Accelerated alpha particle and beam soft error testing may be utilized together to project the
field soft error rate. For parts without B10 in the process, the only beam soft error testing required is
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high energy neutron or proton soft error testing; thermal neutron soft error beam testing is not
required for such parts. This test is required for devices with a significant portion of the circuit
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utilizing volatile memory elements or latches. Generic data taken on products or test devices with
similar memory elements or latches and equivalent critical charge may be substituted.
j) SSER  System soft error testing requires enough device hours to be accumulated to produce 10
failures or at least 1E6 device hours must be accumulated. High altitude testing may be used to
accelerate this stress. This test may be utilized in lieu of or in addition to accelerated soft error testing.
Generic data taken on products or test devices with similar memory elements or latches and
equivalent critical charge may be substituted.

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Table 5-1a — Additional qualification tests for nonvolatile memory device

Requirements
Stress Ref. Abbv. Conditions #
Lots/SS Duration/ Accept
per lot
Nonvolatile FG-CT TA  125 °C
Memory 1000 hrs/
3 Lots/
Uncycled High JESD22-A117 UCHTDR
Temperature PCM TA  90 °C 77 units 0 Fail/ note (a)
Data Retention
Nonvolatile 25 °C and Up to Spec. Max

3 Lots/
Memory Cycling JESD22-A117 NVCE 85 °C ≥TJ  77 units
Cycles per note (b)
Endurance 55 °C / 0 Fails
Option 1: TJ = 100 °C Cycles per NVCE
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(55 °C)/ 96 and
FG-CT
1000 hrs / 0 Fail /
Nonvolatile
Memory Post-
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3 Lots/
note (c)
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cycling High JESD22-A117 PCHTDR
Temperature 39 units
Option 1: TJ = 90 °C Cycles per NVCE
Data Retention
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(55 °C) / 10 and

PCM
100 hrs / 0 Fail /
Option 2: TJ  100 °C note (c)
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Nonvolatile
Memory Low- Cycles per NVCE
3 Lots/
Temperature JESD22-A117 LTDDR TA = 25 °C (25 °C) / 500 hrs /
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38 units
Data Retention 0 Fail / note (d)
and Read Disturb
NOTE FG-CT are intended to denote Floating Gate and Charge Trapping memories whereas PCM denotes Phase
Change memories.
a) UCHTDR – Uncycled nonvolatile memories data retention failure mechanisms are generally
accelerated by temperature and are modeled using the Arrhenius Equation for acceleration. The
duration listed is generally acceptable for qualification but do not necessarily demonstrate the
retention requirement for a particular use condition, which depends on failure mechanisms,
acceleration factors and application environment. If the application requirement does not match the
UCHTDR test’s retention values then a knowledge-based qualification should be followed (see
JESD94). For devices specified to have some non-zero bit error rate, bit errors may not be counted
towards device failure but must be shown to meet the bit error rate specification (see JESD22-A117).

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b) NVCE  Figure 1 describes the flow for NVCE, PCHTDR and LTDDR. 38 units are cycled at room
temperature and 39 units are cycled at elevated temperature.
Quantity of Cycling: Cycling should be performed to the max spec. cycle count on 50% of cells and to
10% of max spec. cycle count on the other 50% of cells when this is possible within 500 hours. For large
memories where this is not possible, the total program/erase operations are to be the number possible in
500 hours. This will be accomplished by reducing the fraction of cells cycled to max spec. and increasing
the fraction cycled to 10% of max spec. In some cases it will be necessary to cycle some fraction of cells
to less than 10% of max spec. to ensure that all cells receive some cycling, excluding any limited number
of uncycled sectors which are used as a reference for post-cycling comparison. At least one-third of the
operations should be devoted to cycling blocks to 100% of maximum specification, if possible within the
specified cycling time frame. For multi-block memories, at least one block of each device must be cycled
to the max. spec. cycle count, regardless of the time required. Such cycling conditions are generally
acceptable also for system implementing wear leveling; otherwise, a knowledge based qualification can be
implemented.
Delays and Cycling Rate: The supplier may specify that cycling not exceed a certain rate per day or that
delays or bakes be inserted between cycles, to avoid overstress due to unrealistic conditions or to emulate
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delays expected in intended application. Consider these five constraints:
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1. The quantity of cycling is for 500 hours of actual cycling operations, not counting inserted delays.
2.
3.
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Inserted delays must be distributed per the guideline in JESD22-A117.
For room-temperature cycling, no high-temperature delays are to be inserted.
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4. For high-temperature cycling, the delays plus the cycling time itself must not add up to more than 500
hours at 85 °C (longer delays acceptable at lower temperatures per JESD22-A117, 4.1.2.4).
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5. If the cycling activation energy is significantly lower than 1.1eV, cycling temperatures higher than
85 °C are allowed, with a strong technical justification consistent with JESD94.
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These delays do not necessarily demonstrate the effect that would be seen with a particular use condition.
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For example, with apparent activation energy of 1.1 eV for dielectric charge detrapping, the delay
durations are equivalent to 1.5 years of cycling at 55 °C. An application condition with less delay would
be more severe than is represented by the qualification delays specified above. If application use
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conditions deviate considerably from the cycle counts or equivalent times described above, then an
application-specific qualification methodology can be pursued per JESD94. For devices operated with
Bad Block Management and specified to have a non-zero bad-block rate, a unit with blocks failing
program/erase is to be counted as a failure if the number of such blocks exceeds the allowed bad-block
specification (see JESD22-A117, 2.5). For devices specified to have some non-zero bit read error rate, bit
errors are not to be counted towards device failure but must be shown to meet the bit error rate
specification (see JESD22-A117, 2.8, and 5.2).
c) High Temp NVCE + PCHTDR  Figure 1 describes the flow for PCHTDR. Units sent through High
Temperature NVCE are placed in high-temperature retention bake. Two options are given, either of which
is acceptable for qualification, and for each option, there are two bake durations. The longer of the two
durations is to be applied to the blocks cycled to  10% of the max. spec. cycles. The shorter of the two is
to be applied to blocks cycled to 100% of max. spec. cycles. For example option 2 requires that blocks
cycled to  10% of max. spec. cycles retain data for 100 hours of 125 °C (FG-CT)/100 °C (PCM) bake,
and blocks cycled to 100% of max. spec. cycles must retain data for 10 hours of 125 °C (FG-CT)/100 °C
(PCM) bake. The durations listed are generally acceptable for qualification but do not necessarily
demonstrate the retention requirement for a particular use condition, which depends on failure mechanisms
and application environments. For example, with activation energy of 1.1 eV for dielectric charge
detrapping, 125 °C stress temperature (option 2) and 55 °C use temperature, the acceleration factor
(Arrhenius equation) is 939.

Page 11

Bake time is then equivalent to 11.3 years for 10% of max. spec. cycles and 1.1 years for 100% of max.
spec. Retention lifetime necessary in use will be less than total product lifetime, because the PCHTDR
requirement is a sequential reliability stress that is preceded by up to one lifetime’s worth of endurance
cycling (NVCE). If the application requirement does not match these retention values, or the technology
has different activation energy, then a knowledge-based qualification should be followed (see JESD94).
For devices specified to have some non-zero bit error rate, bit errors may not be counted towards device
failure but must be shown to meet the bit error rate specification (see JESD22-A117).
d) Room Temp NVCE + LTDDR  Figure 1 describes the flow for LTDDR. Units sent through Room
Temperature NVCE are placed into room-temperature operating-life stress which sequentially
performs dynamic read accesses on all memory addresses. 25 °C stress temperature is used to
determine sensitivity to non-temperature-accelerated retention failure mechanisms, or to mechanisms
that can entirely recover at high temperatures, such as the SILC mechanism. Biased life stress is
performed to detect voltage-induced disturbs due to random bit accesses, in addition to unbiased data
retention mechanisms which occur when a bit is not being accessed. Inserted bakes as described for
NVCE are not acceptable for the 25 °C cycling condition used prior to LTDDR. If the cycle counts
from note (b) or the retention lifetimes of 500 hours are insufficient to meet a specific application
requirement, or if bit accesses in application are expected to be highly concentrated on specific bits,
l
then knowledge-based qualification methods using special techniques should be used (see JESD94).
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Note that at the end of the NVCE + LTDDR test, data retention must be verified. For devices
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specified to have some non-zero bit error rate, bit errors may not be counted towards device failure
but must be shown to meet the bit error rate specification (see JESD22-A117).
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77 Units/Lot
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38 units 39 units
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Room Temp NVCE High Temp NVCE

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Room-temperature cycling per table. P/E cycle at 55 °C to 85 °C Cycling time plus

No inserted high-temperature delays any inserted delays must be ≤ 3 weeks at 85 °C
LTDDR PCHTDR
Dynamic life test High-temperature bakes as follows:
Room temperature FG-CT PCM
Cycle
500 hr Option 1 Option 2 Option 1 Option 2
Count
100 °C 125 °C 90 °C 100 °C
100%
96 hr 10 hr 96 hr 10 hr
spec
10%
1000 hr 100 hr 1000 hr 100 hr
spec
<10%
1000 hr 100 hr 1000 hr 100 hr
spec
Figure 1 — NVCE/PCHTDR/LTDDR

Page 12
Table 5-2 — Minimum sample size to demonstrate various ELFR targets in FPM
(Failures per million) at 60% confidence level
Equivalent Minimum sample sizes required to meet FPM target
Number of failures at at 60% confidence level
observed 60% 4000 2000 1000 500 250 100
failures Confidence
Level (X2 /2) FPM FPM FPM FPM FPM FPM
0 0.92 229 458 916 1,833 3,665 9,163
1 2.02 505 1,011 2,022 4,045 8,089 20,223
2 3.11 778 1,553 3,105 6,211 12,422 31,054
3 4.18 1004 2,088 4,175 8,351 16,701 41,753
4 5.24 1310 2,618 5,237 10,473 20,946 52,366
5 6.29 1573 3,146 6,292 12,584 25,168 62,919
6 7.34 1835 3,671 7,343 14,685 29,371 73,426
7 8.39 2098 4,195 8,390 16,780 33,559 83,898
8 9.43 2358 4,717 9,434 18,868 37,736 94,340
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9 10.48 2620 5,238 10,476 20,951 41,903 104,757
10 11.52 2800 5,758 11,515 23,031 46,061 115,153
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Page 13
5.6 Nonhermetic package qualification test requirements
Table 5-3 — Qualification tests for components in nonhermetic packages

Requirements
# Lots /
Stress Ref. Abbv Conditions
SS per Duration /Accept
lot
MSL Preconditioning
Must be performed
JESD22 - Per appropriate MSL level Electrical Test
prior to: THB, PC
A113 per J-STD-020 (optional)
HAST,TC, AC, &
UHAST
JESD22-
High Temperature 150 °C + Preconditioning if 3 Lots /
A103 & HTSL 1000 hrs / 0 Fail
Storage1 Required 25 units
A113
Temperature2
JESD22- 85 °C, 85 % RH, Vcc max 3 Lots /
Humidity bias THB 1000 hrs / 0 Fail
A101 25 units
(standard 85/85)
Temperature2, 3
96/264 hours or
Humidity Bias
l
JESD22- 130 °C / 110 °C, 85 % RH, 3 Lots / equivalent per
ta
( Highly Accelerated HAST
A110 Vcc max 25 units package construction /
Temperature and
0 Fail
Humidity Stress) gi
B 4 -55 °C to +125 °C 700 cycles / 0 Fail
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G 4 -40 °C to +125 °C 850 cycles / 0 Fail
JESD22- 3 Lots /
Temperature Cycling TC C 4 -65 °C to +150 °C 500 cycles / 0 Fail
A104 25 units
K 4 0 °C to +125 °C
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1500 cycles / 0 Fail

J4 0 °C to +100 °C 2300 cycles / 0 Fail
Unbiased
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JESD22- 130 °C / 85% RH 3 Lots / 96 hrs / 0 Fail

Temperature/Humidity UHAST
A118 110 °C / 85% RH 25 units 264 hrs / 0 Fail
(Unbiased HAST3)
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Unbiased
JESD22- 3 Lots / 96 hrs / 0 Fail
Temperature/Humidit AC 121 C / 100% RH
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A102 25 units Not Recommended

y (Autoclave5)
JESD22- 30 balls /
Solder Ball Shear SBS Characterization
B117 5 units
1 Lot /
Characterization, Pre Ppk≥1.66
Bond Pull Strength7 M2011 BPS 30 bonds
Encapsulation or Cpk≥1.33 (note 6)
/ 5 units
1 Lot /
JESD22- Characterization, Pre Ppk≥1.66
Bond Shear7 BS 30 bonds
B116 Encapsulation or Cpk≥1.33 (note 6)
/ 5 units
M2003
3 lots /
Solderability J-STD- SD Characterization 0 Fail
22 leads
002
JESD22-
A121 See JESD201, Based
Tin Whisker Characterization per See
through WSR on Appropriate
Acceptance JESD201 JESD201
rqmts of Classification
JESD201

Page 14
5.6 Nonhermetic package qualification test requirements (cont’d)

Notes to Table 5-3 — Qualification tests for components in nonhermetic packages
NOTE 1 Preconditioning to JESD22-A113 is recommended, specifically for wire-bonded products qualified to Pb-free reflow
profiles. Moisture soak as part of the preconditioning is optional.
NOTE 2 Either HAST or THB may be chosen.
NOTE 3 If THB or HAST is run, then UHAST need not be run.
NOTE 4 It is recommended that the Temperature Cycling condition is chosen applying the following criteria:
 Condition G, B or C may not be appropriate unless the device will be subjected to a sub 0 C cycle in its routine field
operating life.
 Condition G, B or C may not be appropriate for Flip Chip packages with organic substrates.
 The condition chosen should encompass the range that device will be subjected to in its routine field operating life.
 Annex A explains the failure mechanisms and models used for the choice of temperature cycling conditions. Please refer to
JEP122 for reliability models and JESD94 for application-specific test method when selecting a different test condition or
defining a different test duration. Selection should correspond to a targeted failure mechanism and reconcile with application
and use condition if possible because stress test durations can be quite different depending on the coefficient value (n).
 Any Temperature Cycling condition specified in JESD22-A104 may be used following the methodology in Annex A. Different
conditions may be established per supplier and customer agreement.
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NOTE 5 Autoclave is not recommended as a qualification test; Unbiased or biased HAST is the recommended stress and is
required for organic substrates instead of Autoclave.
x  LSL USL  x gi
NOTE 6 Ppk = ,  1.66 . Process capability data may be substituted for Ppk with data on more than 30
3 3
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lots with the requirement that Cpk  1.33 .
NOTE 7 See 7.1 for Bond Shear and 7.3 for Bond Pull Strength failure criteria.
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CONDITIONS:
A) HTSL This test is basically used to determine if the effects of diffusion, oxidation, intermetallic growth, and
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chemical degradation of packaging components will affect product life.

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B) THB will accelerate the three basic corrosion models: Galvanic, Electrochemical and direct Chemical. It will
also accelerate ion migration. Must be run at minimum power dissipation.
C) HAST is a test used to accelerate the THB test. Must be run at minimum power dissipation. It is suggested
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that 130 °C for 96 hours be used for leaded devices and 110 °C for 264 hours be used for Ball Grid Arrays.
D) TC will accelerate damage caused by thermal-mechanical stress as a result of thermal mismatch and
dimensional differences.
E) UHAST is the preferred technique to test for Galvanic and direct Chemical corrosion.
F) AC (Autoclave) is the less desirable alternative to UHAST testing. It can introduce condensation and pressure
induced mechanical damage that are not representative of package field life stresses. Autoclave is not
recommended for organic substrate packages.
G) PC (Pre-Conditioning) ensures that a device will be able to withstand multiple assembly cycles, and to
simulate the stress from Printed Circuit Board assembly that a device in a field operation would receive prior to
acceleration stress testing.
H) SBS (Solder Ball Shear) ensures that the BGA balls have the desired shear strength attachment to the package.
I) BPS (Bond Pull Strength) ensures that wire bond exhibits the desired tensile strength. See 7.3 for failure
criteria.
J) BS (Bond Shear) ensures that the wire ball bond exhibits the desired shear strength. See 7.1 for failure criteria.
K) SD (Solderability) ensures that the device leads are capable of being wetted by the board attachment solder.
L) WSR (Tin Whisker Susceptibility) for use when tin (Sn) or tin alloy surface finishes are used. This acceptance
procedure provides a basis for comparison between surface finishes with respect to the propensity for whisker
growth, but does not provide a basis for prediction of whisker growth in field use conditions.

Page 15
5.7 Hermetic package qualification tests

These packages are typically used in long term applications and severe environments so some
requirements may be different than for non-hermetic packages.
Table 5-4 — Qualification test for components in hermetic packages
Requirements
Stress Ref. Abbv. Conditions
# Lots/SS per lot Duration/Accept
-55 °C to +125 °C or
JESD22- 3 Lots / 25 700 cycles / 0
Temperature Cycling TC alternatives with temperature
A104 units Fail
justification
1 lot / 30 bonds Ppk ≥ 1.66
Bond Pull Strength 3,4 M2011 BPS Characterization
/ 5 units or Cpk ≥ 1.33
JESD22- 1 lot / 30 bonds Ppk ≥ 1.66
Bond Shear 3,4 BS Characterization
B116 / 5 units or Cpk ≥ 1.33
M2003 3 lots /
Solderability SD Characterization 0
J-STD-002 22 leads
JESD22- 5
Solderball Shear SBS Characterization 10 balls per unit
B117 units
JESD22- Y1 plane only, 5 pulses, 0.5
Mechanical Shock1 B104 MS ms duration, 1500 g peak 3 lots / 39 units TEST after CA
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M2002 acceleration
20 Hz to 2 kHz (log
JESD22-
Vibration Variable
Frequency1
B103
M2007
VVF gi
variation) in > 4 minutes, 4X
in each orientation, 50g peak
Sequence from
MS
TEST after CA
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acceleration
Y1 plane only, 30 kg force Test at room
Constant Sequence from
M2001 CA <40 pin packages, 20 kg temp. pre & post
Acceleration1
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VVF
for > 40 pins. –stress
JESD22-
Any fine test followed by gross test. May also be performed at the
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Gross /Fine Leak A109 GFL

beginning of the mechanical sequence before mechanical shock test.
M1014
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1
External Visual EV
2
Physical Dimensions PD 1 lot / 30 units
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45 leads; min 1
Lead Integrity LI
of 5 units
1
Lid Torque LT 1 lot / 5 units
Residual Gas Analysis of
MIL-STD 3 lots / 1 unit
Internal Water Vapor IWVC Package Cavity Water Vapor Characterization
883 M1018 ea.
Content
See JESD201,
Tin Whisker JESD22- Characterization per Based on
WSR See JESD201
Acceptance A121 JESD201 Appropriate
Classification
NOTE 1 Based upon manufacturer specification or applicable procurement documents.
NOTE 2 Reference applicable JEDEC spec, supplier specification, or procurement document for significant dimensions and tolerances.
x  LSL USL  x
NOTE 3 Ppk  ,  1.66 . Process capability data may be substituted for Ppk with data on more than 30 lots with the
3 3
requirement that Cpk  1.33 .
NOTE 4 See 7.1 for Bond Shear and 7.3 for Bond Pull Strength failure criteria
5.8 Additional Device Information

Any additional information (e.g., device construction, materials, manufacturing locations, etc.) should be
reported in accordance with JESD69 Information Requirements for the Qualification of Silicon Devices.

Page 16
6 Explanatory comments regarding process/product changes
6.1 To conform to J-STD-046, the following are typical changes that require re-qualification
Active Circuit Element: New type of circuit element or modification of transistors beyond original
qualification or spec limits.
Major Circuit Elements: Addition of a major new circuit block to an existing circuit such as adding a
Digital Signal Processor or embedded memory block to an existing product.
Wafer Diameter Change
Metallization: New Materials or a significant change in composition
Change In Minimum Feature Size: A reduction of greater than 20% shall be considered a new process.
Wafer Fab Process: Utilizing different process techniques at critical points (excluding wafer transport
equipment)
Diffusion/Dopant: New material or technique
Polysilicon or other MOSFET gate material: Composition, design rules, process
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Lithography: Change in wavelength, method (air / immersion / ebeam), or etch technique
gi
Wafer Frontside Metallization: Composition, design rules, process and/or technique
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VIA: Composition, design rules, process and/or technique
Passivation Overcoat: Either glass or organic material composition, design rules, process and/or technique
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Dielectric Materials: Composition, design rules, process and/or technique

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Low-K Dielectric: A dielectric material used for inter-metal isolation with a K value less than 3.2.
Wafer Backside Operation: Metal composition, design rules, process and/or technique
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New Wafer Manufacturing Line: Not already qualified for the fabrication process
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Assembly Process: Utilizing different process techniques at critical points

Die Coating: Material, process, and/or technique
Lead Frame: Base material, finish, and critical dimensions
Bond Wire: Material, diameter
Bonding: Process and/or technique
Die Preparation: Separation and clean methods
Die Attach: Material, process, and/or technique
Encapsulation: Material, composition, process and/or technique
Hermetic Package: Material, composition, seal material, process and/or technique
Wafer Bumping Material: process, or technique (including flip chip assembly process)
Package Dimension Change: Larger package body size or reduction in lead or solder ball pitch.
Die Thickness
New Chip-Package Combination

Page 17
6.2 Changes that may not require re-qualification
Previously qualified foundries or assembly locations, unless the previously qualified facility, or
packages/products from said facility, have been dormant, suspended or discontinued for a period longer
than three years.
The addition of previously qualified equipment requires completion of process capability study only, to
assure that the added equipment delivers an adequate process distribution.
A change to a test program or test equipment requires proof of continued conformance to product
specification only.
Any change in a process, product or material parameter that does not exceed the current specified
production process range is not a major change.
Minor changes to device logic operation may only require functional verification.
Smaller package or die where the product family has already been qualified.
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6.3 Multiple family qualifications
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When the specific product attribute to be qualified will affect more than one wafer fab or assembly family,
the qualification test vehicles should be:
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1) One lot of a single device type from each of the three (3) products that are projected to be most
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sensitive to the changed attribute, or

2) Three lots total from the most sensitive families if only one or two exist.
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The following is the recommended process for qualifying changes across many process and product
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families:
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1) Identify all products affected by the proposed changes.

2) Identify the critical structures and interfaces potentially affected by the proposed change.
3) Identify and list the potential failure mechanisms and associated failure modes for the critical
structures and interfaces. Note that steps 1 to 3 are equivalent to the creation of an FMEA.
4) Define the product groupings or families based upon similar characteristics as they relate to the
structures and device sensitivities to be evaluated, and provide technical justification for these
groupings.
5) Provide the qualification test plan, including a description of the change, the matrix of tests and the
representative products that will address each of the potential failure mechanisms and associated
failure modes including any justifiable generic family data.
6) Robust process capability must be demonstrated at each site (e.g., control of each process step,
capability of each piece of equipment involved in the process, equivalence of the process step-by-step
across all affected sites) for each of the affected process steps.

Page 18
6.4 Guidelines for stress tests for product/process changes
Table 6-1 lists the recommended (R) qualification tests for each type of change in the process, package, or
device design, and additional tests that should be considered (C) based upon technology considerations.
Table 6-1 — Guidance for selection of tests per product/process changes
T
N E E
H
V S S U
H E L H A B T
C D D H B S V G B
T L T T L E S / T B S M C L L E H D
Process Attribute E - - A P B V F T
O F O S U D E H C S D S A I T M C D
+ H C S S S F L I
L R L L R A B
D B D T
S
R M M
T
Active Circuit Element C C R R
Major Circuit Change R C C C C C
5% to 20% Die Shrink R R C C R R R R R R C C R R
Lithography C C R C C
Doping C C C R R
Polysilicon C R R R R C
Metallization C C R C R C R
Gate Oxide R C C R C R R R
Interlayer Dielectric Non
C C C C R C
low-k
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Low-K Dielectric R C R R R R C
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Passivation C C C C C R
Contact C C R C R
Via
Bump Site
C C R
R *
giR
R
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Wafer diameter R C C R C C C R C R R R R
Wafer Bump Materials
C * R R
or Process
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Wafer Bump Under-

R * C R
Metal
Wafer Saw Technique C C
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Fab site R R C R C
New Package to
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C C C C R R R R R R R R R R R C
Qualified Product
Leadframe plating1 R C
Leadframe Material C R C C R
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Package Dimensions,
C C C C C C C
including trace pitch
Wire Bonding R C R C R R C C
Multi-Chip Module Die
R C
Separation
Die Attach R C C C C
Die thickness C C R R
Molding Compound C R R R
Package Substrate
C R R C C C
Material
Package Substrate
C R R
Plating
Molding Process C R C
Flip Chip Attach Method C R R
Flip Chip Underfill * R R
Assembly Site R R R R R R C C C C C C
Burn-in Elimination R
Burn-in Reduction** C
R – Recommended * - Measure material alpha emissivity
C – Consider ** - May be based upon defect density reduction with justification
NOTE 1 Additional consideration may be necessary when evaluating product changes with respect to tin whiskers.
Consult JESD201 when making changes involving high tin content materials. A separate table is located in
JESD201 that addresses whisker test requirements based on various types of changes.

Page 19
7 Wire bond qualification requirements
7.1 Failure criteria for wire bond shear test method (JESD22-B116) of unencapsulated and
unstressed bonds
The following failure criteria are intended to be applied as a production monitor of the wire bonding
process as well as for qualification and process development. They are not valid for devices that have
undergone environmental stress testing, have been desoldered from circuit boards, or were preconditioned
(some procurement or qualification documents require that the samples be preconditioned prior to the
performing of this test method).
Please refer to 4.6 in JESD22-B116 for guidance on acceptable and non-acceptable fail modes.
7.1.1 Shear failure criteria for gold and copper ball bonds on aluminum bond pads
The equation below is applicable for “gold” and “copper” wire ball bonds on aluminum alloy bond pads.
“Gold” wire includes doped gold wire. “Copper” wire includes palladium coated copper, palladium
coated copper with gold flash, and doped copper wires.
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The determination of whether a shear value is acceptable is determined by using the equation below.
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(measured shear force value ÷ ball bond area) ≥ 0.0062 gf/m2
di
The above shear failure criteria shall be applied to all copper ball bonds on aluminum bond pads. This
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criteria shall also be applied to all new device qualifications with gold ball bonds on aluminum bond
pads. Previously qualified devices with gold ball bonds on aluminum bond pads may either meet the
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above criteria or the previous criteria stated in Table 5-1 of JESD-B116A (August 2009).
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If alternate units of force or area are used for this test, the value of 0.0062 gf/m2 shall be replaced with
one of the following appropriate conversions: 61 N/mm2 or 4.0 gf/mil2.
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Alternate minimum bond shear values may be proposed by the supplier if supporting data justifies the
proposed minimum values and the customer agrees.
Other material combinations (wire and/or bonding surface) may require a new set of failure criteria.
7.1.2 Shear failure criteria for gold and copper ball bonds on copper base metal bonding surfaces
At the time of the most recent revision of this document there was not enough data available to propose a
value for acceptable shear force for gold or copper ball bonds on copper base metal bonding surfaces.
7.2 Failure criteria for wire bond shear test method (JESD22-B116) for encapsulated and
stressed bonds
There is too much variability between device construction, decapsulation processes, and stress conditions
for this document to propose failure criteria for the shearing of ball bonds that have been decapsulated or
have been exposed to production or qualification stresses.

Page 20
7.3 Failure criteria for wire bond pull testing (Mil-Std 883, Method 2011)
At the time of the most recent revision of this document there was not enough data available to propose a
value for acceptable pull force for copper wire bonds. The failure criteria for unstressed, unencapsulated
gold bond wires currently reside within Mil-Std 883, Method 2011.
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Page 21
Annex A (informative) Nonhermetic Package Temperature Cycling Variations for Solder Joint
Solder joint Reliability is generally the limiting factor for component life in a system subjected to
temperature cycling. Solder joint life is well modeled by a Coffin-Manson relation of ∆Tn where n=2
(e.g., board level / SMT attach – solder joint fatigue). Other failure mechanisms as reported in JEP122
have larger acceleration factors so this is considered a worst case condition. The temperature cycling
requirements have been normalized to the historical requirement of 500 cycles of Condition C using the
n=2 factor. As a sanity check the typical use conditions for a number of common applications have been
compared to these qualification conditions. As can been seen in the table below the qualification
requirements exceed the use conditions by a wide margin.
Table A — Nonhermetic package temperature cycling variations

Equivalent Equivalent Equivalent
Use Condition Condition B Condition G Condition J
Use Condition
Requirement -55 °C to +125 °C -40 °C to +125 °C 0 °C to +100 °C
700 cycles 850 cycles 2300 cycles
14,175 cy 14,463 cy 14,375 cy
l
Desktop ∆T 40 °C
ta
(12,475 cy)* (12,761 cy)* (12,675 cy)*
5 yr Life 2000 cy
(11,057 cy)** (11,332 cy)** (11,250 cy)**
Mobile
4 yr Life
∆T 15 °C
1500 cy
100,800 cy gi 102,850 cy 102,221 cy
di
Server ∆T 40 °C
14,175 cy 14,463 cy 14,375 cy
11 yr Life 44 cy
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Telecom
(uncontrolled) /
∆T 25 °C
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Avionics 36,288 cy 37,026 cy 36,800 cy

5500 cy
Controlled
es
15 yr Life
Telecom
∆T 6 °C
W
(controlled) 630,000 cy 642,812 cy 638,889 cy

5500 cy
15 yr Life
Networking ∆T 30 °C
25,200 cy 25,712 cy 25,557 cy
10 year Life 3000 cy
*JESD94, Table 5-1, Consider desktop with add’l ∆T 8 °C for 31,025 cycles and ∆T 20 °C for 1828 cycles
** Consider Desktop with additional ∆T 10 °C for 50,000 cycles

Page 22
Annex B (informative) Sampling options with nonzero failures
Table B provides a list of sampling plans with varying Lot Tolerance Percent Defect (LTPD) and defect
quantity. Each column value – LTPD – corresponds to a demonstrate defect rate that is achieved when
the defect does not exceed the acceptance number.
For instance, setting qualification requirements of LTPD=1, then for a sampling of n=230, 0 rejects would
be permitted. Conversely, if 668 samples were tested, then to achieve LTPD=1, the corresponding
maximum number of rejects would be 3 assuming that failures were equally distributed (based on
consecutive sampling).
Table B — Sample size for a maximum % defective at a 90% confidence level

Acceptance
LTPD LTPD LTPD LTPD LTPD LTPD LTPD
Number
C 10 7 5 3 2 1.5 1
0 22 32 45 76 114 153 230
1 38 55 77 129 194 259 389
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2 53 76 106 177 266 355 532
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3 67 96 134 223 334 446 668
4
5
80
94
115
133
160
186
267
310
gi 400
465
533
619
800
928
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6 107 152 212 352 528 703 1054
7 119 170 237 394 590 786 1179
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8 132 188 262 435 652 868 1301

9 144 205 287 476 713 949 1423
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10 157 223 311 516 773 1030 1543

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11 169 240 335 556 833 1110 1663

12 181 258 359 596 893 1189 1782
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Page 23
Annex C (informative) Differences between revisions
Summary of changes made to entries that appear in this standard, JESD47K, compared to its predecessor,
JESD47J.01 (September 2017).
C.1 Differences between JESD47K and JESD47J.01
Clause Description of Change

1, 3.1 Scope clarification for potential tailoring of requirements based on device application and use
condition.
2.1, 2.2 Update references (MIL-PRF-38535, JESD91, JEP156)
3, 5, 6 Re-numbering Tables for consistency (Table A to Table 3-1, Table 1 to 5-1, Table 1a to Table 5-
1a, Table B to Table 5-2, Table 2 to Table 5-3, Table 3 to Table 5-4 and Table 4 to Table 6-1)
3.6 Temperature considerations for electrical testing post stress test
3.2, 3.7 Reference to JEP156
3.8 Table 3-1 clarification and usage
4.2, 4.2.1 Requalification consideration
5.2 Replacement of organic package
5.5 Clarification for HTOL example (eV, acceleration factor impact) and HTSL (defect occurrence)
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Table 5-1 Clarification on JESD89-1 or JESD89-2 and JESD89-3 test selection
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Table 5-1a Alignment for FG-CT and PCM options with Figure 1 flowchart and update LTDDR
5.5 b), c) Improve readability for descriptive test steps
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5.5 d) Update to LTDDR (Low Temperature Data Retention and Read Disturb) per Figure 1
5.6 Typesetting correction (NOTE) per revised JEDEC manuals and clarification on selection of stress
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test condition
5.8 Expanding clause – previously omitted
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Table 6-1 Title clarification

6.1, 6.2 Alignment with 4.2, 4.2.1 – requalification considerations (J-STD-046 and other changes)
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6.3 Generic data use

Annex A Clarification on CM parameter (solder joint fatigue)
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Annex B New, for legacy purposes, the Sampling table ( previously listed as Table 3-1)
C.2 Differences between JESD47J.01 and JESD47J (August 2017)

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7.1.1 2nd paragraph, changed equation from “(measured shear force value ball bond area) ≥
0.0062 gf/m2”, to “(measured shear force value ball bond area) ≥ 0.0062 gf/m2”
C.3 Differences between JESD47J and JESD47I.01 (October 2016)

5.6 In Table 5-3 modified sample requirement for wire pull and bond shear to be from 1 Lot which
now matches requirement in Table 5-4. Added Footnote 7 which states that failure criteria for
bond pull strength and bond shear are in new subclauses 7.3 and 7.1 respectively
5.7 Added Footnote 4 which states that failure criteria for bond pull strength and bond shear are in
subclauses 7.3 and 7.1 respectively
6.4 Added “C” (Consider) for THB/HAST stress for Wire Bonding
7 Added new clause 7, “Wire bond qualification requirements”. Subclause 7.1 states the failure
criteria for the bond shear test for both gold and copper ball bonds on aluminum bond pads.
Subclause 7.2 provides guidance for performing shear testing on bonds that have been
encapsulated or stressed. Subclause 7.3 provides guidance regarding the failure criteria for the
wire pull test method.

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C.4 Differences between JESD47I.01 and JESD47I (July 2012)

2.2 Added JS-001, JS-002, and J-STD-002 to References. Removed JESD22-A121 specific reference.
5.5 Table 5-1 CDM spec reference changed to JS-002 from JESD22-C101
5.5 Changed “resistance” to “sensitivity” in notes g) and h)
5.6 Table 5-3 Solderability spec reference changed to J-STD-002 from JESD22-B102
5.7 Table 5-4 Solderability spec reference changed to J-STD-002 from JESD22-B102
C.5 Differences between JESD47I and JESD47H.01 (April 2011)

1 Added material to 2nd and 5th paragraph and removed material in Scope
5.5 add last sentence to a), b), c), and d)
Figure 1 Added details for PCM
Global changed Ta to TA and changed Tj to TJ
C.6 Differences between JESD47H.01 and JESD47H
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Table 5-1 Updated Human Body Model reference from JESD22A-114 to JS-001
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C.7 Differences between JESD47H and JESD47G.01

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Table 5-1 001Updated Latchup requirements to align with latest revision of JESD78
C.8 Differences between JESD47G.01 and JESD47G

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Table 5-1 Under latch-up changed Conditions, from TA = 25 °C and Tjmax to Class I or Class II.
5.5(h) Added “per JESD78” to end of sentence.
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C.9 Differences between JESD47G and JESD47F

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Page Description of Change

7 In Table 5-1, NVCE, change temperature range to 85°C ≥ TJ  55 °C and add fail criteria (0 fails)
7 In Table 5-1, LTDR, change reference document to JESD22-A117
7 In Table 5-1, NVCE, HTDR and LTDR entries, add number of note.
8 note (e): Specify fraction of device that needs to be cycled 100%, 10% and less than 10% of endurance
spec. Specify constrains for delays between cycles
9 note (e): In definition of failure, add consideration of Bad Block management and allowed bit-error rate.
9 note (f), (g): In definition of failure, add consideration of allowed bit-error rate
10 Figure: Set NVCE temperature range to 85°C ≥ TJ  55 °C, remove table redundant to note (e),
C.10 Differences between JESD47F and JESD47E
In 2.2; added references, JESD201 and JESD22A121

In Table 5-3; added “Tin Whisker Acceptance” row
In Table 5-4; added “Tin Whisker Acceptance” row
In 6.4, Table 6-1; under “New package to Qualified Product”, changed ESD-HBM from “R” to blank (no
requirements) and ESD-CDM from “R” to “C”. Added reference 1 below table

Page 25
C.11 Differences between JESD47E and JESD47D
This summary briefly describes most of the changes made to entries that appear in this standard, JESD47E,
compared to its predecessor, JESD47D (November 2004). Some punctuation changes are not included.
JESD47E is a complete rewrite of the Specification for Stress Driven Qualification of Integrated Circuits. Every
section was upgraded. This document lists the major changes by section. Many changes are for clarification or to
conform to current JEDEC specification formats.
1. Scope: Updated references to allied JEDEC specifications that address similar issues.
2. Reference Documents: A more complete and current list is provided.
3. General Requirements: Clarifies using family qualification and generic data. Breaks up qualification into
Silicon and Package Requirements. Clarifies use of Χ2 distribution for generic and larger sample sizes. Gives
guidance on the use of accelerated voltage stressing in addition to temperature.
4. Qualification and Requalification: No major changes
5. Qualification Tests: Test information is organized by fabrication process and package requirements.
Information regarding a test is contained within a single table. More extensive reference to requirements for
wearout testing and reference to JP001 Fabrication Process Qualification. Sample sizes were reduced for many
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tests that are intrinsic wearout mechanisms. The traditional 77 piece per lot sample size was only retained for
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lifetest and nonvolatile memory endurance for which defect mechanisms are significant contributors to the
observed failure rate.
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Extensive notes were added to explain test methodologies.
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a. Early Life Failure Testing: The methodology was specified and requirements were enumerated in Table 5-
2.
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b. Low Temperature Operating Life: Minimum temperature was raised max frequency operation required,
can be replaced by wafer level HCI testing.
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c. NonVolatile memory: Endurance and Data Retention methodology was changed along with test method
JESD22-A117 and JEP122.
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d. Preconditioning: Is now required before all package tests

e. Temperature Cycling: Requirements were changed for all conditions except condition “C”.
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f. Autoclave: No longer recommended, especially for BGAs.

g. Power Temperature Cycling no longer required
h. Explained Cpk vs Ppk
6. Process/Product Changes: Improved explanation of changes requiring requalification and testing required.
7. Annex A: Added to explain change in component temperature cycling requirements.

Page 26
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Standard Improvement Form JEDEC JESD47K
The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry
regarding usage of the subject standard. Individuals or companies are invited to submit comments to
JEDEC. All comments will be collected and dispersed to the appropriate committee(s).
If you can provide input, please complete this form and return to:
JEDEC Fax: 703.907.7583
Attn: Publications Department
3103 North 10th Street, Suite 240 South
Arlington, VA 22201
1. I recommend changes to the following:

Requirement, clause number
Test method number Clause number
The referenced clause number has proven to be:
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Unclear Too Rigid In Error
Other gi
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2. Recommendations for correction:
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3. Other suggestions for document improvement:
Submitted by
Name: Phone:
Company: E-mail:
Address:
City/State/Zip: Date:

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JEDEC

(Revision of JESD47J.01, September 2017)

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

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Standards and Documents for alternative contact information.

©JEDEC Solid State Technology Association 2018

PRICE: Contact JEDEC

Printed in the U.S.A.

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This document is copyrighted by JEDEC and may not be

or refer to www.jedec.org under Standards-Documents/Copyright Information.

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STRESS DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

5.5 Device qualification requirements ..................................................................................................................... 7

6 Explanatory comments regarding process/product changes ..................................................................... 16

6.1 To conform to J-STD-046 ................................................................................................................................ 16

6.4 Guidelines for stress tests for product/process changes ................................................................................... 18

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STRESS DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

reliability can be developed by applying JESD94.

a) Any potential new and unique failure mechanisms.

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MIL-STD-883, Test Methods and Procedures for Microelectronics.

Model (CDM) – Device Level

JESD22 Series, Reliability Test Methods for Packaged Devices

JESD46, Guidelines for User Notification of Product/process Changes by Semiconductor Suppliers.

JESD69, Information Requirements for the Qualification of Silicon Devices.

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3.2 Qualification family

3.3 Lot requirements

requirements to larger sample sizes.

the sample size listed in the qualification tables.

3.4 Production requirements

3.5 Reusability of test samples

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3.6 Definition of electrical test failure after stressing

3.7 Required stress tests for qualification

N >= 0.5 [Χ2 (2C+2, 0.1)] [1/LTPD – 0.5] + C

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3.8 Pass/Fail criteria (cont’d)

Table 3-1 — Zero Defect Sample Sizes for Stress Tests

refer to Annex B for different sampling plan.

4 Qualification and requalification

4.1 Qualification of a new device

4.2 Requalification of a changed device

4.2.1 Process change notification

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4.2.2 Changes requiring requalification

4.2.3 Criteria for passing requalification

5.1 General tests

the associated qualification family:

5.3 Wearout reliability tests

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