IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE

A Continuous-Time Adaptive FIR Equalizer with

INV-AIL Delay Line for 2.5Gb/s Data Communication
Xiaofeng Lin(1) Hoi Lee(2) and Jin Liu(2)
(1)
Texas Instruments, Inc. 12500 TI BLVD, Dallas, TX, USA
(2)
University of Texas at Dallas, Dept. of EE, Richardson, TX, USA
xlin@ti.com, hoilee@utdallas.edu, jinliu@utdallas.edu

Abstract-This paper presents a continuous-time adaptive FIR The experimental results and conclusion are presented in
filter as a fractionally spaced receiver equalizer. Inverter-based Sections IV and V, respectively.
delay units with active-inductor load (INV-AIL) are proposed to
implement the tap delay line for the bandwidth enhancement. A II. CIRCUIT DESIGN OF THE FIR FILTER
pulse extraction technique is employed for the equalizer
adaptation to different channel characteristics. Implemented in Fig. 1 shows the block diagram of the 4-tap 4x fractionally
a standard CMOS 0.25-Pm process, the proposed adaptive spaced FIR filter. It consists of three delay stages, plus one
equalizer has achieved over 75% horizontal eye opening when dummy delay at the end of the delay line to provide similar
the PCB trace varies from 20 to 120 inches for 2.5Gb/s load for the previous stage. The multiplying digital-to-analog
transmission in the adaptation mode. converters (MDAC) serve as multipliers. The current outputs
of the MDACs are directly connected together to sum up the
I. INTRODUCTION current. Then, the differential current signals are converted to
In high-speed chip-to-chip communications for backplane, voltage signals through the load resistor. Common mode
frontplane, and mainframe/personal computer applications, feedback circuit (CMFB) tunes the two pairs of current
frequency-dependent channel characteristics cause sources to set the output common-mode voltage. The slicer is
intersymbol interference (ISI) problem for Gb/s data a continuous-time amplifier served as a comparator.
transmission. Equalization is essential in the clock and data Previous 1Gb/s filter design [3] used current mirror with
recovery circuit to restore timing information for achieving current-mode second-order biquad, as well as fractionally
low bit-error-rate. In recent years, continuous-time FIR filters spaced delay to increase the bandwidth of the delay line.
have been widely used as transmitter or receiver equalizers to However, due to the current-mirror topology, there is a mirror
compensate for the ISI problem due to wider tuning range and pole in each delay unit, thereby limiting the bandwidth of the
lower power consumption [1] [2]. Both the implementation of delay line. In this design, INV-AIL delay cell is proposed.
the tap delay line and the adaptation to different channel Fig. 2 shows the schematic of the proposed delay cell and each
conditions are important to continuous-time FIR filters for delay unit consists of three delay cells. The transistor PM3
high-speed data transmission. Although the tap delay line (NM3) in the gate connection of NM2 (PM2) realizes an
implemented by an artificial transmission line can achieve active inductor to increase the bandwidth of the delay cell by
10Gb/s data rate, 87 on-chip inductors on the tap delay line generating a low-frequency zero. In order to justify the
consume large die area [2]. To improve the area efficiency, a generation of the low-frequency zero, the transfer function of
fractionally spaced FIR equalizer using an active inductor-less the proposed INV-AIL delay cell is investigated. Fig. 3 shows
tap delay line has been developed [3]. The fractionally spaced the small signal model of the delay cell. The Cgsn2 and Cgsp2
equalizer, however, did not address the issue of adaptation and are the gate capacitors of transistors NM2 and PM2
the bandwidth of the delay line is still limited by multiple respectively. R1 and R2 are the channel resistors of PM3 and
poles in each current-mirror based delay unit. NM3, which function in the triode region. The go is the total
In this paper, inverter-based delay units with active- outb

inductor-load (INV-AIL) are proposed to implement the tap W0 W1 W2 W3

outa

delay line in the fractionally spaced equalizer. With the MDAC MDAC MDAC MDAC

proposed delay line, an additional zero is introduced in each Input

Delay Unit
Slicer
Delay Unit
delay cell, thereby greatly enhancing the bandwidth of the Delay Unit
Delay Unit

Delay Unit
Delay Unit

Delay Unit
Delay Unit

Delay Unit
Output
Output
delay line and the speed of the equalizer. On the other hand, a Input Delay Unit
pulse extraction method [4] is employed in the equalizer to W0
MDAC
W1
MDAC
W2
MDAC
W3
MDAC VP
generate an error signal in order for the FIR filter to adapt to outb
different channel conditions. The paper is organized as outa
CMFB

follows. Section II will discuss the circuit design of the FIR VN

filter including INV-AIL delay unit, MDAC and slicer, while

Section III will describe the adaptation issues of the equalizer.
Fig. 1. Block diagram of a 4-tap FIR filter

0-7803-9023-7/05/$20.00 ©2005 IEEE. 11-2-1 413

 VDD
outa
PM3 outb
PM1 NM2
In
In Out

NM1 PM2
1a 1b2a 2b2a 2b3a 3b3a 3b3a 3b3a 3b
NM3

Fig. 4. Schematic of 3-bit MDAC

VDD
Fig. 2. Schematic of an INV-AIL delay cell
M5 M6 M11 M12
channel conductance of PM1, NM1, PM2 and NM2 and CL is M3 M4 M9 M10
the total input capacitance of next delay stage. If the widths of Dout Dout
NM3 and PM3 are selected to let R1Cgs1= R2Cgs2= RCgs and
make gmn1= gmp1= gm, the transfer function of the delay cell is Din
M1 M2 M7 M8
Din
approximated as follows:
2 gm 1 2 gm 1
(s  ) (s  )
vout CL Rcgs CL Rcgs
 |
vin §g 1 · 2 gm 1 1 2g 1
s2  s ¨ o   s2  s  m
¨C Rc ¸¸ C Rc Rcgs CL Rcgs
Fig. 5. The slicer
© L gs ¹ L gs

This equation shows that a low-frequency zero to the transfer signal has wide open eyes with low bit error rate. Based on
function is generated due to channel resistance of NM3 and the error signal, the adaptation controller generates a set of
PM3. In particular, the position of the low-frequency zero is coefficients for the FIR filter.
close to that of the poles. Fig. 7 shows the block diagram of the error detector using
To realize above transfer function, each delay cell is pulse extraction method [5]. The pulse extraction circuit
required to biased as a high-gain amplifier. This is achieved consists of a symbol period delay unit, an inverter and an
by shorting the output of a delay cell with its input, as shown AND gate. It extracts a pulse for every rising edge of the
in Fig. 1 in front of the delay line. input signal A. The DC component of the pulse extractor
output, signal D, is the weighted integration of the input signal
Vgs2
power spectrum; the weight factor is equivalent to a bandpass
Vgs1
Vout filter bank [5]. The error signal is generated by comparing the
vin Cgsn2 Cgsp2
go CL power spectrum of the equalized signal with that of a
Vingmn1 Vingmp1 Vgs1gmn2 Vgs1gmp2 R1 R2 reference signal using the pulse extraction method. Since the
reference signal is only required to have the same power
spectrum as that of the transmitted data, it can be easily
Fig. 3. Small signal model of the delay cell generated in the receiver. Compared with LMS-based
algorithms, the pulse extraction method does not require the
The MDAC multiplies the tap delayed signal, “In”, with the synchronization of the equalized signal with the transmitted
tap coefficients represented by digital bits. In this design, data. Since the adaptation part is not in the critical signal path,
each coefficient has 4 bits. The MSB is a sign bit, which the speed requirement is relaxed and the power consumption
directs the output signal of MDAC to the positive output port is reduced.
“outa” or the negative port “outb”. Other three bits set the Based on the error signal, the adaptation controller
gain of the MDAC are shown in Fig. 4. In this design, the generates the tap coefficients using generic search algorithms.
transistors whose gates are connected to the coefficients are In this design, serial perturbation algorithm is adopted. This
placed above the transistors whose gates are controlled by the algorithm sequentially increases or decreases each tap
“In” signal. This topology prevents the signals at “outa” and coefficient of the FIR filter to test whether the error has been
“outb” from coupling back to the tap delay line through the reduced. In each tuning period, the error signal is calculated
gate-drain capacitances. Fig. 5 shows the schematic of the and compared with the error in the previous period. If the
slicer; it is a low gain differential amplifier [4]. To increase current error is smaller than the previous one, the tap value is
the bandwidth, AIL similar to that in the delay unit is used. adjusted in the same direction. After reaching the optimal
coefficient for one tap, the adaptation controller will tune the
III. ADAPTATION OF THE EQUALIZER
next tap. This process is repeated until the error is smaller
Fig. 6 illustrates the essential blocks of an adaptive FIR than a preset threshold. This algorithm can converge faster
equalizer – the FIR filter, the error detector, and the adaptation than other generic algorithms, when the error space has only
controller. The error detector generates an error signal (cost one global minimum. The implementation of the algorithm in
function) such that when the error is minimized, the equalized hardware is also less complicated than others. However, the

414 11-2-2
 The test setup is shown in Fig. 9. An Anritsu pulse pattern
Input Delay Delay Delay Delay generator MP1763B generates a differential 215-1 PRBS as the
Unit Unit Unit Dummy
transmitted data. The BER is measured with Anritsu error
W0 W1 W2 W3 detector MP1764A and the eye diagram is measured with a
Tektronix 20GS/s digital phosphor oscilloscope. The PCB
trace (FR4 material) is composed of two differential
microstrip transmission lines with characteristic impedance of
50ȍ. The received signal after the PCB trace is applied to the
Slicer FIR filter through SMA connectors and coaxial cables. To
FIR filter
test the adaptation performance of the adaptive equalizer, the
Error
length of PCB trace is varied from 20 inches to 120 inches.
Adaptation
Controller Detector The measured S21 parameters of the differential PCB trace
with different length are plotted in Fig. 10. Both the FIR filter
To CDR and the error detection circuit (pulse extractor and LPF) are
Fig. 6. Block diagram of the adaptive equalizer included on the same chip. The adaptation controller is
implemented using FPGA to have the flexibility of evaluating
Pulse extraction LPF & Comparison different generic search algorithms. The reference error was
Equalized Signal calculated by passing a random sequence through an on-chip
A pulse extraction followed by a LPF.
D
Fig. 11 shows the adaptation process of the equalizer for
Z-1
80-inch PCB trace. Within four iterations, the absolute error
AND LPF
B drops to a significantly small value. After the adaptation
C
Reference Signal process, a 215-1 PRBS produced by the pulse generator is
+ Error
Abs
Abs transmitted through the 80-inch PCB trace channel. Fig. 12
_ Signal
shows the measured eye diagram of the received signal and
Z-1
the equalized signal. The voltage scale for both plots is
AND LPF 100mV per unit. The equalized eye has about 80% horizontal
FPGA EVALUATION BOARD
Fig. 7. Block diagram of the error detector using pulse extraction Tap Coeff. Reference Error
FPGA
Error
Received Signal A/D
influences of the tap coefficients to a FIR filter frequency
response are generally not orthogonal; this could lead to
Pulse Pattern
multiple local minimum points in the error space. To ensure Generator FIR Filter Pulse Extractor LPF
convergence of the tuning process, the FIR coefficients are MP1763B Channel
limited to a fixed pattern: [c1 c2 0 –c1], the first tap is always
Error Driver Driver
the reverse to the fourth tap and the third tap is kept zero.
Detector
Such pattern corresponds to a high-pass filter and results in MP1764A CHIP
only one global minimum in the error space.
Equalized Signal
Oscilloscope
IV. MEASUREMENT RESULTS TDS7404
The 2.5Gb/s adaptive equalizer was fabricated using a
CMOS 0.25-μm single-poly six-metal N-well process. The Fig. 9. Test setup for the adaptive equalizer
chip micrograph is shown in Fig. 8. Without using inductors, 0
the die size of the FIR filter is only 0.085mm2. By adding the -5
error detector circuit, the total size of the adaptive equalizer is 60"
-10
0.095mm2. -15
80"
-20
S21 (dB)

FIR Filter -25

100"
-30
MDAC Error i h
-35
Slicer Detector 120"
Delay Unit -40
Output -45
CMFB Driver
MDAC -50
0 0.5 1 1.5 2 2.5 3
Frequency (GHz)

Fig. 8. Chip micrograph Fig. 10: Measured S21 parameters of the PCB traces with different length

11-2-3 415
opening and about 65% vertical opening, compared with the the equalizer. Pulse extraction error detection method enables
totally closed eye of the received signal. Fig. 13 shows the the use of static power spectrum information for equalizer
horizontal eye opening of received signal and equalized signal adaptation, eliminating the need of synchronization between
for 2.5Gb/s 215-1 PRBS data. Horizontal eye opening over the equalized signal and the transmitted data. Experimental
75% has been achieved when the PCB trance varies from 20 results show that the proposed adaptive equalizer has achieved
to 120 inches. over 75% horizontal eye opening when the PCB trace varies
0.12 8
from 20 inches to 120 inches for 2.5Gb/s transmission in the
Tap1 adaptation mode. The adaptive equalizer including the FIR
7 filter and the error detection circuits consumes 95mW from
0.1
Absolute Error (volt)

6 2.5V supply and occupies 0.095mm2 of die area.

Tap Digit Value

0.08
5
Tap2 100%
0.06 4
After Equalization

Horizontal Eye Opening

3 80%
0.04
Abosolute Error 2
0.02 60%
1
0 0 40%
0 1 2 3 4 5
Iteration 20%
Before Equalization
Fig. 11. Tuning process of 2.5Gb/s adaptive equalizer for 80-inch PCB trace
0%
0 50 100 150
PCB trace (inch)
(a)

80%

After Equalization
Vertical Eye Opening

60%

40%

20%
Before Equalization
(a) 0%
0 50 100 150
PCB trace (inch)

(b)
Fig. 13. (a) Horizontal and (b) vertical eye openings of the received signal
before equalization and the equalized signal with adaptive tuning

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