20-Bit, Low-Power Digital-to-Analog Converter: Features Description

DA
C1
220
DAC1220
www.ti.com...................................................................................................................................... SBAS082G – FEBRUARY 1998 – REVISED SEPTEMBER 2009
20-Bit, Low-Power
Digital-to-Analog Converter
Check for Samples: DAC1220
1FEATURES DESCRIPTION
2• 20-Bit Monotonicity Ensured Over –40°C to The DAC1220 is a 20-bit digital-to-analog (D/A)
+85°C converter offering 20-bit monotonic performance over
• Low Power: 2.5mW the specified temperature range. It utilizes
delta-sigma technology to achieve inherently linear
• Voltage Output
performance in a small package at very low power.
• Settling Time: 2ms to 0.012% The resolution of the device can be programmed to
• Maximum Linearity Error: ±0.0015% 20 bits for Full-Scale, settling to 0.003% within 15ms
• On-Chip Calibration typical, or 16 bits for Full-Scale, settling to 0.012%
within 2ms max. The output range is two times the
external reference voltage. On-chip calibration
APPLICATIONS circuitry dramatically reduces low offset and gain
• Process Control errors.
• ATE Pin Electronics
The DAC1220 features a synchronous serial
• Closed-Loop Servo Control interface; in single-converter applications, the serial
• Smart Transmitters interface can be accomplished with just two wires,
• Portable Instruments allowing low-cost isolation. For multiple converters, a
CS signal allows for selection of the appropriate D/A
converter.
The DAC1220 has been designed for closed-loop
control applications in the industrial process control
market and high-resolution applications in the test
and measurement market. It is also ideal for remote
applications, battery-powered instruments, and
isolated systems. The DAC1220 is available in an
SSOP-16 package.
XIN XOUT VREF AVDD AGND
Clock Generator
Microcontroller
C1
Instruction Register 2nd−Order 1st−Order 2nd−Order
Command Register ∆Σ Switched Continuous VOUT
Data Register Modulator Capacitor Filter Time Post Filter
Offset Register C2
Full−Scale Register
SDIO Serial Modulator Control

SCLK Interface
CS DVDD DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1998–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAC1220
SBAS082G – FEBRUARY 1998 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)

Over operating free-air temperature range (unless otherwise noted).
DAC1220 UNIT
AVDD to DVDD ±0.3 V
AVDD to AGND –0.3 to +6 V
DVDD to DGND –0.3 to +6 V
AGND to DGND ±0.3 V
VREF voltage to AGND +2.0 to +3.0 V
Digital input voltage to DGND –0.3 to DVDD + 0.3 V
Digital output voltage to DGND –0.3 to DVDD + 0.3 V
Package power dissipation (TJmax – TA) / θ JA W
Maximum junction temperature (TJmax) +150 °C
Thermal resistance, θ JA SSOP-16 200 °C/W
Lead temperature (soldering, 10s) +300 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2 Submit Documentation Feedback Copyright © 1998–2009, Texas Instruments Incorporated
Product Folder Link(s): DAC1220

DAC1220
ELECTRICAL CHARACTERISTICS
All specifications at TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 2.5MHz, VREF = +2.5V, and 16-bit mode, unless otherwise noted.
DAC1220E
PARAMETER CONDITIONS MIN TYP MAX UNIT
ACCURACY
Monotonicity 16 Bits
Monotonicity 20-bit mode 20 Bits
Linearity error ±15 (1) ppm of FSR
Unipolar offset error and gain error (2) ±60 ppm of FSR
Unipolar offset error drift (3) 1 ppm/°C
Bipolar zero offset error (2) VOUT = VREF ±15 ppm of FSR
Bipolar zero offset drift (3) 1 ppm/°C
Gain error (2) ±150 ppm of FSR
Gain error drift (3) 2 ppm/°C
Power-supply rejection ratio (PSRR) at DC, dB = –20log(ΔVOUT/ΔVDD) 60 dB
ANALOG OUTPUT
Output voltage (4) 0 2 × VREF V
Output current 0.5 mA
Capacitive load 500 pF
Short-circuit current ±20 mA
Short-circuit duration GND or VDD Indefinite
DYNAMIC PERFORMANCE
Settling time (5) To ±0.012% 1.8 2 ms
20-bit mode, to ±0.003% 15 ms
Output noise voltage 0.1Hz to 10Hz 1 μVRMS
REFERENCE INPUT
Input voltage 2.25 2.5 2.75 V
Input impedance 100 kΩ
DIGITAL INPUT/OUTPUT
Logic family TTL-compatible CMOS
Logic levels (all except XIN)
VIH 2.0 DVDD + 0.3 V
VIL –0.3 0.8 V
VOH IOH = –0.8mA 3.6 V
VOL IOL = 1.6mA 0.4 V
Input-leakage current ±10 μA
XIN frequency range (fXIN) 0.5 2.5 MHz
Offset binary two's complement
Data format User-programmable
or straight binary
POWER-SUPPLY REQUIREMENTS
Power-supply voltage 4.75 5.25 V
Supply current
Analog current 360 μA
Digital current 140 μA
Analog current 20-bit mode 460 μA
(1) Valid from AGND + 20mV to AVDD – 20mV.

(2) Applies after calibration.
(3) Recalibration can remove these errors.
(4) Ideal output voltage; does not take into account gain and offset error.
(5) Valid from AGND + 20mV to AVDD – 20mV. Outside of this range, settling time can be twice the value indicated.
For 16-bit mode, C1 = 2.2nF, C2 = 0.22nF; for 20-bit mode, C1 = 10nF, C2 = 3.3nF.
Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback 3

DAC1220
ELECTRICAL CHARACTERISTICS (continued)

All specifications at TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 2.5MHz, VREF = +2.5V, and 16-bit mode, unless otherwise noted.
DAC1220E
PARAMETER CONDITIONS MIN TYP MAX UNIT
POWER-SUPPLY REQUIREMENTS, continued
Digital current 20-bit mode 140 μA
Power dissipation 2.5 3.5 mW
20-bit mode 3.0 mW
Sleep mode 0.45 mW
TEMPERATURE RANGE
Specified performance –40 +85 °C
DEVICE INFORMATION
DVDD 1 16 SCLK
XOUT 2 15 SDIO
XIN 3 14 CS
DGND 4 13 AGND
DAC1220E
AVDD 5 12 VREF
DNC 6 11 VOUT
DNC 7 10 C2
DNC 8 9 C1
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1 DVDD Digital supply, +5V nominal
2 XOUT System clock output (for crystal)
3 XIN System clock input
4 DGND Digital ground
5 AVDD Analog supply, +5V nominal
6 DNC Do not connect
9 C1 Filter capacitor (see text)
10 C2 Filter capacitor (see text)
11 VOUT Analog output voltage
12 VREF Reference input
13 AGND Analog ground
14 CS Chip-select input
15 SDIO Serial data input/output
16 SCLK Clock input for serial data transfer

DAC1220
TYPICAL CHARACTERISTICS
At TA = +25°C, AVDD = DVDD = +5.0V, fXIN = 2.5MHz, VREF = 2.5V, C1 = 2.2nF, and calibrated mode, unless otherwise
specified.
POWER-SUPPLY REJECTION RATIO
vs
FREQUENCY LARGE-SIGNAL SETTLING TIME
60 5.0
4.5
50
4.0
3.5
40
PSRR (dB)
3.0
(V)
30 2.5
2.0
20
1.5
400mVPP Ripple 1.0

10
Mid−Range Output 0.5
0 0
10 100 1k 10k 0 1 2 3 4
Frequency (Hz) Time (ms)
Figure 1. Figure 2.
OUTPUT NOISE VOLTAGE LINEARITY ERROR

vs vs
FREQUENCY CODE
10k 10
−40°C
8
+25°C
1k
Linearity Error (ppm)
+85°C
Noise (nV/√Hz)
100 4
2
10
0
1 2
10 100 1k 10k 100k 1M 0 10k 20k 30k 40k 50k 60k 70k
Frequency (Hz) Code
Figure 3. Figure 4.

DAC1220
THEORY OF OPERATION
Self-Calibration System
The DAC1220 is a monolithic 20-bit delta-sigma (ΔΣ)
digital-to-analog converter (DAC) designed for The self-calibration system of the DAC1220
applications requiring extremely high precision. The measures the DAC output and calculates appropriate
delta-sigma topology used in the DAC1220 ensures gain and offset calibration constants. The output
20-bit monotonicity over the industrial temperature changes during calibration, but can optionally be
range. The DAC1220 can also be operated in 16-bit disconnected during the procedure.
mode, which gives a faster settling time at the
Offset calibration is performed by setting the DAC
expense of higher noise.
output voltage to mid-scale and repeatedly comparing
The core of the DAC1220 consists of an interpolation the DAC output to the VREF voltage using an
filter and a second-order delta-sigma modulator. The auto-zeroed comparator, which is re-zeroed after
output of the modulator is passed to a first-order every comparison. The comparator results are
switched-capacitor filter in series with a second-order recorded and averaged, two’s complement adjusted,
continuous-time filter, which generates the output and placed in the Offset Calibration Register.
voltage.
Gain calibration is performed in a similar way, except
To increase settling time, the DAC1220 can adjust its that the correction is done against an
filter cutoff frequency when it detects a voltage output internally-generated reference voltage, and the final
step of greater than approximately 40mV. This register value is calculated differently. The Full-Scale
behavior can be disabled. Calibration Register result represents the gain code
and is not two’s complement adjusted. Changing the
An onboard self-calibration facility compensates for Gain Register value can change the range of
internal offset and gain errors. Calibration values may voltages that are output for the same digital codes,
be stored and loaded externally if desired. centered on VREF.
The DAC1220 can be put into a sleep mode, in which
power consumption is cut by about 1/6 to BASIC CONNECTIONS
approximately 0.45mW. In sleep mode, the output is
A schematic showing basic connections to the
disconnected.
DAC1220 is given in Figure 5.
The DAC1220 is controlled using a synchronous
serial interface, using either two or three wires. The
interface may be operated bidirectionally or
unidirectionally; readback is optional.
+5V
4.7µF
Ceramic
DVDD SCLK SPI CLOCK

12pF(1)
XOUT SDIO SPI DATA
2.5MHz
XIN CS From Chip Select or Ground
12pF(1)
DGND AGND
+2.5V from
+5V AVDD VREF Voltage Reference
DNC VOUT VOUT
C2(2)
C1 (2)
4.7µF DNC C2
Ceramic
DNC C1
NOTES: (1) Depends on crystal and board layout. (2) See text for recommended values.
Figure 5. DAC1220 Schematic

DAC1220
Output Digital Connections

The output voltage range is nominally 0V to 2 × VREF. The digital lines, except for the crystal oscillator lines,
It does not go below ground. The output amplifier is operate at TTL-compatible CMOS logic levels. They
not designed for heavy loads; it can drive a maximum can be driven from 3.3V logic sources.
of 0.5mA. At power-on and during sleep mode, the
In noise-sensitive applications, it may be helpful to
amplifier is disconnected, so the output is high
keep the level transition rates on the digital lines
impedance.
slow. Fast transitions can couple through the device
The output is not fully linear to the rails; maximum to the output, causing noise. Rate limiting can be
linearity is specified from (AGND + 20mV) to (AVDD – done with resistance or even an RC filter.
20mV). For linearity from 0–5V, AVDD can be
increased to 5.02V or more, and AGND can be Clock Oscillator
decreased to –20mV or less. As long as the specified
operating limits are observed, this will not damage The DAC1220 has a built-in crystal oscillator at pins
the device. XIN and XOUT. To use it, connect a crystal and load
capacitors as shown in Figure 5.
Filter Capacitors 12pF load capacitors are shown in the schematic, but
the correct value depends mainly on the crystal and
The continuous-time output filter requires two external
layout, and not on the oscillator itself. Load
capacitors to operate. The recommended values of
capacitance affects startup time, oscillation
these capacitors depend on whether the DAC1220
frequency, and reliability. If startup is unreliable, try
will be operated in 16-bit or 20-bit mode, and are
lowering the capacitor values. Remember that
shown in Table 1.
parasitic board and pin capacitance can be a
significant portion of the crystal load capacitance.
Table 1. Filter Capacitor Values
CAPACITOR 16-BIT MODE 20-BIT MODE When the crystal oscillator is operating, a sinusoidal
signal of relatively low amplitude will be observed at
C1 2.2nF 10nF
both the XIN and XOUT pins.
C2 0.22nF 3.3nF
The typical frequency to use with the DAC1220 is
The capacitors should be stable and high grade. Film 2.5MHz. Deviating too far from this may alter noise
types, or other capacitors designed for precision and settling time, as well as timing characteristics.
filtering, are strongly recommended. Low-quality
capacitors will degrade performance significantly. Connecting an External Clock
The C1 and C2 pins are very sensitive. It is critical to An external clock signal can be connected at XIN. A
surround them with a guard ring at the reference CMOS or TTL logic signal can be used. If an external
voltage for best noise performance. See the Layout clock signal is used, XOUT should be left unconnected.
section for more information.
In some cases, an RC filter on the clock line may
reduce noise.
Voltage Reference
The voltage reference input is designed for +2.5V. At
this voltage, the output will range from ground to
approximately 5V, as noted above.

DAC1220
Serial Interface Most designs will use a single power supply for AVDD
and DVDD. In these designs, the supplies ramp
The DAC1220 can be operated from most SPI simultaneously, which is acceptable. In those designs
peripherals, or it can be bit-banged. that use separate sources for AVDD and DVDD, the
Note that if SDIO is operated bidirectionally, it may be two supplies must be sequenced properly. This is
necessary to place a pullup resistor on the line, so easily done using a Schottky diode, as shown in
that the line will not be floating. Figure 6. The diode ensures that DVDD will not
exceed AVDD by more than a Schottky diode drop.
The serial clock is limited to one-tenth of the master
clock frequency. For a 2.4576MHz master clock, the Brownouts and Power-On Reset
serial clock may be no faster than 245.76kHz. The
designer should bear this in mind, as it may prevent The DAC1220 incorporates a power-on reset (POR)
the DAC1220 from being shared with other SPI circuit. The circuit will trigger as long as the power
devices or placed on an SPI bus, which may run supply ramps up at 50mV/ms or faster. If the power
much faster. supply ramps more slowly than this, the POR may not
trigger.
If the DAC1220 is placed on a shared SPI bus, the
chip-select line must be controlled; otherwise, it can The DAC1220 does not have a brownout detector.
be grounded. The POR circuit will not retrigger unless the supply
voltages have approached ground. Because of this, if
Although the SDIO line is bidirectional, it can be the supply falls to a low voltage, it may corrupt the
operated as an input only, as long as no register logic of the DAC1220, causing it to operate erratically
reads are performed. The DAC1220 can be operated or to fail entirely. It may be necessary to forcibly
without register reads, although for situations discharge the supply, since the DAC1220 may
requiring high reliability, this is not recommended, occasionally fail to detect the SCLK reset pattern in
since the device registers and operation cannot be this condition.
directly verified.
The SCLK reset pattern serves in place of a reset
Power Supplies pin. See the SCLK Reset Pattern section for
information.
The DAC1220 has separate analog and digital power
supply connections. Both are intended to operate at Supply Decoupling
+5V.
Both supply pins should be heavily decoupled at the
The digital supply must never exceed the analog device for best performance. A 10μF multi-layer
supply by more than 300mV. If it does, the DAC1220 ceramic capacitor can be used for this, or a tantalum
may be permanently damaged. The analog supply capacitor in parallel with a small (0.1μF) ceramic
may be greater than the digital supply without capacitor can be used. Both capacitors, particularly
damage, however. the ceramic capacitor, should be placed as close to
the pins as possible being decoupled.
5V
Digital DVDD
Supply
5V
Analog AVDD
Supply
Figure 6. Supply Sequence Protection

DAC1220
DIGITAL INTERFACE
Timing
The serial interface is synchronous and controlled by the SCLK input. The DAC1220 latches incoming bits on the
falling edge of SCLK, and shifts outgoing bits on the rising edge of SCLK. An external interface should shift
outgoing bits on the rising edge of SCLK, and latch incoming bits on the falling edge of SCLK. The relevant
waveforms are illustrated in the timing diagrams (see Figure 7 to Figure 11). Timing numbers are given in
Table 2 through Table 4.
tXIN
t1 t2
XIN
Figure 7. XIN Clock Timing
Table 2. XIN Timing Characteristics

SYMBOL DESCRIPTION MIN NOM MAX UNITS
fXIN XIN clock frequency 1 2.5 MHz
tXIN XIN clock period 400 1000 ns
t1 XIN clock high 0.4 × tXIN ns
t2 XIN clock low 0.4 × tXIN ns
t3
t4 t5
SCLK
t6 t7
SDIO
t8
Figure 8. Serial Input/Output Timing
Table 3. Serial I/O Timing Characteristics

t3 SCLK high 5 × tXIN ns
t4 SCLK low 5 × tXIN ns
t5 Data in valid to SCLK falling edge (setup) 40 ns
t6 SCLK falling edge to data in not valid (hold) 20 ns
t7 Data out valid to rising edge of SCLK (hold) 0 ns
t8 SCLK rising edge to new data out valid (delay) 50 ns

DAC1220
t9 t14
SCLK
SDIO IN7 IN1 IN0 INM IN1 IN0 IN7

Write Register Data
SDIO IN7 IN1 IN0 OUTM OUT1 OUT0 IN7

Read Register Data
Figure 9. Serial Interface Timing (CS Low)
t15
CS
t 10 t9 t10
SCLK
SDIO IN7 IN1 IN0 INM IN1 IN0 IN7

Write Register Data
SDIO IN7 IN1 IN0 OUTM OUT1 OUT0 IN7

Read Register Data
Figure 10. Serial Interface Timing (Using CS)
CS
t11 t12
t 10
SCLK
t13
SDIO IN7 IN0 OUT MSB OUT0
t9
SDIO is an input SDIO is an output
Figure 11. SDIO Input to Output Transition Timing
Table 4. Serial Interface Timing Characteristics

Falling edge of last SCLK for command to
t9 13 × tXIN ns
rising edge of first SCLK for register data
t10 Falling edge of CS to rising edge of SCLK 11 × tXIN ns
Falling edge of last SCLK for command to SDIO as
t11 8 × tXIN 10 × tXIN ns
output
SDIO as output to rising edge of first SCLK
t12 4 × tXIN ns
for register data
Falling edge of last SCLK for register data to SDIO
t13 4 × tXIN 6 × tXIN ns
tri-state
Falling edge of last SCLK for register data to
t14 rising edge of first SCLK of next command (CS tied 41 × tXIN ns
low)
t15 Rising edge of CS to falling edge of CS (using CS) 22 × tXIN ns

DAC1220
The chip-select pin CS is active low. When CS is SCLK Reset Pattern

high, activity on SCLK is ignored. There are certain
The DAC1220 does not have a dedicated reset pin.
timing limits and delays which apply to the
Instead, it contains a circuit which waits for a special
manipulation of CS, as shown in Figure 10. These
pattern to appear on SCLK, and triggers the internal
must be observed, or the DAC1220 may malfunction.
hardware reset line when it detects the special
If CS is not used, it should be tied low. When CS is pattern.
tied low, different timing limits and delays must be
This pattern, called the SCLK reset pattern, is shown
observed, as shown in Figure 9. If these are violated,
in Figure 12, with timing information given in Table 5.
the DAC1220 may malfunction.
The pattern is very different from the usual clocking
The serial interface is byte-oriented. All data is patterns which appear on SCLK, and is unlikely to be
transferred in groups of eight bits. detected by accident during normal operation.
The SCLK reset pattern can only be triggered when
I/O Recovery CS is low. When CS is high, the SCLK line is ignored,
The DAC1220 has a timeout on the serial interface. If and the SCLK reset pattern is not detected.
fCLK is 2.5MHz, the timeout is approximately 100ms.
At 2.5MHz, if a command is interrupted, and no
activity occurs on the SCLK or CS lines for 100ms,
the DAC1220 will cancel the command. If the
command was a write command, no registers are
affected.
The timeout period scales with the frequency of fCLK.
Reset On
Falling Edge
t17 t 17
SCLK
t16 t18 t19
Figure 12. Resetting the DAC1220
Table 5. Reset Timing Characteristics

t16 First high period 512 × tXIN 800 × tXIN ns
t17 Low period 10 × tXIN ns
t18 Second high period 1024 × tXIN 1800 × tXIN ns
t19 Third high period 2048 × tXIN 2400 × tXIN ns

DAC1220
PROGRAMMING
Commands
Communication with the DAC1220 consists entirely of Registers
commands, which access the DAC1220 registers.
There are four registers in the DAC1220, as shown in
Commands consist of a command byte followed by
the register map in Table 11. The Data Input Register
one, two or three data bytes. The data bytes can be
(DIR) and the two calibration registers are 24 bits in
sent to the DAC1220 or read from the DAC1220,
length, and the Command Register (CMR), which
depending on whether the command is a read
contains configuration bits, is 16 bits in length.
command or a write command.
The format of the command byte is shown in Table 6, Modes
and the bits are described in Table 7. DAC1220
commands access the register map, which is shown The DAC1220 has three operating modes: Sleep,
in Table 11. A DAC1220 command can read or write Normal, and Self Calibration.
one byte, or two or three adjacent bytes, in the In Sleep mode, the DAC1220 output is off (high
register map. impedance), and much of the internal circuitry is
switched off. In this mode the DAC1220 draws little
Bit and Byte Order power. The oscillator continues to run, however.
Sleep is the mode entered after reset.
The order of the bits of data bytes in a command is
configurable. The DAC1220 can be programmed to In Normal mode, the DAC1220 is fully active, and the
output data bytes MSB first or LSB first. The output is on.
command byte is always transmitted MSB first. See
the description of the MSB bit in Table 6 for further In Self Calibration mode, the DAC1220 runs its
details. The order of the data bytes themselves is self-calibration sequence. After the sequence is
also configurable. See the description of the BD bit in complete, the DAC1220 switches to Normal mode.
Table 13 for details. Note that the BD bit does not See the Calibration section for more information.
affect the command byte; this always comes first.
Table 6. Command Byte Format
7 6 5 4 3 2 1 0
R/W MB 0 ADR
Table 7. Command Byte Bits

BIT(S) NAME VALUE DESCRIPTION
7 R/W 0 Write to register map
1 Read from register map
6–5 MB Number of bytes to read or write
00b 1 byte
01b 2 bytes
10b 3 bytes
11b Reserved; do not use
3–0 ADR 0–15 Start address in register map

DAC1220
Startup Sequence Since the calibration functions are linear, calibration

results can be averaged for greater precision. For
At startup, the following procedure should generally example, it may be beneficial to perform several
be followed to properly initialize the DAC1220: self-calibrations in succession, record the result of
1. If the DAC1220 is being clocked from a crystal, each, average them together, and store the averages
wait for the oscillator to start—at least in the OCR and FCR.
25ms—before attempting to communicate with it.
Trying to communicate with the DAC1220 before Self-Calibration Procedure
the crystal oscillator has reached its final
frequency will usually result in corrupt To perform a self-calibration, place the DAC1220 into
communication. Self Calibration mode by setting the MD1 bit to '0'
and the MD0 bit to '1' in the Command Register. At a
2. Optionally apply the SCLK reset pattern. This
clock frequency of 2.5MHz, self-calibration takes
should also only be done once the oscillator is
between 300ms and 500ms; the actual time is
started, since the pattern is detected using
indeterminate and depends on the results.
oscillator cycles. Applying the reset pattern at
power-up ensures that the DAC1220 is reset If the CALPIN bit in the Command Register is '1', the
properly, and not lingering in an unknown state in output remains connected during calibration. The
case of POR failure, brownout, etc. DAC voltage will change during the calibration
After a successful reset, the DAC1220 enters process. This can be important if the DAC output is
Normal mode. loaded significantly; disconnecting the output during
3. Set up the Command Register as desired. This calibration places a high load impedance on the
may include changing the mode from Sleep to output amplifier, which may be different from normal
Self Calibration or Normal. operation.
4. Calibrate the DAC1220. Although this step is If the CALPIN bit in the Command Register is '0', the
optional, the DAC1220 should almost always be output will be disconnected during calibration. If this
calibrated. It is permissible to run calibration is the case, when calibration begins, the DAC1220
every time, or to use values from a previous briefly charges the C2 capacitor to the current output
calibration. See the Calibration section for details. voltage. If the output is buffered, C2 effectively
becomes a sample-and-hold capacitor, so that the
After calibration, the DAC1220 returns to Normal
final output voltage remains during calibration.
mode. The DAC1220 is ready to accept data once it
is in Normal mode, but calibration or the use of saved When the calibration is complete, the DAC1220
calibration values is highly recommended. switches to Normal mode. If the output was
disconnected, it is reconnected at that time. The end
Calibration of the calibration procedure can be detected by
polling the MD1 and MD0 bits. When they become 0,
Calibration is governed by two registers. The Offset the calibration is complete.
Calibration Register (OCR) stores a value
determining the offset calibration, and the Full-Scale If readback is not being performed, simply wait at
Calibration Register (FCR) stores a value determining least 500ms before sending further commands to the
the gain calibration. device, assuming that the clock frequency is 2.5MHz.
The value in the OCR is scaled and additive. It has a Once calibration is complete, the OCR and FCR
linear relationship to the generated offset calibration contain the results of the calibration, and the new
voltage. The value in the FCR is scaled and constants are effective immediately.
multiplicative. It has a linear relationship to the
generated gain calibration multiplier.

DAC1220
Setting the Output Voltage The code may be given in either straight binary or
offset two's complement format. This is controlled by
To set the DAC1220 output voltage, write a code to the DF bit in the Command Register (see the register
the Data Input Register (DIR). A write to any of the description in Table 13 for details). The two data
bytes in the DIR causes the voltage to change at the format options and the 16- or 20-bit option give rise to
completion of the write command. four transfer functions, which are shown in Table 8.
The DAC1220 operates in either 16- or 20-bit mode. For reference, several ideal output voltages for given
The DIR is 24 bits wide, and the code stored in it is input codes are shown in Table 9.
left justified, with the least significant bits ignored. Note that the DIR code can also be considered a
Therefore, in 16-bit mode, only the upper 16 bits of 24-bit number. This may be convenient in software. In
the DIR are significant, and in 20-bit mode, only the this case the transfer functions for 16- and 20-bit
upper 20 bits of the DIR are significant. modes are the same, except that in 16-bit mode the
In 20-bit mode, all three bytes of the DIR must be code is truncated by eight bits, and in 20-bit mode the
written to in order to completely update the code. In code is truncated by four bits.
16-bit mode, it is only necessary to write to the two
upper bytes; a write to the lower byte has no effect on
the output.
Table 8. Transfer Functions

DATA FORMAT 20-BIT MODE 16-BIT MODE
Offset two's complement
V OUT + 2VREF code)2
19
V OUT + 2VREF code)2
15
2 20 2 16
Straight binary
V OUT + 2VREF code V OUT + 2VREF code
2 20 2 16
Table 9. Example Output Voltages

APPROXIMATE
OUTPUT
(1)
VOLTAGE RESOLUTION DATA FORMAT CODE DIR CONTENT
Two's complement 8000h 8000xxh
16-bit
Straight binary 0000h 0000xxh
0V
Two's complement 8000h 80000xh
20-bit
Straight binary 0000h 00000xh
Two's complement 0000h 0000xxh
16-bit
Straight binary 8000h 8000xxh
2.5V
Two's complement 0000h 00000xh
20-bit
Straight binary 8000h 80000xh
Two's complement 7FFFh 7FFFxxh
16-bit
Straight binary FFFFh FFFFxxh
5V
Two's complement 7FFFFh 7FFFFxh
20-bit
Straight binary FFFFFh FFFFFxh
(1) x = Do not care

DAC1220
Fast Settling Mode

To speed up settling, the DAC1220 can change the REGISTERS
cutoff frequency of its output filter. Raising the cutoff
The register map is shown in Table 11.
frequency causes the DAC1220 to settle faster, but at
the expense of higher noise. The adaptive filtering
Table 11. Register Memory Map
mode provides a good compromise by increasing the
filter frequency only while the DAC is changing its ADDRESS CONTENT
output by more than approximately 40mV. When the 0 DIR byte 2 (MSB)
output has settled, the filter frequency is reduced 1 DIR byte 1
again.
2 DIR byte 0 (LSB)
Adaptive filtering is controlled by the ADPT and DISF 3 Reserved
bits in the Command Register. The action of these 4 CMR byte 1 (MSB)
bits together is described in Table 10.
5 CMR byte 0 (LSB)
Table 10. Fast Settling Modes 6 Reserved
7 Reserved
ADPT DISF
(CMR bit 15) (CMR bit 4) FAST SETTLING MODE 8 OCR byte 2 (MSB)
0 0 Fast settling only during > 40mV 9 OCR byte 1
step 10 OCR byte 0 (LSB)
0 1 Disabled 11 Reserved
1 0 Fast settling always on (filter cutoff 12 FCR byte 2 (MSB)
increased)
13 FCR byte 1
1 1 Disabled
14 FCR byte 0 (LSB)
space 15 Reserved
Command Register (CMR)

The command register contains the configuration bits of the DAC1220. It is shown in Table 12. The bits in the
command register are shown in Table 13.
Writes to the CMR take effect at the negative edge of SCLK during the last bit of the last byte of the write
command.
blank
Table 12. Command Register
15 14 13 12 11 10 9 8
ADPT CALPIN Reserved Reserved Reserved Reserved CRST Reserved
R/W-0 R/W-0 R-1(1) R-0 R-1 R-0 R/W-0 R-0
(1) In early versions of the DAC1220, this bit was rw-0. See the Calibration section for details.
7 6 5 4 3 2 1 0
RES CLR DF DISF BD MSB MD
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-10b
LEGEND: R = Read, W = Write

DAC1220
Table 13. Command Register Bits

15 ADPT Controls adaptive filtering. if DISF is set, this bit has no effect.
0 Adaptive filtering enabled (default).
1 Adaptive filtering disabled.
14 CALPIN 0 Output is disconnected (high impedance) during calibration (default).
1 Output is connected during calibration.
13 Reserved Write '1' to this bit. On early versions of the device, this bit is writable and
defaults to zero, but still should be set to '1'. On current devices this bit is read-
only and always reads '1'. See the Calibration section for details.
12 Reserved Read-only. Always '0'.
9 CRST In Normal mode, writing '1' to this bit resets the calibration registers, setting
OCR to 000000h and FCR to 800000h. In Normal mode, this bit always reads
'0'.
In Sleep mode, this bit is read/write, and has no effect.
Writing '1' to this bit and switching to Normal mode at the same time will reset
the calibration registers.
0 Do not clear calibration registers.
1 Clear calibration registers.
7 RES Selects resolution.
0 16-bit resolution (default).
1 20-bit resolution.
6 CLR In Normal mode, writing '1' to this bit writes 0 to the data register.
In Sleep mode, this bit is read/write, and has no effect.
Writing '1' to this bit and switching to Normal mode at the same time will reset
the data register.
The actual voltage that the DAC1220 will output on setting this bit depends on
the data format selected by DF. If DF is 1, zero gives 0V; if DF is 0, zero gives
VREF (mid-scale).
0 Do not clear calibration registers.
1 Clear calibration registers.
5 DF Selects binary number format of the data register.
0 Offset two's complement (default).
1 Straight binary.
4 DISF Can be used to inhibit fast settling and/or adaptive filtering. See text for details.
0 Fast settling and/or adaptive filtering enabled (default).
1 Fast settling disabled; filter always at default cutoff.
3 BD Selects address increment or decrement when reading or writing multiple bytes,
except when writing to the command register. The command register is always
written to in increment mode (most significant byte first). Reads from the
command register are according to this bit.
0 Address is incremented after each byte (default).
1 Address is decremented after each byte.

DAC1220
Table 13. Command Register Bits (continued)

2 MSB Selects the order in which bits are shifted in and out of the DAC1220, except
when writing to the command register. The command register is always written
to MSB first. Reads from the command register are according to this bit.
0 Data is shifted MSB first (default).
1 Data is shifted LSB first.
1-0 MD Operating mode.
00b Normal mode (default).
01b Self calibration mode. (No other bits should be changed in the Command
Register when setting this mode.)
10b Sleep mode.
11b Reserved.
Data Input Register (DIR)

The Data Input Register determines the output After reset, the OCR contains zero. See the
voltage in Normal mode. Calibration section for further details about the OCR.
In Sleep mode, writing to this register has no effect Full-Scale Calibration Register (FCR)
on the output, but the value is stored. The value in
the DIR becomes effective immediately upon entering The Full-Scale Calibration Register stores the gain
Normal mode. calibration constant. The content of the DIR is
adjusted multiplicatively by this value before
After reset, the DIR contains zero. conversion by the DAC.
See the section, Setting the Output Voltage for further In Sleep mode, writing to this register has no effect
details about the Data Input Register. on the output, but the value is stored. The value in
the FCR becomes effective immediately upon
Offset Calibration Register (OCR) entering Normal mode.
The Offset Calibration Register contains a 24-bit After reset, the FCR contains 800000h.
two's complement value. This value is added to the
value in the DIR before conversion by the DAC. See the Calibration section for further details about
the FCR.
In Sleep mode, writing to this register has no effect
on the output, but the value is stored. The value in
the OCR becomes effective immediately upon
entering Normal mode.

DAC1220
APPLICATION INFORMATION
Note that the delays are slightly different if chip-select

Layout Recommendations (CS) is not being used.
The DAC1220 is a high-precision analog component Timing delays from the beginning of an SPI byte
incorporating digital elements. Achieving good transmission are a common problem in
precision is not difficult, but achieving excellent microcontroller firmware that uses an SPI peripheral.
precision may require several attempts. Be sure that any delay routine begins once a byte
It is critical to supply a guard ring, or fill, around the has completed transmission, or add the byte
C1 and C2 pins. The guard ring should be connected transmission time to the delay time.
to the voltage reference. These nodes are very Some programmers may find that bit-banging, or
sensitive, and are good places for noise to couple direct manipulation of microcontroller I/O pins, is the
through to the output. A ground fill on the opposite easiest way to communicate with the DAC1220,
side of the board, or a ground plane, is also a good because of the delays and direction changes
idea. required.
The capacitors themselves should be placed as near
the pins as possible. In particular, the traces leading Write-Only Interfacing
from C1 and C2 should be kept very short. The traces
In some situations, such as isolated interfacing, it is
leading to VOUT and VREF can be longer.
inconvenient to use the DAC1220 bidirectionally,
It is also very important to route digital traces away since the SDIO pin changes direction for readback.
from analog traces, so that their associated return The DAC1220 can be used write-only. The following
currents will not couple into the analog side. considerations apply:
If a crystal is used, do not route the traces connecting • When used write-only, it is not possible to verify
the crystal to the device through vias, if possible, that the DAC1220 is operating using its serial
because this will increase the trace inductance and interface alone. The operation of the DAC is
may affect startup and reliability. Keep the traces open-loop.
short, and place the crystal close to the device. Keep • It may be helpful to wait at least 150ms-200ms
in mind that extra ground planes and trace lengths after startup. This ensures that, in case the reset
increase parasitic capacitance, and this should be was a result of firmware problems and not
deducted from the load capacitor values. power-up, any previous communication with the
DAC has been cancelled by the I/O recovery
Software Considerations timeout.
• When applying the SCLK reset pattern, which can
A key to communicating successfully with the
be done in place of the above steps, allow time for
DAC1220 is observing the delays in the interface
the oscillator to start before applying the pattern.
timing diagrams. A violation of these delays, at best,
The pattern is detected based on oscillator cycles,
results in lack of correct output; at worse, violating the
so it will not be detected if the oscillator is not yet
delays can corrupt communications entirely.
running.

DAC1220
Isolation Full-Scale Range (FSR)—This is the magnitude of

the typical analog output voltage range, which is 2 ×
The DAC1220 serial interface allows for connection VREF. For example, when the converter is configured
using as few as two wires. This is an advantage with a 2.5V reference, the Full-Scale range is 5.0V.
when galvanic isolation is required. An example
isolated connection is shown in Figure 13. Here, Gain Error—This error represents the difference in
chip-select is unused and therefore grounded, and the slope between the actual and ideal transfer
the DAC1220 is being operated unidirectionally. functions.
Linearity Error—The deviation of the actual transfer
DAC1220 Revisions function from an ideal straight line between the data
As of this writing, there have been two released end points.
revisions of the DAC1220. The only difference Least Significant Bit (LSB) Weight—This is the
between the two versions is bit 13 of the Command ideal change in voltage that the analog output
Register. In the first revision, this bit was writable, changes with a change in the digital input code of
and defaulted to '0'. In the current revision, which was 1LSB.
released in 1999, this bit is fixed at '1', and is not
writable. Monotonicity—Monotonicity assures that the analog
output will increase or stay the same for increasing
For first revision chips, always write a '1' to this bit. digital input codes.
Although the bit is not critical, performance is not
optimal unless this bit is set. Offset Error—The difference between the expected
and actual output, when the output is zero. The value
This does no harm in current revision chips, and is calculated from measurements made when VOUT =
ensures that first revision chips perform optimally. 20mV.
Definition of Terms Settling Time—The time it takes the output to settle
to a new value after the digital code has been
Differential Nonlinearity Error—The difference changed.
between an actual step width and the ideal value of
1LSB. If the step width is exactly 1LSB, the fXIN —The frequency of the crystal oscillator or
differential nonlinearity error is zero. A differential CMOS-compatible input signal at the XIN input of the
nonlinearity specification of less than 1LSB ensures DAC1220.
monotonicity.
Drift—The change in a parameter over temperature.
Isolated
Power
DVDD
Opto 8051
DAC1220 Coupler P1.1
C1
12pF 1 DVDD SCLK 16
Opto
2 XOUT SDIO 15 P1.0
Coupler
XTAL
3 XIN CS 14
C2
4 DGND AGND 13
12pF AVDD
5 AVDD VREF 12 VREF
= Isolated
6 DNC VOUT 11 VOUT
C2
7 DNC C2 10 = DGND
C1
8 DNC C1 9
= AGND
Figure 13. Isolation for Two-Wire Interface

DAC1220
REVISION HISTORY
Changes from Revision F (March, 2008) to Revision G ................................................................................................. Page
• Revised Table 4, Serial Interface Timing Characteristics; changed INSR to command for all occurrences ...................... 10
Changes from Revision E (December 2007) to Revision F ............................................................................................ Page
• Updated device graphic to TI logo ........................................................................................................................................ 1

• Changed description of the 01b row in the 1-0 bits section of Table 13 ............................................................................ 16

PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing Qty (2) (3) (4)
DAC1220E ACTIVE SSOP DBQ 16 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC
& no Sb/Br) 1220E
DAC1220E/2K5 ACTIVE SSOP DBQ 16 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC
& no Sb/Br) 1220E
DAC1220E/2K5G4 ACTIVE SSOP DBQ 16 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC
& no Sb/Br) 1220E
DAC1220EG4 ACTIVE SSOP DBQ 16 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC
& no Sb/Br) 1220E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC1220E/2K5 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC1220E/2K5 SSOP DBQ 16 2500 367.0 367.0 35.0
Pack Materials-Page 2
IMPORTANT NOTICE
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DA

www.ti.com...................................................................................................................................... SBAS082G – FEBRUARY 1998 – REVISED SEPTEMBER 2009

SDIO Serial Modulator Control

SBAS082G – FEBRUARY 1998 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com

ABSOLUTE MAXIMUM RATINGS (1)

2 Submit Documentation Feedback Copyright © 1998–2009, Texas Instruments Incorporated

Product Folder Link(s): DAC1220

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(1) Valid from AGND + 20mV to AVDD – 20mV.

Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback 3

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ELECTRICAL CHARACTERISTICS (continued)

4 Submit Documentation Feedback Copyright © 1998–2009, Texas Instruments Incorporated

Product Folder Link(s): DAC1220

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400mVPP Ripple 1.0

OUTPUT NOISE VOLTAGE LINEARITY ERROR

Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback 5

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DVDD SCLK SPI CLOCK

Figure 5. DAC1220 Schematic

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Output Digital Connections

Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback 7

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Figure 6. Supply Sequence Protection

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Product Folder Link(s): DAC1220

www.ti.com...................................................................................................................................... SBAS082G – FEBRUARY 1998 – REVISED SEPTEMBER 2009

Figure 7. XIN Clock Timing

Table 2. XIN Timing Characteristics

Figure 8. Serial Input/Output Timing

Table 3. Serial I/O Timing Characteristics

Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback 9

SBAS082G – FEBRUARY 1998 – REVISED SEPTEMBER 2009...................................................................................................................................... www.ti.com

SDIO IN7 IN1 IN0 INM IN1 IN0 IN7

SDIO IN7 IN1 IN0 OUTM OUT1 OUT0 IN7

Figure 9. Serial Interface Timing (CS Low)

SDIO IN7 IN1 IN0 INM IN1 IN0 IN7

SDIO IN7 IN1 IN0 OUTM OUT1 OUT0 IN7

Figure 10. Serial Interface Timing (Using CS)

SDIO IN7 IN0 OUT MSB OUT0

Figure 11. SDIO Input to Output Transition Timing

Table 4. Serial Interface Timing Characteristics

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The chip-select pin CS is active low. When CS is SCLK Reset Pattern

Figure 12. Resetting the DAC1220

Table 5. Reset Timing Characteristics

Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback 11

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Table 7. Command Byte Bits

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Startup Sequence Since the calibration functions are linear, calibration