AMD Processor and Its Architecture
AMD Processor and Its Architecture
AMD and Intel both uses x86 architecture named as x86 Core “Zen 2”
architecture and Intel Core x86 respectively.
Architecture Diagram
8 general-purpose registers – 32 bits.
Segmen Size
t (bits Purpose
Register )
Data segment register. Default location for These registers are used to break up a
16 variables (.data section). Used for data program into parts. As it executes, the
DS segment registers are assigned the
accesses.
base values of each segment. From
Extra segment register. Used during string here, offset values are used to access
16
ES operations. each command in the program.
Stack segment register. Base location of the
stack segment. Used when implicitly using
SS 16
SP or ESP or when explicitly using BP,
EBP.
16 Extra segment register.
FS
16 Extra segment register.
GS
Falgs
Flag Bit Purpose
Carry flag. Set if an arithmetic operation generate a carry or a borrow out of the most
0 significant bit of the result, cleared otherwise. This flag indicate an overflow condition
CF
for unsigned integer arithmetic. It is also used in multiple-precision arithmetic.
Parity flag. Set if the least-significant byte of the result contains an even number of 1
2
PF bit, cleared otherwise.
AF 4 Adjust flag. Set if an arithmetic operation generates a carry or a borrow out of bit 3 of
the result, cleared otherwise. This flag is used in Binary-Coded-Decimal (BCD)
arithmetic.
6 Zero flag. Set if the result is zero, cleared otherwise.
ZF
Sign flag. Set equal to the most-significant bit of the result, which is the sign bit of a
7
SF signed integer. 0 indicates a positive value, 1 indicates a negative value.
Overflow flag. Set if the integer result is too large a positive number or too small a
negative number, excluding the sign bit, to fit in the destination operand, cleared
11
OF otherwise. This flag indicates an overflow condition for signed-integer that is two’s
complement arithmetic.
Instruction Pointer
Registe
size (bits) Purpose
r
The instruction pointer holds the address of the next instruction to be
IP/EIP 16/32
executed.
Zen Microarchitecture:
Source: AMD
Instruction Execution
Source: Intel