Sai Srinivasan: Ummary

SAI SRINIVASAN
1615 Crest Rd, Raleigh, NC-27606 | schakr23@ncsu.edu | linkedin.com/in/saisrinivasancv/ | github.com/living2code/ | 919-514-8266

SUMMARY
Graduate Student (Computer Engineering) seeking full time opportunities as an ASIC/CPU/GPU/RTL Architecture, Design & Verification Engineer.
EDUCATION
North Carolina State University, Raleigh, NC Aug 2018 - Dec 2019
Master of Science in Computer Engineering GPA: 3.95/4.0
Courses: ASIC Verification with SystemVerilog, Microprocessor Architecture, ASIC and FPGA Design with Verilog, Digital Imaging Systems,
Computer Vision, Neural Networks.
SRM University, Chennai, India Aug 2012 - May 2016
Bachelor of Technology in Electronics & Communication Engineering GPA: 8.8/10.0
Relevant Courses: Computer Architecture, Data Structures, VLSI Design, Signal Processing, Digital Design, Analog design.
TECHNICAL SKILLS
Programming: Verilog, SystemVerilog, C++, Java, Makefile, XML, Python, Unix/Linux shell programming. VHDL Assembly, CUDA, UVM
Tools: ModelSim, QuestaSim, Synopsys Design Vision, Verdi, Git, Visual Studio, Eclipse, DVE, Vim/Gvim.
DevOps Tools: G-Suite, Atlassian Tools, Version Control-Bit-Bucket, Build & Deploy-Jenkins, Ticketing-JIRA, Collaboration- Confluence.
Technologies: UVM (ongoing), JavaEE, Spring Boot Netflix-OSS, SQL, HTML, CSS, JavaScript.
ACADEMIC PROJECTS
Functional Verification of I2C Multiple Bus Controller (language: SystemVerilog; tool: ModelSim)
 Designed a layered test bench architecture (Environment, Generator, Agent & Scoreboards) & golden reference model in SystemVerilog, to
verify data & control paths of an open source project, i2c multiple bus controller.
 Developed Behavioral modelling of the Design for the Golden Reference within the Predictor. Also created Interfaces from the TB to DUT.
 Created Test-Plan and Test Sequences to exercise the DUT on various scenarios.
 Performed Coverage driven verification (code/functional/assertion coverage) and closed coverage.
Architecture Simulators (language: C++, Java)
 Cache Hierarchy Simulator: Modeled a cache hierarchy simulator consisting L1, L2 & Victim cache. Implemented WBWA & WTNA write
policies along with LRU replacement policy and configurable cache parameters.
Compared and analyze performance, area & energy for different memory hierarchy configurations on this simulator, using a subset of SPEC-
2000 benchmark suite.
Branch Predictor Simulator: Designed a branch predictor simulator for Bimodal, Gshare & Hybrid predictors well suited for SPEC CINT95
benchmarks. Also included a Branch Target Buffer (BTB) to store the history of branches.
Analyzed performance of above simulator configurations for different instruction traces having varied degree of branch bias.
 Out of order Superscalar Simulator: Modeled simulator for 5-stage superscalar processor based on Tomasulo’s algorithm that fetches,
dispatches & issues N instruction/cycle integrated with Renaming Map Table & Reorder Buffer.
Implementation of SHA256 Hashing Function-Synthesizable ASIC (language: Verilog; tools: Modelsim; Synopsys)
 Designed synthesizable ASIC to perform SHA 256 encryption on a given message, interacting with SRAMs to read and write data of length <
=55 ASCII characters.
 Implemented pipelining, FSM design to modularize functions, utilized DesignWare Libraries to reduce area by 30% and clock period by 8ns.
 Carried out gate level synthesis and netlist generation with Synopsys Design Vision. Achieved minimum area & highest throughput.
WORK EXPERIENCE
Graduate Intern, Intel Corporation, Allentown, PA. May 2019 - Aug 2019
SoC Design Intern, Network Communications Solutions Group.
 Architected a Val Strategy to perform Block Level Verification of an IP, housed in a SoC for 5G LTE products.
 Created a reusable test bench using SystemVerilog and UVM 1.2, primarily followed an Object Oriented Design Approach.
 Created Agents, Interfaces, Predictor/Scoreboard, and Test Sequences, and used TLM 1.2 Connections to exercise the DUT
 Sequences of Directed Tests, Constrained Random Tests, were generated according to Test-Plan and Coverage was reported.
Software Engineer, Verizon Data Services India (Verizon Wireless), Chennai, India Jul 2016 - Jun 2018
Backend Developer for Mobility and Self-Service Team, MyVerizon®.
 Migrated a critical middleware application (serves 1.5 million customers) to a cloud based Microservice application, ensuring the continuation
and enhancements of services while maintaining 99.9% website availability.
Key Achievement: Drop in Churn rate by 0.5%.Increased sales (4300 new customer accounts, 68000 lines to existing accounts). Reduced Call-
In Rate.
 Other Contributions: Debugging, Unit-Testing, Application Security of some internal projects.

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SAI SRINIVASAN

1615 Crest Rd, Raleigh, NC-27606 | schakr23@ncsu.edu | linkedin.com/in/saisrinivasancv/ | github.com/living2code/ | 919-514-8266

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