Documents - Pub Power Electronics by Daniel Whart

har80679_FC.
qxd 12/11/09 6:23 PM Page ii
Commonly used Power

and Converter Equations
Instantaneous power: p(t) ⫽ v(t)i(t)

t2
Energy: W ⫽ p(t)dt
3
t1
t0 ⫹T t0 ⫹T
W 1 1
Average power: P ⫽ ⫽ p(t) dt ⫽ v(t)i(t) dt
T T3 T3
t0 t0
Average power for a dc voltage source: Pdc ⫽ Vdc Iavg
1 T 2
rms voltage: Vrms ⫽ v (t)dt
BT3
0
rms for v ⫽ v1 ⫹ v2 ⫹ v3 ⫹ . . . : Vrms ⫽ 2V 1,2 rms ⫹ V 2,2 rms ⫹ V 3,2 rms ⫹ Á
Im
rms current for a triangular wave: Irms ⫽
13
Im 2
rms current for an offset triangular wave: Irms ⫽ a b ⫹ I dc
2
B 13
Vm
rms voltage for a sine wave or a full-wave rectified sine wave: Vrms ⫽
12
har80679_FC.qxd 12/11/09 6:23 PM Page iii
Vm
rms voltage for a half-wave rectified sine wave: Vrms ⫽
2
P P
Power factor: pf ⫽ ⫽
S Vrms Irms
I 2n
Aa
Total harmonic distortion: THD ⫽ n⫽2
I1
1
Distortion factor: DF ⫽
A 1 ⫹ (THD)2
Irms
Form factor ⫽
Iavg
Ipeak
Crest factor ⫽
Irms
Buck converter: Vo ⫽ Vs D
Vs
Boost converter: Vo ⫽
1⫺D
D
Buck-boost and Ćuk converters: Vo ⫽ ⫺ Vs a b
1⫺D
D
SEPIC: Vo ⫽ Vs a b
1⫺D
D N
Flyback converter: Vo ⫽ Vs a b a 2b
1 ⫺ D N1
N2
Forward converter: Vo ⫽ Vs D a b
N1
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Power Electronics
Daniel W. Hart
Valparaiso University
Valparaiso, Indiana
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POWER ELECTRONICS
Published by McGraw-Hill, a business unit of The McGraw-Hill Companies, Inc., 1221 Avenue of the
Americas, New York, NY 10020. Copyright © 2011 by The McGraw-Hill Companies, Inc. All rights
reserved. No part of this publication may be reproduced or distributed in any form or by any means,
or stored in a database or retrieval system, without the prior written consent of The McGraw-Hill
Companies, Inc., including, but not limited to, in any network or other electronic storage or transmission,
or broadcast for distance learning.
Some ancillaries, including electronic and print components, may not be available to customers outside
the United States.
This book is printed on acid-free paper.
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ISBN 978-0-07-338067-4
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Library of Congress Cataloging-in-Publication Data
Hart, Daniel W.
Power electronics / Daniel W. Hart.
p. cm.
Includes bibliographical references and index.
ISBN 978-0-07-338067-4 (alk. paper)
1. Power electronics. I. Title.
TK7881.15.H373 2010
621.31'7—dc22
2009047266
www.mhhe.com
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To my family, friends, and the many students

I have had the privilege and pleasure of guiding
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BRIEF CONTENTS
Chapter 1 Chapter 7
Introduction 1 DC Power Supplies 265
Chapter 2 Chapter 8
Power Computations 21 Inverters 331
Chapter 3 Chapter 9
Half-Wave Rectifiers 65 Resonant Converters 387
Chapter 4 Chapter 10
Full-Wave Rectifiers 111 Drive Circuits, Snubber Circuits,
and Heat Sinks 431
Chapter 5 Appendix A Fourier Series for Some

Common Waveforms 461
AC Voltage Controllers 171
Appendix B State-Space Averaging 467
Index 473
Chapter 6
DC-DC Converters 196
iv
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CONTENTS
Chapter 1 2.5 Effective Values: RMS 34

Introduction 1 2.6 Apparent Power and Power
Factor 42
1.1 Power Electronics 1
Apparent Power S 42
1.2 Converter Classification 1
Power Factor 43
1.3 Power Electronics Concepts 3
2.7 Power Computations for Sinusoidal
1.4 Electronic Switches 5 AC Circuits 43
The Diode 6
2.8 Power Computations for Nonsinusoidal
Thyristors 7 Periodic Waveforms 44
Transistors 8
Fourier Series 45
1.5 Switch Selection 11 Average Power 46
1.6 Spice, PSpice, and Capture 13 Nonsinusoidal Source and
1.7 Switches in Pspice 14 Linear Load 46
The Voltage-Controlled Switch 14 Sinusoidal Source and Nonlinear
Transistors 16 Load 48
Diodes 17 2.9 Power Computations Using
Thyristors (SCRs) 18 PSpice 51
Convergence Problems in 2.10 Summary 58
PSpice 18 2.11 Bibliography 59
1.8 Bibliography 19 Problems 59
Problems 20
Chapter 3
Chapter 2 Half-Wave Rectifiers 65
Power Computations 21
3.1 Introduction 65
2.1 Introduction 21 3.2 Resistive Load 65
2.2 Power and Energy 21 Creating a DC Component
Instantaneous Power 21 Using an Electronic Switch 65
Energy 22 3.3 Resistive-Inductive Load 67
Average Power 22 3.4 PSpice Simulation 72
2.3 Inductors and Capacitors 25 Using Simulation Software for
2.4 Energy Recovery 27 Numerical Computations 72
v
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vi Contents
3.5 RL-Source Load 75 Capacitance Output Filter 122

Supplying Power to a DC Source Voltage Doublers 125
from an AC Source 75 LC Filtered Output 126
3.6 Inductor-Source Load 79 4.3 Controlled Full-Wave Rectifiers 131
Using Inductance to Resistive Load 131
Limit Current 79 RL Load, Discontinuous Current 133
3.7 The Freewheeling Diode 81 RL Load, Continuous Current 135
Creating a DC Current 81 PSpice Simulation of Controlled Full-Wave
Reducing Load Current Harmonics 86 Rectifiers 139
3.8 Half-Wave Rectifier With a Capacitor Controlled Rectifier with
RL-Source Load 140
Filter 88
Controlled Single-Phase Converter
Creating a DC Voltage from an
Operating as an Inverter 142
AC Source 88
4.4 Three-Phase Rectifiers 144
3.9 The Controlled Half-Wave
Rectifier 94 4.5 Controlled Three-Phase
Rectifiers 149
Resistive Load 94
Twelve-Pulse Rectifiers 151
RL Load 96
The Three-Phase Converter Operating
RL-Source Load 98
as an Inverter 154
3.10 PSpice Solutions For
4.6 DC Power Transmission 156
Controlled Rectifiers 100
4.7 Commutation: The Effect of Source
Modeling the SCR in PSpice 100
Inductance 160
3.11 Commutation 103
Single-Phase Bridge Rectifier 160
The Effect of Source Inductance 103
Three-Phase Rectifier 162
3.12 Summary 105 4.8 Summary 163
3.13 Bibliography 106 4.9 Bibliography 164
Problems 106 Problems 164
Chapter 4 Chapter 5
Full-Wave Rectifiers 111 AC Voltage Controllers 171
4.1 Introduction 111 5.1 Introduction 171
4.2 Single-Phase Full-Wave Rectifiers 111 5.2 The Single-Phase AC Voltage
The Bridge Rectifier 111 Controller 171
The Center-Tapped Transformer Basic Operation 171
Rectifier 114
Single-Phase Controller with a
Resistive Load 115 Resistive Load 173
RL Load 115 Single-Phase Controller with
Source Harmonics 118 an RL Load 177
PSpice Simulation 119 PSpice Simulation of Single-Phase
RL-Source Load 120 AC Voltage Controllers 180
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Contents vii
5.3 Three-Phase Voltage 6.11 Discontinuous-Current Operation 241

Controllers 183 Buck Converter with Discontinuous
Y-Connected Resistive Load 183 Current 241
Y-Connected RL Load 187 Boost Converter with Discontinuous
Delta-Connected Resistive Load 189 Current 244
5.4 Induction Motor Speed Control 191 6.12 Switched-Capacitor Converters 247
5.5 Static VAR Control 191 The Step-Up Switched-Capacitor
Converter 247
5.6 Summary 192
The Inverting Switched-Capacitor
5.7 Bibliography 193 Converter 249
Problems 193 The Step-Down Switched-Capacitor
Converter 250
6.13 PSpice Simulation of DC-DC
Chapter 6 Converters 251
DC-DC Converters 196 A Switched PSpice Model 252
An Averaged Circuit Model 254
6.1 Linear Voltage Regulators 196 6.14 Summary 259
6.2 A Basic Switching Converter 197 6.15 Bibliography 259
6.3 The Buck (Step-Down) Problems 260
Converter 198
Voltage and Current Relationships 198
Output Voltage Ripple 204
Capacitor Resistance—The Effect
on Ripple Voltage 206 Chapter 7
Synchronous Rectification for the DC Power Supplies 265
Buck Converter 207
7.1 Introduction 265
6.4 Design Considerations 207
7.2 Transformer Models 265
6.5 The Boost Converter 211
7.3 The Flyback Converter 267
Voltage and Current Relationships 211
Continuous-Current Mode 267
Output Voltage Ripple 215
Discontinuous-Current Mode in the Flyback
Inductor Resistance 218 Converter 275
6.6 The Buck-Boost Converter 221 Summary of Flyback Converter
Voltage and Current Relationships 221 Operation 277
Output Voltage Ripple 225 7.4 The Forward Converter 277
6.7 The Ćuk Converter 226 Summary of Forward Converter
6.8 The Single-Ended Primary Inductance Operation 283
Converter (SEPIC) 231 7.5 The Double-Ended (Two-Switch)
6.9 Interleaved Converters 237 Forward Converter 285
6.10 Nonideal Switches and Converter 7.6 The Push-Pull Converter 287
Performance 239 Summary of Push-Pull Operation 290
Switch Voltage Drops 239 7.7 Full-Bridge and Half-Bridge DC-DC
Switching Losses 240 Converters 291
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viii Contents
7.8 Current-Fed Converters 294 8.7 Amplitude and Harmonic

7.9 Multiple Outputs 297 Control 342
7.10 Converter Selection 298 8.8 The Half-Bridge Inverter 346
7.11 Power Factor Correction 299 8.9 Multilevel Inverters 348
7.12 PSpice Simulation of DC Multilevel Converters with Independent
Power Supplies 301 DC Sources 349
Equalizing Average Source Power
7.13 Power Supply Control 302
with Pattern Swapping 353
Control Loop Stability 303
Diode-Clamped Multilevel
Small-Signal Analysis 304 Inverters 354
Switch Transfer Function 305 8.10 Pulse-Width-Modulated
Filter Transfer Function 306 Output 357
Pulse-Width Modulation Transfer Bipolar Switching 357
Function 307
Unipolar Switching 358
Type 2 Error Amplifier with
Compensation 308 8.11 PWM Definitions and
Design of a Type 2 Compensated
Considerations 359
Error Amplifier 311 8.12 PWM Harmonics 361
PSpice Simulation of Feedback Control 315 Bipolar Switching 361
Type 3 Error Amplifier with Unipolar Switching 365
Compensation 317 8.13 Class D Audio Amplifiers 366
Design of a Type 3 Compensated 8.14 Simulation of Pulse-Width-Modulated
Error Amplifier 318 Inverters 367
Manual Placement of Poles and Zeros
Bipolar PWM 367
in the Type 3 Amplifier 323
Unipolar PWM 370
7.14 PWM Control Circuits 323
8.15 Three-Phase Inverters 373
7.15 The AC Line Filter 323
The Six-Step Inverter 373
7.16 The Complete DC Power Supply 325
PWM Three-Phase
7.17 Bibliography 326 Inverters 376
Problems 327 Multilevel Three-Phase
Inverters 378
8.16 PSpice Simulation of
Chapter 8 Three-Phase Inverters 378
Six-Step Three-Phase
Inverters 331
Inverters 378
8.1 Introduction 331 PWM Three-Phase
8.2 The Full-Bridge Converter 331 Inverters 378
8.3 The Square-Wave Inverter 333 8.17 Induction Motor Speed
8.4 Fourier Series Analysis 337 Control 379
8.5 Total Harmonic Distortion 339 8.18 Summary 382
8.6 PSpice Simulation of Square Wave 8.19 Bibliography 383
Inverters 340 Problems 383
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Contents ix
Chapter 9 Chapter 10
Resonant Converters 387 Drive Circuits, Snubber Circuits,
and Heat Sinks 431
9.1 Introduction 387
9.2 A Resonant Switch Converter: 10.1 Introduction 431
Zero-Current Switching 387 10.2 MOSFET and IGBT Drive
Basic Operation 387 Circuits 431
Output Voltage 392 Low-Side Drivers 431
9.3 A Resonant Switch Converter: High-Side Drivers 433
Zero-Voltage Switching 394 10.3 Bipolar Transistor Drive
Basic Operation 394 Circuits 437
Output Voltage 399 10.4 Thyristor Drive Circuits 440
9.4 The Series Resonant Inverter 401 10.5 Transistor Snubber Circuits 441
Switching Losses 403 10.6 Energy Recovery Snubber
Amplitude Control 404 Circuits 450
9.5 The Series Resonant 10.7 Thyristor Snubber Circuits 450
DC-DC Converter 407 10.8 Heat Sinks and Thermal
Basic Operation 407 Management 451
Operation for ωs ⬎ ωo 407 Steady-State Temperatures 451
Operation for ω0 /2 ⬍ ωs⬍ ω0 413 Time-Varying Temperatures 454
Operation for ωs ⬍ ω0 /2 413 10.9 Summary 457
Variations on the Series Resonant DC-DC 10.10 Bibliography 457
Converter 414 Problems 458
9.6 The Parallel Resonant
DC-DC Converter 415 Appendix A Fourier Series for Some
9.7 The Series-Parallel DC-DC Common Waveforms 461
Converter 418
9.8 Resonant Converter Comparison 421 Appendix B State-Space Averaging 467
9.9 The Resonant DC Link Converter 422 Index 473
9.10 Summary 426
9.11 Bibliography 426
Problems 427
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PREFACE
T
his book is intended to be an introductory text in power electronics, primar-
ily for the undergraduate electrical engineering student. The text assumes
that the student is familiar with general circuit analysis techniques usually
taught at the sophomore level. The student should be acquainted with electronic
devices such as diodes and transistors, but the emphasis of this text is on circuit
topology and function rather than on devices. Understanding the voltage-current
relationships for linear devices is the primary background required, and the concept
of Fourier series is also important. Most topics presented in this text are appropriate
for junior- or senior-level undergraduate electrical engineering students.
The text is designed to be used for a one-semester power electronics
course, with appropriate topics selected or omitted by the instructor. The text
is written for some flexibility in the order of the topics. It is recommended that
Chap. 2 on power computations be covered at the beginning of the course in
as much detail as the instructor deems necessary for the level of students.
Chapters 6 and 7 on dc-dc converters and dc power supplies may be taken before
Chaps. 3, 4, and 5 on rectifiers and voltage controllers. The author covers chap-
ters in the order 1, 2 (introduction; power computations), 6, 7 (dc-dc converters;
dc power supplies), 8 (inverters), 3, 4, 5 (rectifiers and voltage controllers), fol-
lowed by coverage of selected topics in 9 (resonant converters) and 10 (drive and
snubber circuits and heat sinks). Some advanced material, such as the control
section in Chapter 7, may be omitted in an introductory course.
The student should use all the software tools available for the solution
to the equations that describe power electronics circuits. These range from
calculators with built-in functions such as integration and root finding to
more powerful computer software packages such as MATLAB®, Mathcad®,
Maple™, Mathematica®, and others. Numerical techniques are often sug-
gested in this text. It is up to the student to select and adapt all the readily
available computer tools to the power electronics situation.
Much of this text includes computer simulation using PSpice® as a supple-
ment to analytical circuit solution techniques. Some prior experience with
PSpice is helpful but not necessary. Alternatively, instructors may choose to use
a different simulation program such as PSIM® or NI Multisim™ software instead
of PSpice. Computer simulation is never intended to replace understanding of
fundamental principles. It is the author’s belief that using computer simulation
for the instructional benefit of investigating the basic behavior of power elec-
tronics circuits adds a dimension to the student’s learning that is not possible
from strictly manipulating equations. Observing voltage and current waveforms
from a computer simulation accomplishes some of the same objectives as those
xi
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xii Preface
of a laboratory experience. In a computer simulation, all the circuit’s voltages

and currents can be investigated, usually much more efficiently than in a hard-
ware lab. Variations in circuit performance for a change in components or oper-
ating parameters can be accomplished more easily with a computer simulation
than in a laboratory. PSpice circuits presented in this text do not necessarily rep-
resent the most elegant way to simulate circuits. Students are encouraged to use
their engineering skills to improve the simulation circuits wherever possible.
The website that accompanies this text can be found at www.mhhe
.com/hart, and features Capture circuit files for PSpice simulation for students
and instructors and a password-protected solutions manual and PowerPoint®
lecture notes for instructors.
My sincere gratitude to reviewers and students who have made many
valuable contributions to this project. Reviewers include
Ali Emadi
Illinois Institute of Technology
Shaahin Filizadeh
University of Manitoba
James Gover
Kettering University
Peter Idowu
Penn State, Harrisburg
Mehrdad Kazerani
University of Waterloo
Xiaomin Kou
University of Wisconsin-Platteville
Alexis Kwasinski
The University of Texas at Austin
Medhat M. Morcos
Kansas State University
Steve Pekarek
Purdue University
Wajiha Shireen
University of Houston
Hamid Toliyat
Texas A&M University
Zia Yamayee
University of Portland
Lin Zhao
Gannon University
A special thanks to my colleagues Kraig Olejniczak, Mark Budnik, and
Michael Doria at Valparaiso University for their contributions. I also thank
Nikke Ault for the preparation of much of the manuscript.
har80679_FM_i-xiv.qxd 12/17/09 12:38 PM Page xiii
Preface xiii
Complete Online Solutions Manual Organization System (COSMOS). Pro-

fessors can benefit from McGraw-Hill’s COSMOS electronic solutions manual.
COSMOS enables instructors to generate a limitless supply of problem mate-
rial for assignment, as well as transfer and integrate their own problems
into the software. For additional information, contact your McGraw-Hill sales
representative.
Electronic Textbook Option. This text is offered through CourseSmart for both
instructors and students. CourseSmart is an online resource where students can
purchase the complete text online at almost one-half the cost of a traditional text.
Purchasing the eTextbook allows students to take advantage of CourseSmart’s Web
tools for learning, which include full text search, notes and highlighting, and e-mail
tools for sharing notes among classmates. To learn more about CourseSmart options,
contact your McGraw-Hill sales representative or visit www.CourseSmart.com.
Daniel W. Hart
Valparaiso University
Valparaiso, Indiana
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C H A P T E R 1
Introduction
1.1 POWER ELECTRONICS

Power electronics circuits convert electric power from one form to another using
electronic devices. Power electronics circuits function by using semiconductor
devices as switches, thereby controlling or modifying a voltage or current. Appli-
cations of power electronics range from high-power conversion equipment such
as dc power transmission to everyday appliances, such as cordless screwdrivers,
power supplies for computers, cell phone chargers, and hybrid automobiles.
Power electronics includes applications in which circuits process milliwatts or
megawatts. Typical applications of power electronics include conversion of ac to
dc, conversion of dc to ac, conversion of an unregulated dc voltage to a regulated
dc voltage, and conversion of an ac power source from one amplitude and fre-
quency to another amplitude and frequency.
The design of power conversion equipment includes many disciplines from
electrical engineering. Power electronics includes applications of circuit theory,
control theory, electronics, electromagnetics, microprocessors (for control), and
heat transfer. Advances in semiconductor switching capability combined with the
desire to improve the efficiency and performance of electrical devices have made
power electronics an important and fast-growing area in electrical engineering.
1.2 CONVERTER CLASSIFICATION

The objective of a power electronics circuit is to match the voltage and current re-
quirements of the load to those of the source. Power electronics circuits convert one
type or level of a voltage or current waveform to another and are hence called
converters. Converters serve as an interface between the source and load (Fig. 1-1).
1
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2 C H A P T E R 1 Introduction
Input Output
Source Converter Load
Figure 1-1 A source and load interfaced by a power electronics converter.
Converters are classified by the relationship between input and output:

ac input/dc output
The ac-dc converter produces a dc output from an ac input. Average power
is transferred from an ac source to a dc load. The ac-dc converter is
specifically classified as a rectifier. For example, an ac-dc converter
enables integrated circuits to operate from a 60-Hz ac line voltage by
converting the ac signal to a dc signal of the appropriate voltage.
dc input/ac output
The dc-ac converter is specifically classified as an inverter. In the inverter,
average power flows from the dc side to the ac side. Examples of inverter
applications include producing a 120-V rms 60-Hz voltage from a 12-V
battery and interfacing an alternative energy source such as an array of
solar cells to an electric utility.
dc input/dc output
The dc-dc converter is useful when a load requires a specified (often
regulated) dc voltage or current but the source is at a different or
unregulated dc value. For example, 5 V may be obtained from a 12-V
source via a dc-dc converter.
ac input/ac output
The ac-ac converter may be used to change the level and/or frequency of
an ac signal. Examples include a common light-dimmer circuit and speed
control of an induction motor.
Some converter circuits can operate in different modes, depending on circuit
and control parameters. For example, some rectifier circuits can be operated as
inverters by modifying the control on the semiconductor devices. In such cases,
it is the direction of average power flow that determines the converter classifica-
tion. In Fig. 1-2, if the battery is charged from the ac power source, the converter
is classified as a rectifier. If the operating parameters of the converter are changed
and the battery acts as a source supplying power to the ac system, the converter
is then classified as an inverter.
Power conversion can be a multistep process involving more than one type
of converter. For example, an ac-dc-ac conversion can be used to modify an ac
source by first converting it to direct current and then converting the dc signal to
an ac signal that has an amplitude and frequency different from those of the orig-
inal ac source, as illustrated in Fig. 1-3.
har80679_ch01_001-020.qxd 12/17/09 12:49 PM Page 3
1.3 Power Electronics Concepts 3
Rectifier
P
+
+
Converter
− −
P
Inverter
Figure 1-2 A converter can operate as a rectifier or an inverter, depending on the direction
of average power P.
Input Output
Source Converter 1 Converter 2 Load
Figure 1-3 Two converters are used in a multistep process.
1.3 POWER ELECTRONICS CONCEPTS

To illustrate some concepts in power electronics, consider the design problem of
creating a 3-V dc voltage level from a 9-V battery. The purpose is to supply 3 V
to a load resistance. One simple solution is to use a voltage divider, as shown in
Fig. 1-4. For a load resistor RL, inserting a series resistance of 2RL results in 3 V
across RL. A problem with this solution is that the power absorbed by the 2RL
resistor is twice as much as delivered to the load and is lost as heat, making the
circuit only 33.3 percent efficient. Another problem is that if the value of the load
resistance changes, the output voltage will change unless the 2RL resistance
changes proportionally. A solution to that problem could be to use a transistor in
place of the 2RL resistance. The transistor would be controlled such that the volt-
age across it is maintained at 6 V, thus regulating the output at 3 V. However, the
same low-efficiency problem is encountered with this solution.
To arrive at a more desirable design solution, consider the circuit in Fig. 1-5a.
In that circuit, a switch is opened and closed periodically. The switch is a short
circuit when it is closed and an open circuit when it is open, making the voltage
2RL +
+
9V RL 3V
−
−
Figure 1-4 A simple voltage divider for creating 3 V from a 9-V source.
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 4
+
+
9V vx(t)
− −
(a)
vx(t)
9V
3V Average
t
T T
3
(b)
Figure 1-5 (a) A switched circuit; (b) a pulsed voltage waveform.
across RL equal to 9 V when the switch is closed and 0 V when the switch is open.
The resulting voltage across RL will be like that of Fig. 1-5b. This voltage is
obviously not a constant dc voltage, but if the switch is closed for one-third of the
period, the average value of vx (denoted as Vx) is one-third of the source voltage.
Average value is computed from the equation
T T/3 T
1 1 1
avg(vx) ⫽ Vx ⫽ vx(t) dt ⫽ 9 dt ⫹ 0 dt ⫽ 3 V (1-1)
T3 T3 T3
0 0 T/3
Considering efficiency of the circuit, instantaneous power (see Chap. 2)
absorbed by the switch is the product of voltage and current. When the switch is
open, power absorbed by it is zero because the current in it is zero. When the
switch is closed, power absorbed by it is zero because the voltage across it is
zero. Since power absorbed by the switch is zero for both open and closed con-
ditions, all power supplied by the 9-V source is delivered to RL, making the cir-
cuit 100 percent efficient.
The circuit so far does not accomplish the design object of creating a dc volt-
age of 3 V. However, the voltage waveform vx can be expressed as a Fourier series
containing a dc term (the average value) plus sinusoidal terms at frequencies that
are multiples of the pulse frequency. To create a 3-V dc voltage, vx is applied to a
low-pass filter. An ideal low-pass filter allows the dc component of voltage to pass
through to the output while removing the ac terms, thus creating the desired dc
output. If the filter is lossless, the converter will be 100 percent efficient.
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1.4 Electronic Switches 5
+ + +
9V vx(t) Low-Pass Filter RL 3V
− − −
Figure 1-6 A low-pass filter allows just the average value of vx to pass through to the load.
Switch Control
+ +
+
Vs vx(t) Low-Pass Filter Vo
− −
−
Figure 1-7 Feedback is used to control the switch and maintain the desired output voltage.
In practice, the filter will have some losses and will absorb some power.
Additionally, the electronic device used for the switch will not be perfect and will
have losses. However, the efficiency of the converter can still be quite high (more
than 90 percent). The required values of the filter components can be made smaller
with higher switching frequencies, making large switching frequencies desirable.
Chaps. 6 and 7 describe the dc-dc conversion process in detail. The “switch” in this
example will be some electronic device such as a metal-oxide field-effect transis-
tors (MOSFET), or it may be comprised of more than one electronic device.
The power conversion process usually involves system control. Converter
output quantities such as voltage and current are measured, and operating para-
meters are adjusted to maintain the desired output. For example, if the 9-V bat-
tery in the example in Fig. 1-6 decreased to 6 V, the switch would have to be
closed 50 percent of the time to maintain an average value of 3 V for vx. A feed-
back control system would detect if the output voltage were not 3 V and adjust
the closing and opening of the switch accordingly, as illustrated in Fig. 1-7.
1.4 ELECTRONIC SWITCHES

An electronic switch is characterized by having the two states on and off, ideally
being either a short circuit or an open circuit. Applications using switching
devices are desirable because of the relatively small power loss in the device. If
the switch is ideal, either the switch voltage or the switch current is zero, making
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 6
the power absorbed by it zero. Real devices absorb some power when in the on
state and when making transitions between the on and off states, but circuit effi-
ciencies can still be quite high. Some electronic devices such as transistors can
also operate in the active range where both voltage and current are nonzero, but
it is desirable to use these devices as switches when processing power.
The emphasis of this textbook is on basic circuit operation rather than on
device performance. The particular switching device used in a power electronics
circuit depends on the existing state of device technology. The behaviors of
power electronics circuits are often not affected significantly by the actual device
used for switching, particularly if voltage drops across a conducting switch are
small compared to other circuit voltages. Therefore, semiconductor devices are
usually modeled as ideal switches so that circuit behavior can be emphasized.
Switches are modeled as short circuits when on and open circuits when off. Tran-
sitions between states are usually assumed to be instantaneous, but the effects of
nonideal switching are discussed where appropriate. A brief discussion of semi-
conductor switches is given in this section, and additional information relating to
drive and snubber circuits is provided in Chap. 10. Electronic switch technology
is continually changing, and thorough treatments of state-of-the-art devices can
be found in the literature.
The Diode
A diode is the simplest electronic switch. It is uncontrollable in that the on and
off conditions are determined by voltages and currents in the circuit. The diode
is forward-biased (on) when the current id (Fig. 1-8a) is positive and reverse-
biased (off) when vd is negative. In the ideal case, the diode is a short circuit
Anode
id
+ id i
vd On
− Off
vd v
Cathode
(a) (b) (c)
i
On
Off
t
trr
(d) (e)
Figure 1-8 (a) Rectifier diode; (b) i-v characteristic; (c) idealized i-v characteristic;
(d) reverse recovery time trr; (e) Schottky diode.
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 7
when it is forward-biased and is an open circuit when reverse-biased. The actual

and idealized current-voltage characteristics are shown in Fig. 1-8b and c. The
idealized characteristic is used in most analyses in this text.
An important dynamic characteristic of a nonideal diode is reverse recovery
current. When a diode turns off, the current in it decreases and momentarily
becomes negative before becoming zero, as shown in Fig. 1-8d. The time trr is
the reverse recovery time, which is usually less than 1 ␮s. This phenomenon
may become important in high-frequency applications. Fast-recovery diodes
are designed to have a smaller trr than diodes designed for line-frequency appli-
cations. Silicon carbide (SiC) diodes have very little reverse recovery, resulting
in more efficient circuits, especially in high-power applications.
Schottky diodes (Fig. 1-8e) have a metal-to-silicon barrier rather than a P-N
junction. Schottky diodes have a forward voltage drop of typically 0.3 V. These
are often used in low-voltage applications where diode drops are significant rel-
ative to other circuit voltages. The reverse voltage for a Schottky diode is limited
to about 100 V. The metal-silicon barrier in a Schottky diode is not subject to
recovery transients and turn-on and off faster than P-N junction diodes.
Thyristors
Thyristors are electronic switches used in some power electronic circuits where
control of switch turn-on is required. The term thyristor often refers to a family
of three-terminal devices that includes the silicon-controlled rectifier (SCR), the
triac, the gate turnoff thyristor (GTO), the MOS-controlled thyristor (MCT), and
others. Thyristor and SCR are terms that are sometimes used synonymously. The
SCR is the device used in this textbook to illustrate controlled turn-on devices in
the thyristor family. Thyristors are capable of large currents and large blocking
voltages for use in high-power applications, but switching frequencies cannot be
as high as when using other devices such as MOSFETs.
The three terminals of the SCR are the anode, cathode, and gate (Fig.1-9a).
For the SCR to begin to conduct, it must have a gate current applied while it has
a positive anode-to-cathode voltage. After conduction is established, the gate sig-
nal is no longer required to maintain anode current. The SCR will continue to
conduct as long as the anode current remains positive and above a minimum
value called the holding level. Figs. 1-9a and b show the SCR circuit symbol and
the idealized current-voltage characteristic.
The gate turnoff thyristor (GTO) of Fig. 1-9c, like the SCR, is turned on by
a short-duration gate current if the anode-to-cathode voltage is positive. How-
ever, unlike the SCR, the GTO can be turned off with a negative gate current.
The GTO is therefore suitable for some applications where control of both
turn-on and turnoff of a switch is required. The negative gate turnoff current
can be of brief duration (a few microseconds), but its magnitude must be very
large compared to the turn-on current. Typically, gate turnoff current is one-
third the on-state anode current. The idealized i-v characteristic is like that of
Fig. 1-9b for the SCR.
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 8
Anode
A Anode
i A
+ iA
vAK On
Gate −
Off
G Gate
K vAK
Cathode Cathode
(a) (b) (c)
Anode
MT2 A A
G
Gate
or
G
Gate
K K
MT1 Cathode
(d) (e)
Figure 1-9 Thyristor devices: (a) silicon-controlled rectifier (SCR); (b) SCR idealized i-v
characteristic; (c) gate turnoff (GTO) thyristor; (d) triac; (e) MOS-controlled thyristor (MCT).
The triac (Fig. 1-9d) is a thyristor that is capable of conducting current in

either direction. The triac is functionally equivalent to two antiparallel SCRs
(in parallel but in opposite directions). Common incandescent light-dimmer cir-
cuits use a triac to modify both the positive and negative half cycles of the input
sine wave.
The MOS-controlled thyristor (MCT) in Fig. 1-9e is a device functionally
equivalent to the GTO but without the high turnoff gate current requirement. The
MCT has an SCR and two MOSFETs integrated into one device. One MOSFET
turns the SCR on, and one MOSFET turns the SCR off. The MCT is turned on
and off by establishing the proper voltage from gate to cathode, as opposed to es-
tablishing a gate current in the GTO.
Thyristors were historically the power electronics switch of choice because
of high voltage and current ratings available. Thyristors are still used, especially
in high-power applications, but ratings of power transistors have increased
greatly, making the transistor more desirable in many applications.
Transistors
Transistors are operated as switches in power electronics circuits. Transistor drive
circuits are designed to have the transistor either in the fully on or fully off state.
This differs from other transistor applications such as in a linear amplifier circuit
where the transistor operates in the region having simultaneously high voltage
and current.
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 9
Drain
D iD iD iD
On
+ vGS3
vGS2
Gate vDS
G + vGS1
−
vGS = 0 Off
vGS
vDS vDS
− S
Source
Figure 1-10 (a) MOSFET (N-channel) with body diode; (b) MOSFET characteristics;
(c) idealized MOSFET characteristics.
Unlike the diode, turn-on and turnoff of a transistor are controllable. Types of
transistors used in power electronics circuits include MOSFETs, bipolar junction
transistors (BJTs), and hybrid devices such as insulated-gate bipolar junction tran-
sistors (IGBTs). Figs. 1-10 to 1-12 show the circuit symbols and the current-voltage
characteristics.
The MOSFET (Fig. 1-10a) is a voltage-controlled device with characteris-
tics as shown in Fig. 1-10b. MOSFET construction produces a parasitic (body)
diode, as shown, which can sometimes be used to an advantage in power elec-
tronics circuits. Power MOSFETs are of the enhancement type rather than the
depletion type. A sufficiently large gate-to-source voltage will turn the device on,
Collector
C
iC iC iB3
B +
vCE iB2
Base
iB − iB1
E iB = 0
Emitter vCE(SAT) vCE
(a)
(b)
iC
On
Off
vCE
(c) (d)
Figure 1-11 (a) BJT (NPN); (b) BJT characteristics; (c) idealized BJT characteristics;
(d) Darlington configuration.
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 10
E
(a)
Collector
C
Gate G
E
Emitter
(b)
Figure 1-12 IGBT: (a) Equivalent circuit; (b) circuit symbols.
resulting in a small drain-to-source voltage. In the on state, the change in vDS is

linearly proportional to the change in iD. Therefore, the on MOSFET can be mod-
eled as an on-state resistance called RDS(on). MOSFETs have on-state resistances
as low as a few milliohms. For a first approximation, the MOSFET can be mod-
eled as an ideal switch with a characteristic shown in Fig. 1-10c. Ratings are to
1500 V and more than 600 A (although not simultaneously). MOSFET switching
speeds are greater than those of BJTs and are used in converters operating into
the megahertz range.
Typical BJT characteristics are shown in Fig. 1-11b. The on state for the
transistor is achieved by providing sufficient base current to drive the BJT
into saturation. The collector-emitter saturation voltage is typically 1 to 2 V
for a power BJT. Zero base current results in an off transistor. The idealized
i-v characteristic for the BJT is shown in Fig. 1-11c. The BJT is a current-
controlled device, and power BJTs typically have low hFE values, sometimes
lower than 20. If a power BJT with hFE = 20 is to carry a collector current of
60 A, for example, the base current would need to be more than 3 A to put the
transistor into saturation. The drive circuit to provide a high base current is a
significant power circuit in itself. Darlington configurations have two BJTs
connected as shown in Fig. 1-11d. The effective current gain of the combina-
tion is approximately the product of individual gains and can thus reduce the
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 11
1.5 Switch Selection 11
current required from the drive circuit. The Darlington configuration can be
constructed from two discrete transistors or can be obtained as a single inte-
grated device. Power BJTs are rarely used in new applications, being sur-
passed by MOSFETs and IGBTs.
The IGBT of Fig. 1-12 is an integrated connection of a MOSFET and
a BJT. The drive circuit for the IGBT is like that of the MOSFET, while the
on-state characteristics are like those of the BJT. IGBTs have replaced BJTs in
many applications.
1.5 SWITCH SELECTION

The selection of a power device for a particular application depends not only on
the required voltage and current levels but also on its switching characteristics.
Transistors and GTOs provide control of both turn-on and turnoff, SCRs of turn-
on but not turnoff, and diodes of neither.
Switching speeds and the associated power losses are very important in
power electronics circuits. The BJT is a minority carrier device, whereas the
MOSFET is a majority carrier device that does not have minority carrier storage
delays, giving the MOSFET an advantage in switching speeds. BJT switching
times may be a magnitude larger than those for the MOSFET. Therefore, the
MOSFET generally has lower switching losses and is preferred over the BJT.
When selecting a suitable switching device, the first consideration is the
required operating point and turn-on and turnoff characteristics. Example 1-1
outlines the selection procedure.
EXAMPLE 1-1
Switch Selection
The circuit of Fig. 1-13a has two switches. Switch S1 is on and connects the voltage
source (Vs = 24 V) to the current source (Io = 2 A). It is desired to open switch S1 to dis-
connect Vs from the current source. This requires that a second switch S2 close to provide
a path for current Io, as in Fig. 1-13b. At a later time, S1 must reclose and S2 must open to
restore the circuit to its original condition. The cycle is to repeat at a frequency of 200 kHz.
Determine the type of device required for each switch and the maximum voltage and cur-
rent requirements of each.
■ Solution
The type of device is chosen from the turn-on and turnoff requirements, the voltage and
current requirements of the switch for the on and off states, and the required switching
speed.
The steady-state operating points for S1 are at (v1, i1) = (0, Io) for S1 closed and (Vs, 0)
for the switch open (Fig. 1-13c). The operating points are on the positive i and v axes, and
S1 must turn off when i1 = Io ⬎ 0 and must turn on when v1 = Vs ⬎ 0. The device used for
S1 must therefore provide control of both turn-on and turnoff. The MOSFET characteristic
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 12
i1 i1 S1
S1
+ v1 − + v1 −
− −
+ + v2
Vs v2 Io Vs S2 Io
− S2 −
+ +
i2 i2
(a) (b)
i1 i2
S1 S2
(0, Io) Closed (0, Io) Closed
Open Open
v1 v2
(Vs, 0) (−Vs, 0)
(c) (d)
S1
S1
+
Vs S2 Io
− +
Io
−
S2
(e) (f)
Figure 1-13 Circuit for Example 1-1. (a) S1 closed, S2 open; (b) S1 open, S2 closed;
(c) operating points for S1; (d) operating points for S2; (e) switch implementation using
a MOSFET and diode; (f) switch implementation using two MOSFETs (synchronous
rectification).
of Fig. 1-10d or the BJT characteristic of Fig. 1-11c matches the requirement. A MOSFET
would be a good choice because of the required switching frequency, simple gate-drive
requirements, and relatively low voltage and current requirement (24 V and 2 A).
The steady-state operating points for S2 are at (v2, i2) = (⫺Vs, 0) in Fig. 1-13a and
(0, Io) in Fig. 1-13b, as shown in Fig. 1-13d. The operating points are on the positive cur-
rent axis and negative voltage axis. Therefore, a positive current in S2 is the requirement
to turn S2 on, and a negative voltage exists when S2 must turn off. Since the operating
points match the diode (Fig. 1-8c) and no other control is needed for the device, a diode
is an appropriate choice for S2. Figure 1-13e shows the implementation of the switching
circuit. Maximum current is 2 A, and maximum voltage in the blocking state is 24 V.
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 13
1.6 SPICE, PSpice, and Capture 13
Although a diode is a sufficient and appropriate device for the switch S2, a MOSFET
would also work in this position, as shown in Fig. 1-13f. When S2 is on and S1 is off, cur-
rent flows upward out of the drain of S2. The advantage of using a MOSFET is that it has
a much lower voltage drop across it when conducting compared to a diode, resulting in
lower power loss and a higher circuit efficiency. The disadvantage is that a more complex
control circuit is required to turn on S2 when S1 is turned off. However, several control cir-
cuits are available to do this. This control scheme is known as synchronous rectification
or synchronous switching.
In a power electronics application, the current source in this circuit could represent
an inductor that has a nearly constant current in it.
1.6 SPICE, PSPICE, AND CAPTURE

Computer simulation is a valuable analysis and design tool that is emphasized
throughout this text. SPICE is a circuit simulation program developed in the
Department of Electrical Engineering and Computer Science at the University of
California at Berkeley. PSpice is a commercially available adaptation of SPICE
that was developed for the personal computer. Capture is a graphical interface
program that enables a simulation to be done from a graphical representation of
a circuit diagram. Cadence provides a product called OrCAD Capture, and a
demonstration version at no cost.1 Nearly all simulations described in this text-
book can be run using the demonstration version.
Simulation can take on various levels of device and component modeling,
depending on the objective of the simulation. Most of the simulation examples
and exercises use idealized or default component models, making the results
first-order approximations, much the same as the analytical work done in the first
discussion of a subject in any textbook. After understanding the fundamental op-
eration of a power electronics circuit, the engineer can include detailed device
models to predict more accurately the behavior of an actual circuit.
Probe, the graphics postprocessor program that accompanies PSpice, is
especially useful. In Probe, the waveform of any current or voltage in a cir-
cuit can be shown graphically. This gives the student a look at circuit behav-
ior that is not possible with pencil-and-paper analysis. Moreover, Probe is
capable of mathematical computations involving currents and/or voltages,
including numerical determination of rms and average values. Examples of
PSpice analysis and design for power electronics circuits are an integral part
of this textbook.
The PSpice circuit files listed in this text were developed using version
16.0. Continuous revision of software necessitates updates in simulation
techniques.
1
https://www.cadence.com/products/orcad/pages/downloads.aspx#demo
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 14
R = 106 Ω Off (Open)

R = 10−3 Ω On (Closed)
Figure 1-14 Implementing a switch with a resistance in PSpice.
1.7 SWITCHES IN PSPICE

The Voltage-Controlled Switch
The voltage-controlled switch Sbreak in PSpice can be used as an idealized model
for most electronic devices. The voltage-controlled switch is a resistance that has
a value established by a controlling voltage. Fig. 1-14 illustrates the concept of
using a controlled resistance as a switch for PSpice simulation of power electron-
ics circuits. A MOSFET or other switching device is ideally an open or closed
switch. A large resistance approximates an open switch, and a small resistance ap-
proximates a closed switch. Switch model parameters are as follows:
Parameter Description Default Value

RON “On” resistance 1 (reduce this to 0.001 or 0.01 ⍀)
ROFF “Off” resistance 106 ⍀
VON Control voltage for on state 1.0 V
VOFF Control voltage for off state 0V
The resistance is changed from large to small by the controlling voltage. The
default off resistance is 1 M⍀, which is a good approximation for an open circuit
in power electronics applications. The default on resistance of 1 ⍀ is usually too
large. If the switch is to be ideal, the on resistance in the switch model should be
changed to something much lower, such as 0.001 or 0.01 ⍀.
EXAMPLE 1-2
A Voltage-Controlled Switch in PSpice

The Capture diagram of a switching circuit is shown in Fig. 1-15a. The switch is
implemented with the voltage-controlled switch Sbreak, located in the Breakout li-
brary of devices. The control voltage is VPULSE and uses the characteristics shown.
The rise and fall times, TR and TF, are made small compared to the pulse width and
period, PW and PER. V1 and V2 must span the on and off voltage levels for the
switch, 0 and 1 V by default. The switching period is 25 ms, corresponding to a fre-
quency of 40 kHz.
The PSpice model for Sbreak is accessed by clicking edit, then PSpice model. The
model editor window is shown in Fig 1-15b. The on resistance Ron is changed to 0.001 ⍀
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 15
1.7 Switches in PSpice 15
VPULSE
S1
V1 = 0 + + +
V2 = 5 Vs
+ Vcontrol – –
24V
TD = 0 Sbreak
TR = 1n − −
TF = 1n 0
Rload 2
PW = 10us
PER = 25us
0
(a)
(b)
(c)
Figure 1-15 (a) Circuit for Example 1-2; (b) editing the PSpice Sbreak switch model to
make Ron = 0.001⍀; (c) the transient analysis setup; (d) the Probe output.
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 16
10.0 V
Switch Control Voltage

7.5 V
5.0 V
2.5 V
0V
V(Vcontrol:+)
40 V
Load Resistor Voltage
20 V
SEL>>
0V
0s 20 ␮s 40 ␮s 60 ␮s 80 ␮s
V(Rload:2)
Time
(d)
Figure 1-15 (continued)
to approximate an ideal switch. The Transient Analysis menu is accessed from Simulation
Settings. This simulation has a run time of 80 ␮s, as shown in Fig. 1-15c.
Probe output showing the switch control voltage and the load resistor voltage wave-
forms is seen in Fig. 1-15d.
Transistors
Transistors used as switches in power electronics circuits can be idealized for
simulation by using the voltage-controlled switch. As in Example 1-2, an ideal
transistor can be modeled as very small on resistance. An on resistance matching
the MOSFET characteristics can be used to simulate the conducting resistance
RDS(ON) of a MOSFET to determine the behavior of a circuit with nonideal com-
ponents. If an accurate representation of a transistor is required, a model may be
available in the PSpice library of devices or from the manufacturer’s website. The
IRF150 and IRF9140 models for power MOSFETs are in the demonstration ver-
sion library. The default MOSFET MbreakN or MbreakN3 model must have
parameters for the threshold voltage VTO and the constant KP added to the
PSpice device model for a meaningful simulation. Manufacturer’s websites, such
as International Rectifier at www.irf.com, have SPICE models available for their
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 17
1.7 Switches in PSpice 17
VPULSE RG M1
V1 = 0 IRF150
V2 = 12 + Vcontrol 10 + Vs
TD = 0 24V
− −
TR = 1n
TF = 1n
Rload 2
PW = 10us
PER = 25us
0
Figure 1-16 An idealized MOSFET drive circuit in PSpice.
products. The default BJT QbreakN can be used instead of a detailed transistor
model for a rudimentary simulation.
Transistors in PSpice must have drive circuits, which can be idealized if the
behavior of a specific drive circuit is not required. Simulations with MOSFETs
can have drive circuits like that in Fig. 1-16. The voltage source VPULSE estab-
lishes the gate-to-source voltage of the MOSFET to turn it on and off. The gate
resistor may not be necessary, but it sometimes eliminates numerical conver-
gence problems.
Diodes
An ideal diode is assumed when one is developing the equations that describe a
power electronics circuit, which is reasonable if the circuit voltages are much
larger than the normal forward voltage drop across a conducting diode. The
diode current is related to diode voltage by
id ⫽ ISevd>nVT ⫺ 1 (1-2)
where n is the emission coefficient which has a default value of 1 in PSpice. An

ideal diode can be approximated in PSpice by setting n to a small number such
as 0.001 or 0.01. The nearly ideal diode is modeled with the part Dbreak with
PSpice model
model Dbreak D n ⫽ 0.001
With the ideal diode model, simulation results will match the analytical
results from the describing equations. A PSpice diode model that more accu-
rately predicts diode behavior can be obtained from a device library. Simula-
tions with a detailed diode model will produce more realistic results than the
idealized case. However, if the circuit voltages are large, the difference
between using an ideal diode and an accurate diode model will not affect the
results in any significant way. The default diode model for Dbreak can be used
as a compromise between the ideal and actual cases, often with little differ-
ence in the result.
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 18
Figure 1-17 Simplified thyristor (SCR) model for PSpice.
Thyristors (SCRs)
An SCR model is available in the PSpice demonstration version part library and
can be used in simulating SCR circuits. However, the model contains a relatively
large number of components which imposes a size limit for the PSpice demonstra-
tion version. A simple SCR model that is used in several circuits in this text is a
switch in series with a diode, as shown in Fig. 1-17. Closing the voltage-controlled
switch is equivalent to applying a gate current to the SCR, and the diode prevents
reverse current in the model. This simple SCR model has the significant disadvan-
tage of requiring the voltage-controlled switch to remain closed during the entire
on time of the SCR, thus requiring some prior knowledge of the behavior of a cir-
cuit that uses the device. Further explanation is included with the PSpice examples
in later chapters.
Convergence Problems in PSpice

Some of the PSpice simulations in this book are subject to numerical conver-
gence problems because of the switching that takes place in circuits with
inductors and capacitors. All the PSpice files presented in this text have been
designed to avoid convergence problems. However, sometimes changing a
circuit parameter will cause a failure to converge in the transient analysis. In
the event that there is a problem with PSpice convergence, the following
remedies may be useful:
• Increase the iteration limit ITL4 from 10 to 100 or larger. This is an
option accessed from the Simulation Profile Options, as shown in
Fig. 1-18.
• Change the relative tolerance RELTOL to something other than the default
value of 0.001.
• Change the device models to something that is less than ideal. For example,
change the on resistance of a voltage-controlled switch to a larger value, or
use a controlling voltage source that does not change as rapidly. An ideal
diode could be made less ideal by increasing the value of n in the model.
Generally, idealized device models will introduce more convergence
problems than real device models.
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 19
1.8 Bibliography 19
Figure 1-18 The Options menu for settings that can solve convergence problems. RELTOL
and ITL4 have been changed here.
Figure 1-19 RC circuit to aid in PSpice convergence.
• Add an RC “snubber” circuit. A series resistance and capacitance with a

small time constant can be placed across switches to prevent voltages
from changing too rapidly. For example, placing a series combination of
a 1-k⍀ resistor and a 1-nF capacitor in parallel with a diode (Fig. 1-19)
may improve convergence without affecting the simulation results.
1.8 BIBLIOGRAPHY
M. E. Balci and M. H. Hocaoglu, “Comparison of Power Definitions for Reactive
Power Compensation in Nonsinusoidal Circuits,” International Conference on
Harmonics and Quality of Power, Lake Placid, N.Y. 2004.
har80679_ch01_001-020.qxd 12/15/09 2:27 PM Page 20
L. S. Czarnecki, “Considerations on the Reactive Power in Nonsinusoidal Situations,”

International Conference on Harmonics in Power Systems, Worcester Polytechnic
Institute, Worcester, Mass., 1984, pp 231–237.
A. E. Emanuel, “Powers in Nonsinusoidal Situations, A Review of Definitions
and Physical Meaning,” IEEE Transactions on Power Delivery, vol. 5, no. 3,
July 1990.
G. T. Heydt, Electric Power Quality, Stars in a Circle Publications, West Lafayette,
Ind., 1991.
W. Sheperd and P. Zand, Energy Flow and Power Factor in Nonsinusoidal Circuits,
Cambridge University Press, 1979.
Problems
1-1. The current source in Example 1-1 is reversed so that positive current is upward.
The current source is to be connected to the voltage source by alternately closing
S1 and S2. Draw a circuit that has a MOSFET and a diode to accomplish this
switching.
1-2. Simulate the circuit in Example 1-1 using PSpice. Use the voltage-controlled
switch Sbreak for S1 and the diode Dbreak for S2. (a) Edit the PSpice models to
idealize the circuit by using RON = 0.001 ⍀ for the switch and n = 0.001 for the
diode. Display the voltage across the current source in Probe. (b) Use RON = 0.1 ⍀
in Sbreak and n = 1 (the default value) for the diode. How do the results of parts
a and b differ?
1-3. The IRF150 power MOSFET model is in the EVAL library that accompanies the
demonstration version of PSpice. Simulate the circuit in Example 1-1, using the
IRF150 for the MOSFET and the default diode model Dbreak for S2. Use an
idealized gate drive circuit similar to that of Fig. 1-16. Display the voltage
across the current source in Probe. How do the results differ from those using
ideal switches?
1-4. Use PSpice to simulate the circuit of Example 1-1. Use the PSpice default BJT
QbreakN for switch S1. Use an idealized base drive circuit similar to that of the
gate drive circuit for the MOSFET in Fig. 1-9. Choose an appropriate base
resistance to ensure that the transistor turns on for a transistor hFE of 100. Use the
PSpice default diode Dbreak for switch S2. Display the voltage across the current
source. How do the results differ from those using ideal switches?
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 21
C H A P T E R 2
Power Computations
2.1 INTRODUCTION
Power computations are essential in analyzing and designing power electronics
circuits. Basic power concepts are reviewed in this chapter, with particular em-
phasis on power calculations for circuits with nonsinusoidal voltages and currents.
Extra treatment is given to some special cases that are encountered frequently in
power electronics. Power computations using the circuit simulation program
PSpice are demonstrated.
2.2 POWER AND ENERGY

Instantaneous Power
The instantaneous power for any device is computed from the voltage across it
and the current in it. Instantaneous power is
p(t) v(t)i(t) (2-1)
This relationship is valid for any device or circuit. Instantaneous power is
generally a time-varying quantity. If the passive sign convention illustrated in
Fig. 2-1a is observed, the device is absorbing power if p(t) is positive at a
specified value of time t. The device is supplying power if p(t) is negative.
Sources frequently have an assumed current direction consistent with supply-
ing power. With the convention of Fig. 2-1b, a positive p(t) indicates the
source is supplying power.
21
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22 C H A P T E R 2 Power Computations
i(t) i(t)
+ +
v(t) v(t)
− −
(a) (b)
Figure 2-1 (a) Passive

sign convention: p(t) 0
indicates power is being
absorbed; (b) p(t) 0
indicates power is being
supplied by the source.
Energy
Energy, or work, is the integral of instantaneous power. Observing the passive
sign convention, energy absorbed by a component in the time interval from
t1 to t2 is
t2
W p(t) dt (2-2)
3
t1
If v(t) is in volts and i(t) is in amperes, power has units of watts and energy has
units of joules.
Average Power
Periodic voltage and current functions produce a periodic instantaneous power
function. Average power is the time average of p(t) over one or more periods.
Average power P is computed from
t0 T t0 T
1 1
P p(t) dt v(t)i(t) dt (2-3)
T3 T3
t0 t0
where T is the period of the power waveform. Combining Eqs. (2-3) and (2-2),
power is also computed from energy per period.
W
P (2-4)
T
Average power is sometimes called real power or active power, especially in ac
circuits. The term power usually means average power. The total average power
absorbed in a circuit equals the total average power supplied.
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2.2 Power and Energy 23
EXAMPLE 2-1
Power and Energy

Voltage and current, consistent with the passive sign convention, for a device are shown
in Fig. 2-2a and b. (a) Determine the instantaneous power p(t) absorbed by the device.
(b) Determine the energy absorbed by the device in one period. (c) Determine the aver-
age power absorbed by the device.
■ Solution
(a) The instantaneous power is computed from Eq. (2-1). The voltage and current are
expressed as
20 V 0 t 10 ms
v(t) b
0 10 ms t 20 ms
20 V 0 t 6 ms
i(t) b
15 A 6 ms t 20 ms
Instantaneous power, shown in Fig. 2-2c, is the product of voltage and current and
is expressed as
400 W 0 t 6 ms
p(t) c 300 W 6 ms t 10 ms
0 10 ms t 20 ms
v(t)
20 V
0 t
10 ms 20 ms
(a)
i(t)
20 A
0 t
6 ms 20 ms
−15 A
(b)
p(t)
400 W
0 t
6 ms 10 ms 20 ms
−300 W
(c)
Figure 2-2 Voltage, current, and instantaneous power for Example 2-1.
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(b) Energy absorbed by the device in one period is determined from Eq. (2-2).
T 0.006 0.010 0.020
W p(t) dt 400 dt 300 dt 0 dt 2.4 1.2 1.2 J

3 3 3 3
0 0 0.006 0.010
(c) Average power is determined from Eq. (2-3).
T 0.006 0.010 0.020
0.020 P 3 Q
1 1
P p(t) dt 400 dt 300 dt 0 dt
T3 3 3
0 0 0.006 0.010
2.4 1.2 0
60 W
0.020
Average power could also be computed from Eq. (2-4) by using the energy per period
from part (b).
W 1.2 J
P 60 W
T 0.020 s
A special case that is frequently encountered in power electronics is the power

absorbed or supplied by a dc source. Applications include battery-charging cir-
cuits and dc power supplies. The average power absorbed by a dc voltage source
v(t) Vdc that has a periodic current i(t) is derived from the basic definition of
average power in Eq. (2-3):
t0 T t0 T
1 1
Pdc v(t)i(t) dt V i(t) dt
T 3 T 3 dc
t0 t0
Bringing the constant Vdc outside of the integral gives

t0 T
1
Pdc Vdc C i(t) dt S
T3
t0
The term in brackets is the average of the current waveform. Therefore, average
power absorbed by a dc voltage source is the product of the voltage and the
average current.
Pdc Vdc Iavg (2-5)
Similarly, average power absorbed by a dc source i(t) Idc is

Pdc Idc Vavg (2-6)
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2.3 Inductors and Capacitors 25
2.3 INDUCTORS AND CAPACITORS

Inductors and capacitors have some particular characteristics that are important
in power electronics applications. For periodic currents and voltages,
i(t T) i(t)
(2-7)
v(t T) v(t)
For an inductor, the stored energy is
1 2
w(t) Li (t) (2-8)
2
If the inductor current is periodic, the stored energy at the end of one period is the
same as at the beginning. No net energy transfer indicates that the average power
absorbed by an inductor is zero for steady-state periodic operation.
PL 0 (2-9)
Instantaneous power is not necessarily zero because power may be absorbed
during part of the period and returned to the circuit during another part of the
period.
Furthermore, from the voltage-current relationship for the inductor
t0 T
1
i(t 0 T) v (t) dt i(t 0) (2-10)
L3 L
t0
Rearranging and recognizing that the starting and ending values are the same for
periodic currents, we have
t0 T
1
i(t 0 T) i(t 0) v (t) dt 0 (2-11)
L3 L
t0
Multiplying by L/T yields an expression equivalent to the average voltage across

the inductor over one period.
t0 T
1
avg[vL(t)] VL v (t) dt 0 (2-12)
T3 L
t0
Therefore, for periodic currents, the average voltage across an inductor is zero.
This is very important and will be used in the analysis of many circuits, includ-
ing dc-dc converters and dc power supplies.
For a capacitor, stored energy is
1 2
w(t) Cv (t) (2-13)
2
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If the capacitor voltage is periodic, the stored energy is the same at the end of a
period as at the beginning. Therefore, the average power absorbed by the capac-
itor is zero for steady-state periodic operation.
PC 0 (2-14)
From the voltage-current relationship for the capacitor,

t0 T
1
v(t 0 T) i (t) dt v(t 0) (2-15)
C3 C
t0
Rearranging the preceding equation and recognizing that the starting and ending
values are the same for periodic voltages, we get
t0 T
1
v(t 0 T) v(t 0) i (t) dt 0 (2-16)
C3 C
t0
Multiplying by C/T yields an expression for average current in the capacitor over
one period.
t0 T
1
avg [i C(t)] IC i (t) dt 0 (2-17)
T3 C
t0
Therefore, for periodic voltages, the average current in a capacitor is zero.
EXAMPLE 2-2
Power and Voltage for an Inductor

The current in a 5-mH inductor of Fig. 2-3a is the periodic triangular wave shown
in Fig. 2-3b. Determine the voltage, instantaneous power, and average power for the
inductor.
■ Solution
The voltage across the inductor is computed from v(t) L(di/dt) and is shown in
Fig. 2-3c. The average inductor voltage is zero, as can be determined from Fig. 2-3c
by inspection. The instantaneous power in the inductor is determined from p(t) v(t)i(t)
and is shown in Fig. 2-3d. When p(t) is positive, the inductor is absorbing power, and
when p(t) is negative, the inductor is supplying power. The average inductor power
is zero.
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2.4 Energy Recovery 27
i(t)
4A
0 t
1 ms 2 ms 3 ms 4 ms
(b)
v(t)
20 V
−20 V
(c)
p(t)
80 W
+
i(t) t
5 mH v(t)
−
−80 W
(a) (d)
Figure 2.3 (a) Circuit for Example 2-2; (b) inductor current; (c) inductor
voltage; (d) inductor instantaneous power.
2.4 ENERGY RECOVERY

Inductors and capacitors must be energized and deenergized in several applica-
tions of power electronics. For example, a fuel injector solenoid in an automobile
is energized for a set time interval by a transistor switch. Energy is stored in the
solenoid’s inductance when current is established. The circuit must be designed
to remove the stored energy in the inductor while preventing damage to the tran-
sistor when it is turned off. Circuit efficiency can be improved if stored energy
can be transferred to the load or to the source rather than dissipated in circuit
resistance. The concept of recovering stored energy is illustrated by the circuits
described in this section.
Fig. 2-4a shows an inductor that is energized by turning on a transistor
switch. The resistance associated with the inductance is assumed to be negligi-
ble, and the transistor switch and diode are assumed to be ideal. The diode-
resistor path provides a means of opening the switch and removing the stored
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+VCC VCC VCC
is iS = iL iS = 0
R +
iL L
vL = VCC iL iL
-
0 t1 T
(a) (b) (c)
iL(t)
t
0 t1 T
iS (t)
t
0 t1 T
(d)
Figure 2-4 (a) A circuit to energize an inductance and then transfer the stored energy
to a resistor; (b) Equivalent circuit when the transistor is on; (c) Equivalent circuit
when the transistor is off and the diode is on; (d) Inductor and source currents.
energy in the inductor when the transistor turns off. Without the diode-resistor
path, the transistor could be destroyed when it is turned off because a rapid
decrease in inductor current would result in excessively high inductor and tran-
sistor voltages.
Assume that the transistor switch turns on at t 0 and turns off at t t1.
The circuit is analyzed first for the transistor switch on and then for the
switch off.
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Transistor on: 0 ⬍ t ⬍ t1
The voltage across the inductor is VCC, and the diode is reverse-biased when the
transistor is on (Fig. 2-4b).
vL ⫽ VCC (2-18)
An expression for inductor current is obtained from the voltage-current relationship:

t t
1 1 V t
i L(t) ⫽ v (l) dl ⫹ i L(0) ⫽ V dl ⫹ 0 ⫽ CC (2-19)
L3 L L 3 CC L
0 0
Source current is the same as inductor current.

is(t) ⫽ iL(t) (2-20)
Inductor and source currents thus increase linearly when the transistor is on.
The circuit is next analyzed for the transistor switch off.
Transistor off: t1 ⬍ t ⬍ T
In the interval t1 ⬍ t ⬍ T, the transistor switch is off and the diode is on (Fig. 2-4c).
The current in the source is zero, and the current in the inductor and resistor is a
decaying exponential with time constant L/R. The initial condition for inductor
current is determined from Eq. (2-19):
VCC t1
iL(t1) ⫽ (2-21)
L
Inductor current is then expressed as
VCC t 1 ⫺(t⫺t1)/␶
i L(t) ⫽ i L(t 1)e ⫺(t⫺t1)/␶ ⫽ a be t1 ⬍ t ⬍ T (2-22)
L
where ␶ ⫽ L/R. Source current is zero when the transistor is off.
iS ⫽ 0 (2-23)
Average power supplied by the dc source during the switching period is

determined from the product of voltage and average current [Eq. (2-5)].
T
1
PS ⫽ VS IS ⫽ VCC C i (t) dt S
T3 s
0
(2-24)
t1 T
1 VCC t 1 (V t )2
⫽ VCC C dt ⫹ 0 dt S ⫽ CC 1
T3 L T3 2LT
0 t1
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Average power absorbed by the resistor could be determined by integrating

an expression for instantaneous resistor power, but an examination of the circuit
reveals an easier way. The average power absorbed by the inductor is zero, and
power absorbed by the ideal transistor and diode is zero. Therefore, all power
supplied by the source must be absorbed by the resistor:
(VCC t 1)2
PR PS (2-25)
2LT
Another way to approach the problem is to determine the peak energy stored in
the inductor,
1 2 1 V t 2 (V t )2
W Li (t 1) La CC 1 b CC 1 (2-26)
2 2 L 2L
The energy stored in the inductor is transferred to the resistor while the tran-
sistor switch is open. Power absorbed by the resistor can be determined from
Eq. (2-4).
W (VCC t 1)2
PR (2-27)
T 2LT
which must also be the power supplied by the source. The function of the resis-
tor in this circuit of Fig. 2-4a is to absorb the stored energy in the inductance and
protect the transistor. This energy is converted to heat and represents a power
loss in the circuit.
Another way to remove the stored energy in the inductor is shown in Fig. 2-5a.
Two transistor switches are turned on and off simultaneously. The diodes provide
a means of returning energy stored in the inductor back to the source. Assume
that the transistors turn on at t 0 and turn off at t t1. The analysis of the cir-
cuit of Fig. 2-5a begins with the transistors on.
Transistors on: 0 ⬍ t ⬍ t1
When the transistors are on, the diodes are reverse-biased, and the voltage across
the inductor is VCC. The inductor voltage is the same as the source when the tran-
sistors are on (Fig. 2-5b):
vL VCC (2-28)
Inductor current is the function

t t
1 1 V t
i L(t) v (l) dl i L(0) V dl 0 CC (2-29)
L3 L L 3 CC L
0 0
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+ VCC VCC VCC
iS iS = iL iS = −iL
+
+
L iL vL = VCC iL vL = −VCC iL
−
0 t1 T
(a) (b) (c)
iL(t)
0 t1 2t1 T t
iS(t)
0
t1 2t1 T t
(d )
Figure 2-5 (a) A circuit to energize an inductance and recover the stored
energy by transferring it back to the source; (b) Equivalent circuit when the
transistors are on; (c) Equivalent circuit when the transistors are off and the
diodes are on; (d) Inductor and source currents.
Source current is the same as inductor current.

iS (t) iL (t) (2-30)
From the preceding equations, inductor and source currents increase linearly
while the transistor switches are on, as was the case for the circuit of
Fig. 2-4a.
The circuit is next analyzed for the transistors off.
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Transistors off: t1 ⬍ t ⬍ T
When the transistors are turned off, the diodes become forward-biased to provide
a path for the inductor current (Fig. 2-5c). The voltage across the inductor then
becomes the opposite of the source voltage:
vL VCC (2-31)
An expression for inductor current is obtained from the voltage-current
relationship.
t t
1 1 V t
i L(t) vL(l) dl i L(t 1) (VCC) dl CC 1
L3 L3 L
t1 t1
VCC
a b [(t 1 t) t 1]
L
or,
VCC
i L(t) a b (2t 1 t) t 1 t 2t 1 (2-32)
L
Inductor current decreases and becomes zero at t 2t1, at which time the diodes
turn off. Inductor current remains at zero until the transistors turn on again.
Source current is the opposite of inductor current when the transistors are off
and the diodes are on:
iS (t) iL (t) (2-33)
The source is absorbing power when the source current is negative. Average
source current is zero, resulting in an average source power of zero.
The source supplies power while the transistors are on, and the source absorbs
power while the transistors are off and the diodes are on. Therefore, the energy
stored in the inductor is recovered by transferring it back to the source. Practical
solenoids or other magnetic devices have equivalent resistances that represent
losses or energy absorbed to do work, so not all energy will be returned to the
source. The circuit of Fig. 2-5a has no energy losses inherent to the design and is
therefore more efficient than that of Fig. 2-4a.
EXAMPLE 2-3
Energy Recovery
The circuit of Fig. 2-4a has VCC 90 V, L 200 mH, R 20 , t1 10 ms, and
T 100 ms. Determine (a) the peak current and peak energy storage in the inductor,
(b) the average power absorbed by the resistor, and (c) the peak and average power sup-
plied by the source. (d) Compare the results with what would happen if the inductor were
energized using the circuit of Fig. 2-5a.
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■ Solution
(a) From Eq. (2-19), when the transistor switch is on, inductor current is
90
i L(t) a
VCC
bt a b t 450 t A 0 t 10 ms
L 0.2
Peak inductor current and stored energy are
i L(t 1) 450(0.01) 4.5 A
1 1
WL Li 2(t 1) (0.2)(4.5)2 2.025 J
2 2
(b) The time constant for the current when the switch is open is L/R 200 mH/20
10 ms. The switch is open for 90 ms, which is 10 time constants, so essentially all
stored energy in the inductor is transferred to the resistor:
WR WL 2.025 J
Average power absorbed by the resistor is determined from Eq. (2-4):
WR 2.025 J
PR 20.25 W
T 0.1 s
(c) The source current is the same as the inductor current when the switch is closed and
is zero when the switch is open. Instantaneous power supplied by the source is
(90 V)(450t A) 40,500t W 0 t 10 ms

pS(t) vS(t)i S(t) b
0 10 ms t 100 ms
which has a maximum value of 405 W at t 10 ms. Average power supplied by the
source can be determined from Eq. (2-3):
T 0.01 0.1
1 1
PS pS(t) dt £ 40,500t dt 0 dt≥ 20.25 W
T3 0.1 3 3
0 0 0.01
Average source power also can be determined from Eq. (2-5). Average of the
triangular source current waveform over one period is
1 (0.01 s)(4.5 A)
IS B R 0.225 A
2 0.1 s
and average source power is then
PS VCCIS (90 V)(0.225 A) 20.25 W

Still another computation of average source power comes from recognizing that the
power absorbed by the resistor is the same as that supplied by the source.
PS PR 20.25 W
(See Example 2-13 at the end of this chapter for the PSpice simulation of this circuit.)
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(d) When the inductor is energized from the circuit of Fig. 2-5a, the inductor current is
described by Eqs. (2-29) and (2-32).
450t A 0 ⬍ t ⬍ 10 ms
i L(t) ⫽ c 9⫺450t A 10 ms ⬍ t ⬍ 20 ms
0 20 ms ⬍ t ⬍ 100 ms
The peak current and peak energy storage are the same as for the circuit of Fig. 2-4a.
The source current has the form shown in Fig. 2-5d and is expressed as
450 t A 0 ⬍ t ⬍ 10 ms
i S (t) ⫽ c 450t ⫺ 9 A 10 ms ⬍ t ⬍ 20 ms
0 20 ms ⬍ t ⬍ 100 ms
Instantaneous power supplied by the source is
40,500t W 0 ⬍ t ⬍ 10 ms
pS (t) ⫽ 90i S (t) ⫽ c 40,500t ⫺ 810 W 10 ms ⬍ t ⬍ 20 ms
0 20 ms ⬍ t ⬍ 100 ms
Average source current is zero, and average source power is zero. Peak source
power is peak current times voltage, which is 405 W as in part (c).
2.5 EFFECTIVE VALUES: RMS

The effective value of a voltage or current is also known as the root-mean-square
(rms) value. The effective value of a periodic voltage waveform is based on the
average power delivered to a resistor. For a dc voltage across a resistor,
2
Vdc
P⫽ (2-34)
R
For a periodic voltage across a resistor, effective voltage is defined as the voltage
that is as effective as the dc voltage in supplying average power. Effective volt-
age can be computed using the equation
V2eff
P⫽ (2-35)
R
Computing average resistor power from Eq. (2-3) gives
T T T
1 1 1 v 2(t)
P⫽ p(t) dt ⫽ v(t)i(t) dt ⫽ dt
T3 T3 T3 R
0 0 0 (2-36)
T
1 1
⫽ C v 2(t) dt S
R T3
0
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2.5 Effective Values: RMS 35
Equating the expressions for average power in Eqs. (2-35) and (2-36) gives
T
V 2eff 1 1
P C v 2(t) dt S
R R T3
0
or
T
1
V 2eff v 2(t) dt
T3
0
resulting in the expression for effective or rms voltage
T
1
Veff Vrms v 2(t) dt (2-37)
CT 3
0
The effective value is the square root of the mean of the square of the voltage—
hence the term root mean square.
2
Similarly, rms current is developed from P Irms as
T
1
Irms i 2(t) dt (2-38)
CT 3
0
The usefulness of the rms value of voltages and currents lies in the computing
power absorbed by resistances. Additionally, ac power system voltages and cur-
rents are invariably given in rms values. Ratings of devices such as transformers
are often specified in terms of rms voltage and current.
EXAMPLE 2-4
RMS Value of a Pulse Waveform

Determine the rms value of the periodic pulse waveform that has a duty ratio of D as
shown in Fig. 2-6.
Vm
DT T t
Figure 2-6 Pulse waveform for Example 2-4.

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■ Solution
The voltage is expressed as
Vm 0 t DT
v(t) e
0 DT t T
Using Eq. (2-37) to determine the rms value of the waveform gives
T DT T
1 1 1 2
Vrms v 2 (t) dt a V 2m dt 0 2 dtb (V m DT )
CT 3 CT 3 3 AT
0 0 DT
yielding
Vrms Vm 2D
EXAMPLE 2-5
RMS Values of Sinusoids

Determine the rms values of (a) a sinusoidal voltage of v(t) Vm sin( t), (b) a full-wave
rectified sine wave of v(t) |Vm sin( t)|, and (c) a half-wave rectified sine wave of
v(t) Vm sin( t) for 0 t T/2 and zero otherwise.
■ Solution
(a) The rms value of the sinusoidal voltage is computed from Eq. (2-37):
T
1 2
Vrms V 2m sin2( t) dt where T

FT 3
0
An equivalent expression uses t as the variable of integration. Without showing the

details of the integration, the result is
1 Vm
Vrms V 2m sin2( t) d( t)
F 2
3 12
0
Note that the rms value is independent of the frequency.

(b) Equation (2-37) can be applied to the full-wave rectified sinusoid, but the results of
part (a) can also be used to advantage. The rms formula uses the integral of the
square of the function. The square of the sine wave is identical to the square of the
full-wave rectified sine wave, so the rms values of the two waveforms are identical:
Vm
Vrms
12
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(c) Equation (2-37) can be applied to the half-wave rectified sinusoid.
1 1
Vrms £ V 2m sin2( t) d( t) 0 2 d( t)≥ V 2m sin2( t) d( t)
F 2
3 3 F 2
3
0
0
The result of part (a) will again be used to evaluate this expression. The square
of the function has one-half the area of that of the functions in (a) and (b).
That is,
1 1 1
Vrms V 2m sin2( t) d( t) a b V 2m sin2( t) d( t)
F 2
3 F 2 2
3
0 0
Taking the 1/2 outside of the square root gives
1 1
Vrms a b V 2m sin2( t) d( t)
A 2 F 2
3
0
The last term on the right is the rms value of a sine wave which is known to be
Vm / 12, so the rms value of a half-wave rectified sine wave is
1 Vm V
Vrms m
A 2 12 2
Figure 2-7 shows the waveforms.
i2 (t)
i(t)
(a)
Figure 2-7 Waveforms and their squares for

Example 2-5 (a) Sine wave; (b) full-wave
rectified sine wave; (c) half-wave rectified
sine wave.
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i2 (t)
i(t)
(b)
i2 (t)
i(t)
(c)
EXAMPLE 2-6
Neutral Conductor Current in a Three-Phase System

An office complex is supplied from a three-phase four-wire voltage source (Fig. 2-8a).
The load is highly nonlinear as a result of the rectifiers in the power supplies of the equip-
ment, and the current in each of the three phases is shown in Fig. 2-8b. The neutral cur-
rent is the sum of the phase currents. If the rms current in each phase conductor is known
to be 20 A, determine the rms current in the neutral conductor.
■ Solution
Equation (2-38) may be applied to this case. Noting by inspection that the area of the
square of the current function in the neutral in, is 3 times that of each of the phases ia
(Fig. 2-8c)
T T
1 1
In, rms i 2n(t) d(t) 3¢ i 2a(t) d(t) ≤ 23 Ia, rms
FT 3 F T3
0 0
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ia
ib
ic
+ + +
van vbn vcn
- - -
in
(a)
van, ia
vbn, ib
vcn, ic
in
(b)
i2a
i2n
(c)
Figure 2-8 (a) Three-phase source supplying a balanced

nonlinear three-phase load for Example 2-8; (b) phase and
neutral currents; (c) squares of ia and in.
The rms current in the neutral is therefore

In, rms 23 (20) 34.6 A
Note that the rms neutral current is larger than the phase currents for this situation.
This is much different from that for balanced linear loads where the line currents are
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 40
sinusoids which are displaced by 120 and sum to zero. Three-phase distribution systems
supplying highly nonlinear loads should have a neutral conductor capable of carrying 13
times as much current as the line conductor.
If a periodic voltage is the sum of two periodic voltage waveforms,

v(t) v1(t) v2(t), the rms value of v(t) is determined from Eq. (2-37) as
T T
A v v2 B 2 dt A v 21 2v1v2 v 22 B dt
1 1
V 2rms
T3 1 T3
0 0
or
T T T
1 1 1
V 2rms v 21 dt 2v1v2 dt v 22 dt
T3 T3 T3
0 0 0
The term containing the product v1v2 in the above equation is zero if
the functions v1 and v2 are orthogonal. A condition that satisfies that requirement
occurs when v1 and v2 are sinusoids of different frequencies. For orthogonal
functions,
T T
1 1
V 2rms v 21(t) dt v 2(t) dt
T3 T3 2
0 0
Noting that
T T
1 1
v 2(t) dt V 21, rms and v 22(t) dt V 22, rms
T3 1 T3
0 0
then
Vrms 2V 21, rms V 22, rms

If a voltage is the sum of more than two periodic voltages, all orthogonal, the rms
value is
N
Vrms 2V 21, rms V 22, rms V 23, rms Á a V 2n, rms (2-39)
B n1
Similarly,
N
Irms 2I 21, rms I 22, rms I 23, rms Á a I 2n, rms (2-40)
B n1
Note that Eq. (2-40) can be applied to Example 2-6 to obtain the rms value of the
neutral current.
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 41
EXAMPLE 2-7
RMS Value of the Sum of Waveforms

Determine the effective (rms) value of v(t) 4 8 sin( 1t 10) 5 sin ( 2t 50) for
(a) 2 2 1 and (b) 2 1.
■ Solution
(a) The rms value of a single sinusoid is Vm / 12, and the rms value of a constant is the
constant. When the sinusoids are of different frequencies, the terms are orthogonal
and Eq. (2-39) applies.
8 2 5 2
Vrms 2V 21, rms V 22, rms V 23, rms 42 a b a b 7.78 V
C 12 12
(b) For sinusoids of the same frequency, Eq. (2-39) does not apply because the integral
of the cross product over one period is not zero. First combine the sinusoids using
phasor addition:
8⬔10 5⬔50 12.3⬔25.2
The voltage function is then expressed as
v(t) 4 12.3 sin ( 1t 25.2) V
The rms value of this voltage is determined from Eq. (2-39) as
12.3 2
Vrms 42 a b 9.57 V
C 12
EXAMPLE 2-8
RMS Value of Triangular Waveforms

(a) A triangular current waveform like that shown in Fig. 2-9a is commonly
encountered in dc power supply circuits. Determine the rms value of this current.
(b) Determine the rms value of the offset triangular waveform in Fig. 2-9b.
■ Solution
(a) The current is expressed as
2Im
t Im 0 t t1
t1
i(t) μ
2Im I (T t 1)
t m t1 t T
T t1 T t1
The rms value is determined from Eq. (2-38).
t1 T
2
1 2I 2Im I (T t 1) 2
I 2rms C ¢ m t Im ≤ dt ¢ t m ≤ dt S
T 3 t1 3 T t1 T t1
0 t1
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 42
Im
t
t1 T 2T
-Im
(a)
5
Im
3 Idc
0 t
1 ms 3 ms
(b)
Figure 2-9 (a) Triangular waveform for Example

2-8; (b) offset triangular waveform.
The details of the integration are quite long, but the result is simple: The rms value
of a triangular current waveform is
I
Irms m
13
(b) The rms value of the offset triangular waveform can be determined by using
the result of part (a). Since the triangular waveform of part (a) contains no dc
component, the dc signal and the triangular waveform are orthogonal, and Eq.
(2-40) applies.
Im 2 2 2
Irms 2I 21, rms I 22, rms a
b I 2dc a b 32 3.22 A
C 13 C 13
2.6 APPARENT POWER AND POWER FACTOR

Apparent Power S
Apparent power is the product of rms voltage and rms current magnitudes and
is often used in specifying the rating of power equipment such as transformers.
Apparent power is expressed as
S Vrms Irms (2-41)
har80679_ch02_021-064.qxd 12/17/09 1:56 PM Page 43
2.7 Power Computations for Sinusoidal AC Circuits 43
In ac circuits (linear circuits with sinusoidal sources), apparent power is the mag-
nitude of complex power.
Power Factor
The power factor of a load is defined as the ratio of average power to apparent
power:
P P
pf ⫽ ⫽ (2-42)
S Vrms Irms
In sinusoidal ac circuits, the above calculation results in pf ⫽ cos␪ where ␪ is the
phase angle between the voltage and current sinusoids. However, that is a special
case and should be used only when both voltage and current are sinusoids. In
general, power factor must be computed from Eq. (2-42).
2.7 POWER COMPUTATIONS FOR SINUSOIDAL

AC CIRCUITS
In general, voltages and/or currents in power electronics circuits are not sinu-
soidal. However, a nonsinusoidal periodic waveform can be represented by a
Fourier series of sinusoids. It is therefore important to understand thoroughly
power computations for the sinusoidal case. The following discussion is a review
of power computations for ac circuits.
For linear circuits that have sinusoidal sources, all steady-state voltages and
currents are sinusoids. Instantaneous power and average power for ac circuits are
computed using Eqs. (2-1) and (2-3) as follows:
For any element in an ac circuit, let

v(t) ⫽ Vm cos (␻t ⫹ ␪ )
(2-43)
i(t) ⫽ Im cos (␻t ⫹ ␾)
Then instantaneous power is
p(t) ⫽ v(t)i(t) ⫽ [Vm cos (␻t ⫹ ␪ )][Im cos (␻t ⫹ ␾)] (2-44)
Using the trigonometric identity gives
1
(cos A)(cos B) ⫽ [cos (A ⫹ B) ⫹ cos (A ⫺ B)] (2-45)
2
VmIm
p(t) ⫽ a b[cos (2␻t ⫹ ␪ ⫹ ␾) ⫹ cos (␪ ⫺ ␾)] (2-46)
2
Average power is
T T
1 VI
P⫽ p(t) dt ⫽ ¢ m m ≤ [cos (2␻t ⫹ ␪ ⫹ ␾) ⫹ cos(␪ ⫺ ␾)]dt (2-47)
T3 2 3
0 0
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 44
The result of the above integration can be obtained by inspection. Since the first
term in the integration is a cosine function, the integral over one period is zero
because of equal areas above and below the time axis. The second term in the
integration is the constant cos( ), which has an average value of cos( ).
Therefore, the average power in any element in an ac circuit is
VmIm
P ¢ ≤ cos ( ) (2-48)
2
This equation is frequently expressed as
P VrmsIrms cos ( ) (2-49)
where Vrms Vm / 12 , Irms Im / 12, and – is the phase angle between voltage
and current. The power factor is determined to be cos ( – ) by using Eq. (2-42).
In the steady state, no net power is absorbed by an inductor or a capacitor.
The term reactive power is commonly used in conjunction with voltages and cur-
rents for inductors and capacitors. Reactive power is characterized by energy
storage during one-half of the cycle and energy retrieval during the other half.
Reactive power is computed with a relationship similar to Eq. (2-49):
Q VrmsIrms sin ( ) (2-50)
By convention, inductors absorb positive reactive power and capacitors absorb
negative reactive power.
Complex power combines real and reactive powers for ac circuits:
S P jQ (Vrms)(I rms)* (2-51)
In the above equation, Vrms and Irms are complex quantities often expressed as
phasors (magnitude and angle), and (Irms)* is the complex conjugate of phasor
current, which gives results consistent with the convention that inductance, or
lagging current, absorbs reactive power. Apparent power in ac circuits is the
magnitude of complex power:
S ƒ S ƒ 2P 2 Q 2 (2-52)
It is important to note that the complex power in Eq. (2-52) and power factor
of cos ( – ) for sinusoidal ac circuits are special cases and are not applicable to
nonsinusoidal voltages and currents.
2.8 POWER COMPUTATIONS FOR NONSINUSOIDAL

PERIODIC WAVEFORMS
Power electronics circuits typically have voltages and/or currents that are peri-
odic but not sinusoidal. For the general case, the basic definitions for the power
terms described at the beginning of this chapter must be applied. A common error
that is made when doing power computations is to attempt to apply some special
relationships for sinusoids to waveforms that are not sinusoids.
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 45
2.8 Power Computations for Nonsinusoidal Periodic Waveforms 45
The Fourier series can be used to describe nonsinusoidal periodic waveforms

in terms of a series of sinusoids. The power relationships for these circuits can be
expressed in terms of the components of the Fourier series.
Fourier Series
A nonsinusoidal periodic waveform that meets certain conditions can be described
by a Fourier series of sinusoids. The Fourier series for a periodic function f(t) can
be expressed in trigonometric form as
q
f(t) a0 a [an cos (n 0t) bn sin (n 0t)] (2-53)

n1
where
T>2
1
a0 f(t) dt
T 3
T>2
T>2
2
an f(t) cos (n 0t) dt (2-54)
T 3
T>2
T>2
2
bn f(t) sin (n 0t) dt
T 3
T>2
Sines and cosines of the same frequency can be combined into one sinusoid,
resulting in an alternative expression for a Fourier series:
q
f(t) a0 a Cn cos (n 0t n)
n1
where (2-55)
bn
Cn 2a 2n b 2n and n tan1 a b
an
or
q
f(t) a0 a Cn sin (n 0t n)
n1
where (2-56)
an
Cn 2a 2n b 2n and n tan1 a b
bn
The term a0 is a constant that is the average value of f(t) and represents a dc volt-
age or current in electrical applications. The coefficient C1 is the amplitude of the
term at the fundamental frequency 0. Coefficients C2, C3, . . . are the amplitudes
of the harmonics that have frequencies 2 0, 3 0, . . . .
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 46
The rms value of f(t) can be computed from the Fourier series:
C 2
a 20 a a n b
q q
2
Frms a F n, rms (2-57)
A n0 C n1 12
Average Power
If periodic voltage and current waveforms represented by the Fourier series
q
v(t) V0 a Vn cos (n 0t n)
n1
q
(2-58)
i(t) I0 a In cos (n 0t n)
n1
exist for a device or circuit, then average power is computed from Eq. (2-3).
T
1
P v(t)i(t) dt
T3
0
The average of the products of the dc terms is V0 I0. The average of voltage and
current products at the same frequency is described by Eq. (2-49), and the average
of voltage and current products of different frequencies is zero. Consequently,
average power for nonsinusoidal periodic voltage and current waveforms is
q q
P a Pn V0 I0 a Vn, rms In, rms cos ( n n)

n0 n1
or (2-59)
Vn, max In, max

P V0I0 a a b cos ( n n)
q
n1 2
Note that total average power is the sum of the powers at the frequencies in the
Fourier series.
Nonsinusoidal Source and Linear Load

If a nonsinusoidal periodic voltage is applied to a load that is a combination of
linear elements, the power absorbed by the load can be determined by using
superposition. A nonsinusoidal periodic voltage is equivalent to the series
combination of the Fourier series voltages, as illustrated in Fig. 2-10. The current
in the load can be determined using superposition, and Eq. (2-59) can be ap-
plied to compute average power. Recall that superposition for power is not valid
when the sources are of the same frequency. The technique is demonstrated in
Example 2-9.
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 47
+
Vm cos(nω0t + θn)
−
i(t)
+
V1 cos(ω0t + θ1) Load
− 5Ω
+
v(t)
−
+
15 mH
Vdc
−
Figure 2.10 Equivalent circuit for Figure 2.11 Circuit for

Fourier analysis. Example 2-9.
EXAMPLE 2-9
Nonsinusoidal Source and Linear Load

A nonsinusoidal periodic voltage has a Fourier series of v(t) 10 20 cos(2
60t 25)
30 cos(4
60t 20) V. This voltage is connected to a load that is a 5- resistor and a
15-mH inductor connected in series as in Fig. 2-11. Determine the power absorbed by the
load.
■ Solution
Current at each source frequency is computed separately. The dc current term is
V0 10
I0 2A
R 5
The amplitudes of the ac current terms are computed from phasor analysis:
V1 20 ∠(25°)
I1 2.65∠(73.5°) A
R j 1L 5 j(2
60)(0.015)
V2 30∠ 20°
I2 2.43 ∠ (46.2°) A
R j 2L 5 j(4
60)(0.015)
Load current can then be expressed as
i(t) 2 2.65 cos (2
60t 73.5°) 2.43 cos (4
60t 46.2°) A
Power at each frequency in the Fourier series is determined from Eq. (2-59):
dc term: P0 (10 V)(2 A) 20 W
(20)(2.65)
2
60: P1 cos(25° 73.5°) 17.4 W
2
(30)(2.43)
4
60: P2 cos (20° 46°) 14.8 W
2
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 48
Total power is then

P 20 17.4 14.8 52.2 W
2
Power absorbed by the load can also be computed from Irms R in this circuit because the
average power in the inductor is zero.
2.65 2 2.43 2
P I 2rms R B22 a b a b R 5 52.2 W
12 12
Sinusoidal Source and Nonlinear Load

If a sinusoidal voltage source is applied to a nonlinear load, the current waveform
will not be sinusoidal but can be represented as a Fourier series. If voltage is the
sinusoid
v(t) V1 sin ( 0t 1) (2-60)
and current is represented by the Fourier series
q
i(t) I0 a In sin (n 0t n) (2-61)

n1
then average power absorbed by the load (or supplied by the source) is computed
from Eq. (2-59) as
Vn, max In, max
P V0I0 a a b cos ( n n)
q
n1 2
V1I1 (0)(In, max)
(0)(I0) a b cos ( 1 1) a
q
cos ( n n) (2-62)
2 n2 2
V1I1
a b cos ( 1 1) V1, rmsI1, rms cos ( 1 1)
2
Note that the only nonzero power term is at the frequency of the applied voltage.
The power factor of the load is computed from Eq. (2-42).
P P
pf
S VrmsIrms
(2-63)
V1, rmsI1, rms cos ( 1 1) I1, rms
pf ¢ ≤ cos ( 1 1)
V1, rms Irms Irms
where rms current is computed from
q q
I 2
Irms 2
a I n, rms I 20 a ¢ n ≤ (2-64)
C n0 C n1 12
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 49
Note also that for a sinusoidal voltage and a sinusoidal current,

pf cos(1 1), which is the power factor term commonly used in linear cir-
cuits and is called the displacement power factor. The ratio of the rms value of
the fundamental frequency to the total rms value, I1, rms/Irms in Eq. (2-63), is the
distortion factor (DF).
I1, rms
DF (2-65)
Irms
The distortion factor represents the reduction in power factor due to the nonsinu-
soidal property of the current. Power factor is also expressed as
pf [cos ( 1 1)] DF (2-66)
Total harmonic distortion (THD) is another term used to quantify the non-
sinusoidal property of a waveform. THD is the ratio of the rms value of all the
nonfundamental frequency terms to the rms value of the fundamental frequency
term.
2 2
a I n, rms a I n, rms
nZ1 A nZ1
THD (2-67)
Q I 21, rms I1, rms
THD is equivalently expressed as
I 2rms I 21, rms
THD (2-68)
B I 21, rms
Total harmonic distortion is often applied in situations where the dc term is zero,
in which case THD may be expressed as
q
I 2n
Aa
THD n2 (2-69)
I1
Another way to express the distortion factor is
1
DF (2-70)
A 1 (THD)2
Reactive power for a sinusoidal voltage and a nonsinusoidal current can be
expressed as in Eq. (2-50). The only nonzero term for reactive power is at the
voltage frequency:
V1I1
Q sin( 1 1) (2-71)
2
With P and Q defined for the nonsinusoidal case, apparent power S must include
a term to account for the current at frequencies which are different from the
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 50
voltage frequency. The term distortion volt-amps D is traditionally used in the

computation of S,
S 2P 2 Q 2 D 2 (2-72)
where
q
2 V1 q
D V1, rms a I n, rms In (2-73)
A nZ1 2 A na
Z1
Other terms that are sometimes used for nonsinusoidal current (or voltages) are
form factor and crest factor.
Irms
Form factor (2-74)
Iavg
Ipeak
Crest factor (2-75)
Irms
EXAMPLE 2-10
Sinusoidal Source and a Nonlinear Load

A sinusoidal voltage source of v(t) 100 cos(377t) V is applied to a nonlinear load,
resulting in a nonsinusoidal current which is expressed in Fourier series form as
i(t) 8 15 cos (377t 30°) 6 cos [2(377)t 45°] 2 cos [3(377)t 60°]
Determine (a) the power absorbed by the load, (b) the power factor of the load, (c) the
distortion factor of the load current, (d) the total harmonic distortion of the load
current.
■ Solution
(a) The power absorbed by the load is determined by computing the power absorbed at
each frequency in the Fourier series [Eq. (2-59)].
100 15 6 2
P (0)(8) a ba b cos 30° (0) a b cos 45° (0) a b cos 60°
12 12 12 12
100 15
P a ba b cos 30° 650 W
12 12
(b) The rms voltage is

100
Vrms 70.7 V
12
har80679_ch02_021-064.qxd 12/17/09 5:18 PM Page 51
2.9 Power Computations Using PSpice 51
and the rms current is computed from Eq. (2-64):
15 2 6 2 2 2
Irms ⫽ 82 ⫹ a b ⫹a b ⫹a b ⫽ 14.0 A
C 12 12 12
The power factor is
P P 650
pf ⫽ ⫽ ⫽ ⫽ 0.66
S VrmsIrms (70.7)(14.0)
Alternatively, power factor can be computed from Eq. (2-63):

15
a b cos(0 ⫺ 30°)
I cos( ␪ 1 ⫺ ␾1) 12
pf ⫽ 1, rms ⫽ ⫽ 0.66
Irms 14.0
(c) The distortion factor is computed from Eq. (2-65) as
15
I1, rms 12
DF ⫽ ⫽ ⫽ 0.76
Irms 14.0
(d) The total harmonic distortion of the load current is obtained from Eq. (2-68).
15 2
142 ⫺ a b
I 2rms ⫺ I 21, rms 12
THD ⫽ ⫽ ⫽ 0.86 ⫽ 86%.
I 21, rms 15 2
a b
B
a 12
2.9 POWER COMPUTATIONS USING PSPICE

PSpice can be used to simulate power electronics circuits to determine voltages,
currents, and power quantities. A convenient method is to use the numerical
analysis capabilities of the accompanying graphics postprocessor program Probe
to obtain power quantities directly. Probe is capable of
• Displaying voltage and current waveforms (v)(t) and i(t)
• Displaying instantaneous power p(t)
• Computing energy absorbed by a device
• Computing average power P
• Computing average voltage and current
• Computing rms voltages and currents
• Determining the Fourier series of a periodic waveform
The examples that follow illustrate the use of PSpice to do power computations.
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 52
EXAMPLE 2-11
Instantaneous Power, Energy, and Average Power Using PSpice

PSpice can be used to display instantaneous power and to compute energy. A simple example
is a sinusoidal voltage across a resistor. The voltage source has amplitude Vm 10 V and
frequency 60 Hz, and the resistor is 5 . Use VSIN for the source, and select Time Domain
(Transient) in the Simulation Setup. Enter a Run Time (Time to Stop) of 16.67 ms for one
period of the source.
The circuit is shown in Fig. 2-12a. The top node is labeled as 1. When placing the
resistor, rotate it 3 times so that the first node is upward. After running the simulation, the
Netlist should look like this:
*source EXAMPLE 2-11
V_V1 10
SIN 0 10 60 0 0 0
R_R1 105
When the simulation is completed, the Probe screen appears. The waveforms of volt-
age and current for the resistor are obtained by entering V(1) and I(R1). Instantaneous
VOFF = 0
+
VAMPL = 10 V1 R1 5
–
FREQ = 60
0
(a)
p(t)
20
v(t)
10
i(t)
0
-10
0s 5 ms 10 ms 15 ms 20 ms
V(1) I(R1) W(R1) Time
(b)
Figure 2.12 (a) PSpice circuit for Example 2-11; (b) voltage, current, and
instantaneous power for the resistor; (c) energy absorbed by the resistor;
(d) average power absorbed by the resistor.
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 53
200 m
ENERGY AFTER ONE PERIOD
166.664 mJ
(16.670 m, 166.664 m)
100 m
0
0s 5 ms 10 ms 15 ms 20 ms
S (W(R1))
Time
(c)
15 W
(16.670 m, 9.998)
10 W
AVERAGE POWER
9.998 W
5W
0W
0s 5 ms 10 ms 15 ms 20 ms
AVG (W(R1))
Time
(d )
Figure 2.12 (continued)
power p(t) v(t)i(t) absorbed by the resistor is obtained from Probe by entering the
expression V(1)*I(R1) or by selecting W(R1). The resulting display showing V(1), I(R1),
and p(t) is in Fig. 2-12b.
Energy can be computed using the definition of Eq. (2-2). When in Probe, enter the
expression S(V(1)*I(R1)) or S(W(R1)), which computes the integral of instantaneous
power. The result is a trace that shows that the energy absorbed increases with time. The
energy absorbed by the resistor after one period of the source is determined by placing the
cursor at the end of the trace, revealing WR 166.66 mJ (Fig. 2-12c).
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 54
The Probe feature of PSpice can also be used to determine the average value of
power directly. For the circuit in the above example, average power is obtained by enter-
ing the expression AVG(V(1)*I(R1)) or AVG(W(R1)). The result is a “running” value of
average power as computed in Eq. (2-3). Therefore, the average value of the power wave-
form must be obtained at the end of one or more periods of the waveform. Figure. 2-12d
shows the output from Probe. The cursor option is used to obtain a precise value of aver-
age power. This output shows 9.998 W, very slightly different from the theoretical value
of 10 W. Keep in mind that the integration is done numerically from discrete data points.
PSpice can also be used to determine power in an ac circuit containing an inductor
or capacitor, but the simulation must represent steady-state response to be valid for
steady-state operation of the circuit.
EXAMPLE 2-12
RMS and Fourier Analysis Using PSpice

Fig. 2-13a shows a periodic pulse voltage that is connected to a series R-L circuit with
R 10 and L 10 mH. PSpice is used to determine the steady-state rms current and
the Fourier components of the current.
Figure 2-13 (a) A v(t)

pulse waveform 1
voltage source is 20 V
V1 = 0
applied to a series V2 = 20 R1
TD = 0 2
R-L circuit; (b) Probe +
TR = 1 n V1
output showing the - 1
TF = 1 n
steady-state current PW = 8 m L1
PER = 20 m 10 mH
and the rms value.
0
8 ms 20 ms t 0
(a)
10 A
(80.000 m, 4.6389) RMS CURRENT

(100.000 m, 4.6389)
5A
0A
60 ms 70 ms 80 ms 90 ms 100 ms 110 ms
I(R1) RMS(I(R1)) Time
(b)
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 55
In PSpice power calculations, it is extremely important that the output

being analyzed represent steady-state voltages and currents. Steady-state cur-
rent is reached after several periods of the pulse waveform. Therefore, the
Simulation Settings have the Run Time (Time to Stop) at 100 ms and the
Start Saving Data set at 60 ms. The 60-ms delay allows for the current to
reach steady state. A maximum step size is set at 10 s to produce a smooth
waveform.
Current is displayed in Probe by entering I(R1), and steady state is verified
by noting that the starting and ending values are the same for each period. The
rms current is obtained by entering the expression RMS(I(R1)). The value of rms
current, 4.6389 A, is obtained at the end of any period of the current waveform.
Fig. 2-13b shows the Probe output.
The Fourier series of a waveform can be determined using PSpice. Fourier
analysis is entered under Output File Options in the Transient Analysis menu.
The Fast Fourier Transform (FFT) on the waveforms of the source voltage and
(a)
3.75 A (0.000, 4.0010) FOURIER ANALYSIS (FFT)

(50.000, 3.2523)
2.50 A
1.25 A
(100.000, 567.635 m)
0A
0 Hz 50 Hz 100 Hz 150 Hz 200 Hz 250 Hz
I(R1) Frequency
(b)
Figure 2-14 (a) Fourier analysis setup; (b) Fourier Series Spectrum
from Probe using FFT.
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 56
the load current will appear in the output file. The fundamental frequency
(Center Frequency) of the Fourier series is 50 Hz (1/20 mS). In this example,
five periods of the waveform are simulated to ensure steady-state current for
this L/R time constant.
A portion of the output file showing the Fourier components of source volt-
age and resistor current is as follows:
FOURIER COMPONENTS OF TRANSIENT RESPONSE I(R_R1)
DC COMPONENT 4.000000E00
HARMONIC FREQUENCY FOURIER NORMALIZED PHASE NORMALIZED

NO (HZ) COMPONENT COMPONENT (DEG) PHASE (DEG)
1 5.000E01 3.252E00 1.000E00 3.952E01 0.000E00
2 1.000E02 5.675E01 1.745E01 1.263E02 4.731E01
3 1.500E02 2.589E01 7.963E02 2.402E01 9.454E01
4 2.000E02 2.379E01 7.317E02 9.896E01 5.912E01
5 2.500E02 1.391E07 4.277E08 5.269E00 2.029E02
6 3.000E02 1.065E01 3.275E02 6.594E01 1.712E02
7 3.500E02 4.842E02 1.489E02 1.388E02 1.378E02
8 4.000E02 3.711E02 1.141E02 3.145E01 2.847E02
9 4.500E02 4.747E02 1.460E02 1.040E02 2.517E02
TOTAL HARMONIC DISTORTION 2.092715E01 PERCENT
When you use PSpice output for the Fourier series, remember that the values
are listed as amplitudes (zero-to-peak), and conversion to rms by dividing by 12
is required for power computations. The phase angles are referenced to the sine
rather than the cosine. The numerically computed Fourier components in PSpice
may not be exactly the same as analytically computed values. Total harmonic
distortion (THD) is listed at the end of the Fourier output. [Note: The THD com-
puted in PSpice uses Eq. (2-69) and assumes that the dc component of the wave-
form is zero, which is not true in this case.]
The rms value of the load current can be computed from the Fourier series in
the output file from Eq. (2-43).
3.252 2 0.5675 2 p
Irms (4.0)2 a b a b L 4.63 A
C 12 12
A graphical representation of the Fourier series can be produced in Probe. To dis-
play the Fourier series of a waveform, click the FFT button on the toolbar. Upon
entering the variable to be displayed, the spectrum of the Fourier series will
appear. It will be desirable to adjust the range of frequencies to obtain a useful
graph. Fig. 2-14b shows the result for this example. Fourier component magni-
tudes are represented by the peaks of the graph, which can be determined pre-
cisely by using the cursor option.
har80679_ch02_021-064.qxd 12/17/09 1:57 PM Page 57
EXAMPLE 2-13
PSpice Solution of Example 2-3

Use PSpice to simulate the inductor circuit of Fig. 2-4a with the parameters of
Example 2-3.
■ Solution
Fig. 2-15 shows the circuit used in the PSpice simulation. The transistor is used as a
switch, so a voltage-controlled switch (Sbreak) can be used in the PSpice circuit. The
switch is idealized by setting the on resistance to Ron ⫽ 0.001 ⍀. The control for
the switch is a pulse voltage source which has a pulse width of 10 ms and period of 100 ms.
The diode Dbreak is used.
Some of the possible results that can be obtained from the Probe output are listed
below. All traces except the maximum inductor current and the stored inductor energy are
read at the end of the Probe trace, which is after one complete period. Note the agreement
between the results of Example 2-3 and the PSpice results.
Desired Quantity Probe Entry Result

Inductor current I(L1) max ⫽ 4.5 A
Energy stored in inductor 0.5*0.2*I(L1)*I(L1) max ⫽ 2.025 J
Average switch power AVG(W(S1)) 0.010 W
Average source power (absorbed) AVG(W(VCC)) ⫺20.3 W
Average diode power AVG(W(D1)) 0.464 W
Average inductor power AVG(W(L1)) ⬇0
Average inductor voltage AVG(V(1,2)) ⬇0
Average resistor power AVG(W(R1)) 19.9 W
Energy absorbed by resistor S(W(R1)) 1.99 J
Energy absorbed by diode S(W(D1)) 0.046 J
Energy absorbed by inductor S(W(L1)) ⬇0
RMS resistor current RMS(I(R1)) 0.998 A
1 R1
20
L1 VCC
D1 30V
200 mH
Dbreak
V1 = -10 2 2
V2 = 10 4 S1
+
TD = 0 -
Ron = 0.001
TR = 10 n +
TF = 10 n - VCONTROL Sbreak
PW = 10 m
PER = 100 m 0
Figure 2-15 Circuit for Example 2-13, a PSpice simulation of the circuit
in Example 2-4.
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 58
2.10 Summary
• Instantaneous power is the product of voltage and current at a particular time:
p(t) v(t)i(t)
Using the passive sign convention, the device is absorbing power if (p)(t) is
positive, and the device is supplying power if (p)(t) is negative.
• Power usually refers to average power, which is the time average of periodic
instantaneous power:
t0 T t0 T
1 1
P v(t)i(t) dt p(t) dt
T3 T3
t0 t0
• The rms value is the root-mean-square or effective value of a voltage or current

waveform.
T
1
Vrms v 2(t) dt
CT 3
0
T
1
Irms i 2(t) dt
CT 3
0
• Apparent power is the product of rms voltage and current.

S VrmsIrms
• Power factor is the ratio of average power to apparent power.
P P
pf
S VrmsIrms
• For inductors and capacitors that have periodic voltages and currents, the average
power is zero. Instantaneous power is generally not zero because the device stores
energy and then returns energy to the circuit.
• For periodic currents, the average voltage across an inductor is zero.
• For periodic voltages, the average current in a capacitor is zero.
• For nonsinusoidal periodic waveforms, average power may be computed from the
basic definition, or the Fourier series method may be used. The Fourier series
method treats each frequency in the series separately and uses superposition to
compute total power.
q q
P a Pn V0I0 a Vn, rms In, rms cos ( n n)

n0 n1
• A simulation using the program PSpice may be used to obtain not only voltage and
current waveforms but also instantaneous power, energy, rms values, and average
power by using the numerical capabilities of the graphic postprocessor program
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 59
Problems 59
Probe. For numerical computations in Probe to be accurate, the simulation must

represent steady-state voltages and currents.
• Fourier series terms are available in PSpice by using the Fourier Analysis in the
Simulation Settings or by using the FFT option in Probe.
2.11 Bibliography
M. E. Balci and M. H. Hocaoglu, “Comparison of Power Definitions for Reactive
Power Compensation in Nonsinusoidal Circuits,” International Conference on
Harmonics and Quality of Power, Lake Placid, New York, 2004.
L. S. Czarnecki, “Considerations on the Reactive Power in Nonsinusoidal Situations,”
International Conference on Harmonics in Power Systems, Worcester Polytechnic
Institute, Worcester, Mass., 1984, pp. 231–237.
A. E. Emanuel, “Powers in Nonsinusoidal Situations, A Review of Definitions
and Physical Meaning,” IEEE Transactions on Power Delivery, vol. 5, no. 3,
July 1990.
G. T. Heydt, Electric Power Quality, Stars in a Circle Publications, West Lafayette,
Ind., 1991.
W. Sheperd and P. Zand, Energy Flow and Power Factor in Nonsinusoidal Circuits,
Cambridge University Press, 1979.
Problems
Instantaneous and Average Power
2-1. Average power generally is not the product of average voltage and average
current. Give an example of periodic waveforms for v(t) and i(t) that have zero
average values and average power absorbed by the device is not zero. Sketch
v(t), i(t), and p(t).
2-2. The voltage across a 10- resistor is v(t) 170 sin (377t) V. Determine (a) an
expression for instantaneous power absorbed by the resistor, (b) the peak power,
and (c) the average power.
2-3. The voltage across an element is v(t) 5 sin (2
t) V. Use graphing software to
graph instantaneous power absorbed by the element, and determine the average
power if the current, using the passive sign convention, is (a) i(t) 4 sin (2
t) A
and (b) i(t) 3 sin (4
t) A.
2-4. The voltage and current for a device (using the passive sign convention) are
periodic functions with T 100 ms described by
10 V 0 t 70 ms
v(t) b
0 70 ms t 100 ms
0 0 t 50 ms
i(t) b
4A 50 ms t 100 ms
Determine (a) the instantaneous power, (b) the average power, and (c) the energy
absorbed by the device in each period.
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 60
2-5. The voltage and current for a device (using the passive sign convention) are
periodic functions with T 20 ms described by
v(t) e
10 V 0 t 14 ms
0 14 ms t 20 ms
7A 0 t 6 ms
i(t) c 5 A 6 ms t 10 ms
4A 10 ms t 20 ms
Determine (a) the instantaneous power, (b) the average power, and (c) the energy
absorbed by the device in each period.
2-6. Determine the average power absorbed by a 12-V dc source when the current
into the positive terminal of the source is that given in (a) Prob. 2-4 and
(b) Prob. 2-5.
2-7. A current of 5 sin (2
60t) A enters an element. Sketch the instantaneous power
and determine the average power absorbed by the load element when the element
is (a) a 5- resistor, (b) a 10-mH inductor, and (c) a 12-V source (current into the
positive terminal).
2-8. A current source of i(t) 2 6 sin(2
60t) A is connected to a load that is a
series combination of a resistor, an inductor, and a dc voltage source (current into
the positive terminal). If R 4 , L 15 mH, and Vdc 6 V, determine the
average power absorbed by each element.
2-9. An electric resistance space heater rated at 1500 W for a voltage source of
v(t) 120 12 sin (2
60t) V has a thermostatically controlled switch. The
heater periodically switches on for 5 min and off for 7 min. Determine
(a) the maximum in stantaneous power, (b) the average power over the
12-min cycle, and (c) the electric energy converted to heat in each 12-min
cycle.
Energy Recovery
2-10. An inductor is energized as in the circuit of Fig. 2-4a. The circuit has L 100 mH,
R 20 , VCC 90 V, t1 4 ms, and T 40 ms. Assuming the transistor and
diode are ideal, determine (a) the peak energy stored in the inductor, (b) the
energy absorbed by the resistor in each switching period, and (c) the average
power supplied by the source. (d) If the resistor is changed to 40 , what is the
average power supplied by the source?
2-11. An inductor is energized as in the circuit of Fig. 2-4a. The circuit has L 10 mH
and VCC 14 V. (a) Determine the required on time of the switch such that the peak
energy stored in the inductor is 1.2 J. (b) Select a value for R such that the switching
cycle can be repeated every 20 ms. Assume the switch and the diode are ideal.
2-12. An inductor is energized as in the circuit of Fig. 2-5a. The circuit has L 50 mH,
VCC 90 V, t1 4 ms, and T 50 ms. (a) Determine the peak energy stored in
the inductor. (b) Graph the inductor current, source current, inductor
instantaneous power, and source instantaneous power versus time. Assume the
transistors are ideal.
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 61
Problems 61
2-13. An alternative circuit for energizing an inductor and removing the stored
energy without damaging a transistor is shown in Fig. P2-13. Here VCC 12 V,
L 75 mH, and the zener breakdown voltage is VZ 20 V. The transistor
switch opens and closes periodically with ton 20 ms and toff 50 ms.
(a) Explain how the zener diode allows the switch to open. (b) Determine and
sketch the inductor current iL(t) and the zener diode current iZ(t) for one
switching period. (c) Sketch (p)(t) for the inductor and the zener diode.
(d) Determine the average power absorbed by the inductor and by the
zener diode.
VCC
iL
iZ
2-14. Repeat Prob. 2-13 with VCC 20 V, L 50 mH, VZ 30 V, ton 15 ms, and
toff 60 ms.
Effective Values: RMS

2-15. The rms value of a sinusoid is the peak value divided by 12. Give two
examples to show that this is generally not the case for other periodic
waveforms.
2-16. A three-phase distribution system is connected to a nonlinear load that has line
and neutral currents like those of Fig. 2-8. The rms current in each phase is 12 A,
and the resistance in each of the line and neutral conductors is 0.5 . Determine
the total power absorbed by the conductors. What should the resistance of the
neutral conductor be such that it absorbs the same power as one of the phase
conductors?
2-17. Determine the rms values of the voltage and current waveforms in Prob. 2-4.
2-18. Determine the rms values of the voltage and current waveforms in Prob. 2-5.
Nonsinusoidal Waveforms
2-19. The voltage and current for a circuit element are v(t) 2 5 cos (2
60t)
3cos(4
60t 45) V and i(t) 1.5 2cos(2
60t 20) 1.1cos(4
60t 20) A.
(a) Determine the rms values of voltage and current. (b) Determine the power
absorbed by the element.
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 62
2-20. A current source i(t) 3 4 cos(2

60t) 6 cos (4
60t) A is connected to a
parallel RC load with R 100 and C 50 F. Determine the average power
absorbed by the load.
2-21. In Fig. P2-21, R 4 , L 10 mH, Vdc 12 V, and vs(t) 50 30 cos (4
60t)
10 cos(8
60t) V. Determine the power absorbed by each component.
+
vs
− L
+
Vdc
−
Figure P2-21
2-22. A nonsinusoidal periodic voltage has a Fourier series of v(t) 6 5 cos(2

60t)
3cos(6
60t). This voltage is connected to a load that is a 16- resistor in
series with a 25-mH inductor as in Fig. 2-11. Determine the power absorbed by
the load.
2-23. Voltage and current for a device (using the passive sign convention) are
20
v(t) 20 a a b cos (n
t) V
q
n1 n
5
i(t) 5 a a 2 b cos (n
t) A
q
n1 n
Determine the average power based on the terms through n 4.

2-24. Voltage and current for a device (using the passive sign convention) are
50
v(t) 50 a a b cos (n
t) V
q
n1 n
i(t) 10 a a 2 b cos A n
t tan1n>2 B
q
10
n1 n
Determine the average power based on the terms through n 4.

2-25. In Fig. P2-21, R 20 , L 25 mH, and Vdc 36 V. The source is a periodic
voltage that has the Fourier series
b sin A 200n
t B
400
vs(t) 50 a a
q
n1 n
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 63
Problems 63
Using the Fourier series method, determine the average power absorbed by R,
L, and Vdc when the circuit is operating in the steady state. Use as many terms
in the Fourier series as necessary to obtain a reasonable estimate of power.
2-26. A sinusoidal current of 10 A rms at a 60-Hz fundamental frequency is
contaminated with a ninth harmonic current. The current is expressed as
i(t) 1022 sin (2

60t) I9 22 sin (18
60t) A
Determine the value of the ninth harmonic rms current I9 if the THD is (a) 5 percent,
(b) 10 percent, (c) 20 percent, and (d) 40 percent. Use graphing software or PSpice
to show i(t) for each case.
2-27. A sinusoidal voltage source of v(t) 170 cos (2
60t) V is applied to a nonlinear
load, resulting in a nonsinusoidal current that is expressed in Fourier series form
as i(t) 10 cos (2
60t 30) 6 cos (4
60t 45) 3 cos (8
60t 20) A.
Determine (a) the power absorbed by the load, (b) the power factor of the load,
(c) the distortion factor, and (d) the total harmonic distortion of the load current.
2-28. Repeat Prob. 2-27 with i(t) 12 cos (2
60t 40) 5 sin (4
60t)
4 cos (8
60t) A.
2-29. A sinusoidal voltage source of v(t) 240 12 sin (2
60t) V is applied to a
nonlinear load, resulting in a current i(t) 8 sin (2
60t) 4 sin (4
60t) A.
Determine (a) the power absorbed by the load, (b) the power factor of the load,
(c) the THD of the load current, (d) the distortion factor of the load current, and
(e) the crest factor of the load current.
2-30. Repeat Prob. 2-29 with i(t) 12 sin (2
60t) 9 sin (4
60t) A.
2-31. A voltage source of v(t) 5 25 cos (1000t) 10 cos (2000t) V is connected to
a series combination of a 2- resistor, a 1-mH inductor, and a 1000-F capacitor.
Determine the rms current in the circuit, and determine the power absorbed by
each component.
PSpice
2-32. Use PSpice to simulate the circuit of Example 2-1. Define voltage and current
with PULSE sources. Determine instantaneous power, energy absorbed in one
period, and average power.
2-33. Use PSpice to determine the instantaneous and average power in the circuit
elements of Prob. 2-7.
2-34. Use PSpice to determine the rms values of the voltage and current waveforms in
(a) Prob. 2-5 and (b) Prob. 2-6.
2-35. Use PSpice to simulate the circuit of Prob. 2-10. (a) Idealize the circuit by using
a voltage-controlled switch that has Ron 0.001 and a diode with n 0.001.
(b) Use Ron 0.5 and use the default diode.
2-36. Use PSpice to simulate the circuit of Fig. 2-5a. The circuit has VCC 75 V,
t0 40 ms, and T 100 ms. The inductance is 100 mH and has an internal
resistance of 20 . Use a voltage-controlled switch with Ron 1 for the
transistors, and use the PSpice default diode model. Determine the average
power absorbed by each circuit element. Discuss the differences between the
behavior of this circuit and that of the ideal circuit.
har80679_ch02_021-064.qxd 12/15/09 3:01 PM Page 64
2-37. Use PSpice to simulate the circuit of Prob. 2-13. Use Ron 0.001 for the
switch model and use n 0.001, BV 20 V for the breakdown voltage and
IBV 10 A for the current at breakdown for the zener diode model. (a) Display
iL(t) and iZ(t). Determine the average power in the inductor and in the zener
diode. (b) Repeat part (a) but include a 1.5- series resistance with the inductor
and use Ron 0.5 for the switch.
2-38. Repeat Prob. 2-37, using the circuit of Prob. 2-14.
2-39. Use PSpice to determine the power absorbed by the load in Example 2-10.
Model the system as a voltage source and four current sources in parallel.
2-40. Modify the switch model so Ron 1 in the PSpice circuit file in Example 2-13.
Determine the effect on each of the quantities obtained from Probe in the
example.
2-41. Demonstrate with PSpice that a triangular waveform like that of Fig. 2-9a has an
rms value of Vm/ 13. Choose an arbitrary period T, and use at least three values
of t1. Use a VPULSE source with the rise and fall times representing the
triangular wave.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 65
C H A P T E R 3
Half-Wave Rectifiers
The Basics of Analysis
3.1 INTRODUCTION
A rectifier converts ac to dc. The purpose of a rectifier may be to produce an out-
put that is purely dc, or the purpose may be to produce a voltage or current wave-
form that has a specified dc component.
In practice, the half-wave rectifier is used most often in low-power applica-
tions because the average current in the supply will not be zero, and nonzero aver-
age current may cause problems in transformer performance. While practical
applications of this circuit are limited, it is very worthwhile to analyze the half-
wave rectifier in detail. A thorough understanding of the half-wave rectifier circuit
will enable the student to advance to the analysis of more complicated circuits
with a minimum of effort.
The objectives of this chapter are to introduce general analysis techniques
for power electronics circuits, to apply the power computation concepts of the
previous chapter, and to illustrate PSpice solutions.
3.2 RESISTIVE LOAD

Creating a DC Component Using an Electronic Switch
A basic half-wave rectifier with a resistive load is shown in Fig. 3-1a. The source
is ac, and the objective is to create a load voltage that has a nonzero dc component.
The diode is a basic electronic switch that allows current in one direction only. For
the positive half-cycle of the source in this circuit, the diode is on (forward-biased).
65
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 66
66 C H A P T E R 3 Half-Wave Rectifiers
Vm
vs
π 2π ωt
vd
+ − −Vm
i Vm
+ +
vs = Vm sin (ω t) R vo
− − vo
π 2π ωt
..
(a) .
vd
π 2π ωt
−Vm
(b)
Figure 3-1 (a) Half-wave rectifier with resistive load; (b) Voltage waveforms.
Considering the diode to be ideal, the voltage across a forward-biased diode is zero
and the current is positive.
For the negative half-cycle of the source, the diode is reverse-biased, mak-
ing the current zero. The voltage across the reverse-biased diode is the source
voltage, which has a negative value.
The voltage waveforms across the source, load, and diode are shown in
Fig. 3-1b. Note that the units on the horizontal axis are in terms of angle (t).
This representation is useful because the values are independent of frequency.
The dc component Vo of the output voltage is the average value of a half-wave
rectified sinusoid

1 V
Vo Vavg V sin(t)d(t) m (3-1)
2 L m
0
The dc component of the current for the purely resistive load is
V V
Io o m (3-2)
R R
Average power absorbed by the resistor in Fig. 3-1a can be computed from
P I2rmsR V2rmsR. When the voltage and current are half-wave rectified sine
waves,

1 V
Vrms [Vm sin (t)]2 d(t) m
E 2 L 2
0 (3-3)
Vm
Irms
2R
In the preceding discussion, the diode was assumed to be ideal. For a real
diode, the diode voltage drop will cause the load voltage and current to be
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 67
3.3 Resistive-Inductive Load 67
reduced, but not appreciably if Vm is large. For circuits that have voltages much
larger than the typical diode drop, the improved diode model may have only
second-order effects on the load voltage and current computations.
EXAMPLE 3-1
Half-Wave Rectifier with Resistive Load

For the half-wave rectifier of Fig. 3-1a, the source is a sinusoid of 120 V rms at a fre-
quency of 60 Hz. The load resistor is 5 . Determine (a) the average load current, (b) the
average power absorbed by the load and (c) the power factor of the circuit.
■ Solution
(a) The voltage across the resistor is a half-wave rectified sine wave with peak value
Vm 120 12 169.7 V. From Eq. (3-2), the average voltage is Vm , and
average current is
Vo Vm 22(120)
Io 10.8 A
R R 5
(b) From Eq. (3-3), the rms voltage across the resistor for a half-wave rectified sinusoid is
Vm 22(120)
Vrms 84.9 V
2 2
The power absorbed by the resistor is
2
V rms 84.9 2
P 1440 W
R 4
The rms current in the resistor is Vm (2R) 17.0 A, and the power could also be
calculated from I2rmsR (17.0)2(5) 1440 W.
(c) The power factor is
P P 1440
pf 0.707
S Vs, rms Is, rms (120)(17)
3.3 RESISTIVE-INDUCTIVE LOAD

Industrial loads typically contain inductance as well as resistance. As the source
voltage goes through zero, becoming positive in the circuit of Fig. 3-2a, the
diode becomes forward-biased. The Kirchhoff voltage law equation that
describes the current in the circuit for the forward-biased ideal diode is
di(t)
Vm sin(t) Ri(t) L (3-4)
dt
The solution can be obtained by expressing the current as the sum of the
forced response and the natural response:
i(t) i f (t) i n(t) (3-5)
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 68
Vm
vs, io 0 ωt
π β 2π
vo 0 ωt
π β 2π
ωt
vR 0
π β 2π
vL 0 ωt
vd π β 2π
+ −
+
i
+
R vR
− v ωt
o
0
+ + π β 2π
vs = Vm sin(ωt) vd
− L vL
−
− -Vm
(a) (b)
Figure 3-2 (a) Half-wave rectifier with an RL load; (b) Waveforms.
The forced response for this circuit is the current that exists after the natural
response has decayed to zero. In this case, the forced response is the steady-state
sinusoidal current that would exist in the circuit if the diode were not present.
This steady-state current can be found from phasor analysis, resulting in
Vm
i f (t) sin (t ) (3-6)
Z
L
where Z 2R2 (L)2 and tan 1 a b
R
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 69
The natural response is the transient that occurs when the load is energized. It is
the solution to the homogeneous differential equation for the circuit without the
source or diode:
di(t)
R i(t) L 0 (3-7)
dt
For this first-order circuit, the natural response has the form
i n(t) Ae t>
(3-8)
where
is the time constant L/R and A is a constant that is determined from the ini-
tial condition. Adding the forced and natural responses gets the complete solution.
Vm
i(t) i f (t) i n(t) sin(t ) Ae t>
(3-9)
Z
The constant A is evaluated by using the initial condition for current. The ini-
tial condition of current in the inductor is zero because it was zero before the
diode started conducting and it cannot change instantaneously.
Using the initial condition and Eq. (3-9) to evaluate A yields
Vm
i(0) sin(0 ) Ae0 0
Z
(3-10)
V V
A m sin( ) m sin
Z Z
Substituting for A in Eq. (3-9) gives
Vm V
i(t) sin (t ) m sin () e t>
Z Z
(3-11)
m Csin (t ) sin () e t>
D
V
Z
It is often convenient to write the function in terms of the angle t rather
than time. This merely requires t to be the variable instead of t. To write the
above equation in terms of angle, t in the exponential must be written as t,
which requires
to be multiplied by also. The result is
Csin (t ) sin () e t>

D
Vm
i(t) (3-12)
Z
A typical graph of circuit current is shown in Fig. 3-2b. Equation (3-12) is
valid for positive currents only because of the diode in the circuit, so current is
zero when the function in Eq. (3-12) is negative. When the source voltage again
becomes positive, the diode turns on, and the positive part of the waveform in
Fig. 3-2b is repeated. This occurs at every positive half-cycle of the source. The
voltage waveforms for each element are shown in Fig. 3-2b.
Note that the diode remains forward-biased longer than rad and that the
source is negative for the last part of the conduction interval. This may seem
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 70
unusual, but an examination of the voltages reveals that Kirchhoff’s voltage law
is satisfied and there is no contradiction. Also note that the inductor voltage is
negative when the current is decreasing (vL L didt).
The point when the current reaches zero in Eq. (3-12) occurs when the diode
turns off. The first positive value of t in Eq. (3-12) that results in zero current is
called the extinction angle .
Substituting t in Eq. (3-12), the equation that must be solved is
Csin ( ) sin ()e >

D 0
Vm
i( ) (3-13)
Z
which reduces to
sin ( ) sin ()e >
0 (3-14)
There is no closed-form solution for , and some numerical method is required. To

summarize, the current in the half-wave rectifier circuit with RL load (Fig. 3-2) is
expressed as
Csin (t ) sin ()e t>

D
Vm
for 0 t
Z
i(t) d
0 for t 2
(3-15)
L L
where Z 2R2 (L)2 tan 1 a b and

R R
The average power absorbed by the load is I2rmsR, since the average power
absorbed by the inductor is zero. The rms value of the current is determined from
the current function of Eq. (3-15).
2
1 1
Irms i 2(t) d(t) i 2(t) d(t) (3-16)
F 2 L F 2 L
0 0
Average current is

1
Io i(t) d(t) (3-17)
2 L
0
EXAMPLE 3-2
Half-Wave Rectifier with RL Load

For the half-wave rectifier of Fig. 3-2a, R 100 , L 0.1 H, 377 rad/s, and
Vm 100 V. Determine (a) an expression for the current in this circuit, (b) the average cur-
rent, (c) the rms current, (d) the power absorbed by the RL load, and (e) the power factor.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 71
■ Solution
For the parameters given,
Z [R2 (L)2]0.5 106.9
tan 1(LR) 20.7 0.361 rad
t LR 0.377 rad
(a) Equation (3-15) for current becomes
i(t) 0.936 sin(t 0.361) 0.331e t>0.377 A for 0 t
Beta is found from Eq. (3-14).
sin( 0.361) sin(0.361) e >0.377 0
Using a numerical root-finding program, is found to be 3.50 rad, or 201
(b) Average current is determined from Eq. (3-17).
3.50
C 0.936sin(t 0.361) 0.331e t>0.377 D d(t) 0.308 A

1
Io
2 L
0
(A numerical integration program is recommended.)
(c) The rms current is found from Eq. (3-16) to be
3.50
C 0.936 sin(t 0.361) 0.331e t>0.377 D d(t) 0.474 A

1 2
Irms
F 2 L
0
(d) The power absorbed by the resistor is
P I 2rms R (0.474)2(100) 22.4 W
The average power absorbed by the inductor is zero. Also P can be computed from
the definition of average power:
2 2
1 1
P p(t)d(t) v(t)i(t)d(t)
2 L 2 L
0 0
3.50
[100 sin (t)] C 0.936 sin (t 0.361) 0.331e t>0.377 D d(t)
1

2 L
0
22.4 W
(e) The power factor is computed from the definition pf PS, and P is power
supplied by the source, which must be the same as that absorbed by the load.
P P 22.4
S Vs, rms Irms A100> 12B 0.474
pf 0.67
Note that the power factor is not cos .

har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 72
3.4 PSPICE SIMULATION

Using Simulation Software for Numerical Computations
A computer simulation of the half-wave rectifier can be performed using PSpice.
PSpice offers the advantage of having the postprocessor program Probe which
can display the voltage and current waveforms in the circuit and perform numer-
ical computations. Quantities such as the rms and average currents, average
power absorbed by the load, and power factor can be determined directly with
PSpice. Harmonic content can be determined from the PSpice output.
A transient analysis produces the desired voltages and currents. One com-
plete period is a sufficient time interval for the transient analysis.
EXAMPLE 3-3
PSpice Analysis
Use PSpice to analyze the circuit of Example 3-2.
■ Solution
The circuit of Fig. 3-2a is created using VSIN for the source and Dbreak for the diode.
In the simulation settings, choose Time Domain (transient) for the analysis type, and set
the Run Time to 16.67 ms for one period of the source. Set the Maximum Step Size to
10 s to get adequate sampling of the waveforms. A transient analysis with a run time of
16.67 ms (one period for 60 Hz) and a maximum step size of 10 s is used for the sim-
ulation settings.
If a diode model that approximates an ideal diode is desired for the purpose of com-
paring the simulation with analytical results, editing the PSpice model and using
n 0.001 will make the voltage drop across the forward-biased diode close to zero.
Alternatively, a model for a power diode may be used to obtain a better representation of
a real rectifier circuit. For many circuits, voltages and currents will not be affected sig-
nificantly when different diode models are used. Therefore, it may be convenient to use
the Dbreak diode model for a preliminary analysis.
When the transient analysis is performed and the Probe screen appears, display the
current waveform by entering the expression I(R1). A method to display angle instead of
time on the x axis is to use the x-variable option within the x-axis menu, entering
TIME*60*360. The factor of 60 converts the axis to periods (f 60 Hz), and the factor
360 converts the axis to degrees. Entering TIME*60*2*3.14 for the x variable converts
the x axis to radians. Figure 3-3a shows the result. The extinction angle is found to be
200 using the cursor option. Note that using the default diode model in PSpice resulted
in a value of very close to the 201 in Example 3-2.
Probe can be used to determine numerically the rms value of a waveform. While in
Probe, enter the expression RMS(I(R1)) to obtain the rms value of the resistor current.
Probe displays a “running” value of the integration in Eq. (3-16), so the appropriate value
is at the end of one or more complete periods of the waveform. Figure 3-3b shows how to
obtain the rms current. The rms current is read as approximately 468 mA. This compares
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 73
3.4 PSpice Simulation 73
1000 mA
LOAD CURRENT
500 mA
BETA = 200 DEC

(200.455, 6.1090u)
0A
0s 100 s 200 s 300 s 400 s
I(R1)
Time*60*360
(a)
1000 mA
DETERMINING RMS CURRENT
I (R1)
RMS (I (R1))
(16.670m, 467.962m)
500 mA
READ RMS VALUE HERE

Irms = 468 mA
0A
0s 5 ms 10 ms 15 ms 20 ms 25 ms
I(R1) RMS ( I (R1)) Time
(b)
Figure 3-3 (a) Determining the extinction angle in Probe. The time
axis is changed to angle using the x-variable option and entering
Time*60*360; (b) Determining the rms value of current in Probe.
very well with the 474 mA calculated in Example 3-2. Remember that the default diode
model is used in PSpice and an ideal diode was used in Example 3-2. The average current
is found by entering AVG(I(R1)), resulting in Io 304 mA.
PSpice is also useful in the design process. For example, the objective may be
to design a half-wave rectifier circuit to produce a specified value of average cur-
rent by selecting the proper value of L in an RL load. Since there is no closed-form
solution, a trial-and-error iterative method must be used. A PSpice simulation that
includes a parametric sweep is used to try several values of L. Example 3-4 illus-
trates this method.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 74
EXAMPLE 3-4
Half-Wave Rectifier Design Using PSpice

Design a circuit to produce an average current of 2.0 A in a 10- resistance. The source
is 120 V rms at 60 Hz.
■ Solution
A half-wave rectifier is one circuit that can be used for this application. If a simple half-
wave rectifier with the 10- resistance were used, the average current would be
(120 12)/8 6.5 A. Some means must be found to reduce the average current to the
specified 2 A. A series resistance could be added to the load, but resistances absorb
power. An added series inductance will reduce the current without adding losses, so an
HALF-WAVE RECTIFIER WITH PARAMETRIC SWEEP

D1 R1
Dbreak 10 1
VOFF = 0 V1
+ PARAMETERS:
VAMPL = {120* sqrt(2)} L1 (L)
FREQ = 60 − L = 0.1
2
0
(a)
(b)
Figure 3-4 (a) PSpice circuit for Example 3-4; (b) A parametric sweep is estab-
lished in the Simulation Settings box; (c) L 0.15 H for an average current of
approximately 2 A.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 75
3.5 RL-Source Load 75
6.0 A
PARAMETRIC SWEEP
4.0 A
(16.670m, 2.0118)
2.0 A
0A
0s 4 ms 8 ms 12 ms 16 ms 20 ms 22 ms
AVG <I (R1)>
Time
(c)
inductor is chosen. Equations (3-15) and (3-17) describe the current function and its
average for RL loads. There is no closed-form solution for L. A trial-and-error technique
in PSpice uses the parameter (PARAM) part and a parametric sweep to try a series of
values for L. The PSpice circuit and the Simulation Settings box are shown in Fig. 3-4.
Average current in the resistor is found by entering AVG(I(R1)) in Probe, yielding a
family of curves for different inductance values (Fig. 3-4c). The third inductance in the
sweep (0.15 H) results in an average current of 2.0118 A in the resistor, which is very
close to the design objective. If further precision is necessary, subsequent simulations can
be performed, narrowing the range of L.
3.5 RL-SOURCE LOAD

Supplying Power to a DC Source from an AC Source
Another variation of the half-wave rectifier is shown in Fig. 3-5a. The load
consists of a resistance, an inductance, and a dc voltage. Starting the analysis
at t 0 and assuming the initial current is zero, recognize that the diode will
remain off as long as the voltage of the ac source is less than the dc voltage.
Letting be the value of t that causes the source voltage to be equal to Vdc,
Vm sin Vdc
or
Vdc
sin 1 a b (3-18)
Vm
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 76
R L
i +
Vm sin(ωt) + Vdc
− −
(a)
R L R
ifac ifdc +
Vm sin(ωt) +
Vdc
− −
(b) (c)
vs
Vdc
α π β 2π ωt
(d)
Figure 3-5 (a) Half-wave rectifier with RL source load; (b) Circuit
for forced responce from ac source; (c) Circuit for forced
responce from dc source; (d) Waveforms.
The diode starts to conduct at t . With the diode conducting, Kirchhoff’s

voltage law for the circuit yields the equation
di(t)
Vm sin(t) Ri(t) L Vdc (3-19)
dt
Total current is determined by summing the forced and natural responses:
i(t) if (t) in(t)
The current if (t) is determined using superposition for the two sources. The
forced response from the ac source (Fig. 3-5b) is (Vm/Z) sin(t ). The
forced response due to the dc source (Fig. 3-5c) is Vdc/R. The entire forced
response is
Vm V
if (t) sin(t ) dc (3-20)
Z R
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 77
3.5 RL-Source Load 77
The natural response is
i n(t) Ae t>
(3-21)
Adding the forced and natural responses gives the complete response.
Vm V
sin (t ) dc Ae t>
for t
Z R
i(t) d (3-22)
0 otherwise
The extinction angle is defined as the angle at which the current reaches zero,
as was done earlier in Eq. (3-15). Using the initial condition of i() 0 and
solving for A,
Vm V
A c sin( ) dc d e >
(3-23)
Z R
Figure 3-5d shows voltage and current waveforms for a half-wave rectifier with
RL-source load.
The average power absorbed by the resistor is I2rmsR, where

1
Irms i 2(t) d(t) (3-24)
E 2 L

The average power absorbed by the dc source is

Pdc IoVdc (3-25)
where Io is the average current, that is,

1
Io i(t)d(t) (3-26)
2 L

Assuming the diode and the inductor to be ideal, there is no average power
absorbed by either. The power supplied by the ac source is equal to the sum of
the power absorbed by the resistor and the dc source
Pac I 2rms R IoVdc (3-27)
or it can be computed from
2
1 1
Pac v(t) i(t)d(t) (Vm sin t) i(t)d(t) (3-28)
2 L 2 L
0
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 78
EXAMPLE 3-5
Half-Wave Rectifier with RL-Source Load

For the circuit of Fig. 3-5a, R 2 , L 20 mH, and Vdc 100 V. The ac source is 120 V
rms at 60 Hz. Determine (a) an expression for the current in the circuit, (b) the power
absorbed by the resistor, (c) the power absorbed by the dc source, and (d) the power sup-
plied by the ac source and the power factor of the circuit.
■ Solution
From the parameters given,
Vm 120 12 169.7 V
Z [R2 (L)2]0.5 7.80
tan 1(LR) 1.31 rad
sin 1(100169.7) 36.1 0.630 rad

377(0.022) 3.77 rad
(a) Using Eq. (3-22),
i(t) 21.8 sin(t 1.31) 50 75.3e t>3.77 A
The extinction angle is found from the solution of
i() 21.8 sin ( 1.31) 50 75.3e >3.77 0
which results in 3.37 rad (193 ) using root-finding software.
(b) Using the preceding expression for i(t) in Eq. (3-24) and using a numerical
integration program, the rms current is
3.37
1
Irms i 2(t)d(t) 3.98 A
E 2 L
0.63
resulting in
PR I 2rms R 3.982(2) 31.7 W
(c) The power absorbed by the dc source is IoVdc. Using Eq. (3-26),
3.37
1
Io i(t)d(t) 2.25 A
2 L
0.63
yielding
Pdc IoVdc (2.25)(100) 225 W
(d) The power supplied by the ac source is the sum of the powers absorbed by the load.
Ps PR Pdc 31.2 225 256 W
The power factor is
P P 256
pf 0.54
S Vs, rms Irms (120)(3.98)
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 79
3.6 Inductor-Source Load 79
■ PSpice Solution
The power quantities in this example can be determined from a PSpice simulation of this
circuit. The circuit of Fig. 3-5a is created using VSIN, Dbreak, R, and L. In the simula-
tion settings, choose Time Domain (transient) for the analysis type, and set the Run Time
to 16.67 ms for one period of the source. Set the Maximum Step Size to 10 s to get ade-
quate sampling of the waveforms. A transient analysis with a run time of 16.67 ms (one
period for 60 Hz) and a maximum step size of 10 s is used for the simulation settings.
Average power absorbed by the 2- resistor can be computed in Probe from the
basic definition of the average of p(t) by entering AVG(W(R1)), resulting in 29.7 W, or
from I2rmsR by entering RMS(I(R1))*RMS(I(R1))*2. The average power absorbed by the
dc source is computed from the Probe expression AVG(W(Vdc)), yielding 217 W.
The PSpice values differ slightly from the values obtained analytically because of
the diode model. However, the default diode is more realistic than the ideal diode in pre-
dicting actual circuit performance.
3.6 INDUCTOR-SOURCE LOAD

Using Inductance to Limit Current
Another variation of the half-wave rectifier circuit has a load that consists of an
inductor and a dc source, as shown in Fig. 3-6. Although a practical implementa-
tion of this circuit would contain some resistance, the resistance may be negligi-
ble compared to other circuit parameters.
Starting at t 0 and assuming zero initial current in the inductor, the diode
remains reverse-biased until the ac source voltage reaches the dc voltage. The
value of t at which the diode starts to conduct is , calculated using Eq. (3-18).
With the diode conducting, Kirchhoff’s voltage law for the circuit is
di(t)
Vm sin(t) L Vdc (3-29)
dt
or
L di(t)
Vm sin(t) Vdc (3-30)
dt
L
Vm sin(ω t) +
−
+
Vdc
−
Figure 3-6 Half-wave rectifier with

inductor source load.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 80
Rearranging gives
di(t) Vm sin(t) Vdc
(3-31)
dt L
Solving for i(t),
t t
1 1
i(t) Vm sin l d(l) V d(l) (3-32)
L L L L dc

Performing the integration,
Vm V
(cos cos t) dc ( t) for t
L L
i(t) d (3-33)
0 otherwise
A distinct feature of this circuit is that the power supplied by the source is the
same as that absorbed by the dc source, less any losses associated with a nonideal
diode and inductor. If the objective is to transfer power from the ac source to the
dc source, losses are kept to a minimum by using this circuit.
EXAMPLE 3-6
Half-Wave Rectifier with Inductor-Source Load

For the circuit of Fig. 3-6, the ac source is 120 V rms at 60 Hz, L 50 mH, and Vdc 72 V.
Determine (a) an expression for the current, (b) the power absorbed by the dc source, and
(c) the power factor.
■ Solution
For the parameters given,
72
sin 1 a b 25.1° 0.438 rad
12012
(a) The equation for current is found from Eq. (3-33).
i(t) 9.83 9.00 cos (t) 3.82 t A for t
where is found to be 4.04 rad from the numerical solution of 9.83 9.00 cos
3.82 0.
(b) The power absorbed by the dc source is IoVdc, where

1
Io i(t) d(t)
2 L

4.04
1
[9.83 9.00 cos (t) 3.82 t] d(t) 2.46 A
2 L
0.438
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 81
3.7 The Freewheeling Diode 81
resulting in
Pdc Vdc Io (2.46)(72) 177 W
(c) The rms current is found from

1
Irms i 2(t) d(t) 3.81 A
E 2 L

Therefore,
P P 177
pf 0.388
S Vrms Irms (120)(3.81)
3.7 THE FREEWHEELING DIODE

Creating a DC Current
A freewheeling diode, D2 in Fig. 3-7a, can be connected across an RL load as
shown. The behavior of this circuit is somewhat different from that of the half-
wave rectifier of Fig. 3-2. The key to the analysis of this circuit is to determine
when each diode conducts. First, it is observed that both diodes cannot be
forward-biased at the same time. Kirchhoff’s voltage law around the path con-
taining the source and the two diodes shows that one diode must be reverse-
biased. Diode D1 will be on when the source is positive, and diode D2 will be on
when the source is negative.
iD1 D1
+ io
i D2 R
vs = Vm sin(ωt) +
D2 vo
−
L
−
(a)
+ io + io
R R
+
vs vo = vs vo = 0
−
L L
− −
(b) (c)
Figure 3-7 (a) Half-wave rectifier with freewheeling

diode; (b) Equivalent circuit for vs 0; (c) Equivalent
circuit for vs 0.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 82
For a positive source voltage,

• D1 is on.
• D2 is off.
• The equivalent circuit is the same as that of Fig. 3-2, shown again in Fig. 3-7b.
• The voltage across the RL load is the same as the source.
For a negative source voltage,
• D1 is off.
• D2 is on.
• The equivalent circuit is the same at that of Fig. 3-7c.
• The voltage across the RL load is zero.
Since the voltage across the RL load is the same as the source voltage when
the source is positive and is zero when the source is negative, the load voltage is
a half-wave rectified sine wave.
When the circuit is first energized, the load current is zero and cannot
change instantaneously. The current reaches periodic steady state after a few
periods (depending on the L/R time constant), which means that the current at
the end of a period is the same as the current at the beginning of the period, as
shown in Fig. 3-8. The steady-state current is usually of greater interest than the
transient that occurs when the circuit is first energized. Steady-state load,
source, and diode currents are shown in Fig. 3-9.
The Fourier series for the half-wave rectified sine wave for the voltage
across the load is
Vm Vm q
2Vm
v(t) sin (0t) a 2 cos (n0t) (3-34)
2 n2,4,6 Á (n 1)
The current in the load can be expressed as a Fourier series by using superposi-
tion, taking each frequency separately. The Fourier series method is illustrated in
Example 3-7.
io(t) Transient Steady State
Figure 3-8 Load current reaching steady state after

the circuit is energized.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 83
vo
io
0 π 2π ωt
iD1
0 π 2π ωt
iD2
0 π 2π ωt
Figure 3-9 Steady-state load voltage and current

waveforms with freewheeling diode.
EXAMPLE 3-7
Half-Wave Rectifier with Freewheeling Diode

Determine the average load voltage and current, and determine the power absorbed by the
resistor in the circuit of Fig. 3-7a, where R 2 and L 25 mH, Vm is 100 V, and the
frequency is 60 Hz.
■ Solution
The Fourier series for this half-wave rectified voltage that appears across the load is
obtained from Eq. (3-34). The average load voltage is the dc term in the Fourier series:
Vm 100
Vo 31.8 V

Average load current is
Vo 31.8
Io 15.9 A
R 2
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 84
Load power can be determined from I2rmsR, and rms current is determined from the Fourier
components of current. The amplitudes of the ac current components are determined from
phasor analysis:
Vn
In
Zn
where Zn ƒ R jn0 L ƒ ƒ 2 jn377(0.025) ƒ
The ac voltage amplitudes are determined from Eq. (3-34), resulting in
Vm 100
V1 50 V
2 2
2V
V2 2 m 21.2 V
(2 1)
2V
V4 2 m 4.24 V
(4 1)
2V
V6 2 m 1.82 V
(6 1)
The resulting Fourier terms are as follows:
n Vn (V) Zn () In (A)

0 31.8 2.00 15.9
1 50.0 9.63 5.19
2 21.2 18.96 1.12
4 4.24 37.75 0.11
6 1.82 56.58 0.03
The rms current is obtained using Eq. (2-64).
5.19 2 1.12 2 0.11 2

15.9 2 a b a b a b 16.34 A
q
Irms a Ik,rms L
A k0 C 12 12 12
Notice that the contribution to rms current from the harmonics decreases as n increases, and
higher-order terms are not significant. Power in the resistor is I2rmsR (16.34)22 534 W.
■ PSpice Solution
The circuit of Fig. 3-7a is created using VSIN, Dbreak, R, and L. The PSpice model for
Dbreak is changed to make n 0.001 to approximate an ideal diode. A transient analysis
is run with a run time of 150 ms with data saved after 100 ms to eliminate the start-up
transient from the data. A maximum step size of 10 s gives a smooth waveform.
A portion of the output file is as follows:

**** FOURIER ANALYSIS TEMPERATURE 27.000 DEG C
FOURIER COMPONENTS OF TRANSIENT RESPONSE V(OUT)
DC COMPONENT 3.183002E+01
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 85

1 6.000E+01 5.000E+01 1.000E+00 -5.804E-05 0.000E+00
2 1.200E+02 2.122E+01 4.244E-01 -9.000E+01 -9.000E+01
3 1.800E+02 5.651E-05 1.130E-06 -8.831E+01 -8.831E+01
4 2.400E+02 4.244E+00 8.488E-02 -9.000E+01 -9.000E+01
5 3.000E+02 5.699E-05 1.140E-06 -9.064E+01 -9.064E+01
6 3.600E+02 1.819E+00 3.638E-02 -9.000E+01 -9.000E+01
7 4.200E+02 5.691E-05 1.138E-06 -9.111E+01 -9.110E+01

8 4.800E+02 1.011E+00 2.021E-02 -9.000E+01 -9.000E+01
9 5.400E+02 5.687E-05 1.137E-06 -9.080E+01 -9.079E+01
FOURIER COMPONENTS OF TRANSIENT RESPONSE I(R_R1)
DC COMPONENT 1.591512E+01

1 6.000E+01 5.189E+00 1.000E+00 -7.802E+01 0.000E+00
2 1.200E+02 1.120E+00 2.158E-01 -1.739E+02 -1.788E+01
3 1.800E+02 1.963E-04 3.782E-05 -3.719E+01 1.969E+02
4 2.400E+02 1.123E-01 2.164E-02 -1.770E+02 1.351E+02
5 3.000E+02 7.524E-05 1.450E-05 6.226E+01 4.524E+02
6 3.600E+02 3.217E-02 6.200E-03 -1.781E+02 2.900E+02
7 4.200E+02 8.331E-05 1.605E-05 1.693E+02 7.154E+02
8 4.800E+02 1.345E-02 2.592E-03 -1.783E+02 4.458E+02
9 5.400E+02 5.435E-05 1.047E-05 -1.074E+02 5.948E+02
Note the close agreement between the analytically obtained Fourier terms and the
PSpice output. Average current can be obtained in Probe by entering AVG(I(R1)), yielding
15.9 A. Average power in the resistor can be obtained by entering AVG(W(R1)), yielding
P 535 W. It is important that the simulation represent steady-state periodic current for
the results to be valid.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 86
Reducing Load Current Harmonics

The average current in the RL load is a function of the applied voltage and the
resistance but not the inductance. The inductance affects only the ac terms in the
Fourier series. If the inductance is infinitely large, the impedance of the load to
ac terms in the Fourier series is infinite, and the load current is purely dc. The
load current is then
Vo V L
i o(t) L Io m : q (3-35)
R R R
A large inductor (L/R W T) with a freewheeling diode provides a means of estab-

lishing a nearly constant load current. Zero-to-peak fluctuation in load current
can be estimated as being equal to the amplitude of the first ac term in the Fourier
series. The peak-to-peak ripple is then
Io L 2I1 (3-36)
EXAMPLE 3-8
Half-Wave Rectifier with Freewheeling Diode: LR →

For the half-wave rectifier with a freewheeling diode and RL load as shown in Fig. 3-7a,
the source is 240 V rms at 60 Hz and R 8 . (a) Assume L is infinitely large. Deter-
mine the power absorbed by the load and the power factor as seen by the source. Sketch
vo, iD1, and iD2. (b) Determine the average current in each diode. (c) For a finite induc-
tance, determine L such that the peak-to-peak current is no more than 10 percent of the
average current.
■ Solution
(a) The voltage across the RL load is a half-wave rectified sine wave, which has an
average value of Vm . The load current is
Vo Vm> A2402 2 B >
i(t) Io 13.5 A L Irms
R R 8
Power in the resistor is
P (Irms)2R (13.5)28 1459 W
Source rms current is computed from

1
Is, rms (13.5)2 d(t) 9.55 A
E 2 L
0
The power factor is
P 1459
pf 0.637
Vs, rms Is, rms (240)(9.55)
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 87
vc
√2 (240) V
ic
13.5 Α
0
π 2π
13.5 Α iD1
0
iD2
13.5 Α
0
Figure 3-10 Waveforms for the half-wave rectifier with

freewheeling diode of Example 3-8 with L/R → .
Voltage and current waveforms are shown in Fig. 3-10.

(b) Each diode conducts for one-half of the time. Average current for each diode is Io 2
13.52 6.75 A.
(c) The value of inductance required to limit the variation in load current to 10 percent
can be approximated from the fundamental frequency of the Fourier series. The
voltage input to the load for n 1 in Eq. (3-34) has amplitude Vm 2 12(240)2
170 V the peak-to-peak current must be limited to
Io (0.10)(Io) (0.10)(13.5) 1.35 A
which corresponds to an amplitude of 1.352 0.675 A. The load impedance at the

fundamental frequency must then be
V1 170
Z1 251 Æ
I1 0.675
The load impedance is
Z1 251 ƒ R jL ƒ ƒ 8 j377L ƒ
Since the 8- resistance is negligible compared to the total impedance, the
inductance can be approximated as
Z1 251
L L 0.67 H
377
The inductance will have to be slightly larger than 0.67 H because Fourier terms
higher than n 1 were neglected in this estimate.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 88
3.8 HALF-WAVE RECTIFIER WITH A CAPACITOR

FILTER
Creating a DC Voltage from an AC Source
A common application of rectifier circuits is to convert an ac voltage input to a
dc voltage output. The half-wave rectifier of Fig. 3-11a has a parallel RC load.
The purpose of the capacitor is to reduce the variation in the output voltage, mak-
ing it more like dc. The resistance may represent an external load, and the capac-
itor may be a filter which is part of the rectifier circuit.
Assuming the capacitor is initially uncharged and the circuit is energized at
t 0, the diode becomes forward-biased as the source becomes positive. With
the diode on, the output voltage is the same as the source voltage, and the capac-
itor charges. The capacitor is charged to Vm when the input voltage reaches its
positive peak at t /2.
As the source decreases after t /2, the capacitor discharges into the load
resistor. At some point, the voltage of the source becomes less than the output
voltage, reverse-biasing the diode and isolating the load from the source. The out-
put voltage is a decaying exponential with time constant RC while the diode is off.
The point when the diode turns off is determined by comparing the rates of
change of the source and the capacitor voltages. The diode turns off when the
iC iR +
iD
+ vo
vs = Vm sin(ωt) C R
−
−
(a)
Vm
Vθ
vo ΔVo
vs
pθ 2π 2π + α
2
α
vs
(b)
Figure 3-11 (a) Half-wave rectifier with RC load; (b) Input

and output voltages.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 89
3.8 Half-Wave Rectifier With a Capacitor Filter 89
downward rate of change of the source exceeds that permitted by the time con-
stant of the RC load. The angle t is the point when the diode turns off in
Fig. 3-11b. The output voltage is described by
Vm sin t diode on
vo(t) c (3-37)
Ve (t )>RC diode off
where V Vm sin (3-38)
The slopes of these functions are

d
[V sin (t)] Vm cos (t) (3-39)
d(t) m
and
AVm sin e (t )>RCB Vm sin a

d 1
b e (t )>RC (3-40)
d(t) RC
At t , the slopes of the voltage functions are equal:
Vm sin ( )>RC Vm sin

Vm cos a be
RC RC
Vm cos 1

Vm sin RC
1 1

tan RC
Solving for and expressing so it is in the proper quadrant, we have
tan 1( RC) tan 1(RC) (3-41)
In practical circuits where the time constant is large,

L and Vm sin L Vm (3-42)
2
When the source voltage comes back up to the value of the output voltage in
the next period, the diode becomes forward-biased, and the output again is the
same as the source voltage. The angle at which the diode turns on in the second
period, t 2 , is the point when the sinusoidal source reaches the same
value as the decaying exponential output:
Vm sin (2 ) (Vm sin )e (2 )>RC

har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 90
or
sin (sin )e (2 )>RC 0 (3-43)
Equation (3-43) must be solved numerically for .

The current in the resistor is calculated from iR vo R. The current in the
capacitor is calculated from
dvo(t)
i C (t) C
dt
which can also be expressed, using t as the variable, as
dvo(t)
i C (t) C
d(t)
Using vo from Eq. (3-37),
Vm sin (t )>RC

a be for t 2 (diode off)
R
i C (t) d (3-44)
CVm cos (t) for 2 t 2 (diode on)
The source current, which is the same as the diode current, is

iS iD iR iC (3-45)
The average capacitor current is zero, so the average diode current is the same
as the average load current. Since the diode is on for a short time in each cycle,
the peak diode current is generally much larger than the average diode current.
Peak capacitor current occurs when the diode turns on at t 2 . From
Eq. (3-44),
IC, peak CVm cos(2 ) CVm cos (3-46)
Resistor current at t 2 + is obtained from Eq. (3-37).
Vm sin(2t ) Vm sin
i R (2t ) (3-47)
R R
Peak diode current is
Vm sin sin
ID, peak CVm cos Vm aC cos b (3-48)
R R
The effectiveness of the capacitor filter is determined by the variation in out-

put voltage. This may be expressed as the difference between the maximum and
minimum output voltage, which is the peak-to-peak ripple voltage. For the half-
wave rectifier of Fig. 3-11a, the maximum output voltage is Vm. The minimum
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 91
output voltage occurs at t 2 + , which can be computed from Vm sin . The

peak-to-peak ripple for the circuit of Fig. 3-11a is expressed as
Vo Vm Vm sin Vm(1 sin ) (3-49)
In circuits where the capacitor is selected to provide for a nearly constant dc

output voltage, the RC time constant is large compared to the period of the sine
wave, and Eq. (3-42) applies. Moreover, the diode turns on close to the peak of
the sine wave when L /2. The change in output voltage when the diode is off
is described in Eq. (3-37). In Eq. (3-37), if V L Vm and L /2, then Eq. (3-37)
evaluated at /2 is
vo(2 ) Vme (2>2 >2)RC Vme 2>RC
The ripple voltage can then be approximated as
Vo L Vm Vme 2>RC Vm A1 e 2>RCB (3-50)
Furthermore, the exponential in the above equation can be approximated by the
series expansion:
2
e 2>RC L 1
RC
Substituting for the exponential in Eq. (3-50), the peak-to-peak ripple is approx-
imately
2 V
Vo L Vm a b m (3-51)
RC f RC
The output voltage ripple is reduced by increasing the filter capacitor C. As

C increases, the conduction interval for the diode decreases. Therefore, increas-
ing the capacitance to reduce the output voltage ripple results in a larger peak
diode current.
EXAMPLE 3-9
Half-Wave Rectifier with RC Load

The half-wave rectifier of Fig. 3-11a has a 120-V rms source at 60 Hz, R 500 , and
C 100 F. Determine (a) an expression for output voltage, (b) the peak-to-peak volt-
age variation on the output, (c) an expression for capacitor current, (d) the peak diode cur-
rent, and (e) the value of C such that Vo is 1 percent of Vm.
■ Solution
Vm 12022 169.7 V
RC (260)(500)(10) 6 18.85 rad
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 92
The angle is determined from Eq. (3-41).

tan 1(18.85) 1.62 rad 93°
Vm sin 169.5 V
The angle is determined from the numerical solution of Eq. (3-43).
sin sin (1.62)e (2 1.62>18.85) 0

yielding
0.843 rad 48°
(a) Output voltage is expressed from Eq. (3-37).
169.7 sin (t) 2 t 2
vo(t) c
169.5e (t 1.62)>18.85 t 2
(b) Peak-to-peak output voltage is described by Eq. (3-49).
Vo Vm(1 sin ) 169.7(1 sin 0.843) 43 V
(c) The capacitor current is determined from Eq. (3-44).
0.339e (t 1.62)>18.85 A t 2
i C(t) c
6.4 cos (t) A 2 t 2
(d) Peak diode current is determined from Eq. (3-48).

sin 8.43
ID, peak 12(120)c377(10) 4 cos 0.843 d
500
4.26 0.34 4.50 A
(e) For Vo 0.01Vm, Eq. (3-51) can be used.
Vm Vm 1
C L F = 3333 F
f R(Vo) (60)(500)(0.01Vm) 300
Note that peak diode current can be determined from Eq. (3-48) using an estimate of
from Eq. (3-49).
Vo 1
L sin 1 a 1 b sin 1 a 1 b 81.9°
Vm f RC
From Eq. (3-48), peak diode current is 30.4 A.
■ PSpice Solution
A PSpice circuit is created for Fig. 3-11a using VSIN, Dbreak, R, and C. The diode
Dbreak used in this analysis causes the results to differ slightly from the analytic solution
based on the ideal diode. The diode drop causes the maximum output voltage to be
slightly less than that of the source.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 93
INPUT AND OUTPUT VOLTAGES

200 V
0V
-200 V
V(1) V(2)
8.0 A
DIODE CURRENT
4.0 A
-0.0 A
0s 10 ms 20 ms 30 ms 40 ms 50 ms
1(D) Time
Figure 3-12 Probe output for Example 3-9.
The Probe output is shown in Fig. 3-12. Angles and are determined directly by
first modifying the x-variable to indicate degrees (x-variable time*60*360) and then
using the cursor option. The restrict data option is used to compute quantities based on
steady-state values (16.67 to 50 ms). Steady state is characterized by waveforms begin-
ning and ending a period at the same values. Note that the peak diode current is largest in
the first period because the capacitor is initially uncharged.
■ Results from the Probe Cursor
Quantity Result
360 408 ( 48 )
98.5
Vo max 168.9 V
Vo min 126 V
Vo 42.9 V
ID,peak 4.42 A steady state; 6.36 A first period
IC,peak 4.12 A steady state; 6.39 A first period
■ Results after Restricting the Data to Steady State
Quantity Probe Expression Result

ID, avg AVG(I(D1)) 0.295 A
IC, rms RMS(I(C1)) 0.905 A
IR, avg AVG(W(R1)) 43.8 W
Ps AVG(W(Vs)) 44.1 W
PD AVG(W(D1)) 345 mW
In this example, the ripple, or variation in output voltage, is very large, and the
capacitor is not an effective filter. In many applications, it is desirable to produce an
output that is closer to dc. This requires the time constant RC to be large compared to
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 94
the period of the input voltage, resulting in little decay of the output voltage. For an
effective filter capacitor, the output voltage is essentially the same as the peak voltage
of the input.
3.9 THE CONTROLLED HALF-WAVE RECTIFIER

The half-wave rectifiers analyzed previously in this chapter are classified as
uncontrolled rectifiers. Once the source and load parameters are established, the
dc level of the output and the power transferred to the load are fixed quantities.
A way to control the output of a half-wave rectifier is to use an SCR1 instead
of a diode. Figure 3-13a shows a basic controlled half-wave rectifier with a resis-
tive load. Two conditions must be met before the SCR can conduct:
1. The SCR must be forward-biased (vSCR 0).
2. A current must be applied to the gate of the SCR.
Unlike the diode, the SCR will not begin to conduct as soon as the source becomes
positive. Conduction is delayed until a gate current is applied, which is the basis for
using the SCR as a means of control. Once the SCR is conducting, the gate current
can be removed and the SCR remains on until the current goes to zero.
Resistive Load
Figure 3-13b shows the voltage waveforms for a controlled half-wave rectifier
with a resistive load. A gate signal is applied to the SCR at t , where is the
delay angle. The average (dc) voltage across the load resistor in Fig. 3-13a is

1 V
Vo Vm sin (t) d(t) m (1 cos ) (3-52)
2 L

2
The power absorbed by the resistor is V2rms/R, where the rms voltage across
the resistor is computed from
2
1
Vrms v 2o(t)d(t)
E 2 L
0

1
[V sin (t)]2 d(t)
E 2 L m

Vm sin (2 )
1
2A 2 (3-53)
1
Switching with other controlled turn-on devices such as transistors or IGBTs can be used to control the
output of a converter.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 95
3.9 The Controlled Half-Wave Rectifier 95
+ vSCR −
iG +
+
vs = Vm sin(ωt) Gate R vo
Control
− −
(a)
vs
ωt
vo
a ωt
vSCR
a ωt
(b)
Figure 3-13 (a) A basic controlled rectifier; (b) Voltage

waveforms.
EXAMPLE 3-10
Controlled Half-Wave Rectifier with Resistive Load

Design a circuit to produce an average voltage of 40 V across a 100- load resistor from
a 120-V rms 60-Hz ac source. Determine the power absorbed by the resistance and the
power factor.
■ Solution
If an uncontrolled half-wave rectifier is used, the average voltage will be Vm/
120 12/ 54 V. Some means of reducing the average resistor voltage to the design
specification of 40 V must be found. A series resistance or inductance could be added to
an uncontrolled rectifier, or a controlled rectifier could be used. The controlled rectifier of
Fig. 3-13a has the advantage of not altering the load or introducing losses, so it is selected
for this application.
Equation (3-52) is rearranged to determine the required delay angle:
2
cos 1 cVo a b 1d
Vm
2
cos 1 e 40c d 1 f 61.2° 1.07 rad
12(120)
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 96
Equation (3-53) gives

22(120) 1.07 sin [2(1.07)]
Vrms 1 75.6 V
2 A 2
Load power is
V 2rms (75.6)2
PR 57.1 W
R 100
The power factor of the circuit is
P P 57.1
pf 0.63
S VS, rms I rms (120)(75.6>100)
RL Load
A controlled half-wave rectifier with an RL load is shown in Fig. 3-14a. The
analysis of this circuit is similar to that of the uncontrolled rectifier. The current
is the sum of the forced and natural responses, and Eq. (3-9) applies:
Vm
i(t) i f (t) i n(t) sin (t ) Ae t>
Z
The constant A is determined from the initial condition i() 0:
Vm
i( ) 0 sin ( ) Ae >
Z
(3-54)
sin ( ) d e >
Vm
A c
Z
Substituting for A and simplifying,
C sin (t ) sin ( )e( t)>

D for t
Vm
Z
i(t) d (3-55)
0 otherwise
The extinction angle is defined as the angle at which the current returns to zero,
as in the case of the uncontrolled rectifier. When t ,
C sin ( ) sin ( )e( )>

D
Vm
i( ) 0 (3-56)
Z
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 97
vSCR
+ −
+
i +
+ vR
vs vo −
− +
vL
− −
(a)
vR
0 ωt
α π β 2π 2π + α
vs
vL
0 ωt
α β 2π + α
vSCR
0 ωt
α β 2π 2π + α
(b)
Figure 3-14 (a) Controlled half-wave rectifier with RL load;

(b) Voltage waveforms.
which must be solved numerically for . The angle is called the conduc-
tion angle . Figure 3-14b shows the voltage waveforms.
The average (dc) output voltage is

1 V
Vo Vm sin (t)d(t) m (cos cos ) (3-57)
2 L 2

The average current is computed from

1
Io i(t)d(t) (3-58)
2 L

where i(t) is defined in Eq. (3-55). Power absorbed by the load is I2rmsR, where
the rms current is computed from

1
Irms i 2(t)d(t) (3-59)
E 2 L

har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 98
EXAMPLE 3-11
Controlled Half-Wave Rectifier with RL Load

For the circuit of Fig. 3-14a, the source is 120 V rms at 60 Hz, R 20 , L 0.04 H,
and the delay angle is 45 . Determine (a) an expression for i(t), (b) the average current,
(c) the power absorbed by the load, and (d) the power factor.
■ Solution
(a) From the parameters given,
Vm 120 12 169.7 V
Z [R2 (L)2]0.5 [202 (377*0.04)2]0.5 25.0
tan 1(LR) tan 1(377*0.04)20) 0.646 rad

LR 377*0.04/20 0.754
45 0.785 rad
Substituting the preceding quantities into Eq. (3-55), current is expressed as
i(t) 6.78 sin (t 0.646) 2.67e t>0.754 A for t
The preceding equation is valid from to , where is found numerically by
setting the equation to zero and solving for t, with the result 3.79 rad (217 ).
The conduction angle is 3.79 0.785 3.01 rad 172 .
(b) Average current is determined from Eq. (3-58).
3.79
C 6.78 sin (t 0.646) 2.67e t>0.754 D d(t) 2.19 A

1
Io
2 L
0.785
(c) The power absorbed by the load is computed from I2rmsR, where
3.79
C 6.78 sin (t 0.646) 2.67e t>0.754 D d(t) 3.26 A

1 2
Irms
E 2 L
0.785
yielding
P I 2rmsR (3.26)2(20) 213 W
(d) The power factor is
P 213
pf 0.54
S (120)(3.26)
RL-Source Load
A controlled rectifier with a series resistance, inductance, and dc source is shown
in Fig. 3-15. The analysis of this circuit is very similar to that of the uncontrolled
half-wave rectifier discussed earlier in this chapter. The major difference is that
for the uncontrolled rectifier, conduction begins as soon as the source voltage
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 99
R L
i
+ +
Vm sin(ωt) Vdc
− −
Figure 3-15 Controlled rectifier with RL-source load.
reaches the level of the dc voltage. For the controlled rectifier, conduction begins
when a gate signal is applied to the SCR, provided the SCR is forward-biased.
Thus, the gate signal may be applied at any time that the ac source is larger than
the dc source:
Vdc
min sin 1 a b (3-60)
Vm
Current is expressed as in Eq. (3-22), with specified within the allowable
range:
Vm V
sin (t ) dc Ae t>
for t
Z R
i(t)d (3-61)
0 otherwise
where A is determined from Eq. (3-61):

Vm
A c
Vdc >
sin( ) de
Z R
EXAMPLE 3-12
Controlled Rectifier with RL-Source Load

The controlled half-wave rectifier of Fig. 3-15 has an ac input of 120 V rms at 60 Hz,
R 2 , L 20 mH, and Vdc 100 V. The delay angle is 45 . Determine (a) an expres-
sion for the current, (b) the power absorbed by the resistor, and (c) the power absorbed by
the dc source in the load.
■ Solution:
Vm 120 12 169.7 V
Z [R2 (L)2]0.5 [22 (377*0.02)2]0.5 7.80
tan 1(LR) tan 1(377*0.02)2) 1.312 rad

LR 377*0.02/2 3.77
45 0.785 rad
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 100
(a) First, use Eq. (3-60) to determine if 45 is allowable. The minimum delay angle is
100
min sin 1 a b 36°
12012
which indicates that 45 is allowable. Equation (3-61) becomes
i(t) 21.8 sin (t 1.312) 50 75.0e t>3.77 A for 0.785t3.37 rad
where the extinction angle is found numerically to be 3.37 rad from the equation
i() 0.
(b) Power absorbed by the resistor is I2rmsR, where Irms is computed from Eq. (3-59)
using the preceding expression for i(t).

1
Irms i 2(t)d(t) 3.90 A
E 2 L

P (3.90) 2 (2) 30.4 W
(c) Power absorbed by the dc source is IoVdc, where Io is computed from Eq. (3-58).

1
Io i(t)d(t) 2.19 A
2 L

Pdc IoVdc (2.19)(100) 219 W
3.10 PSPICE SOLUTIONS FOR CONTROLLED

RECTIFIERS
Modeling the SCR in PSpice
To simulate the controlled half-wave rectifier in PSpice, a model for the SCR
must be selected. An SCR model available in a device library can be utilized in
the simulation of a controlled half-wave rectifier. A circuit for Example
3-10 using the 2N1595 SCR in the PSpice demo version library of devices is
shown in Fig. 3-16a. An alternative model for the SCR is a voltage-controlled
switch and a diode as described in Chap. 1. The switch controls when the SCR
begins to conduct, and the diode allows current in only one direction. The switch
must be closed for at least the conduction angle of the current. An advantage of
using this SCR model is that the device can be made ideal. The major disadvan-
tage of the model is that the switch control must keep the switch closed for the
entire conduction period and open the switch before the source becomes positive
again. A circuit for the circuit in Example 3-11 is shown in Fig. 3-16b.
EXAMPLE 3-13
Controlled Half-Wave Rectifier Design Using PSpice

A load consists of a series-connected resistance, inductance, and dc voltage source with
R 2 , L 20 mH, and Vdc 100 V. Design a circuit that will deliver 150 W to the dc
voltage source from a 120-V rms 60-Hz ac source.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 101
3.10 PSpice Solutions for Controlled Rectifiers 101
Controlled Half-wave Rectifier with SCR 2N1595

Change the SCR model for a higher voltage rating
Source RL
SCR PARAMETERS:
2 alpha = 45
VOFF = 0 Vs 2N1595 freq = 60
+
VAMPL = 170 RG TD = {alpha/360/freq}
FREQ = 60 − V1 = 0
1k + V2 = 5
Vcontrol − TF = 1n
TR = 1n
0 PW = 1m
PER = {1/freq}
(a)
CONTROLLED HALFWAVE RECTIFIER

switch and diode for SCR
SCR Model
Source Dbreak R1
out
Vsource + 20
VOFF = 0 + Control + − Sbreak 1
VAMPL = 170
− + L1
FREQ = 60
Vcontrol 40m
− 2
0
V1 = 0
PARAMETERS:
V2 = 5
Alpha = 45
TD = {Alpha/360/60}
Freq = 60
TR = 1n
TF = 1n
PW = {1/Freq-DLAY*1.1}
PER = {1/Freq}
(b)
Figure 3-16 (a) A controlled half-wave rectifier using an SCR from the library
of devices; (b) An SCR model using a voltage-controlled switch and a diode.
■ Solution
Power in the dc source of 150 W requires an average load current of 150 W/100 V 1.5 A.
An uncontrolled rectifier with this source and load will have an average current of 2.25 A
and an average power in the dc source of 225 W, as was computed in Example 3-5 pre-
viously. A means of limiting the average current to 1.5 A must be found. Options include
the addition of series resistance or inductance. Another option that is chosen for this
application is the controlled half-wave rectifier of Fig. 3-15. The power delivered to the
load components is determined by the delay angle . Since there is no closed-form solu-
tion for , a trial-and-error iterative method must be used. A PSpice simulation that
includes a parametric sweep is used to try several values of alpha. The parametric sweep
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 102
CONTROLLED HALFWAVE RECTIFIER

parametric sweep for alpha
SCR Model
Dbreak R1 L1
SOURCE out 1 2
2 20m
+ +
−
VOFF = 0 Vs + Sbreak
+ Control
−
+ 100 Vdc
VAMPL = {120*sqrt(2)} −
− + −
FREQ = 60 Vcontrol
−
V1 = 0 0
PARAMETERS:
V2 = 5
Alpha = 50
TD = {ALPHA/360/60}
Freq = 60
TR = 1n
TF = 1n
PW = {1/Freq-DLAY*11}
PER = {1/Freq}
(a)
400 W
PARAMETRIC SWEEP FOR ALPHA
200 W
(16.670m, 147.531)
70 deg
0W
0s 4 ms 8 ms 12 ms 16 ms 20 ms 22 ms
AVG {W(Vdc)}
Time
(b)
Figure 3-17 (a) PSpice circuit for Example 3-13; (b) Probe output for showing a
family of curves for different delay angles.
is established in the Simulation Setting menu (see Example 3-4). A PSpice circuit is
shown in Fig. 3-17a.
When the expression AVG(W(Vdc)) is entered, Probe produces a family of curves
representing the results for a number of values of , as shown in Fig. 3-17b. An of 70 ,
which results in about 148 W delivered to the load, is the approximate solution.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 103
3.11 Commutation 103
The following results are obtained from Probe for 70 :
Quantity Expression Result

DC source power AVG(W(Vdc)) 148 W (design
objective of 150 W)
RMS current RMS(I(R1)) 2.87 A
Resistor power AVG(W(R1)) 16.5 W
Source apparent power RMS(V(SOURCE))*RMS(I(Vs)) 344 VA
Source average power AVG(W(Vs)) 166 W
Power factor (P/S) 166/344 0.48
3.11 COMMUTATION
The Effect of Source Inductance
The preceding discussion on half-wave rectifiers assumed an ideal source. In practi-
cal circuits, the source has an equivalent impedance which is predominantly induc-
tive reactance. For the single-diode half-wave rectifiers of Figs. 3-1 and 3-2, the
nonideal circuit is analyzed by including the source inductance with the load ele-
ments. However, the source inductance causes a fundamental change in circuit
behavior for circuits like the half-wave rectifier with a freewheeling diode.
A half-wave rectifier with a freewheeling diode and source inductance Ls is
shown in Fig. 3-18a. Assume that the load inductance is very large, making the
load current constant. At t 0 , the load current is IL, D1 is off, and D2 is on.
As the source voltage becomes positive, D1 turns on, but the source current
does not instantly equal the load current because of Ls. Consequently, D2 must
remain on while the current in Ls and D1 increases to that of the load. The inter-
val when both D1 and D2 are on is called the commutation time or commutation
angle. Commutation is the process of turning off an electronic switch, which
usually involves transferring the load current from one switch to another.2
When both D1 and D2 are on, the voltage across Ls is
vLs Vm sin(t) (3-62)
and current in Ls and the source is
t t
1 1
is vLs d(t) i s (0) V sin (t)d(t) 0
L s L L s L m
0 0 (3-63)
V
i s m (1 cos t)
L s
2
Commutation in this case is an example of natural commutation or line commutation, where the
change in instantaneous line voltage results in a device turning off. Other applications may use forced
commutation, where current in a device such as a thyristor is forced to zero by additional circuitry. Load
commutation makes use of inherent oscillating currents produced by the load to turn a device off.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 104
+ vLs − D1 iD1 = is
+
Ls IL
iD2
+
Vm sin(ωt) D2 vo
−
−
(a)
i D1
Io
0 ωt
i D2
IL
0 ωt
u
vo
Vm
0 ωt
u π 2π 2π + u
(b)
Figure 3-18 (a) Half-wave rectifier with freewheeling diode and source
inductance; (b) Diode currents and load voltage showing the effects of
Commutation.
Current in D2 is
Vm
i D2 IL i s IL (1 cos t)
L s
The current in D2 starts at IL and decreases to zero. Letting the angle at which the
current reaches zero be t u,
Vm
i D2(u) IL (1 cos u) 0
L s
Solving for u,
ILL s IX
u cos 1 a1 b cos 1 a 1 L s b (3-64)
Vm Vm
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 105
3.12 Summary 105
where Xs Ls is the reactance of the source. Figure 3-18b shows the effect of
the source reactance on the diode currents. The commutation from D1 to D2 is
analyzed similarly, yielding an identical result for the commutation angle u.
The commutation angle affects the voltage across the load. Since the voltage
across the load is zero when D2 is conducting, the load voltage remains at zero
through the commutation angle, as shown in Fig. 3-17b. Recall that the load volt-
age is a half-wave rectified sinusoid when the source is ideal.
Average load voltage is

1
Vo V sin (t)d(t)
2 L m
u
Vm Vm
[ cos (t)] ƒ u (1 cos u)
2 2
Using u from Eq. (3-64),
Vm IX
Vo a1 L s b (3-65)
2Vm
Recall that the average of a half-wave rectified sine wave is Vm. Source reac-
tance thus reduces average load voltage.
3.12 Summary
• A rectifier converts ac to dc. Power transfer is from the ac source to the dc load.
• The half-wave rectifier with a resistive load has an average load voltage of Vm /
and an average load current of Vm /R.
• The current in a half-wave rectifier with an RL load contains a natural and a forced
response, resulting in
C sin (t ) sin ()e t>

D
Vm
for 0 t
Z
i(t) d
0 for t 2
L
tan 1 a b
L
where Z 2R2 (L)2, and

R R
The diode remains on as long as the current is positive. Power in the RL load is I2rmsR.
• A half-wave rectifier with an RL-source load does not begin to conduct until the ac
2
source reaches the dc voltage in the load. Power in the resistance is Irms R, and
power absorbed by the dc source is IoVdc, where Io is the average load current. The
load current is expressed as
Vm V
sin (t ) dc Ae t>
for t
Z R
i(t) d
0 otherwise
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 106
where
A c
Vm Vdc >
sin ( ) de
Z R
• A freewheeling diode forces the voltage across an RL load to be a half-wave
rectified sine wave. The load current can be analyzed using Fourier analysis.
A large load inductance results in a nearly constant load current.
• A large filter capacitor across a resistive load makes the load voltage nearly
constant. Average diode current must be the same as average load current, making
the peak diode current large.
• An SCR in place of the diode in a half-wave rectifier provides a means of
controlling output current and voltage.
• PSpice simulation is an effective way of analyzing circuit performance. The
parametric sweep in PSpice allows several values of a circuit parameter to be tried
and is an aid in circuit design.
3.13 Bibliography
S. B. Dewan and A. Straughen, Power Semiconductor Circuits, Wiley,
New York, 1975.
Y.-S. Lee and M. H. L. Chow, Power Electronics Handbook, edited by M. H. Rashid,
Academic Press, New York, 2001, Chapter 10.
N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters,
Applications, and Design, 3d ed., Wiley, New York, 2003.
M. H. Rashid, Power Electronics: Circuits, Devices, and Systems, 3d ed., Prentice-Hall,
Upper Saddle River, NJ., 2004.
R. Shaffer, Fundamentals of Power Electronics with MATLAB, Charles River Media,
Boston, Mass., 2007.
B. Wu, High-Power Converters and AC Drives, Wiley, New York, 2006.
Problems
Half-Wave Rectifier with Resistive Load
3-1. The half-wave rectifier circuit of Fig. 3-1a has vs(t) 170 sin(377t) V and a load
resistance R 15 . Determine (a) the average load current, (b) the rms load
current, (c) the power absorbed by the load, (d) the apparent power supplied by
the source, and (e) the power factor of the circuit.
3-2. The half-wave rectifier circuit of Fig. 3-1a has a transformer inserted between the
source and the remainder of the circuit. The source is 240 V rms at 60 Hz, and
the load resistor is 20 . (a) Determine the required turns ratio of the transformer
such that the average load current is 12 A. (b) Determine the average current in
the primary winding of the transformer.
3-3. For a half-wave rectifier with a resistive load, (a) show that the power factor is 1/ 12
and (b) determine the displacement power factor and the distortion factor as defined
in Chap. 2. The Fourier series for the half-wave rectified voltage is given in Eq. (3-34).
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 107
Problems 107
Half-Wave Rectifier with RL Load

3-4. A half-wave rectifier has a source of 120 V rms at 60 Hz and an RL load with
R 12 and L 12 mH. Determine (a) an expression for load current, (b) the
average current, (c) the power absorbed by the resistor, and (d) the power factor.
(e) Use PSpice to simulate the circuit. Use the default diode model and compare
your PSpice results with analytical results.
3-7. The inductor in Fig. 3-2a represents an electromagnet modeled as a 0.1-H
inductance. The source is 240 V at 60 Hz. Use PSpice to determine the value of a
series resistance such that the average current is 2.0 A.
Half-Wave Rectifier with RL-Source Load

3-8. A half-wave rectifier of Fig. 3-5a has a 240 V rms, 60 Hz ac source. The load is
a series inductance, resistance, and dc source, with L 75 mH, R 10 , and
Vdc 100 V. Determine (a) the power absorbed by the dc voltage source, (b) the
power absorbed by the resistance, and (c) the power factor.
3-9. A half-wave rectifier of Fig. 3-5a has a 120 V rms, 60 Hz ac source. The load is
a series inductance, resistance, and dc source, with L 120 mH, R 12 , and
Vdc 48 V. Determine (a) the power absorbed by the dc voltage source, (b) the
power absorbed by the resistance, and (c) the power factor.
3-10. A half-wave rectifier of Fig. 3-6 has a 120 V rms, 60 Hz ac source. The load is
a series inductance and dc voltage with L 100 mH and Vdc 48 V. Determine
the power absorbed by the dc voltage source.
3-11. A half-wave rectifier with a series inductor-source load has an ac source of 240 V rms,
60 Hz. The dc source is 96 V. Use PSpice to determine the value of inductance
which results in 150 W absorbed by the dc source. Use the default diode model.
3-12. A half-wave rectifier with a series inductor and dc source has an ac source of
120 V rms, 60 Hz. The dc source is 24 V. Use PSpice to determine the value of
inductance which results in 50 W absorbed by the dc source. Use the default diode.
Freewheeling Diode
3-13. The half-wave rectifier with a freewheeling diode (Fig. 3-7a) has R 12 and
L 60 mH. The source is 120 V rms at 60 Hz. (a) From the Fourier series of the
half-wave rectified sine wave that appears across the load, determine the dc
component of the current. (b) Determine the amplitudes of the first four nonzero
ac terms in the Fourier series. Comment on the results.
3-14. In Example 3-8, the inductance required to limit the peak-to-peak ripple in load
current was estimated by using the first ac term in the Fourier series. Use PSpice
to determine the peak-to-peak ripple with this inductance, and compare it to the
estimate. Use the ideal diode model (n 0.001).
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 108
3-15. The half-wave rectifier with a freewheeling diode (Fig. 3-7a) has R 4 and a
source with Vm 50 V at 60 Hz. (a) Determine a value of L such that the amplitude
of the first ac current term in the Fourier series is less than 5 percent of the dc
current. (b) Verify your results with PSpice, and determine the peak-to-peak current.
3-16. The circuit of Fig. P3-16 is similar to the circuit of Fig. 3-7a except that a dc source
has been added to the load. The circuit has vs(t) 170 sin(377t) V, R 10 ,
and Vdc 24 V. From the Fourier series, (a) determine the value of L such that the
peak-to-peak variation in load current is no more than 1 A. (b) Determine the
power absorbed by the dc source. (c) Determine the power absorbed by the resistor.
R L
io +
+
vs(t) Vdc
−
−
Figure P3-16
Half-Wave Rectifier with a Filter Capacitor

3-17. A half-wave rectifier with a capacitor filter has Vm 200 V, R 1 k, C 1000 F,
and 377. (a) Determine the ratio of the RC time constant to the period of the
input sine wave. What is the significance of this ratio? (b) Determine the peak-to-
peak ripple voltage using the exact equations. (c) Determine the ripple using the
approximate formula in Eq. (3-51).
3-18. Repeat Prob. 3-17 with (a) R 100 and (b) R 10 . Comment on the results.
3-19. A half-wave rectifier with a 1-k load has a parallel capacitor. The source is
120 V rms, 60 Hz. Determine the peak-to-peak ripple of the output voltage when
the capacitor is (a) 4000 F and (b) 20 F. Is the approximation of Eq. (3-51)
reasonable in each case?
3-20. Repeat Prob. 3-19 with R 500 .
3-21. A half-wave rectifier has a 120 V rms, 60 Hz ac source. The load is 750 .
Determine the value of a filter capacitor to keep the peak-to-peak ripple across
the load to less than 2 V. Determine the average and peak values of diode current.
3-22. A half-wave rectifier has a 120 V rms 60 Hz ac source. The load is 50 W.
(a) Determine the value of a filter capacitor to keep the peak-to-peak ripple across the
load to less than 1.5 V. (b) Determine the average and peak values of diode current.
Controlled Half-Wave Rectifier

3-23. Show that the controlled half-wave rectifier with a resistive load in Fig. 3-13a
has a power factor of
1 sin (2 )
pf
A 2 2 4
3-24. For the controlled half-wave rectifier with resistive load, the source is 120 V rms
at 60 Hz. The resistance is 100 , and the delay angle is 45 . (a) Determine the
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 109
Problems 109
average voltage across the resistor. (b) Determine the power absorbed by the
resistor. (c) Determine the power factor as seen by the source.
3-25. A controlled half-wave rectifier has an ac source of 240 V rms at 60 Hz. The load is a
30- resistor. (a) Determine the delay angle such that the average load current is
2.5 A. (b) Determine the power absorbed by the load. (c) Determine the power factor.
3-26. A controlled half-wave rectifier has a 120 V rms 60 Hz ac source. The series RL
load has R 25 and L 50 mH. The delay angle is 30 . Determine (a) an
expression for load current, (b) the average load current, and (c) the power
3-27. A controlled half-wave rectifier has a 120 V rms 60 Hz ac source. The series RL
load has R 40 and L 75 mH. The delay angle is 60 . Determine (a) an
expression for load current, (b) the average load current, and (c) the power
3-28. A controlled half-wave rectifier has an RL load with R 20 and L 40 mH.
The source is 120 V rms at 60 Hz. Use PSpice to determine the delay angle
required to produce an average current of 2.0 A in the load. Use the default diode
in the simulation.
3-29. A controlled half-wave rectifier has an RL load with R 16 and L 60 mH.
The source is 120 V rms at 60 Hz. Use PSpice to determine the delay angle
required to produce an average current of 1.8 A in the load. Use the default diode
in the simulation.
3-30. A controlled half-wave rectifier has a 120 V, 60 Hz ac source. The load is a series
inductance, resistance, and dc source, with L 100 mH, R 12 , and Vdc 48 V.
The delay angle is 50 . Determine (a) the power absorbed by the dc voltage source,
(b) the power absorbed by the resistance, and (c) the power factor.
3-31. A controlled half-wave rectifier has a 240 V rms 60 Hz ac source. The load is a
series resistance, inductance, and dc source with R 100 , L 150 mH, and
Vdc 96 V. The delay angle is 60 . Determine (a) the power absorbed by the dc
voltage source, (b) the power absorbed by the resistance, and (c) the power factor.
3-32. Use PSpice to determine the delay angle required such that the dc source in
Prob. 3-31 absorbs 35 W.
3-33. A controlled half-wave rectifier has a series resistance, inductance, and dc voltage
source with R 2 , L 75 mH, and Vdc 48 V. The source is 120 V rms at 60 Hz.
The delay angle is 50 . Determine (a) an expression for load current, (b) the power
absorbed by the dc voltage source, and (c) the power absorbed by the resistor.
3-34. Use PSpice to determine the delay angle required such that the dc source in Prob.
3-33 absorbs 50 W.
3-35. Develop an expression for current in a controlled half-wave rectifier circuit that
has a load consisting of a series inductance L and dc voltage Vdc. The source is
vs Vm sin t, and the delay angle is . (a) Determine the average current if
Vm 100 V, L 35 mH, Vdc 24 V, 260 rad/s, and 75 . (b) Verify
your result with PSpice.
3-36. A controlled half-wave rectifier has an RL load. A freewheeling diode is placed in
parallel with the load. The inductance is large enough to consider the load current
to be constant. Determine the load current as a function of the delay angle alpha.
Sketch the current in the SCR and the freewheeling diode. Sketch the voltage
across the load.
har80679_ch03_065-110.qxd 12/17/09 2:09 PM Page 110
Commutation
3-37. The half-wave rectifier with freewheeling diode of Fig. 3-18a has a 120 V rms ac
source that has an inductance of 1.5 mH. The load current is a constant 5 A.
Determine the commutation angle and the average output voltage. Use PSpice to
verify your results. Use ideal diodes in the simulation. Verify that the
commutation angle for D1 to D2 is the same as for D2 to D1.
source which has an inductance of 10 mH. The load is a series resistance-inductance
with R 20 and L 500 mH. Use PSpice to determine (a) the steady-state
average load current, (b) the average load voltage, and (c) the commutation angle.
Use the default diode in the simulation. Comment on the results.
source which has an inductance of 5 mH. The load is a series resistance-
inductance with R 15 and L 500 mH. Use PSpice to determine (a) the
steady-state average load current, (b) the average load voltage, and (c) the
commutation angle. Use the default diode in the simulation.
3-40. The commutation angle given in Eq. (3-64) for the half-wave rectifier with
a freewheeling diode was developed for commutation of load current from
D2 to D1. Show that the commutation angle is the same for commutation from
D1 to D2.
3-41. Diode D1 in Fig. 3-18a is replaced with an SCR to make a controlled half-wave
rectifier. Show that the angle for commutation from the diode to the SCR is
u cos 1 acos
ILXs
b
Vm
where is the delay angle of the SCR.
Design Problems
3-42. A certain situation requires that either 160 or 75 W be supplied to a 48 V battery
from a 120 V rms 60 Hz ac source. There is a two-position switch on a control
panel set at either 160 or 75. Design a single circuit to deliver both values of
power, and specify what the control switch will do. Specify the values of all the
components in your circuit. The internal resistance of the battery is 0.1 .
3-43. Design a circuit to produce an average current of 2 A in an inductance of
100 mH. The ac source available is 120 V rms at 60 Hz. Verify your design
with PSpice. Give alternative circuits that could be used to satisfy the design
specifications, and give reasons for your selection.
3-44. Design a circuit that will deliver 100 W to a 48 V dc source from a 120 V rms
60 Hz ac source. Verify your design with PSpice. Give alternative circuits that
could be used to satisfy the design specifications, and give reasons for your
selection.
3-45. Design a circuit which will deliver 150 W to a 100 V dc source from a 120 V rms
60 Hz ac source. Verify your design with PSpice. Give alternative circuits that
selection.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 111
C H A P T E R 4
Full-Wave Rectifiers
Converting ac to dc
4.1 INTRODUCTION
The objective of a full-wave rectifier is to produce a voltage or current that is
purely dc or has some specified dc component. While the purpose of the full-
wave rectifier is basically the same as that of the half-wave rectifier, full-wave
rectifiers have some fundamental advantages. The average current in the ac
source is zero in the full-wave rectifier, thus avoiding problems associated with
nonzero average source currents, particularly in transformers. The output of the
full-wave rectifier has inherently less ripple than the half-wave rectifier.
In this chapter, uncontrolled and controlled single-phase and three-phase
full-wave converters used as rectifiers are analyzed for various types of loads.
Also included are examples of controlled converters operating as inverters,
where power flow is from the dc side to the ac side.
4.2 SINGLE-PHASE FULL-WAVE RECTIFIERS

The bridge rectifier and the center-tapped transformer rectifier of Figs. 4-1 and
4-2 are two basic single-phase full-wave rectifiers.
The Bridge Rectifier

For the bridge rectifier of Fig. 4-1, these are some basic observations:
1. Diodes D1 and D2 conduct together, and D3 and D4 conduct together.
Kirchhoff’s voltage law around the loop containing the source, D1, and D3
111
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 112
is
is io
iD1
D4 D1
D1 D3
io +
+ +
vs = vs vo
- – vo + -
–
D2 D3 D4 D2
iD4
(a)
(b)
vs
Vm
wt
0
p 2p
–Vm
vo
Vm
p 2p wt
vD1, vD2
wt
0
p 2p
vD3, vD4
Vm
0
p 2p wt
–Vm
io
0
p 2p wt
iD1, iD2
0
p 2p wt
iD3, iD4
0
p 2p wt
is
wt
0
p 2p
(c)
Figure 4-1 Full-wave bridge rectifier. (a) Circuit diagram. (b) Alternative
representation. (c) Voltages and currents.
112
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 113
4.2 Single-Phase Full-Wave Rectifiers 113
N1 : N2 D1
+
vS1 io
vs + –
− + – vo +
vS2
–
D2
(a)
vs
Vm
0
π 2π 3π 4π ωt
–Vm
vo
Vm
vD1
0
–2Vm
vD2
–2Vm
io
iD1
iD2
is
(b)
Figure 4-2 Full-wave center-tapped rectifier (a) circuit;

(b) voltages and currents.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 114
114 C H A P T E R 4 Full-Wave Rectifiers
shows that D1 and D3 cannot be on at the same time. Similarly, D2 and D4

cannot conduct simultaneously. The load current can be positive or zero but
can never be negative.
2. The voltage across the load is vs when D1 and D2 are on. The voltage
across the load is vs when D3 and D4 are on.
3. The maximum voltage across a reverse-biased diode is the peak value of the
source. This can be shown by Kirchhoff’s voltage law around the loop
containing the source, D1, and D3. With D1 on, the voltage across D3
is vs.
4. The current entering the bridge from the source is iD1 iD4, which is
symmetric about zero. Therefore, the average source current is zero.
5. The rms source current is the same as the rms load current. The source
current is the same as the load current for one-half of the source period and
is the negative of the load current for the other half. The squares of the load
and source currents are the same, so the rms currents are equal.
6. The fundamental frequency of the output voltage is 2, where is the
frequency of the ac input since two periods of the output occur for every
period of the input. The Fourier series of the output consists of a dc term and
the even harmonics of the source frequency.
The Center-Tapped Transformer Rectifier

The voltage waveforms for a resistive load for the rectifier using the center-
tapped transformer are shown in Fig. 4-2. Some basic observations for this cir-
cuit are as follows:
1. Kirchhoff’s voltage law shows that only one diode can conduct at a time.
Load current can be positive or zero but never negative.
2. The output voltage is vs1 when D1 conducts and is vs2 when D2 conducts.
The transformer secondary voltages are related to the source voltage by vs1
vs2 vs( N2/2N1).
3. Kirchhoff’s voltage law around the transformer secondary windings, D1, and
D2 shows that the maximum voltage across a reverse-biased diode is twice
the peak value of the load voltage.
4. Current in each half of the transformer secondary is reflected to the primary,
resulting in an average source current of zero.
5. The transformer provides electrical isolation between the source and the
load.
6. The fundamental frequency of the output voltage is 2 since two periods of
the output occur for every period of the input.
The lower peak diode voltage in the bridge rectifier makes it more suitable
for high-voltage applications. The center-tapped transformer rectifier, in addition
to including electrical isolation, has only one diode voltage drop between the
source and load, making it desirable for low-voltage, high-current applications.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 115
The following discussion focuses on the full-wave bridge rectifier but gen-
erally applies to the center-tapped circuit as well.
Resistive Load
The voltage across a resistive load for the bridge rectifier of Fig. 4-1 is expressed as
Vm sin t for 0 t
vo(t) b (4-1)
Vm sin t for t 2
The dc component of the output voltage is the average value, and load current is
simply the resistor voltage divided by resistance.

1 2V
Vo Vm sin t d(t) m
3
0
(4-2)
V 2V
Io o m
R R
Power absorbed by the load resistor can be determined from I2rms R, where Irms
for the full-wave rectified current waveform is the same as for an unrectified
sine wave,
Im
Irms (4-3)
12
The source current for the full-wave rectifier with a resistive load is a sinu-
soid that is in phase with the voltage, so the power factor is 1.
RL Load
For an RL series-connected load (Fig. 4-3a), the method of analysis is similar to
that for the half-wave rectifier with the freewheeling diode discussed in Chap. 3.
After a transient that occurs during start-up, the load current io reaches a periodic
steady-state condition similar to that in Fig. 4-3b.
For the bridge circuit, current is transferred from one pair of diodes to the
other pair when the source changes polarity. The voltage across the RL load is a
full-wave rectified sinusoid, as it was for the resistive load. The full-wave recti-
fied sinusoidal voltage across the load can be expressed as a Fourier series con-
sisting of a dc term and the even harmonics
q
vo(t) Vo a Vn cos (n0 t )

n 2,4Á
where (4-4)
2Vm 2Vm 1 1
Vo and Vn a b
n1 n1
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 116
+
is io
D1 D4 R
vs(t) = +
Vm sin ωt
vo
−
D3 D2
L
–
(a)
vo, io vo
io
0 π 2π 3π 4π ωt
iD1, iD2
iD3, iD4
vs, is
vs
is
(b)
vo, iD1, iD2
vo, iD3, iD4
vs, is
(c)
Figure 4-3 (a) Bridge rectifier with an RL load; (b) Voltages and
currents; (c) Diode and source currents when the inductance is
large and the current is nearly constant.
116
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 117
The current in the RL load is then computed using superposition, taking each
frequency separately and combining the results. The dc current and current
amplitude at each frequency are computed from
V0
I0
R
(4-5)
Vn Vn
In
Zn ƒ R jnL ƒ
Note that as the harmonic number n increases in Eq.(4-4), the voltage
amplitude decreases. For an RL load, the impedance Zn increases as n increases.
The combination of decreasing Vn and increasing Zn makes In decrease rapidly
for increasing harmonic number. Therefore, the dc term and only a few, if any, of
the ac terms are usually necessary to describe current in an RL load.
EXAMPLE 4-1
Full-Wave Rectifier with RL Load

The bridge rectifier circuit of Fig. 4-3a has an ac source with Vm 100 V at 60 Hz and a
series RL load with R 10 and L 10 mH. (a) Determine the average current in the
load. (b) Estimate the peak-to-peak variation in load current based on the first ac term in
the Fourier series. (c) Determine the power absorbed by the load and the power factor of
the circuit. (d) Determine the average and rms currents in the diodes.
■ Solution
(a) The average load current is determined from the dc term in the Fourier series. The
voltage across the load is a full-wave rectified sine wave that has the Fourier series
determined from Eq. (4-4). Average output voltage is
2Vm 2(200)
V0 63.7 V

and average load current is
V0 63.7 V
I0 6.37 A
R 10 Æ
(b) Amplitudes of the ac voltage terms are determined from Eq. (4-4). For n 2 and 4,
2(100) 1 1
V2 a b 42.4 V
1 3
2(100) 1 1
V4 a b 8.49 V
3 5
The amplitudes of first two ac current terms in the current Fourier series are
computed from Eq. (4-5).
42.4 42.4 V
I2 3.39 A
| 10 j(2)(377)(0.01) | 12.5 Æ
8.49 8.49 V
I4 0.47 A
| 10 j(4)(377)(0.01) | 18.1 Æ
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 118
The current I2 is much larger than I4 and higher-order harmonics, so I2 can be used
to estimate the peak-to-peak variation in load current io L 2(3.39) 6.78 A.
Actual variation in io will be larger because of the higher-order terms.
(c) The power absorbed by the load is determined from I2rms. The rms current is then
determined from Eq. (2-43) as
Irms 3g I 2n, rms
3.39 2 0.47 2 Á
(6.37)2 a b a b L 6.81 A
C 12 12
Adding more terms in the series would not be useful because they are small and
have little effect on the result. Power in the load is
P I 2rms R (6.81)2 (10) 464 W
The rms source current is the same as the rms load current. Power factor is
P P 464
pf 0.964
S Vs, rms Is, rms 100
a b (6.81)
12
(d) Each diode conducts for one-half of the time, so
Io 6.37
ID, avg 3.19 A
2 2
and
I 6.81
ID, rms rms 4.82 A
12 12
In some applications, the load inductance may be relatively large or made

large by adding external inductance. If the inductive impedance for the ac terms
in the Fourier series effectively eliminates the ac current terms in the load, the
load current is essentially dc. If L W R,
Vo 2Vm
i(t) L Io
R R for L W R (4-6)
Irms L Io
Load and source voltages and currents are shown in Fig. 4-3c.
Source Harmonics
Nonsinusoidal source current is a concern in power systems. Source currents like
that of Fig. 4-3 have a fundamental frequency equal to that of the source but are
rich in the odd-numbered harmonics. Measures such as total harmonic distortion
(THD) and distortion factor (DF) as presented in Chap. 2 describe the nonsinu-
soidal property of the source current. Where harmonics are of concern, filters can
be added to the input of the rectifier.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 119
PSpice Simulation
A PSpice simulation will give the output voltage, current, and power for full-
wave rectifier circuits. Fourier analysis from the FOUR command or from Probe
will give the harmonic content of voltages and currents in the load and source.
The default diode model will give results that differ from the analytical results
that assume an ideal diode. For the full-wave rectifier, two diodes will conduct at
a time, resulting in two diode voltage drops. In some applications, the reduced
voltage at the output may be significant. Since voltage drops across the diodes
exist in real circuits, PSpice results are a better indicator of circuit performance
than results that assume ideal diodes. (To simulate an ideal circuit in PSpice, a
diode model with n 0.001 will produce forward voltage drops in the microvolt
range, approximating an ideal diode.)
EXAMPLE 4-2
PSpice Simulation of a Full-Wave Rectifier

For the full-wave bridge rectifier in Example 4-1, obtain the rms current and power
absorbed by the load from a PSpice simulation.
■ Solution
The PSpice circuit for Fig. 4-3 is created using VSIN for the source, Dbreak for the
diodes, and R and L for the load. A transient analysis is performed using a run time of
50 ms and data saved after 33.33 ms to obtain steady-state current.
The Probe output is used to determine the operating characteristics of the rectifier
using the same techniques as presented in Chaps. 2 and 3. To obtain the average value of
the load current, enter AVG(I(R1)). Using the cursor to identify the point at the end of the
resulting trace, the average current is approximately 6.07 A. The Probe output is shown
in Fig. 4-4.
Entering RMS(I(R1)) shows that the rms current is approximately 6.52 A. Power
absorbed by the resistor can be computed from I2rmsR, or average power in the load can
be computed directly from Probe by entering AVG(W(R1)), which yields 425.4 W.
This is significantly less than the 464 W obtained in Example 4-1 when assuming ideal
diodes.
The power supplied by the ac source is computed from AVG(W(V1)) as 444.6 W.
When ideal diodes were assumed, power supplied by the ac source was identical to the
power absorbed by the load, but this analysis reveals that power absorbed by the
diodes in the bridge is 444.6 425.4 19.2 W. Another way to determine power
absorbed by the bridge is to enter AVG(W(D1)) to obtain the power absorbed by diode
D1, which is 4.8 W. Total power for the diodes is 4 times 4.8, or 19.2 W. Better mod-
els for power diodes would yield a more accurate estimate of power dissipation in the
diodes.
Comparing the results of the simulation to the results based on ideal diodes shows
how more realistic diode models reduce the current and power in the load.
har80679_ch04_111-170.qxd 12/17/09 2:35 PM Page 120
10 A
I (R1)
RMS
(50.000m, 6.5224)
AVERAGE
(50.000m, 6.0687)
5A
0A
32 ms 35 ms 40 ms 45 ms 50 ms 55 ms 60 ms
I (R1) AVG (I(R1)) RMS (I(R1))
Time
Figure 4-4 PSpice output for Example 4-2.
RL-Source Load
Another general industrial load may be modeled as a series resistance, induc-
tance, and a dc voltage source, as shown in Fig. 4-5a. A dc motor drive circuit
and a battery charger are applications for this model. There are two possible
modes of operation for this circuit, the continuous-current mode and the
discontinuous-current mode. In the continuous-current mode, the load current
is always positive for steady-state operation (Fig. 4-5b). Discontinuous
load current is characterized by current returning to zero during every period
(Fig. 4-5c).
For continuous-current operation, one pair of diodes is always conducting,
and the voltage across the load is a full-wave rectified sine wave. The only mod-
ification to the analysis that was done for an RL load is in the dc term of the
Fourier series. The dc (average) component of current in this circuit is
2Vm
⫺ Vdc
Vo ⫺ Vdc ␲ (4-7)
Io ⫽ ⫽
R R
The sinusoidal terms in the Fourier analysis are unchanged by the dc source pro-
vided that the current is continuous.
Discontinuous current is analyzed like the half-wave rectifier of Sec. 3.5.
The load voltage is not a full-wave rectified sine wave for this case, so the
Fourier series of Eq. (4-4) does not apply.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 121
R L
+ io
+
+
vo Vdc
− –
(a)
vo
io
(b) t
vo
Vdc
io
(c) t
Figure 4-5 (a) Rectifier with RL-source load; (b) Continuous current: when
the circuit is energized, the load current reaches the steady-state after a few
periods; (c) Discontinuous current: the load current returns to zero during
every period.
EXAMPLE 4-3
Full-Wave Rectifier with RL-Source Load—Continuous Current

For the full-wave bridge rectifier circuit of Fig. 4-5a, the ac source is 120 V rms at 60 Hz,
R 2 , L 10 mH, and Vdc 80 V. Determine the power absorbed by the dc voltage
source and the power absorbed by the load resistor.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 122
■ Solution
For continuous current, the voltage across the load is a full-wave rectified sine wave
which has the Fourier series given by Eq. (4-4). Equation (4-7) is used to compute the
average current, which is used to compute power absorbed by the dc source,
2Vm 222(120)
Vdc 80

I0 14.0 A
R 2
Pdc I0Vdc (14)(80) 1120 W
The first few terms of the Fourier series using Eqs. (4-4) and (4-5) are shown in
Table 4-1.
Table 4-1 Fourier series components
n Vn Zn In
0 108 2.0 14.0
2 72.0 7.80 9.23
4 14.4 15.2 0.90
The rms current is computed from Eq. (2-43).

9.23 2 0.90 2 . . .
Irms 142 a b a b L 15.46 A
C 12 12
Power absorbed by the resistor is
PR I 2rms R (15.46)2(2) 478 W
PSpice Solution
PSpice simulation of the circuit of Fig 4-5a using the default diode model yields these
results from Probe:
Quantity Expression Entered Result

Io AVG(I(R1)) 11.9 A
Irms RMS(I(R1)) 13.6 A
Pac AVG(W(Vs)) 1383 W
PD1 AVG(W(D1)) 14.6 W
Pdc AVG(W(VDC)) 955 W
PR AVG(W(R)) 370 W
Note that the simulation verifies the assumption of continuous load current.
Capacitance Output Filter

Placing a large capacitor in parallel with a resistive load can produce an output
voltage that is essentially dc (Fig. 4-6). The analysis is very much like that of the
half-wave rectifier with a capacitance filter in Chap. 3. In the full-wave circuit,
the time that the capacitor discharges is smaller than that for the half-wave circuit
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 123
+
iC iR
vs(t) = +
vm sin(ωt) C R vo
−
–
(a)
vo
Vm
ΔVo
0 π
–θ π π+α ωt
2 α
(b)
Figure 4-6 (a) Full-wave rectifier with capacitance filter;

(b) Source and output voltage.
because of the rectified sine wave in the second half of each period. The output
voltage ripple for the full-wave rectifier is approximately one-half that of the
half-wave rectifier. The peak output voltage will be less in the full-wave circuit
because there are two diode voltage drops rather than one.
The analysis proceeds exactly as for the half-wave rectifier. The output volt-
age is a positive sine function when one of the diode pairs is conducting and is a
decaying exponential otherwise. Assuming ideal diodes,
ƒ Vm sin t ƒ one diode pair on
vo(t) b (4-8)
(Vm sin
)e (t
)>RC diodes off
where
is the angle where the diodes become reverse biased, which is the same
as that for the half-wave rectifier and is found using Eq. (3-41).

tan1 (RC) tan1(RC) (4-9)
The maximum output voltage is Vm, and the minimum output voltage is deter-
mined by evaluating vo at the angle at which the second pair of diodes turns on,
which is at t . At that boundary point,
(Vm sin
)e (
)>RC Vm sin ( )
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 124
or
(sin
)e (
)>RC sin 0 (4-10)
which must be solved numerically for .

The peak-to-peak voltage variation, or ripple, is the difference between max-
imum and minimum voltages.
Vo Vm ƒ Vm sin ( ) ƒ Vm(1 sin ) (4-11)
This is the same as Eq. (3-49) for voltage variation in the half-wave rectifier, but
is larger for the full-wave rectifier and the ripple is smaller for a given load. Ca-
pacitor current is described by the same equations as for the half-wave rectifier.
In practical circuits where RC W .

L >2 L >2 (4-12)
The minimum output voltage is then approximated from Eq. (4-9) for the diodes
off evaluated at t .
vo ( ) Vme (>2>2)>RC Vme >RC
The ripple voltage for the full-wave rectifier with a capacitor filter can then be
approximated as
Vo L Vm(1 e >RC)
Furthermore, the exponential in the above equation can be approximated by the
series expansion

e >RC L 1
RC
Substituting for the exponential in the approximation, the peak-to-peak ripple is
Vm Vm
Vo L (4-13)
RC 2f RC
Note that the approximate peak-to-peak ripple voltage for the full-wave rectifier
is one-half that of the half-wave rectifier from Eq. (3-51). As for the half-wave
rectifier, the peak diode current is much larger than the average diode current and
Eq. (3-48) applies. The average source current is zero.
EXAMPLE 4-4
Full-Wave Rectifier with Capacitance Filter

The full-wave rectifier of Fig. 4-6a has a 120 V source at 60 Hz, R 500 , and C 100 F.
(a) Determine the peak-to-peak voltage variation of the output. (b) Determine the value of
capacitance that would reduce the output voltage ripple to 1percent of the dc value.
har80679_ch04_111-170.qxd 12/17/09 2:36 PM Page 125
■ Solution
Vm ⫽ 12022 ⫽ 169.7 V
␻RC ⫽ (2␲60)(500)(10)⫺6 ⫽ 18.85
The angle ␪ is determined from Eq. (4-9).
␪ ⫽ ⫺tan⫺1(18.85) ⫹ ␲ ⫽ 1.62 rad ⫽ 93°
Vm sin ␪ ⫽ 169.5 V
The angle ␣ is determined by the numerical solution of Eq. (4-10).
sin (1.62)e ⫺(␲⫹␣⫺1.62)>18.85 ⫺ sin ␣ ⫽ 0
␣ ⫽ 1.06 rad = 60.6°
(a) Peak-to-peak output voltage is described by Eq. (4-11).
⌬Vo ⫽ Vm(1 ⫺ sin ␣ ) ⫽ 169.7 31 ⫺ sin (1.06)4 ⫽ 22 V
Note that this is the same load and source as for the half-wave rectifier of Example 3-9
where ⌬Vo ⫽ 43 V.
(b) With the ripple limited to 1 percent, the output voltage will be held close to Vm and
the approximation of Eq. (4-13) applies.
⌬ Vo 1
⫽ 0.01 L
Vm 2fRC
Solving for C,
1 1
C L ⫽ ⫽ 1670 ␮F
2fR( ⌬ Vo>Vm) (2)(60)(500)(0.01)
Voltage Doublers
The rectifier circuit of Fig. 4-7a serves as a simple voltage doubler, having an
output of twice the peak value of the source. For ideal diodes, C1 charges to Vm
through D1 when the source is positive; C2 charges to Vm through D2 when the
source is negative. The voltage across the load resistor is the sum of the capaci-
tor voltages 2Vm. This circuit is useful when the output voltage of a rectifier must
be larger than the peak input voltage. Voltage doubler circuits avoid using a
transformer to step up the voltage, saving expense, volume, and weight.
The full-wave rectifier with a capacitive output filter can be combined with
the voltage doubler, as shown in Fig. 4-7b. When the switch is open, the circuit
is similar to the full-wave rectifier of Fig. 4-6a, with output at approximately
Vm when the capacitors are large. When the switch is closed, the circuit acts as
the voltage doubler of Fig. 4-7a. Capacitor C1 charges to Vm through D1 when
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 126
D1
+
+
C1 ~ Vm
–
vs = +
Vm sin wt vo ~ 2Vm
-
+
C2 ~ Vm
D2 –
–
(a)
D1 D3 V = V C1
o m
vs(t) = +
Vm sin (wt) - vo ~ Vm or 2Vm
Vo = 2Vm
D4 D2 C2
–
(b)
Figure 4-7 (a) Voltage doubler. (b) Dual-voltage rectifier.
the source is positive, and C2 charges to Vm through D4 when the source is neg-
ative. The output voltage is then 2Vm. Diodes D2 and D3 remain reverse-biased
in this mode.
This voltage doubler circuit is useful when equipment must be used on sys-
tems with different voltage standards. For example, a circuit could be designed
to operate properly in both the United States, where the line voltage is 120 V, and
places abroad where the line voltage is 240 V.
LC Filtered Output
Another full-wave rectifier configuration has an LC filter on the output, as shown
in Fig. 4-8a. The purpose of the filter is to produce an output voltage that is close
to purely dc. The capacitor holds the output voltage at a constant level, and the
inductor smooths the current from the rectifier and reduces the peak current in
the diodes from that of the current of Fig. 4-6a.
The circuit can operate in the continuous- or discontinuous-current mode.
For continuous current, the inductor current is always positive, as illustrated in
Fig. 4-8b. Discontinuous current is characterized by the inductor current return-
ing to zero in each cycle, as illustrated in Fig. 4-8c. The continuous-current case
is easier to analyze and is considered first.
Continuous Current for LC Filtered Output For continuous current, the
voltage vx in Fig. 4-8a is a full-wave rectified sine wave, which has an average
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 127
L
+ +
iL iC iR
vs(t) = +
vm sin(ωt) − vx C R vo
– –
(a)
iL
t
(b)
iL
t
(c)
Normalized Output with LC Filter

1.0
0.8
0.6
Vo / Vm
0.4
0.2
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

3ωL/R
(d)
Figure 4-8 (a) Rectifier with LC filtered output;

(b) Continuous inductor current; (c) Discontinuous inductor
current; (d) Normalized output.
value of 2Vm /. Since the average voltage across the inductor in the steady state
is zero, the average output voltage for continuous inductor current is
2V
Vo m (4-14)

Average inductor current must equal the average resistor current because the
average capacitor current is zero.
V 2V
IL IR o m (4-15)
R R
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 128
The variation in inductor current can be estimated from the first ac term in the
Fourier series. The first ac voltage term is obtained from Eq. (4-4) with n 2.
Assuming the capacitor to be a short circuit to ac terms, the harmonic voltage v2
exists across the inductor. The amplitude of the inductor current for n 2 is
V2 V 4V >3 2Vm
I2 L 2 m (4-16)
Z2 2L 2L 3L
For the current to always be positive, the amplitude of the ac term must be less
than the dc term (average value). Using the above equations and solving for L,
I2 IL
2Vm 2V
m
3L R
R
L
3
or
3L
1 for continuous current (4-17)
R
If 3L/R 1, the current is continuous and the output voltage is 2Vm /. Other-
wise, the output voltage must be determined from analysis for discontinuous cur-
rent, discussed as follows.
Discontinuous Current for LC Filtered Output For discontinuous inductor
current, the current reaches zero during each period of the current waveform
(Fig. 4-8c). Current becomes positive again when the bridge output voltage
reaches the level of the capacitor voltage, which is at t .
V
sin 1 a o b (4-18)
Vm
While current is positive, the voltage across the inductor is
vL Vm sin (t) Vo (4-19)
where the output voltage Vo is yet to be determined. Inductor current is expressed as
t
C V sin (t) Vo D d(t)

1
i L(t)
L 3 m

C V A cos cos t B D Vo(t )

1
(4-20)
L m
for t when
which is valid until the current reaches zero, at t .
The solution for the load voltage Vo is based on the fact that the average in-
ductor current must equal the current in the load resistor. Unfortunately, a closed-
form solution is not available, and an iterative technique is required.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 129
A procedure for determining Vo is as follows:

1. Estimate a value for Vo slightly below Vm and solve for in Eq. (4-18).
2. Solve for numerically in Eq. (4-20) for inductor current,
i L( ) 0 Vm( cos cos ) Vo( )
3. Solve for average inductor current IL.

1
iL i (t) d(t)
3 L

(4-21)

C Vm( cos cos t) Vo(t ) D d(t)

1 1

3 L

4. Solve for load voltage Vo based upon the average inductor current from
step 3.
Vo
IR IL
R
or
Vo ILR (4-22)
5. Repeat steps 1 to 4 until the computed value of Vo in step 4 equals the
estimated Vo in step 1.
Output voltage for discontinuous current is larger than for continuous cur-
rent. If there is no load, the capacitor charges to the peak value of the source so
the maximum output is Vm. Figure 4-8d shows normalized output Vo/Vm as a
function of 3L/R.
EXAMPLE 4-5
Full-Wave Rectifier with LC Filter

A full-wave rectifier has a source of vs(t) 100 sin(377t) V. An LC filter as in Fig. 4-8a
is used, with L 5 mH and C 10,000 F. The load resistance is (a) 5 and (b) 50 .
Determine the output voltage for each case.
■ Solution
Using Eq. (4-17), continuous inductor current exists when
R 3L 3(377)(0.005) 5.7 Æ
which indicates continuous current for 5 and discontinuous current for 50 .
(a) For R 5 with continuous current, output voltage is determined from Eq. (4-14).
2Vm 2(100)
Vo 63.7 V

har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 130
(b) For R 50 with discontinuous current, the iteration method is used to determine
Vo. Initially, Vo is estimated to be 90 V. The results of the iteration are as follows:
Estimated Vo Calculated Vo
90 1.12 2.48 38.8 (Estimate is too high)
80 0.93 2.89 159 (Estimate is too low)
85 1.12 2.70 88.2 (Estimate is slightly low)
86 1.04 2.66 76.6 (Estimate is too high)
85.3 1.02 2.69 84.6 (Approximate solution)
Therefore, Vo is approximately 85.3 V. As a practical matter, three significant figures for

the load voltage may not be justified when predicting performance of a real circuit.
Knowing that the output voltage is slightly above 85 V after the third iteration is proba-
bly sufficient. Output could also be estimated from the graph of Fig. 4-8d.
PSpice Solution
The circuit is created using VSIN for the source and Dbreak for the diodes, with the
diode model modified to represent an ideal diode by using n 0.01. The voltage of the
filter capacitor is initialized at 90 V, and small capacitors are placed across the diodes to
avoid convergence problems. Both values of R are tested in one simulation by using a
parametric sweep. The transient analysis must be sufficiently long to allow a steady-
state periodic output to be observed. The Probe output for both load resistors is shown
in Fig. 4-9. Average output voltage for each case is obtained from Probe by entering
AVG(V(out)V(out)) after restricting the data to represent steady-state output (after
about 250 ms), resulting in Vo 63.6 V for R 5 (continuous current) and Vo 84.1 V
for R 50 (discontinuous current). These values match very well with those of the
analytical solution.
FULL-WAVE RECTIFIER WITH AN L–C FILTER

1 2 out+
L1 5m
1p D1 1p D3
Dbreak PARAMETERS:
C1 R1 R = 5
VOFF = 0 Vs 10000u (R)
+
VAMPL = 100
FREQ = 60 – 1p D4 1p D2
out–
0
(a)
Figure 4-9 PSpice output for Example 4-6. (a) Full-wave rectifier with an LC filter. The small
capacitors across the diodes help with convergence; (b) The output voltage for continuous and
discontinuous inductor current.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 131
4.3 Controlled Full-Wave Rectifiers 131
90 V
R = 50, DISCONTINUOUS CURRENT
80 V
70 V
R = 5, CONTINUOUS CURRENT
60 V
0s 50 ms 100 ms 150 ms 200 ms 250 ms 300 ms
v(OUT+, OUT–)
Time
(b)
4.3 CONTROLLED FULL-WAVE RECTIFIERS

A versatile method of controlling the output of a full-wave rectifier is to substi-
tute controlled switches such as thyristors (SCRs) for the diodes. Output is con-
trolled by adjusting the delay angle of each SCR, resulting in an output voltage
that is adjustable over a limited range.
Controlled full-wave rectifiers are shown in Fig. 4-10. For the bridge recti-
fier, SCRs S1 and S2 will become forward-biased when the source becomes posi-
tive but will not conduct until gate signals are applied. Similarly, S3 and S4 will
become forward-biased when the source becomes negative but will not conduct
until they receive gate signals. For the center-tapped transformer rectifier, S1 is
forward-biased when vs is positive, and S2 is forward-biased when vs is negative,
but each will not conduct until it receives a gate signal.
The delay angle is the angle interval between the forward biasing of the
SCR and the gate signal application. If the delay angle is zero, the rectifiers
behave exactly as uncontrolled rectifiers with diodes. The discussion that follows
generally applies to both bridge and center-tapped rectifiers.
Resistive Load
The output voltage waveform for a controlled full-wave rectifier with a resistive
load is shown in Fig. 4-10c. The average component of this waveform is deter-
mined from

1 V
Vo Vm sin (t) d(t) m (1 cos ) (4-23)
3

har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 132
+
S1 S3
vs = +
Vm sin ωt vo
−
S4 S2 –
(a)
S1
– vo +
+
−
S2
(b)
vo
0 α π π+α 2π ωt
(c)
Figure 4-10 (a) Controlled full-wave bridge rectifier;

(b) Controlled full-wave center-tapped transformer rectifier;
(c) Output for a resistive load.
Average output current is then
Vo Vm
Io
(1 cos ) (4-24)
R R
The power delivered to the load is a function of the input voltage, the delay
angle, and the load components; P I2rms R is used to determine the power in a
resistive load, where

2
1 V
Irms a m sin t b d (t)
C 3 R

(4-25)
Vm 1 sin (2 )

R A 2 2 4
The rms current in the source is the same as the rms current in the load.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 133
EXAMPLE 4-6
Controlled Full-Wave Rectifier with Resistive Load

The full-wave controlled bridge rectifier of Fig. 4-10a has an ac input of 120 V rms at
60 Hz and a 20- load resistor. The delay angle is 40. Determine the average current in
the load, the power absorbed by the load, and the source voltamperes.
■ Solution
The average output voltage is determined from Eq. (4-23).
A 1 cos B A 1 cos 40° B 95.4 V

Vm 22 (120)
Vo

Average load current is
V 95.4
Io o 4.77 A
R 20
Power absorbed by the load is determined from the rms current from Eq. (4-24), remem-
bering to use in radians.
22(120) 1 0.698 sin[2(0.698)]
Irms 5.80 A
20 A 2 2 4
P I 2rms R (5.80)2 (20) 673 W
The rms current in the source is also 5.80 A, and the apparent power of the source is
S Vrms Irms (120)(5.80) 696 VA
Power factor is
P 672
pf 0.967
S 696
RL Load, Discontinuous Current

Load current for a controlled full-wave rectifier with an RL load (Fig. 4-11a) can
be either continuous or discontinuous, and a separate analysis is required for
each. Starting the analysis at t 0 with zero load current, SCRs S1 and S2 in the
bridge rectifier will be forward-biased and S3 and S4 will be reverse-biased as the
source voltage becomes positive. Gate signals are applied to S1 and S2 at t ,
turning S1 and S2 on. With S1 and S2 on, the load voltage is equal to the source
voltage. For this condition, the circuit is identical to that of the controlled half-
wave rectifier of Chap. 3, having a current function
C sin (t
) sin (
) e (t)> D
Vm
i o(t) for t
Z
where (4-26)
L L
Z 2R2 (L)2
tan1 a b and
R R
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 134
io
+
R
vs (ωt) = +
Vm sin(ωt) vo
−
L
–
(a)
io
0
α π β π+α ωt
Vm
vo
0
π 2π ωt
(b)
io
α π π+α ωt
vo
0
π 2π ωt
(c)
Figure 4-11 (a) Controlled rectifier with RL load;

(b) Discontinuous current; (c) Continuous current.
The above current function becomes zero at t . If , the current

remains at zero until t when gate signals are applied to S3 and S4
which are then forward-biased and begin to conduct. This mode of operation is
called discontinuous current, which is illustrated in Fig. 4-11b.
: discontinuous current (4-27)

har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 135
Analysis of the controlled full-wave rectifier operating in the discontinuous-

current mode is identical to that of the controlled half-wave rectifier except that
the period for the output current is rather than 2 rad.
EXAMPLE 4-7
Controlled Full-Wave Rectifier, Discontinuous Current

A controlled full-wave bridge rectifier of Fig. 4-11a has a source of 120 V rms at 60 Hz,
R 10 , L 20 mH, and 60. Determine (a) an expression for load current, (b) the
average load current, and (c) the power absorbed by the load.
■ Solution
120
Vm 169.7 V
12
Z 2R2 (L)2 210 2 [(377)(0.02)]2 12.5 Æ
L (377)(0.02)

tan 1 a b tan 1 c d 0.646 rad
R 10
L (377)(0.02)
0.754 rad
R 10
60° 1.047 rad
(a) Substituting into Eq. (4-26),
i o(t) 13.6 sin (t 0.646) 21.2e t>0.754 A for t
Solving io() 0 numerically for , 3.78 rad (216). Since 4.19 ,
the current is discontinuous, and the above expression for current is valid.
(b) Average load current is determined from the numerical integration of

1
Io i (t) d (t) 7.05 A
3 o

(c) Power absorbed by the load occurs in the resistor and is computed from I2rmsR,
where

1
Irms i (t) d(t) 8.35 A
C 3 o

P (8.35)2(10) 697 W
RL Load, Continuous Current

If the load current is still positive at t when gate signals are applied to
S3 and S4 in the above analysis, S3 and S4 are turned on and S1 and S2 are forced
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 136
off. Since the initial condition for current in the second half-cycle is not zero, the
current function does not repeat. Equation (4-26) is not valid in the steady state
for continuous current. For an RL load with continuous current, the steady-state
current and voltage waveforms are generally as shown in Fig. 4-11c.
The boundary between continuous and discontinuous current occurs when
for Eq. (4-26) is . The current at t must be greater than zero for
continuous-current operation.
i( ) 0
sin(
) sin(
) e ()> 0
Using
sin(
) sin(
)
sin(
) A 1 e (>) B 0
Solving for ,

Using
L

tan1 a b
R
L
tan1 a b for continuous current (4-28)
R
Either Eq. (4-27) or Eq. (4-28) can be used to check whether the load current is
continuous or discontinuous.
A method for determining the output voltage and current for the continuous-
current case is to use the Fourier series. The Fourier series for the voltage wave-
form for continuous-current case shown in Fig. 4-11c is expressed in general
form as
q
vo(t) Vo a Vn cos (n0t

n) (4-29)
n1
The dc (average) value is

1 2V
Vo V sin (t) d(t) m cos (4-30)
3 m

The amplitudes of the ac terms are calculated from
Vn 2a 2n b 2n ()() (4-31)
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 137
where
2Vm cos(n 1) cos(n 1)
an c d
n1 n1
2Vm sin(n 1) sin(n 1) (4-32)

bn c d
n1 n1
n 2, 4, 6, . . .
Figure 4-12 shows the relationship between normalized harmonic content of the
output voltage and delay angle.
The Fourier series for current is determined by superposition as was done for
the uncontrolled rectifier earlier in this chapter. The current amplitude at each
frequency is determined from Eq. (4-5). The rms current is determined by com-
bining the rms currents at each frequency. From Eq. (2-43),
In 2
a b
q
Irms I 2o a
C n2,4,6 Á 12
where
Vo Vn Vn
Io and In (4-33)
R Zn ƒ R jn 0L ƒ
1.0
n=2
0.8
0.6
Vn /Vm
0.4
n=4
n=6
0.2
n=8
0 40 80 120 160
90
Delay Angle
Figure 4-12 Output harmonic voltages as a function

of delay angle for a single-phase controlled rectifier.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 138
As the harmonic number increases, the impedance for the inductance increases.
Therefore, it may be necessary to solve for only a few terms of the series to be
able to calculate the rms current. If the inductor is large, the ac terms will become
small, and the current is essentially dc.
EXAMPLE 4-8
Controlled Full-Wave Rectifier with RL Load, Continuous Current

A controlled full-wave bridge rectifier of Fig. 4-11a has a source of 120 V rms at 60 Hz,
an RL load where R 10 and L 100 mH. The delay angle 60 (same as Exam-
ple 4-7 except L is larger). (a) Verify that the load current is continuous. (b) Determine the
dc (average) component of the current. (c) Determine the power absorbed by the load.
■ Solution
(a) Equation (4-28) is used to verify that the current is continuous.
L (377)(0.1)
tan1 a b tan 1 c d 75°
R 10
60° 75° ‹ continuous current
(b) The voltage across the load is expressed in terms of the Fourier series of Eq. (4-29).
The dc term is computed from Eq. (4-30).
2Vm 222(120)
V0 cos cos(60°) 54.0 V

(c) The amplitudes of the ac terms are computed from Eqs. (4-31) and (4-32) and are
summarized in the following table where, Zn |R jL| and In Vn/Zn.
n an bn Vn Zn In
0 (dc) — — 54.0 10 5.40
2 90 93.5 129.8 76.0 1.71
4 46.8 18.7 50.4 151.1 0.33
6 3.19 32.0 32.2 226.4 0.14
The rms current is computed from Eq. (4-33).
1.71 2 0.33 2 0.14 2 . . .

Irms (5.40)2 a b a b a b L 5.54 A
C 12 12 12
Power is computed from I2rmsR.
P (5.54)2(10) 307 W
Note that the rms current could be approximated accurately from the dc term and
one ac term (n 2). Higher-frequency terms are very small and contribute little to
the power in the load.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 139
PSpice Simulation of Controlled Full-Wave Rectifiers

To simulate the controlled full-wave rectifier in PSpice, a suitable SCR model
must be chosen. As with the controlled half-wave rectifier of Chap. 3, a simple
switch and diode can be used to represent the SCR, as shown in Fig. 4-13a. This
circuit requires the full version of PSpice.
EXAMPLE 4-9
PSpice Simulation of a Controlled Full-Wave Rectifier

Use PSpice to determine the solution of the controlled full-wave rectifier in
Example 4-8.
■ Solution
A PSpice circuit that uses the controlled-switch model for the SCRs is shown in
Fig. 4-13a. (This circuit is too large for the demo version and requires the full production
version of PSpice.)
CONTROLLED FULL-WAVE RECTIFIER

PARAMETERS:
Out+
ALPHA = 60
PW = {.51/60}
DLAY = {ALPHA/360/60}
S1 Dbreak S3
Control12 + + Control34 + +
–– Sbreak ––
R1
10
0 0
VOFF = 0 Vs
VAMPL = 170 1
FREQ = 60 L1
0
100m
S4 S2 2
Control34 ++
Control12 ++
–– ––
0 0
Out–
V1 = 0 Control12 Control34
V1 = 0
V2 = 5 + Vcontrol12 V2 = 5 + Vcontrol34
TD = {DLAY} – –
TD = {DLAY + 0.5/60}
TR = 1n
0 TR = 1n 0
TF = 1n
TF = 1n
PW = {PW}
PW = {PW}
PER = {1/60}
PER = {1/60}
(a)
Figure 4-13 (a) PSpice circuit for a controlled full-wave rectifier of Example 4-8;
(b) Probe output showing load voltage and current.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 140
200 V
0V
VOLTAGE
–200 V
v(2, 4)
10 A
CURRENT
5A
SEL>>
0A
60 ms 70 ms 80 ms 90 ms 100 ms
I (R)
Time
(b)

The controlled rectifier with a load that is a series resistance, inductance, and dc
voltage (Fig. 4-14) is analyzed much like the uncontrolled rectifier of Fig. 4-5a
discussed earlier in this chapter. For the controlled rectifier, the SCRs may be
turned on at any time that they are forward-biased, which is at an angle
Vdc
sin1 a b (4-34)
Vm
For the continuous-current case, the bridge output voltage is the same as in
Fig. 4-11c. The average bridge output voltage is
2Vm
Vo cos (4-35)

R L io
+
+
vs (ωt) = +
Vm sin(ωt) − vo Vdc
–
–
Figure 4-14 Controlled rectifier with RL-source load.

har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 141
The average load current is

Vo Vdc
Io (4-36)
R
The ac voltage terms are unchanged from the controlled rectifier with an RL load
in Fig. 4-11a and are described by Eqs. (4-29) to (4-32). The ac current terms are
determined from the circuit of Fig. 4-14c. Power absorbed by the dc voltage is
Pdc IoVdc (4-37)
Power absorbed by the resistor in the load is I 2rmsR.
If the inductance is large and the
load current has little ripple, power absorbed by the resistor is approximately Io2R.
EXAMPLE 4-10

The controlled rectifier of Fig. 4-14 has an ac source of 240 V rms at 60 Hz, Vdc 100 V,
R 5 , and an inductor large enough to cause continuous current. (a) Determine the
delay angle such that the power absorbed by the dc source is 1000 W. (b) Determine the
value of inductance that will limit the peak-to-peak load current variation to 2 A.
■ Solution
(a) For the power in the 100-V dc source to be 1000 W, the current in it must be 10 A.
The required output voltage is determined from Eq. (4-36) as
Vo Vdc IoR 100 (10)(5) 150 V
The delay angle which will produce a 150 V dc output from the rectifier is
determined from Eq. (4-35).
V (150)()
cos1 a o b cos1 c d 46°
2Vm 212(240)
(b) Variation in load current is due to the ac terms in the Fourier series. The load
current amplitude for each of the ac terms is
V
In n
Zn
where Vn is described by Eqs. (4-31) and (4-32) or can be estimated from the graph
of Fig. 4-12. The impedance for the ac terms is
Zn ƒ R jn0L ƒ
Since the decreasing amplitude of the voltage terms and the increasing magnitude
of the impedance both contribute to diminishing ac currents as n increases, the
peak-to-peak current variation will be estimated from the first ac term. For n 2,
Vn/Vm is estimated from Fig. 4-12 as 0.68 for 46, making V2 0.68Vm
0.68 (240 22) 230 V. The peak-to-peak variation of 2 A corresponds to a 1-A
zero-to-peak amplitude. The required load impedance for n 2 is then
V2 230 V
Z2 230 Æ
I2 1A
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 142
The 5- resistor is insignificant compared to the total 230- required impedance,
so Zn L nL. Solving for L,
Z2 230
L L 0.31 H
2 2(377)
A slightly larger inductance should be chosen to allow for the effect of higher-order
ac terms.
Controlled Single-Phase Converter Operating as an Inverter

The above discussion focused on circuits operating as rectifiers, which means
that the power flow is from the ac source to the load. It is also possible for power
to flow from the load to the ac source, which classifies the circuit as an inverter.
For inverter operation of the converter in Fig. 4-14, power is supplied by the
dc source, and power is absorbed by the bridge and is transferred to the ac sys-
tem. The load current must be in the direction shown because of the SCRs in the
bridge. For power to be supplied by the dc source, Vdc must be negative. For
power to be absorbed by the bridge and transferred to the ac system, the bridge
output voltage Vo must also be negative. Equation (4-35) applies, so a delay
angle larger than 90 will result in a negative output voltage.
0 90° : Vo 0 rectifier operation
(4-38)
90° 180° : Vo 0 inverter operation
The voltage waveform for 150 and continuous inductor current is shown in
Fig. 4-15. Equations (4-36) to (4-38) apply. If the inductor is large enough to
vo
Vm sin ωt –Vm sin ωt
απ ωt
Figure 4-15 Output voltage for the controlled single-phase

converter of Fig. 4-14 operating as an inverter, 150 and
Vdc 0.
har80679_ch04_111-170.qxd 12/17/09 2:36 PM Page 143
effectively eliminate the ac current terms and the bridge is lossless, the power
absorbed by the bridge and transferred to the ac system is
Pbridge ⫽ Pac ⫽ ⫺ IoVo (4-39)
EXAMPLE 4-11
Single-Phase Bridge Operating as an Inverter

The dc voltage in Fig. 4-14 represents the voltage generated by an array of solar cells and
has a value of 110 V, connected such that Vdc ⫽⫺110 V. The solar cells are capable of pro-
ducing 1000 W. The ac source is 120 V rms, R ⫽ 0.5 ⍀, and L is large enough to cause
the load current to be essentially dc. Determine the delay angle ␣ such that 1000 W is sup-
plied by the solar cell array. Determine the power transferred to the ac system and the
losses in the resistance. Assume ideal SCRs.
■ Solution
For the solar cell array to supply 1000 W, the average current must be
Pdc 1000
Io ⫽ ⫽ ⫽ 9.09 A
Vdc 110
The average output voltage of the bridge is determined from Eq. (4-36).
Vo ⫽ Io R ⫹ Vdc ⫽ (9.09)(0.5) ⫹ ( ⫺110) ⫽ ⫺105.5 V
The required delay angle is determined from Eq. (4-35).
Vo␲ ⫺105.5␲
␣ ⫽ cos ⫺1 a b ⫽ cos⫺1 c d ⫽ 165.5°
2Vm 212(120)
Power absorbed by the bridge and transferred to the ac system is determined from
Eq. (4-39).
Pac ⫽ ⫺ Vo Io ⫽ (⫺9.09) (⫺105.5) ⫽ 959 W
Power absorbed by the resistor is
PR ⫽ I 2rms R L I 2o R ⫽ (9.09)2(0.5) ⫽ 41 W
Note that the load current and power will be sensitive to the delay angle and the voltage
drops across the SCRs because bridge output voltage is close to the dc source voltage. For
example, assume that the voltage across a conducting SCR is 1 V. Two SCRs conduct at
all times, so the average bridge output voltage is reduced to
Vo ⫽ ⫺105.5 ⫺ 2 ⫽ ⫺107.5 V
Average load current is then
⫺ 107.5 ⫺ (⫺110)
Io ⫽ ⫽ 5.0 A
0.5
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 144
Power delivered to the bridge is then reduced to

Pbridge (107.5)(5.0) 537.5 W
Average current in each SCR is one-half the average load current. Power absorbed by
each SCR is approximately
1 1
PSCR ISCRVSCR IoVSCR (5)(1) 2.5 W
2 2
Total power loss in the bridge is then 4(2.5) 10 W, and power delivered to the ac source
is 537.5 10 527.5 W.
4.4 THREE-PHASE RECTIFIERS

Three-phase rectifiers are commonly used in industry to produce a dc voltage and
current for large loads. The three-phase full-bridge rectifier is shown in Fig. 4-16a.
The three-phase voltage source is balanced and has phase sequence a-b-c. The
source and the diodes are assumed to be ideal in the initial analysis of the circuit.
+
–
v D1 D1 D3 D5
ia
+
a
b Load vo
Van
+ Vbn c
+ Vcn
− +
− D4 D6 D2
−
–
n
(a)
an bn cn an bn cn iD
iD1
Source iD2
vo iD3
ab ac bc ba ca cb ab ac bc ba iD4
6.1 1.2 2.3 3.4 4.5 5.6 6.1
iD5
iD6
Bridge
ωt
ia
v D1
ωt = 0 π 2π
– —
3 3
(b) (c)
Figure 4-16 (a) Three-phase full-bridge rectifier; (b) Source and output voltages; (c) Currents for a
resistive load.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 145
Some basic observations about the circuit are as follows:

1. Kirchhoff’s voltage law around any path shows that only one diode in the
top half of the bridge may conduct at one time (D1, D3, or D5). The diode
that is conducting will have its anode connected to the phase voltage that is
highest at that instant.
2. Kirchhoff’s voltage law also shows that only one diode in the bottom half of
the bridge may conduct at one time (D2, D4, or D6). The diode that is
conducting will have its cathode connected to the phase voltage that is
lowest at that instant.
3. As a consequence of items 1 and 2 above, D1 and D4 cannot conduct at the
same time. Similarly, D3 and D6 cannot conduct simultaneously, nor can D5
and D2.
4. The output voltage across the load is one of the line-to-line voltages of the
source. For example, when D1 and D2 are on, the output voltage is vac.
Furthermore, the diodes that are on are determined by which line-to-line
voltage is the highest at that instant. For example, when vac is the highest
line-to-line voltage, the output is vac.
5. There are six combinations of line-to-line voltages (three phases taken two
at a time). Considering one period of the source to be 360, a transition of
the highest line-to-line voltage must take place every 360/6 60. Because
of the six transitions that occur for each period of the source voltage, the
circuit is called a six-pulse rectifier.
6. The fundamental frequency of the output voltage is 6, where is the
frequency of the three-phase source.
Figure 4-16b shows the phase voltages and the resulting combinations of
line-to-line voltages from a balanced three-phase source. The current in each of
the bridge diodes for a resistive load is shown in Fig. 4-16c. The diodes conduct
in pairs (6,1), (1,2), (2,3), (3,4), (4,5), (5,6), (6,1), . . . . Diodes turn on in the
sequence 1, 2, 3, 4, 5, 6, 1, . . . .
The current in a conducting diode is the same as the load current. To deter-
mine the current in each phase of the source, Kirchhoff’s current law is applied
at nodes a, b, and c,
i a i D1 i D4
i b i D3 i D6 (4-40)
i c i D5 i D2
Since each diode conducts one-third of the time, resulting in
1
ID, avg Io, avg
3
1
ID, rms I (4-41)
13 o, rms
2
Is, rms Io, rms
A3
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 146
The apparent power from the three-phase source is

S 13 VLL, rms IS, rms (4-42)
The maximum reverse voltage across a diode is the peak line-to-line voltage.
The voltage waveform across diode D1 is shown in Fig. 4-16b. When D1 con-
ducts, the voltage across it is zero. When D1 is off, the output voltage is vab when
D3 is on and is vac when D5 is on.
The periodic output voltage is defined as vo(t) Vm,LL sin(t) for /3
t 2/3 with period /3 for the purpose of determining the Fourier series
coefficients. The coefficients for the sine terms are zero from symmetry, enabling
the Fourier series for the output voltage to be expressed as
q
vo(t) Vo a Vn cos (n0t ) (4-43)

n6,12,18 Á
The average or dc value of the output voltage is

2>3
1 3V
V0 V sin (t) d(t) m, LL 0.955 Vm, LL (4-44)
>3 3 m, LL
>3
where Vm,LL is the peak line-to-line voltage of the three-phase source, which is
22VLL, rms. The amplitudes of the ac voltage terms are
6Vm, LL
Vn n 6, 12, 18, Á (4-45)
(n 2 1)
Since the output voltage is periodic with period one-sixth of the ac supply volt-
age, the harmonics in the output are of order 6k, k 1, 2, 3 . . . An advantage
of the three-phase rectifier over the single-phase rectifier is that the output is
inherently like a dc voltage, and the high-frequency low-amplitude harmonics
enable filters to be effective.
In many applications, a load with series inductance results in a load current
that is essentially dc. For a dc load current, the diode and ac line currents are
shown in Fig. 4-17. The Fourier series of the currents in phase a of the ac line is
223 1 1 1 1
i a(t) I acos 0t cos 50t cos 70t cos 110t cos 130t Á b (4-46)
o 5 7 11 13
which consists of terms at the fundamental frequency of the ac system and har-
monics of order 6k 1, k 1, 2, 3, . . . .
Because these harmonic currents may present problems in the ac system, fil-
ters are frequently necessary to prevent these harmonics from entering the ac sys-
tem. A typical filtering scheme is shown in Fig. 4-18. Resonant filters are used to
provide a path to ground for the fifth and seventh harmonics, which are the two
lowest and are the strongest in amplitude. Higher-order harmonics are reduced
with the high-pass filter. These filters prevent the harmonic currents from propa-
gating through the ac power system. Filter components are chosen such that the
impedance to the power system frequency is large.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 147
io
iD1
iD2
iD3
iD4
iD5
iD6
ia
ib
ic
Figure 4-17 Three-phase rectifier currents when the output is

filtered.
EXAMPLE 4-12
Three-Phase Rectifier
The three-phase rectifier of Fig. 4-16a has a three-phase source of 480 V rms line-to-line,
and the load is a 25- resistance in series with a 50-mH inductance. Determine (a) the dc
level of the output voltage, (b) the dc and first ac term of the load current, (c) the average
and rms current in the diodes, (d) the rms current in the source, and (e) the apparent power
from the source.
■ Solution
(a) The dc output voltage of the bridge is obtained from Eq. (4-44).
3Vm, LL 322 (480)

Vo 648 V

φ Conductor
AC 6-Pulse
System Converter
(Each Phase)
5th 7th High Pass
Figure 4-18 Filters for ac line harmonics.

har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 148
(b) The average load current is

Vo 648
Io 25.9 A
R 25
The first ac voltage term is obtained from Eq. (4-45) with n 6, and current is
V6 0.0546Vm 0.054612(480) 37.0 V
I6 0.32 A
Z6 1R2 (6L)2 1252 [6(377)(0.05)]2 115.8 Æ
0.32
I6, rms 0.23 A
12
This and other ac terms are much smaller than the dc term and can be neglected.
(c) Average and rms diode currents are obtained from Eq. (4-41). The rms load current
is approximately the same as average current since the ac terms are small.
I 25.9
ID, avg o 8.63 A
3 3
Io, rms 25.9
ID, rms L 15.0 A
13 13
(d) The rms source current is also obtained from Eq. (4-41).
2 2
Is, rms a bI a b 25.9 21.2 A
A 3 o, rms
L
A3
(e) The apparent power from the source is determined from Eq. (4-42).
S 23(VLL, rms)(Is, rms) 23 (480)(21.2) 17.6 kVA
PSpice Solution
A circuit for this example is shown in Fig. 4-19a. VSIN is used for each of the sources.
Dbreak, with the model changed to make n 0.01, approximates an ideal diode.
A transient analysis starting at 16.67 ms and ending at 50 ms represents steady-state
currents.
THREE-PHASE RECTIFIER
out+
PARAMETERS:
Vrms = 480
D1 D3 D5
A Dbreak Dbreak Dbreak
B R1
25
C 1
VA VB VC L1
+ + +
– – – 50m
D4 D6 D2
Dbreak Dbreak Dbreak 2
0 PHASE = –120 PHASE = –240 out–
VOFF = 0
VAMPL = [Vrms*sqrt(2/3)]
FREQ = 60
PHASE = 0
(a)
Figure 4-19 (a) PSpice circuit for a three-phase rectifier; (b) Probe output showing
the current waveform and the Fourier analysis in one phase of the source.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 149
4.5 Controlled Three-Phase Rectifiers 149
40 A
SOURCE PHASE CURRENT
0A
–40 A
10 ms 20 ms 30 ms 40 ms 50 ms
I (VA)
Time
30 A
(60.006, 28.606)
20 A n=1
(300.030, 5.7521) (420.042, 4.0529)
10 A n=5 n=7
SEL>> n = 11 n = 13
0A
0 Hz 200 Hz 400 Hz 600 Hz 800 Hz
I (VA)
Frequency
(b)
All the circuit currents as calculated above can be verified. The Probe output
in Fig. 4-19b shows the current and Fourier (FFT) components in one of the
sources. Note that the harmonics correspond to those in Eq. (4-46).
4.5 CONTROLLED THREE-PHASE RECTIFIERS

The output of the three-phase rectifier can be controlled by substituting SCRs for
diodes. Figure 4-20a shows a controlled six-pulse three-phase rectifier. With
SCRs, conduction does not begin until a gate signal is applied while the SCR is
forward-biased. Thus, the transition of the output voltage to the maximum in-
stantaneous line-to-line source voltage can be delayed. The delay angle is ref-
erenced from where the SCR would begin to conduct if it were a diode. The delay
angle is the interval between when the SCR becomes forward-biased and when
the gate signal is applied. Figure 4-20b shows the output of the controlled recti-
fier for a delay angle of 45.
The average output voltage is
2>3
1 3Vm, LL
Vo Vm, LL sin (t) d(t) cos (4-47)
>3 3
>3
Equation (4-47) shows that the average output voltage is reduced as the delay
angle increases.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 150
S1 S3 S5
+
Aφ Bφ Cφ Load vo
–
S4 S6 S2
(a)
α
vo
ωt
(b)
Figure 4-20 (a) A controlled three-phase rectifier; (b) Output

voltage for 45.
Harmonics for the output voltage remain of order 6k, but the amplitudes
are functions of . Figure 4-21 shows the first three normalized harmonic
amplitudes.
EXAMPLE 4-13
A Controlled Three-Phase Rectifier

A three-phase controlled rectifier has an input voltage which is 480 V rms at 60 Hz. The
load is modeled as a series resistance and inductance with R 10 and L 50 mH.
(a) Determine the delay angle required to produce an average current of 50 A in the
load. (b) Determine the amplitude of harmonics n 6 and n 12.
■ Solution
(a) The required dc component in the bridge output voltage is
Vo Io R (50)(10) 500 V
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 151
0.4
n=6
0.3
Vn /Vm
0.2
n = 12
n = 18
0.1
0.0
0 40 80 120 160 200
Delay Angle (degrees)
Figure 4-21 Normalized output voltage harmonics as a

function of delay angle for a three-phase rectifier.
Equation (4-47) is used to determine the required delay angle:
Vo 500
cos 1 a b cos 1 a b 39.5°
3Vm, LL 312(480)
(b) Amplitudes of harmonic voltages are estimated from the graph in Fig. 4-21. For
39.5, normalized harmonic voltages are V6 /Vm L 0.21 and V12 /Vm L 0.10.
Using Vm 12(480), V6 143 V, and V12 68 V, harmonic currents are then
V6 143
I6 1.26 A
Z6 110 2 [6(377)(0.05)]2
V12 68
I12 0.30 A
Z12 110 [12(377)(0.05)]2
2
Twelve-Pulse Rectifiers
The three-phase six-pulse bridge rectifier shows a marked improvement in the
quality of the dc output over that of the single-phase rectifier. Harmonics of
the output voltage are small and at frequencies that are multiples of 6 times the
source frequency. Further reduction in output harmonics can be accomplished by
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 152
Aφ Bφ Cφ
+
Y Y
voY
+
–
Load vo
+
Y Δ
voΔ –
(a)
vo
voY voΔ
0
(b)
Figure 4-22 (a) A 12-pulse three-phase rectifier; (b) Output

voltage for 0.
using two six-pulse bridges as shown in Fig. 4-22a. This configuration is called
a 12-pulse converter.
One of the bridges is supplied through a Y-Y connected transformer, and
the other is supplied through a Y- (or -Y) transformer as shown. The
purpose of the Y- transformer connection is to introduce a 30 phase shift
between the source and the bridge. This results in inputs to the two bridges
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 153
which are 30 apart. The two bridge outputs are similar, but also shifted by
30. The overall output voltage is the sum of the two bridge outputs. The delay
angles for the bridges are typically the same. The dc output is the sum of the
dc output of each bridge
3Vm, LL 3V 6V
Vo Vo, Y Vo, cos m, LL cos m, LL cos (4-48)

The peak output of the 12-pulse converter occurs midway between alternate
peaks of the 6-pulse converters. Adding the voltages at that point for 0 gives
Vo, peak 2Vm, LL cos (15°) 1.932 Vm, LL (4-49)
Figure 4-22b shows the voltages for 0.

Since a transition between conducting thyristors occurs every 30, there are
a total of 12 such transitions for each period of the ac source. The output has har-
monic frequencies that are multiples of 12 times the source frequency (12k, k 1,
2, 3, . . .). Filtering to produce a relatively pure dc output is less costly than that
required for the 6-pulse rectifier.
Another advantage of using a 12-pulse converter rather than a 6-pulse con-
verter is the reduced harmonics that occur in the ac system. The current in the ac
lines supplying the Y-Y transformer is represented by the Fourier series
2 23 1 1
i Y (t) Io a cos 0t cos 50t cos 70t
5 7
(4-50)
1 1
cos110t cos130t .. . b
11 13
The current in the ac lines supplying the Y- transformer is represented by the
Fourier series
2 23 1 1
i (t) I a cos0t cos 50 t cos70t
o 5 7
(4-51)
1 1
cos110t cos130t ... b
11 13
The Fourier series for the two currents are similar, but some terms have opposite
algebraic signs. The ac system current, which is the sum of those transformer
currents, has the Fourier series
i ac (t) i Y (t) i (t)
(4-52)
423 1 1
I a cos0t cos110t cos130t . . . b
o 11 13
Thus, some of the harmonics on the ac side are canceled by using the 12-pulse
scheme rather than the 6-pulse scheme. The harmonics that remain in the ac
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 154
system are of order 12k 1. Cancellation of harmonics 6(2n1) 1 has

resulted from this transformer and converter configuration.
This principle can be expanded to arrangements of higher pulse numbers by
incorporating increased numbers of 6-pulse converters with transformers that
have the appropriate phase shifts. The characteristic ac harmonics of a p-pulse
converter will be pk 1, k 1, 2, 3, . . . . Power system converters have a practi-
cal limitation of 12 pulses because of the large expense of producing high-voltage
transformers with the appropriate phase shifts. However, lower-voltage indus-
trial systems commonly have converters with up to 48 pulses.
The Three-Phase Converter Operating as an Inverter

The above discussion focused on circuits operating as rectifiers, meaning that the
power flow is from the ac side of the converter to the dc side. It is also possible
for the three-phase bridge to operate as an inverter, having power flow from the
dc side to the ac side. A circuit that enables the converter to operate as an inverter
is shown in Fig. 4-23a. Power is supplied by the dc source, and power is
io
+ R L
+
vo vdc
Aφ Bφ Cφ
–
–
(a)
vo
(b)
Figure 4-23 (a) Six-pulse three-phase converter operating as

an inverter; (b) Bridge output voltage for 150.
har80679_ch04_111-170.qxd 12/17/09 2:37 PM Page 155
absorbed by the converter and transferred to the ac system. The analysis of the
three-phase inverter is similar to that of the single-phase case.
The dc current must be in the direction shown because of the SCRs in the
bridge. For power to be absorbed by the bridge and transferred to the ac system,
the bridge output voltage must be negative. Equation (4-47) applies, so a delay
angle larger than 90⬚ results in a negative bridge output voltage.
0 ⬍ ␣ ⬍90° Vo ⬎ 0 : rectifier operation
(4-53)
90° ⬍ ␣ ⬍180° Vo ⬍ 0 : inverter operation
The output voltage waveform for ␣ ⫽ 150⬚ and continuous load current is shown
in Fig. 4-23b.
EXAMPLE 4-14
Three-Phase Bridge Operating as an Inverter

The six-pulse converter of Fig. 4-23a has a delay angle ␣ ⫽ 120⬚. The three-phase ac sys-
tem is 4160 V rms line-to-line. The dc source is 3000 V, R ⫽ 2 ⍀, and L is large enough
to consider the current to be purely dc. (a) Determine the power transferred to the ac
source from the dc source. (b) Determine the value of L such that the peak-to-peak vari-
ation in load current is 10 percent of the average load current.
■ Solution
(a) The dc output voltage of the bridge is computed from Eq. (4-47) as
3Vm, L⫺L 322 (4160)

Vo ⫽ cos ␣ ⫽ cos (120°) ⫽ ⫺ 2809 V
␲ ␲
The average output current is
Vo ⫹ Vdc ⫺2809 ⫹ 3000

Io ⫽ ⫽ ⫽ 95.5 A
R 2
The power absorbed by the bridge and transferred back to the ac system is
Pac ⫽ ⫺ IoVo ⫽ ( ⫺95.5)( ⫺2809) ⫽ 268.3 kW
Power supplied by the dc source is

Pdc ⫽ IoVdc ⫽ (95.5)(3000) ⫽ 286.5 kW
Power absorbed by the resistance is
PR ⫽ I 2rms R L I 2o R ⫽ (95.5)2(2) ⫽ 18.2 kW
(b) Variation in load current is due to the ac terms in the Fourier series. The load
current amplitudes for each of the ac terms is
Vn
In ⫽
Zn
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 156
where Vn can be estimated from the graph of Fig. 4-21 and

Zn ƒ R jn0L ƒ
Since the decreasing amplitude of the voltage terms and the increasing magnitude of the
impedance both contribute to diminishing ac currents as n increases, the peak-to-peak
current variation will be estimated from the first ac term. For n 6, Vn/Vm is estimated
from Fig. 4-21 as 0.28, making V6 0.28(4160 12) 1650 V. The peak-to-peak varia-
tion of 10 percent corresponds to a zero-to-peak amplitude of (0.05)(95.5) 4.8 A. The
required load impedance for n 6 is then
V6 1650 V
Z6 343 Æ
I6 4.8 A
The 2- resistor is insignificant compared to the total 343- required impedance, so
Z6 L 60L. Solving for L,
Z6 343
L L 0.15 H
60 6(377)
4.6 DC POWER TRANSMISSION

The controlled 12-pulse converter of Fig. 4-22a is the basic element for dc power
transmission. DC transmission lines are commonly used for transmission of elec-
tric power over very long distances. Examples include the Pacific Intertie; the
Square Butte Project from Center, North Dakota, to Duluth, Minnesota; and the
Cross Channel Link under the English Channel between England and France. Mod-
ern dc lines use SCRs in the converters, while very old converters used mercury-
arc rectifiers.
Advantages of dc power transmission include the following:
1. The inductance of the transmission line has zero impedance to dc, whereas
the inductive impedance for lines in an ac system is relatively large.
2. The capacitance that exists between conductors is an open circuit for dc. For
ac transmission lines, the capacitive reactance provides a path for current,
resulting in additional I2R losses in the line. In applications where the
conductors are close together, the capacitive reactance can be a significant
problem for ac transmission lines, whereas it has no effect on dc lines.
3. There are two conductors required for dc transmission rather than three for
conventional three-phase power transmission. (There will likely be an
additional ground conductor in both dc and ac systems.)
4. Transmission towers are smaller for dc than ac because of only two
conductors, and right-of-way requirements are less.
5. Power flow in a dc transmission line is controllable by adjustment of the delay
angles at the terminals. In an ac system, power flow over a given transmission
line is not controllable, being a function of system generation and load.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 157
6. Power flow can be modulated during disturbances on one of the ac systems,

resulting in increased system stability.
7. The two ac systems that are connected by the dc line do not need to be in
synchronization. Furthermore, the two ac systems do not need to be of the
same frequency. A 50-Hz system can be connected to a 60-Hz system via a
dc link.
The disadvantage of dc power transmission is that a costly ac-dc converter,
filters, and control system are required at each end of the line to interface with the
ac system.
Figure 4-24a shows a simplified scheme for dc power transmission using
six-pulse converters at each terminal. The two ac systems each have their own
generators, and the purpose of the dc line is to enable power to be interchanged
between the ac systems. The directions of the SCRs are such that current io will
be positive as shown in the line.
In this scheme, one converter operates as a rectifier (power flow from ac to dc),
and the other terminal operates as an inverter (power flow from dc to ac). Either
terminal can operate as a rectifier or inverter, with the delay angle determining
the mode of operation. By adjusting the delay angle at each terminal, power flow
is controlled between the two ac systems via the dc link.
The inductance in the dc line is the line inductance plus an extra series
inductor to filter harmonic currents. The resistance is that of the dc line conduc-
tors. For analysis purposes, the current in the dc line may be considered to be a
ripple-free dc current.
R L
+ io –
AC AC
System vo1 vo2 System
1 2
– +
DC
Transmission
Line
io
R
+ –
Vo1 Vo2
– +
Figure 4-24 (a) An elementary dc transmission system; (b) Equivalent circuit.

har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 158
Voltages at the terminals of the converters Vo1 and Vo2 are positive as shown
for between 0 and 90 and negative for between 90 and 180. The converter
supplying power will operate with a positive voltage while the converter absorb-
ing power will have a negative voltage.
With converter 1 in Fig. 4-24a operating as a rectifier and converter 2 oper-
ating as an inverter, the equivalent circuit for power computations is shown in
Fig. 4-24b. The current is assumed to be ripple-free, enabling only the dc com-
ponent of the Fourier series to be relevant. The dc current is
Vo1 Vo2
Io (4-54)
R
where
3Vm1, LL
Vo1 cos 1

(4-55)
3Vm2, LL
Vo2 cos 2

Power supplied by the converter at terminal 1 is
P1 Vo1 Io (4-56)
Power supplied by the converter at terminal 2 is
P2 Vo2 Io (4-57)
EXAMPLE 4-15
DC Power Transmission
For the elementary dc transmission line represented in Fig. 4-24a, the ac voltage to each
of the bridges is 230 kV rms line to line. The total line resistance is 10 , and the induc-
tance is large enough to consider the dc current to be ripple-free. The objective is to trans-
mit 100 MW to ac system 2 from ac system 1 over the dc line. Design a set of operating
parameters to accomplish this objective. Determine the required current-carrying capac-
ity of the dc line, and compute the power loss in the line.
■ Solution
The relationships that are required are from Eqs. (4-54) to (4-57), where
P2 IoVo2 100 MW (100 MW absorbed)
The maximum dc voltage that is obtainable from each converter is, for 0 in
Eq. (4-47),
3Vm, LL 322 (230 kV)
Vo, max 310.6 kV

har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 159
The dc output voltages of the converters must have magnitudes less than 310.6 kV, so a
voltage of 200 kV is arbitrarily selected for converter 2. This voltage must be negative
because power must be absorbed at converter 2. The delay angle at converter 2 is then
3Vm, LL
Vo2 cos 2 (310.6 kV) cos 2 200 kV

Solving for 2,
200 kV
2 cos 1 a b 130°
310.6 kV
The dc current required to deliver 100 MW to converter 2 is then
100 MW
Io 500 A
200 kV
which is the required current-carrying capacity of the line.
The required dc output voltage at converter 1 is computed as
Vo1 Vo2 Io R 200 kV (500)(10) 205 kV
The required delay angle at converter 1 is computed from Eq. (4-47).

205 kV
1 cos 1 48.7°
310.6 kV
Power loss in the line is I2rmsR, where Irms L Io because the ac components of line current
are filtered by the inductor. Line loss is
Ploss I 2rmsR L (500)2 (10) 2.5 MW
Note that the power supplied at converter 1 is
P1 Vdc1Io (205 kV)(500 A) 102.5 MW
which is the total power absorbed by the other converter and the line resistance.
Certainly other combinations of voltages and current will meet the design objectives,
as long as the dc voltages are less than the maximum possible output voltage and the line
and converter equipment can carry the current. A better design might have higher volt-
ages and a lower current to reduce power loss in the line. That is one reason for using
12-pulse converters and bipolar operation, as discussed next.
A more common dc transmission line has a 12-pulse converter at each ter-

minal. This suppresses some of the harmonics and reduces filtering require-
ments. Moreover, a pair of 12-pulse converters at each terminal provides bipolar
operation. One of the lines is energized at Vdc and the other is energized
at Vdc. In emergency situations, one pole of the line can operate without the
other pole, with current returning through the ground path. Figure 4-25 shows a
bipolar scheme for dc power transmission.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 160
Y Y Y Y
12-Pulse
Y Δ Δ Y
Converter
Y Y Y Y
Y Δ Δ Y
AC system 1 DC line AC system 2
Figure 4-25 A dc transmission system with two 12-pulse converters at each

terminal.
4.7 COMMUTATION: THE EFFECT

OF SOURCE INDUCTANCE
Single-Phase Bridge Rectifier
An uncontrolled single-phase bridge rectifier with a source inductance Ls and an
inductive load is shown in Fig. 4-26a. When the source changes polarity, source
current cannot change instantaneously, and current must be transferred gradu-
ally from one diode pair to the other over a commutation interval u, as shown in
Fig. 4-26b. Recall from Chap. 3 that commutation is the process of transferring
the load current from one diode to another or, in this case, one diode pair to the
other. (See Sec. 3.11.) During commutation, all four diodes are on, and the volt-
age across Ls is the source voltage Vm sin (t).
Assume that the load current is a constant Io. The current in Ls and the source
during the commutation from D1-D2 to D3-D4 starts at Io and goes to Io. This
commutation interval starts when the source changes polarity at t as is
expressed in
t
1
i s(t) V sin (t) d(t) Io
L s 3 m

Evaluating,
Vm
i s(t) (1 cos t) Io (4-58)
L s
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4.7 Commutation: The Effect of Source Inductance 161
is + vLs –
+
D1 D3 Io
+
vs = Vm sin wt vo
–
D4 D2
–
(a)
Vm
vo
Io
iD1
0
Io
iD3
0
Io
is 0
–Io
u
(b)
Figure 4-26 Commutation for the single-phase rectifier (a) circuit

with source inductance Ls; (b) voltage and current waveforms.
When commutation is complete at ␻t ⫽ ␲ ⫹ u,

Vm
i(␲ ⫹ u) ⫽ ⫺ Io ⫽ ⫺ 31 ⫹ cos (␲ ⫹ u)4 ⫹ Io (4-59)
␻L S
Solving for the commutation angle u,
2Io␻L S 2I X
u ⫽ cos ⫺1 a 1 ⫺ b ⫽ cos⫺1 a 1 ⫺ o S b (4-60)
Vm Vm
where Xs ⫽ ␻Ls is the reactance of the source. Figure 4-26b shows the effect of
the source reactance on the load current and voltage.
Average load voltage is
␲
1 V
Vo ⫽ Vm sin (␻t)d(␻t) ⫽ m (1 ⫹ cos u)
␲3 ␲
u
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 162
Using u from Eq. (4-60),

2Vm Io Xs
Vo a1 b (4-61)
Vm
Thus, source inductance lowers the average output voltage of full-wave rectifiers.
Three-Phase Rectifier
For the uncontrolled three-phase bridge rectifier with source reactance (Fig. 4-27a),
assume that diodes D1 and D2 are conducting and the load current is a constant Io.
The next transition has load current transferred from D1 to D3 in the top half of
the bridge. The equivalent circuit during commutation from D1 to D3 is shown in
Fig. 4-27b. The voltage across La is
vAB Vm, LL
vLa sin (t) (4-62)
2 2
Current in La starts at Io and decreases to zero in the commutation interval,
u
1 Vm, LL
i La( u) 0 sin (t) d(t) Io (4-63)
L a 3 2

+
La D1 D3 D5 Io
vA
Lb
vB vo
Lc
vC
D4 D6 D2
–
(a)
+ vLa – D1 D3 Io
vA
La
vB
Lb
vC
Lc
D2
(b)
Figure 4-27 Commutation for the three-

phase rectifier. (a) Circuit; (b) Circuit
during commutation from D1 to D3;
(c) Output voltage and diode currents.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 163
4.8 Summary 163
vo
vo
vBC
vAC
u
vBC + vAC
Io 2
iD1
0
Io
iD3
0
(c)
Solving for u,
2L aIo 2XsIo
u cos1 a 1 b cos1 a 1 b (4-64)
Vm, LL Vm, LL
During the commutation interval from D1 to D3, the converter output voltage is
vbc vac
vo (4-65)
2
Output voltage and diode currents are shown in Fig. 4-27c. Average output volt-
age for the three-phase converter with a nonideal source is
3Vm, LL XsIo
Vo a1 b (4-66)
Vm, LL
Therefore, source inductance lowers the average output voltage of three-phase
rectifiers.
4.8 Summary
• Single-phase full-wave rectifiers can be of the bridge or center-tapped transformer
types.
• The average source current for single-phase full-wave rectifiers is zero.
• The Fourier series method can be used to analyze load currents.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 164
• A large inductor in series with a load resistor produces a load current that is
essentially dc.
• A filter capacitor on the output of a rectifier can produce an output voltage that is
nearly dc. An LC output filter can further improve the quality of the dc output and
reduce the peak current in the diodes.
• Switches such as SCRs can be used to control the output of a single-phase or three-
phase rectifier.
• Under certain circumstances, controlled converters can be operated as inverters.
• The 6-pulse three-phase rectifiers have 6 diodes or SCRs, and 12-pulse rectifiers
have 12 diodes or SCRs.
• Three-phase bridge rectifiers produce an output that is inherently like dc.
• DC power transmission has a three-phase converter at each end of a dc line. One
converter is operated as a rectifier and the other is operated as a converter.
• Source inductance reduces the dc output of a single-phase or three-phase rectifier.
4.9 Bibliography
S. B. Dewan and A. Straughen, Power Semiconductor Circuits, Wiley, New York, 1975.
J. Dixon, Power Electronics Handbook, edited by M. H. Rashid, Academic Press, San
Diego, 2001, Chapter 12.
E. W. Kimbark, Direct Current Transmission, Wiley-Interscience, New York, 1971.
P. T. Krein, Elements of Power Electronics, Oxford University Press, 1998.
Y.-S. Lee and M. H. L. Chow, Power Electronics Handbook, edited by M. H. Rashid,
Academic Press, San Diego, 2001, Chapter 10.
Upper Saddle River, N.J., 2004.
Problems
Uncontrolled Single-Phase Rectifiers
4-1. A single-phase full-wave bridge rectifier has a resistive load of 18 and an ac
source of 120-V rms. Determine the average, peak, and rms currents in the load
and in each diode.
4-2. A single-phase rectifier has a resistive load of 25 . Determine the average
current and peak reverse voltage across each of the diodes for (a) a bridge
rectifier with an ac source of 120 V rms and 60 Hz and (b) a center-tapped
transformer rectifier with 120 V rms on each half of the secondary winding.
4-3. A single-phase bridge rectifier has an RL load with R 15 and L 60 mH.
The ac source is vs 100 sin (377t) V. Determine the average and rms currents
in the load and in each diode.
The ac source is vs 170 sin (377t) V. Determine the average and rms currents
in the load and in each diode.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 165
Problems 165

The ac source is 120 V rms, 60 Hz. Determine (a) the average load current,
(b) the power absorbed by the load, and (c) the power factor.
The ac source is 120 V rms and 60 Hz. Determine (a) the average load current,
(b) the power absorbed by the load, and (c) the power factor.
4-7. A single-phase center-tapped transformer rectifier has an ac source of 240 V rms
and 60 Hz. The overall transformer turns ratio is 3:1 (80 V between the extreme
ends of the secondary and 40 V on each tap). The load is a resistance of 4 .
Determine (a) the average load current, (b) the rms load current, (c) the average
source current, and (d) the rms source current. Sketch the current waveforms of
the load and the source.
4-8. Design a center-tapped transformer rectifier to produce an average current of
10.0 A in a 15- resistive load. Both 120- and 240-V rms 60-Hz sources are
available. Specify which source to use and specify the turns ratio of the
transformer.
4-9. Design a center-tapped transformer rectifier to produce an average current of
5.0 A in an RL load with R 10 and L 50 mH. Both 120- and 240-V rms
60-Hz sources are available. Specify which source to use and specify the turns
ratio of the transformer.
4-10. An electromagnet is modeled as a 200-mH inductance in series with a 4-
resistance. The average current in the inductance must be 10 A to establish the
required magnetic field. Determine the amount of additional series resistance
required to produce the required average current from a bridge rectifier supplied
from a single-phase 120-V, 60-Hz source.
4-11. The full-wave rectifier of Fig. 4-3a has vs(t) 170 sin t V, R 3 , L 15 mH,
Vdc 48 V, and 2(60) rad/s. Determine (a) the power absorbed by the dc
source, (b) the power absorbed by the resistor, and (c) the power factor. (d) Estimate
the peak-to-peak variation in the load current by considering only the first ac term in
the Fourier series for current.
4-12. The full-wave rectifier of Fig. 4-3a has vs(t) 340 sin t V, R 5 , L 40 mH,
Vdc 96 V, and 2(60) rad/s. Determine (a) the power absorbed by the dc
source, (b) the power absorbed by the resistor, and (c) the power factor. (d) Estimate
the peak-to-peak variation in the load current by considering only the first ac term in
the Fourier series for current.
4-13. The peak-to-peak variation in load current in Example 4-1 based on I2 was
estimated to be 6.79 A. Compare this estimate with that obtained from a PSpice
simulation. (a) Use the default diode model Dbreak. (b) Modify the diode model
to make n 0.01 to approximate an ideal diode.
4-14. (a) In Example 4-3, the inductance is changed to 8 mH. Simulate the circuit in
PSpice and determine whether the inductor current is continuous or discontinuous.
Determine the power absorbed by the dc voltage using PSpice. (b) Repeat part (a),
using L 4 mH.
4-15. The single-phase full-wave bridge rectifier of Fig. 4-5a has an RL-source load
with R 4 , L 40 mH, and Vdc 24 V. The ac source is 120 V rms at 60 Hz.
Determine (a) the power absorbed by the dc source, (b) the power absorbed by
the resistor, and (c) the power factor.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 166
4-16. The single-phase full-wave bridge rectifier of Fig. 4-5a has an RL-source load
with R 5 , L 60 mH, and Vdc 36 V. The ac source is 120 V rms at 60 Hz.
Determine (a) the power absorbed by the dc source, (b) the power absorbed by
the resistor, and (c) the power factor.
4-17. Simulate the circuit of Prob. 4-16 using L 40 mH and again with L 100 H.
Discuss the differences in the behavior of the circuits for the two inductors.
Observe steady-state conditions. Use the PSpice default diode model.
4-18. The full-wave rectifier of Fig. 4-6 has a 120-V rms 60 Hz source and a load
resistance of 200 . Determine the filter capacitance required to limit the peak-
to-peak output voltage ripple to 1 percent of the dc output. Determine the peak
and average diode currents.
4-19. The full-wave rectifier of Fig. 4-6 has a 60-Hz ac source with Vm 100 V. It
is to supply a load that requires a dc voltage of 100 V and will draw 0.5 A.
Determine the filter capacitance required to limit the peak-to-peak output
voltage ripple to 1 percent of the dc output. Determine the peak and average
diode currents.
4-20. In Example 3-9, the half-wave rectifier of Fig. 3-11a has a 120 V rms source at
60 Hz, R 500 . The capacitance required for a 1 percent ripple in output
voltage was determined to be 3333 F. Determine the capacitance required for a
1 percent ripple if a full-wave rectifier is used instead. Determine the peak diode
currents for each circuit. Discuss the advantages and disadvantages of each
circuit.
4-21. Determine the output voltage for the full-wave rectifier with an LC filter of
Fig. 4-8a if L 10 mH and (a) R 7 and (b) R 20 . The source is
120 V rms at 60 Hz. Assume the capacitor is sufficiently large to produce a
ripple-free output voltage. (c) Modify the PSpice circuit in Example 4-5 to
determine Vo for each case. Use the default diode model.
4-22. For the full-wave rectifier with an LC filter in Example 4-5, the inductor has a
series resistance of 0.5 . Use PSpice to determine the effect on the output
voltage for each load resistance.
Controlled Single-phase Rectifiers

4-23. The controlled single-phase bridge rectifier of Fig. 4-10a has a 20- resistive
load and has a 120-V rms, 60-Hz ac source. The delay angle is 45. Determine
(a) the average load current, (b) the rms load current, (c) the rms source current,
and (d) the power factor.
4-24. Show that the power factor for the controlled full-wave rectifier with a resistive
load is
sin(2 )
pf 1
A 2
4-25. The controlled single-phase full-wave bridge rectifier of Fig. 4-11a has an RL
load with R 25 and L 50 mH. The source is 240 V rms at 60 Hz.
Determine the average load current for (a) 15 and (b) 75.
4-26. The controlled single-phase full-wave bridge rectifier of Fig. 4-11a has an RL
load with R 30 and L 75 mH. The source is 120 V rms at 60 Hz.
Determine the average load current for (a) 20 and (b) 80.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 167
Problems 167
4-27. Show that the power factor for the full-wave rectifier with RL load where L is
large and the load current is considered dc is 2 12/.
4-28. A 20- resistive load requires an average current that varies from 4.5 to 8.0 A.
An isolation transformer is placed between a 120-V rms 60-Hz ac source and a
controlled single-phase full-wave rectifier. Design a circuit to meet the current
requirements. Specify the transformer turns ratio and the range of delay angle.
4-29. An electromagnet is modeled as a 100-mH inductance in series with a 5-
resistance. The average current in the inductance must be 10 A to establish the
required magnetic field. Determine the delay angle required for a controlled single-
phase rectifier to produce the required average current from a single-phase 120-V,
60-Hz source. Determine if the current is continuous or discontinuous. Estimate the
peak-to-peak variation in current based on the first ac term in the Fourier series.
4-30. The full-wave converter used as an inverter in Fig. 4-14 has an ac source of 240 V
rms at 60 Hz, R 10 , L 0.8 H, and Vdc 100 V. The delay angle for the
converter is 105. Determine the power supplied to the ac system from the dc
source. Estimate the peak-to-peak ripple in load current from the first ac term in
the Fourier series.
4-31. An array of solar cells produces 100 V dc. A single-phase ac power system is 120 V
rms at 60 Hz. (a) Determine the delay angle for the controlled converter in the
arrangement of Fig. 4-14 (Vdc 100) such that 2000 W is transmitted to the ac
system. Assume L is large enough to produce a current that is nearly ripple-free. The
equivalent resistance is 0.8 . Assume that the converter is lossless. (b) Determine
the power supplied by the solar cells. (c) Estimate the value of inductance such that
the peak-to-peak variation in solar cell current is less than 2.5 A.
4-32. An array of solar panels produces a dc voltage. Power produced by the solar
panels is to be delivered to an ac power system. The method of interfacing the
solar panels with the power system is via a full-wave SCR bridge as shown in
Fig. 4-14 except with the dc source having the opposite polarity. Individual solar
panels produce a voltage of 12 V. Therefore, the voltage from the solar panel array
can be established at any multiple of 12 by connecting the panels in appropriate
combinations. The ac source is 12(120) sin (377t) V. The resistance is 1 .
Determine values of Vdc, delay angle , and inductance L such that the power
delivered to the ac system is 1000 W and the maximum variation in solar panel
current is no more than 10 percent of the average current. There are several
solutions to this problem.
4-33. A full-wave converter operating as an inverter is used to transfer power from a
wind generator to a single-phase 240-V rms 60-Hz ac system. The generator
produces a dc output of 150 V and is rated at 5000 W. The equivalent resistance
in the generator circuit is 0.6 . Determine (a) the converter delay angle for
rated generator output power, (b) the power absorbed by the ac system, and
(c) the inductance required to limit the current peak-to-peak ripple to 10 percent
of the average current.
Three-phase Uncontrolled Rectifiers

4-34. A three-phase rectifier is supplied by a 480-V rms line-to-line 60-Hz source. The
load is a 50- resistor. Determine (a) the average load current, (b) the rms load
current, (c) the rms source current, and (d) the power factor.
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 168
load is an 80- resistor. Determine (a) the average load current, (b) the rms load
current, (c) the rms source current, and (d) the power factor.
RL load is a 100- resistor in series with a 15-mH inductor. Determine (a) the
average and rms load currents, (b) the average and rms diode currents, (c) the rms
source current, and (d) the power factor.
4-37. Use PSpice to simulate the three-phase rectifier of Prob. 4-31. Use the default
diode model Dbreak. Determine the average and rms values of load current,
diode current, and source current. Compare your results to Eq. (4-41). How much
power is absorbed by the diodes?
4-38. Using the PSpice circuit of Example 4-12, determine the harmonic content of the
line current in the ac source. Compare the results with Eq. (4-46). Determine the
total harmonic distortion of the source current.
Three-phase Controlled Rectifiers

4-39. The three-phase controlled rectifier of Fig. 4-20a is supplied from a 4160-V rms
line-to-line 60-Hz source. The load is a 120- resistor. (a) Determine the delay
angle required to produce an average load current of 25 A. (b) Estimate the
amplitudes of the voltage harmonics V6, V12, and V18. (c) Sketch the currents in
the load, S1, S4, and phase A of the ac source.
4-40. The three-phase controlled rectifier of Fig. 4-20a is supplied from a 480-V rms
line-to-line 60-Hz source. The load is a 50- resistor. (a) Determine the delay
angle required to produce an average load current of 10 A. (b) Estimate the
amplitudes of the voltage harmonics V6, V12, and V18. (c) Sketch the currents in
the load, S1, S4, and phase A of the ac source.
4-41. The six-pulse controlled three-phase converter of Fig. 4-20a is supplied from a
480-V rms line-to-line 60-Hz three-phase source. The delay angle is 35, and the
load is a series RL combination with R 50 and L 50 mH. Determine
(a) the average current in the load, (b) the amplitude of the sixth harmonic
current, and (c) the rms current in each line from the ac source.
4-42. The six-pulse controlled three-phase converter of Fig. 4-20a is supplied
from a 480-V rms line-to-line 60-Hz three-phase source. The delay
angle is 50, and the load is a series RL combination with R 10 and
L 10 mH. Determine (a) the average current in the load, (b) the amplitude
of the sixth harmonic current, and (c) the rms current in each line from the
ac source.
4-43. The six-pulse controlled three-phase converter of Fig. 4-20a is supplied form a
480-V rms line-to-line 60-Hz three-phase source. The load is a series RL
combination with R 20 . (a) Determine the delay angle required for an
average load current of 20 A. (b) Determine the value of L such that the first ac
current term (n 6) is less than 2 percent of the average current. (c) Verify your
results with a PSpice simulation.
4-44. A three-phase converter is operating as an inverter and is connected to a 300-V
dc source as shown in Fig. 4-23a. The ac source is 240 V rms line to line at 60 Hz.
The resistance is 0.5 , and the inductor is large enough to consider the load
current to be ripple-free. (a) Determine the delay angle such that the output
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Problems 169
voltage of the converter is Vo 280 V. (b) Determine the power supplied or

absorbed by each component in the circuit. The SCRs are assumed to be ideal.
4-45. An inductor having superconducting windings is used to store energy. The
controlled six-pulse three-phase converter of Fig. 4-20a is used to recover the
stored energy and transfer it to a three-phase ac system. Model the inductor as a
1000-A current source load, and determine the required delay angle such that
1.5 MW is transferred to the ac system which is 4160 V line-to-line rms at 60 Hz.
What is the rms current in each phase of the ac system?
4-46. A power company has installed an array of solar cells to be used as an energy
source. The array produces a dc voltage of 1000 V and has an equivalent series
resistance of 0.1 . The peak-to-peak variation in solar cell current should not
exceed 5 percent of the average current. The interface between the solar cell
array and the ac system is the controlled six-pulse three-phase converter of
Fig. 4-23a. A three-phase transformer is placed between the converter and a
12.5-kV line-to-line rms 60-Hz ac line. Design a system to transfer 100 kW
to the ac power system from the solar cell array. (The ac system must absorb
100 kW.) Specify the transformer turns ratio, converter delay angle, and the
values of any other circuit components. Determine the power loss in the
resistance.
Dc Power Transmission
4-47. For the elementary dc transmission line represented in Fig. 4-24a, the ac voltage
to each of the bridges is 345 kV rms line to line. The total line resistance is 15 ,
and the inductance is large enough to consider the dc current to be ripple-free.
AC system 1 is operated with 45.0, and ac system 2 has 134.4.
(a) Determine the power absorbed or supplied by each ac system. (b) Determine
the power loss in the line.
to each of the bridges is 230 kV rms line to line. The total line resistance is 12 ,
The objective is to transmit 80 MW to ac system 2 from ac system 1 over the dc
line. Design a set of operating parameters to accomplish this objective.
Determine the required current-carrying capacity of the dc line, and compute the
power loss in the line.
to each of the bridges is 345 kV rms line-to-line. The total line resistance is 20 ,
The objective is to transmit 300 MW to ac system 2 from ac system 1 over the dc
line. Design a set of operating parameters to accomplish this objective. Determine
the required current-carrying capacity of the dc line, and compute the power loss
in the line.
Design Problems
4-50. Design a circuit that will produce an average current that is to vary from 8 to 12 A
in an 8- resistor. Single-phase ac sources of 120 and 240 V rms at 60 Hz are
available. The current must have a peak-to-peak variation of no more than 2.5 A.
Determine the average and rms currents and maximum voltage for each circuit
har80679_ch04_111-170.qxd 12/15/09 3:48 PM Page 170
element. Simulate your circuit in PSpice to verify that it meets the specifications.
Give alternative circuits that could be used to satisfy the design specifications,
and give reasons for your selection.
4-51. Design a circuit that will produce a current which has an average value of 15 A in
a resistive load of 20 . The peak-to-peak variation in load current must be no
more than 10 percent of the dc current. Voltage sources available are a single-
phase 480 V rms, 60 Hz source and a three-phase 480 V rms line-to-line 60 Hz
source. You may include additional elements in the circuit. Determine the
average, rms, and peak currents in each circuit element. Simulate your circuit in
PSpice to verify that it meets the specifications. Give alternative circuits that
selection.
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 171
C H A P T E R 5
AC Voltage Controllers
AC to ac Converters
5.1 INTRODUCTION
An ac voltage controller is a converter that controls the voltage, current, and aver-
age power delivered to an ac load from an ac source. Electronic switches connect
and disconnect the source and the load at regular intervals. In a switching scheme
called phase control, switching takes place during every cycle of the source, in
effect removing some of the source waveform before it reaches the load. Another
type of control is integral-cycle control, whereby the source is connected and dis-
connected for several cycles at a time.
The phase-controlled ac voltage controller has several practical uses including
light-dimmer circuits and speed control of induction motors. The input voltage
source is ac, and the output is ac (although not sinusoidal), so the circuit is classi-
fied as an ac-ac converter.
5.2 THE SINGLE-PHASE AC VOLTAGE

CONTROLLER
Basic Operation
A basic single-phase voltage controller is shown in Fig. 5-1a. The electronic
switches are shown as parallel thyristors (SCRs). This SCR arrangement makes
it possible to have current in either direction in the load. This SCR connection is
called antiparallel or inverse parallel because the SCRs carry current in opposite
directions. A triac is equivalent to the antiparallel SCRs. Other controlled switch-
ing devices can be used instead of SCRs.
171
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 172
172 C H A P T E R 5 AC Voltage Controllers
S1
+ vsw −
io
+ +
S2
vs R vo
− −
(a)
vs
io
π+α
ωt
0 α π 2π
vo
π+α
ωt
0 α π 2π
vsw
π+α
ωt
0 α π 2π
(b)
Figure 5-1 (a) Single-phase ac voltage controller with a

resistive load; (b) Waveforms.
The principle of operation for a single-phase ac voltage controller using phase

control is quite similar to that of the controlled half-wave rectifier of Sec. 3.9.
Here, load current contains both positive and negative half-cycles. An analysis
identical to that done for the controlled half-wave rectifier can be done on a half-
cycle for the voltage controller. Then, by symmetry, the result can be extrapo-
lated to describe the operation for the entire period.
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 173
5.2 The Single-Phase AC Voltage Controller 173
Some basic observations about the circuit of Fig. 5-1a are as follows:
1. The SCRs cannot conduct simultaneously.
2. The load voltage is the same as the source voltage when either SCR is on.
The load voltage is zero when both SCRs are off.
3. The switch voltage vsw is zero when either SCR is on and is equal to the
source voltage when neither is on.
4. The average current in the source and load is zero if the SCRs are on for
equal time intervals. The average current in each SCR is not zero because of
unidirectional SCR current.
5. The rms current in each SCR is 1/ 12 times the rms load current if the SCRs
are on for equal time intervals. (Refer to Chap. 2.)
For the circuit of Fig. 5-1a, S1 conducts if a gate signal is applied during the
positive half-cycle of the source. Just as in the case of the SCR in the controlled
half-wave rectifier, S1 conducts until the current in it reaches zero. Where this cir-
cuit differs from the controlled half-wave rectifier is when the source is in its neg-
ative half-cycle. A gate signal is applied to S2 during the negative half-cycle of the
source, providing a path for negative load current. If the gate signal for S2 is a half
period later than that of S1, analysis for the negative half-cycle is identical to that
for the positive half, except for algebraic sign for the voltage and current.
Single-Phase Controller with a Resistive Load

Figure 5-1b shows the voltage waveforms for a single-phase phase-controlled
voltage controller with a resistive load. These are the types of waveforms that
exist in a common incandescent light-dimmer circuit. Let the source voltage be
vs(t) Vm sin t (5-1)
Output voltage is
Vm sin t for t and t 2
vo(t) b (5-2)
0 otherwise
The rms load voltage is determined by taking advantage of positive and neg-
ative symmetry of the voltage waveform, necessitating evaluation of only a half-
period of the waveform:
1 Vm sin (2 )
Vo, rms 1 [Vm sin (t)]2 d(t) 1 (5-3)
A 12A 2
Note that for 0, the load voltage is a sinusoid that has the same rms value
as the source. Normalized rms load voltage is plotted as a function of in Fig. 5-2.
The rms current in the load and the source is
Vo, rms
Io, rms (5-4)
R
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Single-phase Voltage Controller

1.0
Normalized rms Output Voltage

0.8
0.6
0.4
0.2
0.0
0 40 80 120 160
Delay Angle (Degrees)
Figure 5-2 Normalized rms load voltage vs. delay angle for a single-phase ac
voltage controller with a resistive load.
and the power factor of the load is

P P V 2o, rms >R V
pf o, rms
S Vs, rms Is, rms Vs, rms(Vo, rms>R) Vs, rms
Vm (sin 2 )
1
12A 2

Vm> 12
sin (2 )
pf 1 (5-5)
A 2
Note that pf 1 for 0, which is the same as for an uncontrolled resistive

load, and the power factor for 0 is less than 1.
The average source current is zero because of half-wave symmetry. The
average SCR current is

1 Vm sin (t) Vm
ISCR, avg d(t) (1 cos ) (5-6)
2 3 R 2R

Since each SCR carries one-half of the line current, the rms current in each
SCR is
Io, rms
ISCR, rms (5-7)
12
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 175
Harmonics, Single-phase Controller

1.0
n=1
0.8
0.6
Cn
0.4
n=3
0.2
n=5
n=7
0.0
0 40 80 120 160
Figure 5-3 Normalized harmonic content vs. delay angle

for a single-phase ac voltage controller with a resistive
load; Cn is the normalized amplitude. (See Chap. 2.)
Since the source and load current is nonsinusoidal, harmonic distortion is a

consideration when designing and applying ac voltage controllers. Only odd har-
monics exist in the line current because the waveform has half-wave symmetry.
Harmonic currents are derived from the defining Fourier equations in Chap. 2.
Normalized harmonic content of the line currents vs. is shown in Fig. 5-3. Base
current is source voltage divided by resistance, which is the current for 0.
EXAMPLE 5-1
Single-Phase Controller with a Resistive Load

The single-phase ac voltage controller of Fig. 5-1a has a 120-V rms 60-Hz source. The
load resistance is 15
. Determine (a) the delay angle required to deliver 500 W to the load,
(b) the rms source current, (c) the rms and average currents in the SCRs, (d) the power
factor, and (e) the total harmonic distortion (THD) of the source current.
■ Solution
(a) The required rms voltage to deliver 500 W to a 15-
load is
V 2o, rms
P
R
Vo, rms 1PR 2(500)(15) 86.6 V
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The relationship between output voltage and delay angle is described by Eq. (5-3)
and Fig. 5-2. From Fig. 5-2, the delay angle required to obtain a normalized output
of 86.6/120 0.72 is approximately 90. A more precise solution is obtained from
the numerical solution for in Eq. (5-3), expressed as
sin (2 )
86.6 120 1 0
A 2
which yields
1.54 rad 88.1°
(b) Source rms current is
Vo, rms 86.6

Io, rms 5.77 A
R 15
(c) SCR currents are determined from Eqs. (5-6) and (5-7),
Irms 5.77
ISCR, rms 4.08 A
12 12
C 1 cos (88.1°) D 1.86 A

12 (120)
ISCR, avg
2(15)
(d) The power factor is
P 500
pf 0.72
S (120)(5.77)
which could also be computed from Eq. (5-5).

(e) Base rms current is
Vs, rms 120

Ibase 8.0 A
R 15
The rms value of the current’s fundamental frequency is determined from C1 in the
graph of Fig. 5-3.
C1 L 0.61 Q I1, rms C1Ibase (0.61)(8.0) 4.9 A
The THD is computed from Eq. (2-68),
2I 2rms I 21, rms 25.772 4.9 2

THD 0.63 63%
I1, rms 4.9
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Single-Phase Controller with an RL Load

Figure 5-4a shows a single-phase ac voltage controller with an RL load. When a
gate signal is applied to S1 at t , Kirchhoff’s voltage law for the circuit is
expressed as
di (t)
Vm sin (t) Ri o(t) L o (5-8)
dt
S1
+ vsw −
io
+
S2
+ R
vs vo
−
L
−
(a)
vs
io
π+α 2π
ωt
0 α π β
vo
β π+α
ωt
0 α π 2π
vsw
β π+α ωt
0 α
(b)
Figure 5-4 (a) Single-phase ac voltage controller with an RL

load; (b) Typical waveforms.
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 178
The solution for current in this equation, outlined in Sec. 3.9, is
Vm
csin(t ) sin( ) e(t)> d for t
Z
i o (t) d
0 otherwise
where (5-9)
L
Z 2R2 (L)2 , and tan1 a b
R
The extinction angle is the angle at which the current returns to zero,
when t ,
Vm
i o( ) 0 csin ( ) sin ( ) e()> d (5-10)
Z
which must be solved numerically for .

A gate signal is applied to S2 at t , and the load current is negative
but has a form identical to that of the positive half-cycle. Figure 5-4b shows typ-
ical waveforms for a single-phase ac voltage controller with an RL load.
The conduction angle is defined as
(5-11)
In the interval between and when the source voltage is negative and the
load current is still positive, S2 cannot be turned on because it is not forward-
biased. The gate signal to S2 must be delayed at least until the current in S1 reaches
zero, at t . The delay angle is therefore at least .
(5-12)
The limiting condition when is determined from an examination
of Eq. (5-10). When , Eq. (5-10) becomes
sin ( ) 0
which has a solution

Therefore,
when (5-13)
If , , provided that the gate signal is maintained beyond t .
In the limit, when , one SCR is always conducting, and the voltage
across the load is the same as the voltage of the source. The load voltage and cur-
rent are sinusoids for this case, and the circuit is analyzed using phasor analysis for
ac circuits. The power delivered to the load is continuously controllable between
the two extremes corresponding to full source voltage and zero.
har80679_ch05_171-195.qxd 12/17/09 2:39 PM Page 179
This SCR combination can act as a solid-state relay, connecting or disconnect-

ing the load from the ac source by gate control of the SCRs. The load is discon-
nected from the source when no gate signal is applied, and the load has the same
voltage as the source when a gate signal is continuously applied. In practice, the gate
signal may be a high-frequency series of pulses rather than a continuous dc signal.
An expression for rms load current is determined by recognizing that the
square of the current waveform repeats every ␲ rad. Using the definition of rms,
␤
1
Io, rms ⫽ i 2(␻t) d(␻t) (5-14)
C␲ L o
␣
where io(␻t) is described in Eq. (5-9).
Power absorbed by the load is determined from
P ⫽ I 2o, rms R (5-15)
The rms current in each SCR is
Io, rms
ISCR, rms ⫽ (5-16)
12
The average load current is zero, but each SCR carries one-half of the current
waveform, making the average SCR current
␤
1
ISCR, avg ⫽ i (␻t) d(␻t) (5-17)
2␲ 3 o
␣
EXAMPLE 5-2
Single-Phase Voltage Controller with RL Load

For the single-phase voltage controller of Fig. 5-4a, the source is 120 V rms at 60 Hz, and
the load is a series RL combination with R ⫽ 20 ⍀ and L ⫽ 50 mH. The delay angle ␣ is
90⬚. Determine (a) an expression for load current for the first half-period, (b) the rms load
current, (c) the rms SCR current, (d) the average SCR current, (e) the power delivered to
the load, and (f) the power factor.
■ Solution
(a) The current is expressed as in Eq. (5-9). From the parameters given,
Z ⫽ 2R2 ⫹ (␻L)2 ⫽ 3(20)2 ⫹ C (377)(0.05) D 2 ⫽ 27.5 Æ
␻L (377)(0.05)
␪ ⫽ tan⫺1 a b ⫽ tan⫺1 ⫽ 0.756 rad
R 20
L 0.05
␻␶ ⫽ ␻a b ⫽ 377a b ⫽ 0.943 rad
R 20
Vm 120 22
⫽ ⫽ 6.18 A
Z 27.5
␣ ⫽ 90° ⫽ 1.57 rad
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 180
Vm
sin ( ) e > 23.8 A
Z
The current is then expressed in Eq. (5-9) as
i o(t) 6.18 sin (t 0.756) 23.8e t>0.943 A for t
The extinction angle is determined from the numerical solution of i() 0 in the
above equation, yielding
3.83 rad 220°
Note that the conduction angle 2.26 rad 130, which is less than
the limit of 180.
(b) The rms load current is determined from Eq. (5-14).
3.83
C 6.18 sin (t 0.756) 23.8e t>0.943 D d(t) 2.71 A

1
Io, rms
F 3
1.57
(c) The rms current in each SCR is determined from Eq. (5-16).
Io, rms 2.71
ISCR, rms 1.92 A
12 12
(d) Average SCR current is obtained from Eq. (5-17).
3.83
C 6.18 sin (t 0.756) 23.8e t>0.943 D d(t) 1.04 A

1
ISCR, avg
2 3
1.57
(e) Power absorbed by the load is
P I 2o, rms R (2.71)2 (20) 147 W
(f) Power factor is determined from P/S.

P P 147
pf 0.45 45%
S Vs, rms Is, rms (120)(2.71)
PSpice Simulation of Single-Phase AC Voltage Controllers

The PSpice simulation of single-phase voltage controllers is very similar to the
simulation of the controlled half-wave rectifier. The SCR is modeled with a
diode and voltage-controlled switch. The diodes limit the currents to positive
values, thus duplicating SCR behavior. The two switches are complementary,
each closed for one-half the period.
The Schematic Capture circuit requires the full version, whereas the text
CIR file will run on the PSpice A/D Demo version.
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 181
EXAMPLE 5-3
PSpice Simulation of a Single-Phase Voltage Controller

Use PSpice to simulate the circuit of Example 5-2. Determine the rms load current, the rms
and average SCR currents, load power, and total harmonic distortion in the source current.
Use the default diode model in the SCR.
■ Solution
The circuit for the simulation is shown in Fig. 5-5. This requires the full version of
Schematic Capture.
The PSpice circuit file for the A/D Demo version is as follows:
SINGLE-PHASE VOLTAGE CONTROLLER (voltcont.cir)

*** OUTPUT VOLTAGE IS V(3), OUTPUT CURRENT IS I(R) ***
**************** INPUT PARAMETERS *********************
.PARAM VS 120 ;source rms voltage
.PARAM ALPHA 90 ;delay angle in degrees
.PARAM R 20 ;load resistance
.PARAM L 50mH ;load inductance
.PARAM F 60 ;frequency
.PARAM TALPHA {ALPHA/(360*F)} PW 5 {0.5/F} ;converts angle to time delay
***************** CIRCUIT DESCRIPTION *********************

VS 1 0 SIN(0 {VS*SQRT(2)} {F})
S1 1 2 11 0 SMOD
D1 2 3 DMOD ; FORWARD SCR
S2 3 5 0 11 SMOD
AC VOLTAGE CONTROLLER
PARAMETERS: Control1 0
ALPHA = 90
+ S1
−
F = 60 +
D1
Vrms = 120
TALPHA = {ALPHA/(360*F)}
A
R1
VOFF = 0 Vs D2 + S2 20
+ + 1
VAMPL = {Vrms*sqrt(2)}
−
− Control2 0 L1
FREQ = {F}
Control1 Control2 50m
V1 = 0 V1 = 0
V2 = 5 VC1 V2 = 5 VC2 2
+ +
TD = {TALPHA} − TD = {TALPHA + 1/(2∗F)} −
0 TR = 1n TR = 1n 0
TF = 1n 0 TF = 1n 0
PW = {0.5/F} PW = {0.5/F}
PER = {1/F} PER = {1/F}
Figure 5-5 The circuit schematic for a single-phase ac voltage controller. The full version of Schematic
Capture is required for this circuit.
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 182
D2 5 1 DMOD ; REVERSE SCR

R 3 4 {R}
L 4 0 {L}
**************** MODELS AND COMMANDS ********************
.MODEL DMOD D
.MODEL SMOD VSWITCH (RON.01)
VCONTROL 11 0 PULSE(-10 10 {TALPHA} 0 0 {PW} {1/F}) ;control for both
switches
.TRAN .1MS 33.33MS 16.67MS .1MS UIC ;one period of output
.FOUR 60 I(R) ;Fourier Analysis to get THD
.PROBE
.END
Using the PSpice A/D input file for the simulation, the Probe output of load current and
related quantities is shown in Fig. 5-6. From Probe, the following quantities are obtained:

RMS load current RMS(I(R)) 2.59 A
RMS SCR current RMS(I(S1)) 1.87 A
Average SCR current AVG(I(S1)) 1.01 A
Load power AVG(W(R)) 134 W
Total harmonic distortion (from the output file) 31.7%
Note that the nonideal SCRs (using the default diode) result in smaller currents and
load power than for the analysis in Example 5-2 which assumed ideal SCRs. A model for
the particular SCR that will be used to implement the circuit will give a more accurate
prediction of actual circuit performance.
5.0 A
(50.000m, 2.5916)
(50.000m, 1.8660)
(50.000m, 1.0090)
0A
-5.0 A
15 ms 20 ms 30 ms 40 ms 50 ms 60 ms 70 ms
I (R) RMS ( I (R)) RMS ( I (S1) AVG ( I (S1))
Time

har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 183
5.3 Three-Phase Voltage Controllers 183
5.3 THREE-PHASE VOLTAGE CONTROLLERS

Y-Connected Resistive Load
A three-phase voltage controller with a Y-connected resistive load is shown in
Fig. 5-7a. The power delivered to the load is controlled by the delay angle on
each SCR. The six SCRs are turned on in the sequence 1-2-3-4-5-6, at 60 inter-
vals. Gate signals are maintained throughout the possible conduction angle.
S1
S4
S3
A B b a
S6 R R
N n
S5 R
C c
S2
(a)
vAB vAN
van 2
vAC
2
van
30° 60° 90° 120° 150° 180°

(α)
(b)
Figure 5-7 (a) Three-phase ac voltage controller with a Y-connected resistive

load; (b) Load voltage van for 30; (c) Load voltages and switch currents
for a three-phase resistive load for 30; (d) Load voltage van for 75;
(e) Load voltage van for 120.
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 184
van
vbn
vcn
iS1
iS2
iS3
iS4
iS5
iS6
(c)
vAB vAN vAC

van 2 2
van
75° 135° 195°
(d)

har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 185
vAB vAN
vAC
van 2 2
van
120° 150° 180° 210°
(e)
The instantaneous voltage across each phase of the load is determined by

which SCRs are conducting. At any instant, three SCRs, two SCRs, or no SCRs
are on. The instantaneous load voltages are either a line-to-neutral voltage (three
on), one-half of a line-to-line voltage (two on), or zero (none on).
When three SCRs are on (one in each phase), all three phase voltages are con-
nected to the source, corresponding to a balanced three-phase source connected to
a balanced three-phase load. The voltage across each phase of the load is the cor-
responding line-to-neutral voltage. For example, if S1, S2, and S6 are on, van vAN,
vbn vBN, and vcn vCN. When two SCRs are on, the line-to-line voltage of those
two phases is equally divided between the two load resistors that are connected.
For example, if only S1 and S2 are on, van vAC /2, vcn vCA/2, and vbn 0.
Which SCRs are conducting depends on the delay angle and on the source
voltages at a particular instant. The following are the ranges of that produce
particular types of load voltages with an example for each:
For 0 60:
Two or three SCRs conduct at any one time for this range of . Figure 5-7b
shows the load line-to-neutral voltage van for 30. At t 0, S5 and S6 are
conducting and there is no current in Ra, making van 0. At t /6 (30),
S1 receives a gate signal and begins to conduct; S5 and S6 remain on, and van
vAN. The current in S5 reaches zero at 60, turning S5 off. With S1 and S6
remaining on, van vAB/2. At 90, S2 is turned on; the three SCRs S1, S2, and
S6 are then on; and van vAN. At 120, S6 turns off, leaving S1 and S2 on, so
van vAC /2. As the firing sequence for the SCRs proceeds, the number of
SCRs on at a particular instant alternates between 2 and 3. All three phase-to-
neutral load voltages and switch currents are shown in Fig. 5-7c. For intervals
to exist when three SCRs are on, the delay angle must be less than 60.
For 60 90:
Only two SCRs conduct at any one time when the delay angle is between
60 and 90. Load voltage van for 75 is shown in Fig. 5-7d. Just
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 186
prior to 75, S5 and S6 are conducting, and van 0. When S1 is turned on at

75, S6 continues to conduct, but S5 must turn off because vCN is negative.
Voltage van is then vAB /2. When S2 is turned on at 135, S6 is forced off, and
van vAC /2. The next SCR to turn on is S3, which forces S1 off, and van
0. One SCR is always forced off when an SCR is turned on for in this
range. Load voltages are one-half line-to-line voltages or zero.
For 90 150:
Only two SCRs can conduct at any one time in this mode. Additionally, there
are intervals when no SCRs conduct. Figure 5-7e shows the load voltage van
for 120. In the interval just prior to 120, no SCRs are on, and van 0.
At 120, S1 is given a gate signal, and S6 still has a gate signal applied.
Since vAB is positive, both S1 and S6 are forward-biased and begin to conduct,
and van vAB /2. Both S1 and S6 turn off when vAB becomes negative. When a
gate signal is applied to S2, it turns on, and S1 turns on again.
For 150, there is no time interval when an SCR is forward-biased while a
gate signal is applied. Output voltage is zero for this condition.
Normalized output voltage vs. delay angle is shown in Fig. 5-8. Note that a
delay angle of zero corresponds to the load being connected directly to the
Output Voltage
1.0
0.8
Normalized Output Voltage
0.6
0.4
0.2
0
0 20 40 60 80 100 120 140
Figure 5-8 Normalized rms output voltage for a three-phase

ac voltage controller with a resistive load.
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 187
three-phase source. The range of output voltage for the three-phase voltage con-
troller is between full source voltage and zero.
Harmonic currents in the load and line for the three-phase ac voltage con-
troller are the odd harmonics of order 6n 1, n 1, 2, 3, . . . (that is, 5th, 7th,
11th, 13th). . . . Harmonic filters may be required in some applications to prevent
harmonic currents from propagating into the ac system.
Since analysis of the three-phase ac voltage controller is cumbersome, sim-
ulation is a practical means of obtaining rms output voltages and power delivered
to a load. PSpice simulation is presented in Example 5-4.
Y-Connected RL Load
The load voltages for a three-phase voltage controller with an RL load are again
characterized by being a line-to-neutral voltage, one-half of a line-to-line volt-
age, or zero. The analysis is much more difficult for an RL load than for a resis-
tive load, and simulation provides results that would be extremely difficult to
obtain analytically. Example 5-4 illustrates the use of PSpice for a three-phase ac
voltage controller.
EXAMPLE 5-4
PSpice Simulation of a Three-Phase Voltage Controller

Use PSpice to obtain the power delivered to a Y-connected three-phase load. Each phase
of the load is a series RL combination with R 10
and L 30 mH. The three-phase
source is 480 V rms line-to-line at 60 Hz, and the delay angle is 75. Determine the rms
value of the line currents, the power absorbed by the load, the power absorbed by the
SCRs, and the total harmonic distortion (THD) of the source currents.
■ Solution
A PSpice A/D input file for the Y-connected three-phase voltage controller with an RL
load is as follows:
THREE-PHASE VOLTAGE CONTROLLER–R-L LOAD (3phvc.cir)

*SOURCE AND LOAD ARE Y-CONNECTED (UNGROUNDED)
********************** INPUT PARAMETERS ****************************
.PARAM Vs 480 ; rms line-to-line voltage
.PARAM ALPHA 75 ; delay angle in degrees
.PARAM R 10 ; load resistance (y-connected)
.PARAM L 30mH ; load inductance
.PARAM F 60 ; source frequency
********************** COMPUTED PARAMETERS **************************

.PARAM Vm {Vs*SQRT(2)/SQRT(3)} ; convert to peak line-neutral volts
.PARAM DLAY {1/(6*F)} ; switching interval is 1/6 period
.PARAM PW {.5/F} TALPHA{ALPHA/(F*360)}
.PARAM TRF 10US ; rise and fall time for pulse switch control
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 188
*********************** THREE-PHASE SOURCE **************************

VAN 1 0 SIN(0 {VM} 60)
VBN 2 0 SIN(0 {VM} 60 0 0 -120)
VCN 3 0 SIN(0 {VM} 60 0 0 -240)
***************************** SWITCHES ********************************
S1 1 8 18 0 SMOD ; A-phase
D1 8 4 DMOD
S4 4 9 19 0 SMOD
D4 9 1 DMOD
S3 2 10 20 0 SMOD ; B-phase
D3 10 5 DMOD
S6 5 11 21 0 SMOD
D6 11 2 DMOD
S5 3 12 22 0 SMOD ; C-phase
D5 12 6 DMOD
S2 6 13 23 0 SMOD
D2 13 3 DMOD
***************************** LOAD **********************************
RA 4 4A {R} ; van v(4,7)
LA 4A 7 {L}
RB 5 5A {R} ; vbn v(5,7)
LB 5A 7 {L}
RC 6 6A {R} ; vcn v(6,7)
LC 6A 7 {L}
************************* SWITCH CONTROL *****************************
V1 18 0 PULSE(-10 10 {TALPHA} {TRF} {TRF} {PW} {1/F})
V4 19 0 PULSE(-10 10 {TALPHA+3*DLAY} {TRF} {TRF} {PW} {1/F})
V2 23 0 PULSE(-10 10 {TALPHA+DLAY} {TRF} {TRF} {PW} {1/F})
************************ MODELS AND COMMANDS *************************
.MODEL SMOD VSWITCH(RON0.01)
.MODEL DMOD D
.TRAN .1MS 50MS 16.67ms .05MS UIC
.FOUR 60 I(RA) ; Fourier analysis of line current
.PROBE
.OPTIONS NOPAGE ITL50
.END
Probe output of the steady-state current in one of the phases is shown in Fig. 5-9.
The rms line current, load power, and power absorbed by the SCRs are obtained by en-
tering the appropriate expression in Probe. The THD in the source current is determined
from the Fourier analysis in the output file. The results are summarized in the following
table.

RMS line current RMS(I(RA)) 12.86 A
Load power 3*AVG(V(4,7)*I(RA)) 4960 W
Total SCR power absorbed 6*AVG(V(1,4)*I(S1)) 35.1 W
THD of source current (from the output file) 13.1%
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 189
20 A
A–PHASE CURRENT
0A
-20 A
10 ms 20 ms 30 ms 40 ms 50 ms
I (RA)
Time
Delta-Connected Resistive Load

A three-phase ac voltage controller with a delta-connected resistive load is shown in
Fig. 5-10a. The voltage across a load resistor is the corresponding line-to-line volt-
age when a SCR in the phase is on. The delay angle is referenced to the zero cross-
ing of the line-to-line voltage. SCRs are turned on in the sequence 1-2-3-4-5-6.
The line current in each phase is the sum of two of the delta currents:
i a i ab i ca
i b i bc i ab (5-18)
i c i ca i bc
The relationship between rms line and delta currents depends on the conduction
angle of the SCRs. For small conduction angles (large ), the delta currents do
not overlap (Fig. 5-10b), and the rms line currents are
IL, rms 12 I, rms (5-19)
For large conduction angles (small ), the delta currents overlap (Fig. 5-10c),
and the rms line current is larger than 12I. In the limit when ( 0), the
delta currents and line currents are sinusoids. The rms line current is determined
from ordinary three-phase analysis.
IL, rms 13 I, rms (5-20)
The range of rms line current is therefore

12 I, rms IL, rms 13 I, rms (5-21)
depending on .
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 190
Figure 5-10 ia
(a) Three-phase ac A
voltage controller with
a delta-connected
resistive load;
R
(b) Current waveforms iab S5
for 130;
(c) Current waveforms
S2
for 90. S4
S1 R
ica
S3
ib ibc
B
R
S6
ic
C
(a)
iab
ica
ia = iab - ica
(b)
iab
ica
ia = iab - ica
(c)
har80679_ch05_171-195.qxd 12/17/09 2:40 PM Page 191
5.5 Static VAR Control 191
Use of the delta-connected three-phase voltage controller requires the load to be

broken to allow thyristors to be inserted in each phase, which is often not feasible.
5.4 INDUCTION MOTOR SPEED CONTROL

Squirrel-cage induction motor speed can be controlled by varying the voltage
and/or frequency. The ac voltage controller is suitable for some speed control
applications. The torque produced by an induction motor is proportional to the
square of the applied voltage. Typical torque-speed curves for an induction
motor are shown in Fig. 5-11. If a load has a torque-speed characteristic like that
also shown in Fig. 5-11, speed can be controlled by adjusting the motor voltage.
Operating speed corresponds to the intersection of the torque-speed curves of the
motor and the load. A fan or pump is a suitable load for this type of speed con-
trol, where the torque requirement is approximately proportional to the square of
the speed.
Single-phase induction motors are controlled with the circuit of Fig. 5-4a, and
three-phase motors are controlled with the circuit of Fig. 5-7a. Energy efficiency
is poor when using this type of control, especially at low speeds. The large slip at
low speeds results in large rotor losses. Typical applications exist where the load
is small, such as single-phase fractional-horsepower motors, or where the time of
low-speed operation is short. Motor speed control using a variable-frequency
source from an inverter circuit (Chap. 8) is usually a preferred method.
5.5 STATIC VAR CONTROL

Capacitors are routinely placed in parallel with inductive loads for power factor
improvement. If a load has a constant reactive voltampere (VAR) requirement, a
fixed capacitor can be selected to correct the power factor to unity. However, if a
v1
Torque
Load
v2
v3
Speed w3 w1
w2
Figure 5-11 Torque-speed curves for an induction motor.

har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 192
C Load
Figure 5-12 Static VAR control.
load has a varying VAR requirement, the fixed-capacitor arrangement results in

a changing power factor.
The circuit of Fig. 5-12 represents an application of an ac voltage controller
to maintain a unity power factor for varying load VAR requirements. The power
factor correction capacitance supplies a fixed amount of reactive power, gener-
ally greater than required by the load. The parallel inductance absorbs a variable
amount of reactive power, depending on the delay angle of the SCRs. The net
reactive power supplied by the inductor-capacitor combination is controlled to
match that absorbed by the load. As the VAR requirement of the load changes,
the delay angle is adjusted to maintain unity power factor. This type of power
factor correction is known as static VAR control.
The SCRs are placed in the inductor branch rather than in the capacitor branch
because very high currents could result from switching a capacitor with a SCR.
Static VAR control has the advantage of being able to adjust to changing
load requirements very quickly. Reactive power is continuously adjustable with
static VAR control, rather than having discrete levels as with capacitor banks
which are switched in and out with circuit breakers. Static VAR control is be-
coming increasingly prevalent in installations with rapidly varying reactive
power requirements, such as electric arc furnaces. Filters are generally required
to remove the harmonic currents generated by the switched inductance.
5.6 Summary
• Voltage controllers use electronic switches to connect and disconnect a load to an
ac source at regular intervals. This type of circuit is classified as an ac-ac converter.
• Voltage controllers are used in applications such as single-phase light-dimmer
circuits, single-phase or three-phase induction motor control, and static VAR control.
• The delay angle for the thyristors controls the time interval for the switch being on
and thereby controls the effective value of voltage at the load. The range of control
for load voltage is between full ac source voltage and zero.
• An ac voltage controller can be designed to function in either the fully on or fully
off mode. This application is used as a solid-state relay.
• The load and source current and voltage in ac voltage controller circuits may
contain significant harmonics. For equal delay angles in the positive and negative
half-cycles, the average source current is zero, and only odd harmonics exist.
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 193
Problems 193
• Three-phase voltage controllers can have Y- or -connected loads.

• Simulation of single-phase or three-phase voltage controllers provides an efficient
analysis method.
5.7 Bibliography
B. K. Bose, Power Electronics and Motor Drives: Advances and Trends, Academic
Press, New York, 2006.
A. K. Chattopadhyay, Power Electronics Handbook, edited by M. H. Rashid, Academic
Press, New York, 2001, Chapter 16.
M. A. El-Sharkawi, Fundamentals of Electric Drives, Brooks/Cole, Pacific Grove,
Calif., 2000.
B. M. Han and S. I. Moon, “Static Reactive-Power Compensator Using Soft-Switching
Current-Source Inverter,” IEEE Transactions on Power Electronics, vol. 48, no. 6,
December 2001.
Upper Saddle River, N. J., 2004.
R. Valentine, Motor Control Electronics Handbook, McGraw-Hill, New York, 1996.
Problems
Single-phase Voltage Controllers
5-1. The single-phase ac voltage controller of Fig. 5-1a has a 480-V rms 60-Hz
source and a load resistance of 50
. The delay angle is 60. Determine (a) the
rms load voltage, (b) the power absorbed by the load, (c) the power factor, (e) the
average and rms currents in the SCRs, and (f) the THD of the source current.
source and a load resistance of 20
. The delay angle is 45. Determine (a) the
rms load voltage, (b) the power absorbed by the load, (c) the power factor, (d) the
average and rms currents in the SCRs, and (e) the THD of the source current.
5-3. The single-phase ac voltage controller of Fig. 5-1a has a 240-V rms source and a
load resistance of 35
. (a) Determine the delay angle required to deliver 800 W
to the load. (b) Determine the rms current in each SCR. (c) Determine the power
factor.
5-4. A resistive load absorbs 200 W when connected to a 120-V rms 60-Hz ac voltage
source. Design a circuit which will result in 200 W absorbed by the same
resistance when the source is 240 V rms at 60 Hz. What is the peak load voltage
in each case?
5-5. The single-phase ac voltage controller of Fig. 5-1a has a 120-V rms source at 60 Hz
and a load resistance of 40
. Determine the range of so that the output power
can be controlled from 200 to 400 W. Determine the range of power factor that
will result.
5-6. Design a circuit to deliver power in the range of 750 to 1500 W to a 32-
resistor
from a 240-V rms 60-Hz source. Determine the maximum rms and average currents
in the switching devices, and determine the maximum voltage across the devices.
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 194
5-7. Design a circuit to deliver a constant 1200 W of power to a load that varies in
resistance from 20 to 40
. The ac source is 240 V rms, 60 Hz. Determine the
maximum rms and average currents in the devices, and determine the maximum
voltage across the devices.
5-8. Design a light-dimmer for a 120-V, 100-W incandescent lightbulb. The source is
120 V rms, 60 Hz. Specify the delay angle for the triac to produce an output
power of (a) 75 W (b) 25 W. Assume that the bulb is a load of constant resistance.
5-9. A single-phase ac voltage controller is similar to Fig. 5-1a except that S2 is
replaced with a diode. S1 operates at a delay angle . Determine (a) an
expression for rms load voltage as a function of and Vm and (b) the range of
rms voltage across a resistive load for this circuit.
5-10. The single-phase ac voltage controller of Fig. 5-1a is operated with unequal
delays on the two SCRs (1 2). Derive expressions for the rms load voltage
and average load voltage in terms of Vm, 1, and 2.
5-11. The single-phase ac voltage controller of Fig. 5-4a has a 120-V rms 60-Hz source.
The series RL load has R 18
and L 30 mH. The delay angle 60.
Determine (a) an expression for current, (b) rms load current, (c) rms current in
each of the SCRs, and (d) power absorbed by the load. (e) Sketch the waveforms
of output voltage and voltage across the SCRs.
source. The RL load has R 22
and L 40 mH. The delay angle 50.
Determine (a) an expression for current, (b) rms load current, (c) rms current in
each of the SCRs, and (d) power absorbed by the load. (e) Sketch the waveforms
of output voltage and voltage across the SCRs.
source. The RL load has R 12
and L 24 mH. The delay angle is 115.
Determine the rms load current.
5-14. The single-phase ac voltage controller of Fig. 5-4a has a 120-V rms 60-Hz source.
The RL load has R 12
and L 20 mH. The delay angle is 70. (a) Determine
the power absorbed by the load for ideal SCRs. (b) Determine the power in the load
from a PSpice simulation. Use the default diode and Ron 0.1
in the SCR model.
(c) Determine the THD of the source current from the PSpice output.
5-15. Use PSpice to determine the delay angle required in the voltage controller of
Fig. 5-4a to deliver (a) 400 W, and (b) 700 W to an RL load with R 15
and
L 15 mH from a 120-V rms 60-Hz source.
5-16. Use PSpice to determine the delay angle required in the voltage controller of
Fig. 5-4a to deliver (a) 600 W, and (b) 1000 W to an RL load with R 25
and
L 60 mH from a 240-V rms 60-Hz source.
5-17. Design a circuit to deliver 250 W to an RL series load, where R 24
and
L 35 mH. The source is 120 V rms at 60 Hz. Specify the rms and average
currents in the devices. Specify the maximum voltage across the devices.
Three-phase Voltage Controllers

5-18. The three-phase voltage controller of Fig. 5-7a has a 480-V rms line-to-line
source and a resistive load with 35
in each phase. Simulate the circuit in
PSpice to determine the power absorbed by the load if the delay angle is
(a) 20, (b) 80, and (c) 115.
har80679_ch05_171-195.qxd 12/15/09 6:01 PM Page 195
Problems 195
5-19. The three-phase Y-connected voltage controller has a 240-V rms, 60-Hz line-to-
line source. The load in each phase is a series RL combination with R 16
and L 50 mH. The delay angle is 90. Simulate the circuit in PSpice to

determine the power absorbed by the load. On a graph of one period of A-phase
current, indicate the intervals when each SCR conducts. Do your analysis for
steady-state current.
5-20. For the delta-connected resistive load in the three-phase voltage controller of
Fig. 5-10, determine the smallest delay angle such that the rms line current is
described by Iline rms 12Irms.
5-21. Modify the PSpice circuit file for the three-phase controller for analysis of a
delta-connected load. Determine the rms values of the delta currents and the line
currents for a 480-V rms source, a resistive load of R 25
in each phase, and
a delay angle of 45. Hand in a Probe output showing iab and ia.
5-22. A three-phase ac voltage controller has a 480-V rms, 60-Hz source. The load is
Y-connected, and each phase has series RLC combination with R 14
, L
10 mH, and C 1 F. The delay angle is 70. Use PSpice to determine (a) the
rms load current, (b) the power absorbed by the load, and (c) the THD of the line
current. Also hand in a graph of one period of A-phase current, indicating which
SCRs are conducting at each time. Do your analysis for steady-state current.
5-23. For a three-phase ac voltage controller with a Y-connected load, the voltage
across the S1-S4 SCR pair is zero when either is on. In terms of the three-phase
source voltages, what is the voltage across the S1-S4 pair when both are off?
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 196
1 C H A P T E R
C H A P T E R 6
DC-DC Converters
Dc-dc converters are power electronic circuits that convert a dc voltage to a dif-
ferent dc voltage level, often providing a regulated output. The circuits described
in this chapter are classified as switched-mode dc-dc converters, also called
switching power supplies or switchers. This chapter describes some basic dc-dc
converter circuits. Chapter 7 describes some common variations of these circuits
that are used in many dc power supply designs.
6.1 LINEAR VOLTAGE REGULATORS

Before we discuss switched-mode converters, it is useful to review the motiva-
tion for an alternative to linear dc-dc converters that was introduced in Chapt. 1.
One method of converting a dc voltage to a lower dc voltage is a simple circuit
as shown in Fig. 6-1. The output voltage is
Vo ILRL
where the load current is controlled by the transistor. By adjusting the transistor
base current, the output voltage may be controlled over a range of 0 to roughly
Vs. The base current can be adjusted to compensate for variations in the supply
voltage or the load, thus regulating the output. This type of circuit is called a lin-
ear dc-dc converter or a linear regulator because the transistor operates in the lin-
ear region, rather than in the saturation or cutoff regions. The transistor in effect
operates as a variable resistance.
While this may be a simple way of converting a dc supply voltage to a lower
dc voltage and regulating the output, the low efficiency of this circuit is a serious
drawback for power applications. The power absorbed by the load is VoIL, and
196
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 197
6.2 A Basic Switching Converter 197
+ VCE −
iL
+ + +
RL Vo Vs RL
− − −
Figure 6-1 A basic linear regulator.
the power absorbed by the transistor is VCE IL, assuming a small base current. The
power loss in the transistor makes this circuit inefficient. For example, if the output
voltage is one-quarter of the input voltage, the load resistor absorbs one-quarter of
the source power, which is an efficiency of 25 percent. The transistor absorbs the
other 75 percent of the power supplied by the source. Lower output voltages
result in even lower efficiencies. Therefore, the linear voltage regulator is suit-
able only for low-power applications.
6.2 A BASIC SWITCHING CONVERTER

An efficient alternative to the linear regulator is the switching converter. In a
switching converter circuit, the transistor operates as an electronic switch by
being completely on or completely off (saturation or cutoff for a BJT or the triode
and cutoff regions of a MOSFET). This circuit is also known as a dc chopper.
Assuming the switch is ideal in Fig. 6-2, the output is the same as the input
when the switch is closed, and the output is zero when the switch is open. Periodic
+ + + +
Vs RL vo Vs RL vo
− − − −
(a) (b)
vo
Vs
Closed Open
0
DT T t
(1 − D)T
(c)
Figure 6-2 (a) A basic dc-dc switching converter; (b) Switching

equivalent; (c) Output voltage.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 198
198 C H A P T E R 6 DC-DC Converters
opening and closing of the switch results in the pulse output shown in Fig. 6-2c.
The average or dc component of the output voltage is
T DT
1 1
Vo vo(t)dt Vs dt Vs D (6-1)
T3 T3
0 0
The dc component of the output voltage is controlled by adjusting the duty ratio
D, which is the fraction of the switching period that the switch is closed
t on t
DK on t on f (6-2)
t on t off T
where f is the switching frequency. The dc component of the output voltage will
be less than or equal to the input voltage for this circuit.
The power absorbed by the ideal switch is zero. When the switch is open, there
is no current in it; when the switch is closed, there is no voltage across it. Therefore,
all power is absorbed by the load, and the energy efficiency is 100 percent. Losses
will occur in a real switch because the voltage across it will not be zero when it is
on, and the switch must pass through the linear region when making a transition
from one state to the other.
6.3 THE BUCK (STEP-DOWN) CONVERTER

Controlling the dc component of a pulsed output voltage of the type in Fig. 6-2c
may be sufficient for some applications, such as controlling the speed of a dc
motor, but often the objective is to produce an output that is purely dc. One way of
obtaining a dc output from the circuit of Fig. 6-2a is to insert a low-pass filter after
the switch. Figure 6-3a shows an LC low-pass filter added to the basic converter.
The diode provides a path for the inductor current when the switch is opened and
is reverse-biased when the switch is closed. This circuit is called a buck converter
or a step-down converter because the output voltage is less than the input.
Voltage and Current Relationships

If the low-pass filter is ideal, the output voltage is the average of the input voltage
to the filter. The input to the filter, vx in Fig. 6-3a, is Vs when the switch is closed
and is zero when the switch is open, provided that the inductor current remains
positive, keeping the diode on. If the switch is closed periodically at a duty ratio
D, the average voltage at the filter input is Vs D, as in Eq. (6-1).
This analysis assumes that the diode remains forward-biased for the entire
time when the switch is open, implying that the inductor current remains positive.
An inductor current that remains positive throughout the switching period is
known as continuous current. Conversely, discontinuous current is characterized
by the inductor current’s returning to zero during each period.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 199
6.3 The Buck (Step-Down) Converter 199
vL
+ -
iC iR
iL
+ + +
Vs vx Vo
- - -
(a)
vL = Vs - Vo
+ -
+ + +
Vs vx = Vs Vo
- -
-
(b)
vL = -Vo
+ -
+ + +
Vs vx = 0 Vo
- - -
(c)
Figure 6-3 (a) Buck dc-dc converter; (b) Equivalent

circuit for the switch closed; (c) Equivalent circuit
for the switch open.
Another way of analyzing the operation of the buck converter of Fig. 6-3a is
to examine the inductor voltage and current. This analysis method will prove
useful for designing the filter and for analyzing circuits that are presented later in
this chapter.
Buck converters and dc-dc converters in general, have the following proper-
ties when operating in the steady state:
1. The inductor current is periodic.
i L(t T ) i L(t) (6-3)
2. The average inductor voltage is zero (see Sec. 2.3).
tT
1
VL v (l)dl 0 (6-4)
T 3 L
t
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 200
3. The average capacitor current is zero (see Sec. 2.3).

tT
1
IC i (l)dl 0 (6-5)
T3 C
t
4. The power supplied by the source is the same as the power delivered to the
load. For nonideal components, the source also supplies the losses.
Ps Po ideal
(6-6)
Ps Po losses nonideal
Analysis of the buck converter of Fig. 6-3a begins by making these assumptions:
1. The circuit is operating in the steady state.
2. The inductor current is continuous (always positive).
3. The capacitor is very large, and the output voltage is held constant at volt-
age Vo. This restriction will be relaxed later to show the effects of finite
capacitance.
4. The switching period is T; the switch is closed for time DT and open for time
(1D)T.
5. The components are ideal.
The key to the analysis for determining the output Vo is to examine the inductor
current and inductor voltage first for the switch closed and then for the switch
open. The net change in inductor current over one period must be zero for steady-
state operation. The average inductor voltage is zero.
Analysis for the Switch Closed When the switch is closed in the buck converter
circuit of Fig. 6-3a, the diode is reverse-biased and Fig. 6-3b is an equivalent cir-
cuit. The voltage across the inductor is
di L
vL Vs Vo L
dt
Rearranging,
di L Vs Vo
switch closed
dt L
Since the derivative of the current is a positive constant, the current increases lin-
early as shown in Fig. 6-4b. The change in current while the switch is closed is
computed by modifying the preceding equation.
di L i L i L Vs Vo

dt t DT L
(6-7)
V Vo
( i L) closed a s b DT
L
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 201
vL
Vs − V o
−Vo
(a)
iL
Imax
IR ΔiL
Imin
DT T t
(b)
iC
Δ iL
t
(c)
Figure 6-4 Buck converter waveforms: (a) Inductor voltage;

(b) Inductor current; (c) Capacitor current.
Analysis for the Switch Open When the switch is open, the diode becomes
forward-biased to carry the inductor current and the equivalent circuit of Fig. 6-3c
applies. The voltage across the inductor when the switch is open is
di L
vL Vo L
dt
Rearranging,
di L Vo
switch open
dt L
The derivative of current in the inductor is a negative constant, and the current
decreases linearly as shown in Fig. 6-4b. The change in inductor current when
the switch is open is
iL iL V
o
t (1 D)T L
(6-8)
Vo
( i L) open a b (1 D) T
L
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 202
Steady-state operation requires that the inductor current at the end of the
switching cycle be the same as that at the beginning, meaning that the net change
in inductor current over one period is zero. This requires
( i L) closed ( i L ) open 0
Using Eqs. (6-7) and (6-8),
Vs Vo
a
V
b (DT ) a o b(1 D)T 0
L L
Solving for Vo,
Vo Vs D (6-9)
which is the same result as Eq. (6-1). The buck converter produces an output
voltage that is less than or equal to the input.
An alternative derivation of the output voltage is based on the inductor volt-
age, as shown in Fig. 6-4a. Since the average inductor voltage is zero for periodic
operation,
VL (Vs Vo)DT (Vo )(1 D)T 0
Solving the preceding equation for Vo yields the same result as Eq. (6-9), Vo Vs D.
Note that the output voltage depends on only the input and the duty ratio D.
If the input voltage fluctuates, the output voltage can be regulated by adjusting
the duty ratio appropriately. A feedback loop is required to sample the output
voltage, compare it to a reference, and set the duty ratio of the switch accord-
ingly. Regulation techniques are discussed in Chap. 7.
The average inductor current must be the same as the average current in the load
resistor, since the average capacitor current must be zero for steady-state operation:
Vo
IL IR (6-10)
R
Since the change in inductor current is known from Eqs. (6-7) and (6-8), the
maximum and minimum values of the inductor current are computed as
iL
I max IL
2
(6-11)
V 1 V 1 1D
o c o (1 D)T d Vo a b
R 2 L R 2Lf
iL
I min IL
2
(6-12)
Vo 1 Vo 1 1D
c (1 D)T d Vo a b
R 2 L R 2Lf
where f 1/T is the switching frequency.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 203
For the preceding analysis to be valid, continuous current in the inductor must
be verified. An easy check for continuous current is to calculate the minimum
inductor current from Eq. (6-12). Since the minimum value of inductor current
must be positive for continuous current, a negative minimum calculated from
Eq. (6-12) is not allowed due to the diode and indicates discontinuous current. The
circuit will operate for discontinuous inductor current, but the preceding analysis is
not valid. Discontinuous-current operation is discussed later in this chapter.
Equation (6-12) can be used to determine the combination of L and f that will
result in continuous current. Since I min 0 is the boundary between continuous
and discontinuous current,
1 1D
Imin 0 Vo a b
R 2Lf
(6-13)
(1 D)R
(L f ) min
2
If the desired switching frequency is established,
(1 D)R
L min for continuous current (6-14)
2f
where Lmin is the minimum inductance required for continuous current. In practice,
a value of inductance greater than Lmin is desirable to ensure continuous current.
In the design of a buck converter, the peak-to-peak variation in the inductor
current is often used as a design criterion. Equation (6-7) can be combined with
Eq. (6-9) to determine the value of inductance for a specified peak-to-peak inductor
current for continuous-current operation:
Vs Vo V Vo V (1 D)
iL a b DT a s bD o (6-15)
L Lf Lf
Vs Vo V (1 D)
or L a bD o (6-16)
i L f iL f
Since the converter components are assumed to be ideal, the power supplied by
the source must be the same as the power absorbed by the load resistor.
Ps Po
Vs Is Vo Io (6-17)
Vo Is
or
Vs Io
Note that the preceding relationship is similar to the voltage-current relationship
for a transformer in ac applications. Therefore, the buck converter circuit is
equivalent to a dc transformer.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 204
Output Voltage Ripple

In the preceding analysis, the capacitor was assumed to be very large to keep the
output voltage constant. In practice, the output voltage cannot be kept perfectly
constant with a finite capacitance. The variation in output voltage, or ripple, is
computed from the voltage-current relationship of the capacitor. The current in
the capacitor is
iC iL iR
shown in Fig. 6-5a.
While the capacitor current is positive, the capacitor is charging. From the
definition of capacitance,
Q CVo
Q C Vo
Q
Vo
C
The change in charge Q is the area of the triangle above the time axis
1 T i T i L
Q a b a L b
2 2 2 8
resulting in
T iL
Vo
8C
iC
ΔiL
ΔQ 2
T t
2
(a)
vo
Vo ΔVo
(b) t
Figure 6-5 Buck converter waveforms. (a) Capacitor current;

(b) Capacitor ripple voltage.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 205
Using Eq. (6-8) for iL,

T Vo V (1 D)
Vo (1 D)T o (6-18)
8C L 8LCf 2
In this equation, Vo is the peak-to-peak ripple voltage at the output, as shown in
Fig. 6-5b. It is also useful to express the ripple as a fraction of the output voltage,
Vo 1D
(6-19)
Vo 8LCf 2
In design, it is useful to rearrange the preceding equation to express required

capacitance in terms of specified voltage ripple:
1D
C (6-20)
8L( Vo>Vo ) f 2
If the ripple is not large, the assumption of a constant output voltage is reason-
able and the preceding analysis is essentially valid.
EXAMPLE 6-1
Buck Converter
The buck dc-dc converter of Fig. 6-3a has the following parameters:
Vs 50 V
D 0.4
L 400 H
C 100 F
f 20 kHz
R 20
Assuming ideal components, calculate (a) the output voltage Vo, (b) the maximum and
minimum inductor current, and (c) the output voltage ripple.
■ Solution
(a) The inductor current is assumed to be continuous, and the output voltage is
computed from Eq. (6-9),
Vo Vs D (50)(0.4) 20 V
(b) Maximum and minimum inductor currents are computed from Eqs. (6-11) and (6-12).
1 1D
I max Vo a b
R 2L f
1 1 0.4
20 c d
20 2(400)(10) 6(20)(10)3
1.5
1 1.75 A
2
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 206
1 1D
I min Vo a b
R 2L f
1.5
1 0.25 A
2
The average inductor current is 1 A, and iL 1.5 A. Note that the minimum inductor
current is positive, verifying that the assumption of continuous current was valid.
(c) The output voltage ripple is computed from Eq. (6-19).
Vo 1D 1 0.4

Vo 8LCf 2 8(400)(10)6 (100)(10)6(20,000)2
0.00469 0.469%
Since the output ripple is sufficiently small, the assumption of a constant output
voltage was reasonable.
Capacitor Resistance—The Effect on Ripple Voltage

The output voltage ripple in Eqs. (6-18) and (6-19) is based on an ideal capaci-
tor. A real capacitor can be modeled as a capacitance with an equivalent series re-
sistance (ESR) and an equivalent series inductance (ESL). The ESR may have a
significant effect on the output voltage ripple, often producing a ripple voltage
greater than that of the ideal capacitance. The inductance in the capacitor is usu-
ally not a significant factor at typical switching frequencies. Figure 6.6 shows a
capacitor model that is appropriate for most applications.
The ripple due to the ESR can be approximated by first determining the cur-
rent in the capacitor, assuming the capacitor to be ideal. For the buck converter
in the continuous-current mode, capacitor current is the triangular current wave-
form of Fig. 6-4c. The voltage variation across the capacitor resistance is
Vo, ESR i C rC i L rC (6-21)
To estimate a worst-case condition, one could assume that the peak-to-peak ripple
voltage due to the ESR algebraically adds to the ripple due to the capacitance. How-
ever, the peaks of the capacitor and the ESR ripple voltages will not coincide, so
Vo Vo,C Vo, ESR (6-22)
where Vo, C is Vo in Eq. (6-18). The ripple voltage due to the ESR can be much
larger than the ripple due to the pure capacitance. In that case, the output capacitor is
chosen on the basis of the equivalent series resistance rather than capacitance only.
Vo L Vo, ESR i C rC (6-23)
ΔiC rC
C
+ − + −
ΔVo,C ΔVo, ESR
Figure 6-6 A model for the

capacitor including the equivalent
series resistance (ESR).
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 207
Capacitor ESR is inversely proportional to the capacitance value—a larger ca-

pacitance results in a lower ESR. Manufacturers provide what are known as low-
ESR capacitors for power supply applications.
In Example 6-1, the 100-F capacitor may have an ESR of rC 0.1 . The
ripple voltage due to the ESR is calculated as
Vo, ESR i C rC i L rC (1.5 A)(0.1 Æ) 0.15 V
Expressed as a percent, Vo /Vo is 0.15/20 0.75 percent. The total ripple can
then be approximated as 0.75 percent.
Synchronous Rectification for the Buck Converter
Many buck converters use a second MOSFET in place of the diode. When S2 is on
and S1 is off, current flows upward out of the drain of S2. The advantage of this con-
figuration is that the second MOSFET will have a much lower voltage drop across
it compared to a diode, resulting in higher circuit efficiency. This is especially im-
portant in low-voltage, high-current applications. A Shottky diode would have a
voltage of 0.3 to 0.4 V across it while conducting, whereas a MOSFET will have
an extremely low voltage drop due to an RDSon as low as single-digit milliohms.
This circuit has a control scheme known as synchronous switching, or synchronous
rectification. The second MOSFET is known as a synchronous rectifier. The two
MOSFETs must not be on at the same time to prevent a short circuit across the
source, so a “dead time” is built into the switching control—one MOSFET is
turned off before the other is turned on. A diode is placed in parallel with the sec-
ond MOSFET to provide a conducting path for inductor current during the dead
time when both MOSFETs are off. This diode may be the MOSFET body diode, or
it may be an extra diode, most likely a Shottky diode, for improved switching. The
synchronous buck converter should be operated in the continuous-current mode
because the MOSFET would allow the inductor current to go negative.
Other converter topologies presented in this chapter and in Chap. 7 can uti-
lize MOSFETs in place of diodes.
6.4 DESIGN CONSIDERATIONS

Most buck converters are designed for continuous-current operation. The
choice of switching frequency and inductance to give continuous current is
given by Eq. (6-13), and the output voltage ripple is described by Eqs. (6-16)
and (6-21). Note that as the switching frequency increases, the minimum size of
the inductor to produce continuous current and the minimum size of the capac-
itor to limit output ripple both decrease. Therefore, high switching frequencies
are desirable to reduce the size of both the inductor and the capacitor.
The tradeoff for high switching frequencies is increased power loss in the
switches, which is discussed later in this chapter and in Chap. 10. Increased power
loss in the switches means that heat is produced. This decreases the converter’s ef-
ficiency and may require a large heat sink, offsetting the reduction in size of the
inductor and capacitor. Typical switching frequencies are above 20 kHz to avoid
audio noise, and they extend well into the 100s of kilohertz and into the megahertz
range. Some designers consider about 500 kHz to be the best compromise
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 208
S1
S2
-
Figure 6-7 A synchronous buck converter. The

MOSFET S2 carries the inductor current when S1 is
off to provide a lower voltage drop than a diode.
between small component size and efficiency. Other designers prefer to use lower
switching frequencies of about 50 kHz to keep switching losses small, while still
others prefer frequencies larger than 1 MHz. As switching devices improve,
switching frequencies will increase.
For low-voltage, high-current applications, the synchronous rectification
scheme of Fig. 6-7 is preferred over using a diode for the second switch. The volt-
age across the conducting MOSFET will be much less than that across a diode, re-
sulting in lower losses.
The inductor value should be larger than Lmin in Eq. (6-14) to ensure continuous-
current operation. Some designers select a value 25 percent larger than Lmin. Other
designers use different criteria, such as setting the inductor current variation, iL
in Eq. (6-15), to a desired value, such as 40 percent of the average inductor cur-
rent. A smaller iL results in lower peak and rms inductor currents and a lower
rms capacitor current but requires a larger inductor.
The inductor wire must be rated at the rms current, and the core should not
saturate for peak inductor current. The capacitor must be selected to limit the out-
put ripple to the design specifications, to withstand peak output voltage, and to
carry the required rms current.
The switch (usually a MOSFET with a low RDSon) and diode (or second
MOSFET for synchronous rectification) must withstand maximum voltage stress
when off and maximum current when on. The temperature ratings must not be
exceeded, often requiring a heat sink.
Assuming ideal switches and an ideal inductor in the initial design is usually
reasonable. However, the ESR of the capacitor should be included because it typi-
cally gives a more significant output voltage ripple than the ideal device and
greatly influences the choice of capacitor size.
EXAMPLE 6-2
Buck Converter Design 1

Design a buck converter to produce an output voltage of 18 V across a 10- load resistor.
The output voltage ripple must not exceed 0.5 percent. The dc supply is 48 V. Design for
continuous inductor current. Specify the duty ratio, the switching frequency, the values of
the inductor and capacitor, the peak voltage rating of each device, and the rms current in
the inductor and capacitor. Assume ideal components.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 209
■ Solution
Using the buck converter circuit in Fig. 6-3a, the duty ratio for continuous-current oper-
ation is determined from Eq. (6-9):
Vo 18
D 0.375
Vs 48
The switching frequency and inductor size must be selected for continuous-current oper-
ation. Let the switching frequency arbitrarily be 40 kHz, which is well above the audio
range and is low enough to keep switching losses small. The minimum inductor size is
(1 D)(R) (1 0.375)(10)
L min 78H
2f 2(40,000)
Let the inductor be 25 percent larger than the minimum to ensure that inductor current is
continuous.
L 1.25L min (1.25)(78 H) 97.5 H
Average inductor current and the change in current are determined from Eqs. (6-10)
and (6-17).
Vo 18
IL 1.8 A
R 10
Vs Vo 48 18 1
i L a bDT (0.375)a b 2.88 A
L 97.5(10)6 40,000
The maximum and minimum inductor currents are determined from Eqs. (6-11) and (6-12).
iL
I max IL 1.8 1.44 3.24 A
2
i L
I min IL 1.8 1.44 0.36 A
2
The inductor must be rated for rms current, which is computed as in Chap. 2 (see Exam-
ple 2-8). For the offset triangular wave,
i L >2 2 1.44 2
IL, rms I 2L ¢ ≤ (1.8)2 a b 1.98 A
C 13 C 13
The capacitor is selected using Eq. (6-20).
1D 1 0.375
C 100 F
8L( Vo >Vo )f 2 8(97.5)(10)6(0.005)(40,000)2
Peak capacitor current is iL/2 1.44 A, and rms capacitor current for the triangular wave-
form is 1.44/ 13 0.83 A. The maximum voltage across the switch and diode is Vs , or
48 V. The inductor voltage when the switch is closed is Vs Vo 48 18 30 V. The
inductor voltage when the switch is open is Vo 18 V. Therefore, the inductor must with-
stand 30 V. The capacitor must be rated for the 18-V output.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 210
EXAMPLE 6-3
Buck Converter Design 2

Power supplies for telecommunications applications may require high currents at low
voltages. Design a buck converter that has an input voltage of 3.3 V and an output volt-
age of 1.2 V. The output current varies between 4 and 6 A. The output voltage ripple must
not exceed 2 percent. Specify the inductor value such that the peak-to-peak variation in
inductor current does not exceed 40 percent of the average value. Determine the required
rms current rating of the inductor and of the capacitor. Determine the maximum equiva-
lent series resistance of the capacitor.
■ Solution
Because of the low voltage and high output current in this application, the synchronous rec-
tification buck converter of Fig. 6-7 is used. The duty ratio is determined from Eq. (6-9).
Vo 1.2
D 0.364
Vs 3.3
The switching frequency and inductor size must be selected for continuous-current
operation. Let the switching frequency arbitrarily be 500 kHz to give a good tradeoff
between small component size and low switching losses.
The average inductor current is the same as the output current. Analyzing the circuit
for an output current of 4 A,
IL Io 4 A
i L (40%)(4) 1.6 A
Using Eq. (6-16),
Vs Vo 3.3 1.2
L a bD (0.364) 0.955 H
i L f (1.6)(500,000)
Analyzing the circuit for an output current of 6 A,

IL Io 6 A
i L (40%)(6) 2.4 A
resulting in
Vs Vo 3.3 1.2
L a bD (0.364) 0.636 H
i L f (2.4)(500,000)
Since 0.636 H would be too small for the 4-A output, use L 0.955 H, which would
be rounded to 1 H.
Inductor rms current is determined from
i L >2 2
IL, rms I L2 a b
C 13
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 211
(see Chap. 2). From Eq. (6-15), the variation in inductor current is 1.6 A for each output
current. Using the 6-A output current, the inductor must be rated for an rms current of
0.8 2
IL, rms 62 a b 6.02 A
C 13
Note that the average inductor current would be a good approximation to the rms current
since the variation is relatively small.
Using L 1 H in Eq. (6-20), the minimum capacitance is determined as
1D 1 0.364
C 0.16 F
8L( Vo >Vo ) f 2 8(1)(10)6 (0.02)(500,000)2
The allowable output voltage ripple of 2 percent is (0.02)(1.2) 24 mV. The maximum
ESR is computed from Eq. (6-23).
Vo L rC i C rC i L
Vo 24 mV
or rC 15 mÆ
i C 1.6 A
At this point, the designer would search manufacturer’s specifications for a capaci-
tor having 15-m ESR. The capacitor may have to be much larger than the calculated
value of 0.16 F to meet the ESR requirement. Peak capacitor current is iL/2 0.8 A,
and rms capacitor current for the triangular waveform is 0.8/ 13 0.46 A.
6.5 THE BOOST CONVERTER

The boost converter is shown in Fig. 6-8. This is another switching converter that
operates by periodically opening and closing an electronic switch. It is called a
boost converter because the output voltage is larger than the input.

The analysis assumes the following:
1. Steady-state conditions exist.
2. The switching period is T, and the switch is closed for time DT and open for
(1D)T.
3. The inductor current is continuous (always positive).
4. The capacitor is very large, and the output voltage is held constant
at voltage Vo.
The analysis proceeds by examining the inductor voltage and current for the
switch closed and again for the switch open.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 212
iD
vL
+ -
iL iC
+ +
Vs Vo
- -
(a)
vL = Vs
+ -
iL
+ +
Vs Vo
- -
(b)
vL = VS - Vo
+ -
iL
+ +
Vs Vo
- -
(c)
Figure 6-8 The boost converter. (a) Circuit;

(b) Equivalent circuit for the switch closed;
(c) Equivalent circuit for the switch open.
Analysis for the Switch Closed When the switch is closed, the diode is reverse-
biased. Kirchhoff’s voltage law around the path containing the source, inductor,
and closed switch is
di di L Vs
vL Vs L L or (6-24)
dt dt L
The rate of change of current is a constant, so the current increases linearly while
the switch is closed, as shown in Fig. 6-9b. The change in inductor current is
computed from
i L i L Vs

t DT L
Solving for iL for the switch closed,
Vs DT
( i L) closed (6-25)
L
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 213
vL
iD
Vs
Imax
Closed Open
DT T t
Imin
Vs − Vo
DT T t
(a) (c)
iL iC
Imax
ΔiL
Imin
DT T t
ΔQ
DT T t V
− o
R
(b) (d)
Figure 6-9 Boost converter waveforms. (a) Inductor voltage; (b) Inductor current; (c) Diode
current; (d) Capacitor current.
Analysis for the Switch Open When the switch is opened, the inductor current
cannot change instantaneously, so the diode becomes forward-biased to provide a
path for inductor current. Assuming that the output voltage Vo is a constant, the
voltage across the inductor is
di L
vL Vs Vo L
dt
di L Vs Vo

dt L
The rate of change of inductor current is a constant, so the current must change
linearly while the switch is open. The change in inductor current while the switch
is open is
iL iL Vs Vo

t (1 D)T L
Solving for iL,
(Vs Vo)(1 D)T
( i L)open (6-26)
L
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 214
For steady-state operation, the net change in inductor current must be zero. Using
Eqs. (6-25) and (6-26),
( i L)closed ( i L)open 0
Vs DT (Vs Vo)(1 D)T
0
L L
Solving for Vo,
Vs(D 1 D) Vo(1 D) 0
Vs
Vo (6-27)
1D
Also, the average inductor voltage must be zero for periodic operation. Express-
ing the average inductor voltage over one switching period,
VL Vs D (Vs Vo)(1 D) 0
Solving for Vo yields the same result as in Eq. (6-27).

Equation (6-27) shows that if the switch is always open and D is zero, the out-
put voltage is the same as the input. As the duty ratio is increased, the denominator
of Eq. (6-27) becomes smaller, resulting in a larger output voltage. The boost con-
verter produces an output voltage that is greater than or equal to the input voltage.
However, the output voltage cannot be less than the input, as was the case with the
buck converter.
As the duty ratio of the switch approaches 1, the output voltage goes to
infinity according to Eq. (6-27). However, Eq. (6-27) is based on ideal compo-
nents. Real components that have losses will prevent such an occurrence, as
shown later in this section. Figure 6-9 shows the voltage and current waveforms
for the boost converter.
The average current in the inductor is determined by recognizing that the
average power supplied by the source must be the same as the average power
absorbed by the load resistor. Output power is
V 2o
Po Vo I o
R
and input power is Vs Is Vs IL. Equating input and output powers and using
Eq. (6-27),
V o2 [Vs>(1 D)]2 V s2
Vs I L R
R R (1 D) 2
By solving for average inductor current and making various substitutions, IL can
be expressed as
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 215
Vs V o2 Vo Io
IL (6-28)
(1 D)2R Vs R Vs
Maximum and minimum inductor currents are determined by using the average
value and the change in current from Eq. (6-25).
iL Vs Vs DT
I max IL 2 (6-29)
2 (1 D) R 2L
iL Vs V DT
Imin IL s (6-30)
2 (1 D)2R 2L
Equation (6-27) was developed with the assumption that the inductor current
is continuous, meaning that it is always positive. A condition necessary for con-
tinuous inductor current is for Imin to be positive. Therefore, the boundary be-
tween continuous and discontinuous inductor current is determined from
Vs V DT
Imin 0 s
(1 D)2R 2L
Vs V DT Vs D
or s
(1 D)2 R 2L 2Lf
The minimum combination of inductance and switching frequency for continu-
ous current in the boost converter is therefore
D(1 D)2R
(Lf )min (6-31)
2
D(1 D)2 R
or L min (6-32)
2f
A boost converter designed for continuous-current operation will have an induc-

tor value greater than Lmin.
From a design perspective, it is useful to express L in terms of a desired iL,
Vs DT VD
L s (6-33)
iL iL f

The preceding equations were developed on the assumption that the output volt-
age was a constant, implying an infinite capacitance. In practice, a finite capaci-
tance will result in some fluctuation in output voltage, or ripple.
The peak-to-peak output voltage ripple can be calculated from the capacitor
current waveform, shown in Fig. 6-9d. The change in capacitor charge can be
calculated from
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 216
Vo
ƒ Q ƒ a b DT C Vo
R
An expression for ripple voltage is then
Vo DT Vo D
Vo
RC RCf
Vo D
or (6-34)
Vo RCf
where f is the switching frequency. Alternatively, expressing capacitance in

terms of output voltage ripple yields
D
C (6-35)
R(Vo >Vo ) f
As with the buck converter, equivalent series resistance of the capacitor can
contribute significantly to the output voltage ripple. The peak-to-peak variation in
capacitor current (Fig. 6-9) is the same as the maximum current in the inductor.
The voltage ripple due to the ESR is
Vo, ESR i C rC IL, max rC (6-36)

EXAMPLE 6-4
Boost Converter Design 1

Design a boost converter that will have an output of 30 V from a 12-V source. Design for
continuous inductor current and an output ripple voltage of less than one percent. The
load is a resistance of 50 . Assume ideal components for this design.
■ Solution
First, determine the duty ratio from Eq. (6-27),
Vs 12
D1 1 0.6
Vo 30
If the switching frequency is selected at 25 kHz to be above the audio range, then the min-
imum inductance for continuous current is determined from Eq. (6-32).
D(1 D)2(R) 0.6(1 0.6)2(50)
L min 96 H
2f 2(25,000)
To provide a margin to ensure continuous current, let L 120 H. Note that L and f are
selected somewhat arbitrarily and that other combinations will also give continuous current.
Using Eqs. (6-28) and (6-25),
Vs 12
IL 1.5 A
(1 D) (R) (1 0.6)2(50)
2
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 217
i L Vs DT (12)(0.6)
1.2 A
2 2L (2)(120)(10)6(25,000)
I max 1.5 1.2 2.7 A
I min 1.5 1.2 0.3A
The minimum capacitance required to limit the output ripple voltage to 1 percent is
D 0.6
C 48 F
R( Vo >Vo )f (50)(0.01)(25,000)
EXAMPLE 6-5
Boost Converter Design 2

A boost converter is required to have an output voltage of 8 V and supply a load current
of 1 A. The input voltage varies from 2.7 to 4.2 V. A control circuit adjusts the duty ratio
to keep the output voltage constant. Select the switching frequency. Determine a value for
the inductor such that the variation in inductor current is no more than 40 percent of
the average inductor current for all operating conditions. Determine a value of an ideal
capacitor such that the output voltage ripple is no more than 2 percent. Determine the
maximum capacitor equivalent series resistance for a 2 percent ripple.
■ Solution
Somewhat arbitrarily, choose 200 kHz for the switching frequency. The circuit must be ana-
lyzed for both input voltage extremes to determine the worst-case condition. For Vs 2.7 V,
the duty ratio is determined from Eq. (6-27).
Vs 2.7
D1 1 0.663
Vo 8
Average inductor current is determined from Eq. (6-28).
Vo Io 8(1)
IL 2.96 A
Vs 2.7
The variation in inductor current to meet the 40 percent specification is then
iL 0.4(2.96) 1.19 A. The inductance is then determined from Eq. (6-33).
Vs D 2.7(0.663)
L 7.5 H
i L f 1.19(200,000)
Repeating the calculations for Vs 4.2V,
Vs 4.2
D1 1 0.475
Vo 8
Vo Io 8(1)
IL 1.90 A
Vs 4.2
The variation in inductor current for this case is iL 0.4(1.90) 0.762 A, and
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 218
Vs D 4.2 (0.475)
L 13.1 H
i L f 0.762 (200,000)
The inductor must be 13.1 H to satisfy the specifications for the total range of input
voltages.
Equation (6-35), using the maximum value of D, gives the minimum capacitance as
D D 0.663
C 20.7 F
R( Vo >Vo) f (Vo>Io)(Vo>Vo) f (8>1)(0.02)(200,000)
The maximum ESR is determined from Eq. (6-36), using the maximum peak-to-peak
variation in capacitor current. The peak-to-peak variation in capacitor current is the same as
maximum inductor current. The average inductor current varies from 2.96 A at Vs 2.7 V
to 1.90 A at Vs 4.2 V. The variation in inductor current is 0.762 A for Vs 4.2 A, but it
must be recalculated for Vs 2.7 V using the 13.1-H value selected, yielding
Vs D 2.7(0.663)
iL 0.683 A
Lf 13.1(10)6(200,000)
Maximum inductor current for each case is then computed as
i L 0.683
IL, max, 2.7V IL 2.96 3.30 A
2 2
i 0.762
IL, max, 4.2V IL L 1.90 2.28 A
2 2
This shows that the largest peak-to-peak current variation in the capacitor will be 3.30 A. The
output voltage ripple due to the capacitor ESR must be no more than (0.02)(8) 0.16 V.
Using Eq. (6-36),
Vo, ESR i C rC IL, max rC 3.3rC 0.16 V
which gives
0.16 V
rC 48 mÆ
3.3 A
In practice, a capacitor that has an ESR of 48 m or less could have a capacitance value
much larger than the 20.7 F calculated.
Inductor Resistance
Inductors should be designed to have small resistance to minimize power loss
and maximize efficiency. The existence of a small inductor resistance does not
substantially change the analysis of the buck converter as presented previously in
this chapter. However, inductor resistance affects performance of the boost con-
verter, especially at high duty ratios.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 219
For the boost converter, recall that the output voltage for the ideal case is
Vs
Vo (6-37)
1D
To investigate the effect of inductor resistance on the output voltage, assume that
the inductor current is approximately constant. The source current is the same as
the inductor current, and average diode current is the same as average load cur-
rent. The power supplied by the source must be the same as the power absorbed
by the load and the inductor resistance, neglecting other losses.
Ps Po PrL
(6-38)
Vs IL Vo ID I L2rL
where rL is the series resistance of the inductor. The diode current is equal to the
inductor current when the switch is off and is zero when the switch is on. There-
fore, the average diode current is
ID IL(1 D) (6-39)
Substituting for ID into Eq. (6-38),
Vs IL Vo IL (1 D) I L2 rL
which becomes
Vs Vo (1 D) I L r L (6-40)
In terms of Vo from Eq. (6-39), IL is

ID V >R
IL o (6-41)
1D 1D
Substituting for IL into Eq. (6-40),
Vo rL
Vs Vo (1 D)
R(1 D)
Solving for Vo,
Vs 1
Vo a ba b (6-42)
1 D 1 rL >[R(1 D)2 ]
The preceding equation is similar to that for an ideal converter but includes a cor-
rection factor to account for the inductor resistance. Figure 6-10a shows the output
voltage of the boost converter with and without inductor resistance.
The inductor resistance also has an effect on the power efficiency of con-
verters. Efficiency is the ratio of output power to output power plus losses. For
the boost converter
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 220
10 Vo / Vs vs. D
Ideal
6
Vo / Vs
4
2 Nonideal
0 0.2 0.4 0.6 0.8 1.0

D
(a)
Efficiency vs. D
1.0
Ideal
0.8
Efficiency
0.6
Nonideal
0.4
0.2
0
0.2 0.4 0.6 0.8 1.0
D
(b)
Figure 6-10 Boost converter for a nonideal inductor.

(a) Output voltage; (b) Boost converter efficiency.
Po V o2>R
h 2 (6-43)
Po Ploss V o >R I L2 r L
Using Eq. (6-41) for IL,
V o2>R 1
h (6-44)
V o >R (Vo>R) >(1 D)rL 1 rL 3R(1 D)24
2 2
As the duty ratio increases, the efficiency of the boost converter decreases, as
indicated in Fig. 6-10b.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 221
6.6 The Buck-Boost Converter 221
6.6 THE BUCK-BOOST CONVERTER

Another basic switched-mode converter is the buck-boost converter shown in
Fig. 6-11. The output voltage of the buck-boost converter can be either higher or
lower than the input voltage.

Assumptions made about the operation of the converter are as follows:
1. The circuit is operating in the steady state.
2. The inductor current is continuous.
3. The capacitor is large enough to assume a constant output voltage.
4. The switch is closed for time DT and open for (1D)T.
iD
iC
+ + +
Vs iL vL Vo
- -
-
(a)
+ + +
Vs iL vL = Vs Vo
- - -
(b)
+ + +
Vs vL = Vo Vo
- - -
(c)
Figure 6-11 Buck-boost converter. (a) Circuit;

(b) Equivalent circuit for the switch closed;
(c) Equivalent circuit for the switch open.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 222
Analysis for the Switch Closed When the switch is closed, the voltage across
the inductor is
di
vL Vs L L
dt
di L Vs

dt L
The rate of change of inductor current is a constant, indicating a linearly increas-
ing inductor current. The preceding equation can be expressed as
i L i L Vs

t DT L
Solving for iL when the switch is closed gives
Vs DT
( i L)closed (6-45)
L
Analysis for the Switch Open When the switch is open, the current in the
inductor cannot change instantaneously, resulting in a forward-biased diode
and current into the resistor and capacitor. In this condition, the voltage across
the inductor is
di L
vL Vo L
dt
di L Vo

dt L
Again, the rate of change of inductor current is constant, and the change in current is
iL iL V
o
t (1 D)T L
Solving for iL,
Vo(1 D)T
( i L)open (6-46)
L
For steady-state operation, the net change in inductor current must be zero over
one period. Using Eqs. (6-45) and (6-46),
( i L)closed ( i L)open 0
Vs DT Vo (1 D)T
0
L L
Solving for Vo,
D
Vo Vs a b (6-47)
1D
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 223
The required duty ratio for specified input and output voltages can be expressed as
| Vo |
D (6-48)
Vs | Vo |
The average inductor voltage is zero for periodic operation, resulting in
VL Vs D Vo (1 D) 0
Solving for Vo yields the same result as Eq. (6-47).
Equation (6-47) shows that the output voltage has opposite polarity from the
source voltage. Output voltage magnitude of the buck-boost converter can be less
than that of the source or greater than the source, depending on the duty ratio of the
switch. If D
0.5, the output voltage is larger than the input; and if D 0.5, the out-
put is smaller than the input. Therefore, this circuit combines the capabilities of the
buck and boost converters. Polarity reversal on the output may be a disadvantage in
some applications, however. Voltage and current waveforms are shown in Fig. 6-12.
Note that the source is never connected directly to the load in the buck-boost
converter. Energy is stored in the inductor when the switch is closed and trans-
ferred to the load when the switch is open. Hence, the buck-boost converter is
also referred to as an indirect converter.
Power absorbed by the load must be the same as that supplied by the source,
where
iL
Imax
ΔiL
Imin
Closed Open
DT T t
(a)
vL
Vs
Vo
(b)
Figure 6-12 Buck-boost converter waveforms.

(a) Inductor current; (b) Inductor voltage; (c) Diode
current; (d) Capacitor current.
har80679_ch06_196-264.qxd 12/16/09 12:53 PM Page 224
iD
DT T Vo t
ID = −
R
(c)
iC
t
ΔQ
(d)
V o2
Po ⫽
R
Ps ⫽ Vs I s
V o2
⫽ Vs I s
R
Average source current is related to average inductor current by
Is ⫽ IL D
resulting in
V o2
⫽ Vs I L D
R
Substituting for Vo using Eq. (6-47) and solving for IL, we find
V o2 Po Vs D
IL ⫽ ⫽ ⫽ (6-49)
Vs RD Vs D R(1 ⫺ D)2
Maximum and minimum inductor currents are determined using Eqs. (6-45) and
(6-49).
⌬ iL Vs D Vs DT
Imax ⫽ IL ⫹ ⫽ 2⫹ (6-50)
2 R(1 ⫺ D) 2L
⌬ iL Vs D Vs DT
Imin ⫽ IL ⫺ ⫽ 2⫺ (6-51)
2 R(1 ⫺ D) 2L
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 225
For continuous current, the inductor current must remain positive. To deter-
mine the boundary between continuous and discontinuous current, Imin is set to
zero in Eq. (6-51), resulting in
(1 D)2 R
(Lf )min (6-52)
2
(1 D)2R
or L min (6-53)
2f
where f is the switching frequency.

The output voltage ripple for the buck-boost converter is computed from the
capacitor current waveform of Fig. 6-12d.
Vo
ƒ Q ƒ a b DT C Vo
R
Solving for Vo,
Vo DT Vo D
Vo
RC RCf
Vo D
or (6-54)
Vo RCf
As is the case with other converters, the equivalent series resistance of the
capacitor can contribute significantly to the output ripple voltage. The peak-to-
peak variation in capacitor current is the same as the maximum inductor current.
Using the capacitor model shown in Fig. 6-6, where IL,max is determined from
Eq. (6-50),
Vo,ESR i C rC IL, max rC (6-55)
EXAMPLE 6-6
Buck-Boost Converter
The buck-boost circuit of Fig. 6-11 has these parameters:
Vs 24 V
D 0.4
R 5
L 20 H
C 80 F
f 100 kHz
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 226
Determine the output voltage, inductor current average, maximum and minimum values,
and the output voltage ripple.
■ Solution
Output voltage is determined from Eq. (6-47).
0.4
Vo Vs a
D
b 24 a b 16 V
1D 1 0.4
Inductor current is described by Eqs. (6-49) to (6-51).
VsD 24(0.4)
IL 5.33 A
R(1 D)2 5(1 0.4)2
VsDT 24(0.4)
i L 4.8 A
L 20(10)6 (100,000)
i L 4.8
IL, max IL 5.33 7.33 A
2 2
i L 4.8
IL, min IL 5.33 2.93 A
2 2
Continuous current is verified by Imin

0.
Output voltage ripple is determined from Eq. (6-54).
Vo D 0.4
0.01 1%
Vo RC f (5)(80)(10)6 (100,000)
6.7 THE ĆUK CONVERTER

The Ćuk switching topology is shown in Fig. 6-13a. Output voltage magnitude
can be either larger or smaller than that of the input, and there is a polarity rever-
sal on the output.
The inductor on the input acts as a filter for the dc supply to prevent large
harmonic content. Unlike the previous converter topologies where energy trans-
fer is associated with the inductor, energy transfer for the Ć´ uk converter depends
on the capacitor C1.
The analysis begins with these assumptions:
1. Both inductors are very large and the currents in them are constant.
2. Both capacitors are very large and the voltages across them are constant.
3. The circuit is operating in steady state, meaning that voltage and current
waveforms are periodic.
4. For a duty ratio of D, the switch is closed for time DT and open for (1D)T.
5. The switch and the diode are ideal.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 227
6.7 The Ćuk Converter 227
VC1
L1 L2
+ -
iL1 iC1 C1 iL2
+ +
Vs C2 R Vo
- -
(a)
iC1 = -iL2
L1 L2
iL1 C1 iL2
+
+
Vs C2 R Vo
- -
(b)
iC1 = iL1
L1 L2
iL1 C1 iL2
+
+
Vs C2 R Vo
- -
(c)
IC
1
IL1
Closed Open
DT T t
-IL2
(d)
Figure 6-13 The Ćuk converter. (a) Circuit; (b) Equivalent

circuit for the switch closed; (c) Equivalent circuit for the switch
open; (d) Current in L1 for a large inductance.
The average voltage across C1 is computed from Kirchhoff’s voltage law around
the outermost loop. The average voltage across the inductors is zero for steady-
state operation, resulting in
VC1 Vs Vo
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 228
With the switch closed, the diode is off and the current in capacitor C1 is
(i C1)closed I L 2 (6-56)
With the switch open, the currents in L1 and L2 force the diode on. The current in
capacitor C1 is
(i C1)open IL1 (6-57)
The power absorbed by the load is equal to the power supplied by the source:
Vo I L 2 Vs I L 1 (6-58)
For periodic operation, the average capacitor current is zero. With the switch on
for time DT and off for (1D)T,
3(i C1)closed4DT 3(i C1)open4(1 D)T 0
Substituting using Eqs. (6-56) and (6-57),
IL2 DT IL1(1 D)T 0
(6-59)
IL1 D
or
IL2 1 D
Next, the average power supplied by the source must be the same as the
average power absorbed by the load,
Ps Po
Vs IL1 Vo IL2 (6-60)
IL1 V
o
IL2 Vs
Combining Eqs. (6-59) and (6-60), the relationship between the output and input
voltages is
D
Vo Vs a b (6-61)
1D
The negative sign indicates a polarity reversal between output and input.
Note that the components on the output (L2, C2, and R) are in the same con-
figuration as the buck converter and that the inductor current has the same form
as for the buck converter. Therefore, the ripple, or variation in output voltage, is
the same as for the buck converter:
Vo 1D
(6-62)
Vo 8L 2C 2 f 2
The output ripple voltage will be affected by the equivalence series resistance of
the capacitor as it was in the convertors discussed previously.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 229
6.7 The Ćuk Converter 229
The ripple in C1 can be estimated by computing the change in vC1 in the inter-
val when the switch is open and the currents iL1 and iC1 are the same. Assuming the
current in L1 to be constant at a level IL1 and using Eqs. (6-60) and (6-61), we have
T
1 I V D2
vC 1 L I L 1 d(t) L 1 (1 D)T s a b
C1 3 C1 RC 1 f 1 D
DT
Vo D
or vC 1 L (6-63)
RC1 f
The fluctuations in inductor currents can be computed by examining the in-

ductor voltages while the switch is closed. The voltage across L1 with the switch
closed is
di L
vL 1 Vs L 1 1 (6-64)
dt
In the time interval DT when the switch is closed, the change in inductor cur-
rent is
i L1 Vs

DT L1
Vs DT VsD
or i L1 (6-65)
L1 L1 f
For inductor L2, the voltage across it when the switch is closed is
di L 2
vL 2 Vo (Vs Vo) Vs L 2 (6-66)
dt
The change in iL2 is then

Vs DT Vs D
iL 2 (6-67)
L2 L2 f
For continuous current in the inductors, the average current must be greater
than one-half the change in current. Minimum inductor sizes for continuous cur-
rent are
(1 D)2R
L 1, min
2Df
(6-68)
(1 D)R
L 2, min
2f
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 230
EXAMPLE 6-7
Ćuk Converter Design

A Ćuk converter has an input of 12 V and is to have an output of 18 V supplying a 40-W
load. Select the duty ratio, the switching frequency, the inductor sizes such that the change in
inductor currents is no more than 10 percent of the average inductor current, the output ripple
voltage is no more than 1 percent, and the ripple voltage across C1 is no more than 5 percent.
■ Solution
The duty ratio is obtained from Eq. (6-61),
Vo D 18
1.5
Vs 1D 12
or D 0.6
Next, the switching frequency needs to be selected. Higher switching frequencies result
in smaller current variations in the inductors. Let f 50 kHz. The average inductor cur-
rents are determined from the power and voltage specifications.
Po 40 W
IL2 2.22 A
Vo 18 V
Ps 40 W
IL1 3.33 A
Vs 12 V
The change in inductor currents is computed from Eqs. (6-65) and (6-67).
Vs D
i L
Lf
The 10 percent limit in changes in inductor currents requires
Vs D (12)(0.6)
L2 649 H
fi L 2 (50,000)(0.222)
Vs D (12)(0.6)
L1 432 H
fi L1 (50,000)(0.333)
From Eq. (6-62), the output ripple specification requires
1D 1 0.6
C2 2 3.08 F
(Vo >Vo)8L 2 f (0.01)(8)(649)(10)6(50,000)2
Average voltage across C1 is Vs Vo 12 (18) 30 V, so the maximum change in

vC1 is (30)(0.05) 1.5 V.
The equivalent load resistance is
V o2 (18) 2
R 8.1 Æ
P 40
Now C1 is computed from the ripple specification and Eq. (6-63).
Vo D (18)(0.6)
C1 17.8 F
Rf vC1 (8.1)(50,000)(1.5)
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 231
6.8 The Single-Ended Primary Inductance Converter (SEPIC) 231
6.8 THE SINGLE-ENDED PRIMARY INDUCTANCE

CONVERTER (SEPIC)
A converter similar to the Ćuk is the single-ended primary inductance converter
(SEPIC), as shown in Fig. 6-14. The SEPIC can produce an output voltage that
is either greater or less than the input but with no polarity reversal.
To derive the relationship between input and output voltages, these initial
assumptions are made:
1. Both inductors are very large and the currents in them are constant.
2. Both capacitors are very large and the voltages across them are constant.
3. The circuit is operating in the steady state, meaning that voltage and current
waveforms are periodic.
4. For a duty ratio of D, the switch is closed for time DT and open for (1 D)T.
5. The switch and the diode are ideal.
L1 i L1 C1 iC1 iD
+ vL1 - +
+ vC1 -
iC
2
-
Vs + L2 vL2 C2 Vo
R
-
+
iL2
-
(a)
L1 iL1 C1 iC1
+
+ vL1 - + v C1 -
- i C2
+ vL2
Vs C2 Vo
-
isw iL2 +
-
(b)
iL1 = iC1
L1 C1
+
+ vL1 - + v C1 -
- iC
Vs + vL2
2
C2 R Vo
-
iL2 +
-
(c)
Figure 6-14 (a) SEPIC circuit; (b) Circuit with the switch
closed and the diode off; (c) Circuit with the switch open and
the diode on.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 232
The inductor current and capacitor voltage restrictions will be removed later
to investigate the fluctuations in currents and voltages. The inductor currents are
assumed to be continuous in this analysis. Other observations are that the aver-
age inductor voltages are zero and that the average capacitor currents are zero for
steady-state operation.
Kirchhoff’s voltage law around the path containing Vs, L1, C1, and L2 gives
Vs vL1 vC1 vL2 0
Using the average of these voltages,
Vs 0 VC1 0 0
showing that the average voltage across the capacitor C1 is
VC1 Vs (6-69)
When the switch is closed, the diode is off, and the circuit is as shown in Fig. 6-14b.
The voltage across L1 for the interval DT is
v L 1 Vs (6-70)
When the switch is open, the diode is on, and the circuit is as shown in Fig. 6-14c.
Kirchhoff’s voltage law around the outermost path gives
Vs vL1 vC1 Vo 0 (6-71)
Assuming that the voltage across C1 remains constant at its average value of Vs
[Eq. (6-69)],
Vs vL1 Vs Vo 0 (6-72)
or vL 1 Vo (6-73)
for the interval (1 D)T. Since the average voltage across an inductor is zero for
periodic operation, Eqs. (6-70) and (6-73) are combined to get
(vL1, sw closed )(DT ) (vL1, sw open ) (1 D) T 0
Vs (DT) Vo (1 D)T 0
where D is the duty ratio of the switch. The result is
D
Vo Vs a b (6-74)
1D
which can be expressed as
Vo
D (6-75)
Vo Vs
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 233
This result is similar to that of the buck-boost and Ćuk converter equations, with
the important distinction that there is no polarity reversal between input and out-
put voltages. The ability to have an output voltage greater or less than the input
with no polarity reversal makes this converter suitable for many applications.
Assuming no losses in the converter, the power supplied by the source is the
same as the power absorbed by the load.
Ps Po
Power supplied by the dc source is voltage times the average current, and the
source current is the same as the current in L1.
Ps VsIs VsIL1
Output power can be expressed as
Po Vo I o
resulting in
Vs I L 1 Vo I o
Solving for average inductor current, which is also the average source current,
Vo Io V o2
IL1 Is (6-76)
Vs Vs R
The variation in iL1 when the switch is closed is found from
di L 1 i L1 i L1
vL1 Vs L 1 a b L1 a b L1 a b (6-77)
dt t DT
Solving for iL1,
Vs DT Vs D
iL1 (6-78)
L1 L1 f
For L2, the average current is determined from Kirchhoff’s current law at the
node where C1, L2, and the diode are connected.
i L2 i D i C1
Diode current is
i D i C2 Io
which makes
i L2 i C2 Io i C1
The average current in each capacitor is zero, so the average current in L2 is
IL 2 Io (6-79)
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 234
The variation in iL2 is determined from the circuit when the switch is closed.
Using Kirchhoff’s voltage law around the path of the closed switch, C1, and L2
with the voltage across C1 assumed to be a constant Vs, gives
di L2 i L2 i L2
vL 2 vC1 Vs L 2 a b L2 a b L2 a b
dt t DT
Solving for iL2

VsDT VsD
i L2 (6-80)
L2 L2 f
Applications of Kirchhoff’s current law show that the diode and switch cur-
rents are
0 when switch is closed

iD b
i L1 i L2 when switch is open
(6-81)
i L1 i L2 when switch is closed
i sw b
0 when switch is open
Current waveforms are shown in Fig. 6-15.

Kirchhoff’s voltage law applied to the circuit of Fig. 6-14c, assuming no
voltage ripple across the capacitors, shows that the voltage across the switch
when it is open is Vs + Vo. From Fig. 6-14b, the maximum reverse bias voltage
across the diode when it is off is also Vs + Vo.
The output stage consisting of the diode, C2, and the load resistor is the same
as in the boost converter, so the output ripple voltage is
Vo D
Vo VC 2 (6-82)
RC2 f
Solving for C2,
D
C2 (6-83)
R( Vo>Vo) f
The voltage variation in C1 is determined form the circuit with the switch
closed (Fig. 6-14b). Capacitor current iC1 is the opposite of iL2, which has previ-
ously been determined to have an average value of Io. From the definition of
capacitance and considering the magnitude of charge,
Q C 1 Io t Io DT
VC1
C C C
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 235
VoIo
Vs DiL1
iL1 (a)
Io DiL2
iL2 (b)
iL1
iC1
0 (c)
iL2
iL + i
1 L2 - i
o
iC
2
0 (d)
–Io
+ iC1
iL1
isw
(e)
iC +
1 iL
iD 2
(f)
Figure 6-15 Currents in the SEPIC converter. (a) L1; (b) L2;
(c) C1; (d ) C2; (e) switch; (f ) diode.
Replacing Io with Vo/R,

Vo D
VC1 (6-84)
RC1 f
Solving for C1,
D
C1 (6-85)
R( VC1 >Vo )f
The effect of equivalent series resistance of the capacitors on voltage variation is
usually significant, and the treatment is the same as with the converters discussed
previously.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 236
EXAMPLE 6-8
SEPIC Circuit
The SEPIC circuit of Fig. 6-14a has the following parameters:
Vs 9 V
D 0.4
f 100 kHz
L1 L2 90 H
C1 C2 80 F
Io 2 A
Determine the output voltage; the average, maximum, and minimum inductor currents; and
the variation in voltage across each capacitor.
■ Solution
The output voltage is determined from Eq. (6-74).
0.4
Vo Vs a
D
b 9a b 6V
1D 1 0.4
The average current in L1 is determined from Eq. (6-76).
Vo Io 6(2)
IL1 1.33 A
Vs 9
From Eq. (6-78)

Vs D 9(0.4)
i L1 0.4 A
L 1 f 90(10)6(100,000)
Maximum and minimum currents in L1 are then

i L1 0.4
IL1, max IL1 1.33 1.53 A
2 2
i L1 0.4
IL1, min IL1 1.33 1.13 A
2 2
For the current in L2, the average is the same as the output current Io 2 A. The variation
in IL2 is determined from Eq. (6-80)
Vs D 9(0.4)
i L 2 0.4 A
L 2 f 90(10)6(100,000)
resulting in maximum and minimum current magnitudes of

0.4
IL 2, max 2 2.2 A
2
0.4
IL 2, min 2 1.8 A
2
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 237
6.9 Interleaved Converters 237
Using an equivalent load resistance of 6 V/2 A 3 , the ripple voltages in the capaci-
tors are determined from Eqs. (6-82) and (6-84).
Vo D 6(0.4)
Vo VC 2 0.1 V
RC2 f (3)80(10)6 (100,000)
Vo D 6(0.4)
VC1 0.1 V
RC1 f (3)80(10)6 (100,000)
In Example 6-8, the values of L1 and L2 are equal, which is not a require-
ment. However, when they are equal, the rates of change in the inductor currents
are identical [Eqs. (6-78) and (6-80)]. The two inductors may then be wound on
the same core, making a 1:1 transformer. Figure 6-16 shows an alternative repre-
sentation of the SEPIC converter.
1:1
L1 L2 = L1
Vs +
-
C1
C2 R
Figure 6-16 A SEPIC circuit using mutually

coupled inductors.
6.9 INTERLEAVED CONVERTERS

Interleaving, also called multiphasing, is a technique that is useful for reducing
the size of filter components. An interleaved buck converter is shown in Fig. 6-17a.
This is equivalent to a parallel combination of two sets of switches, diodes, and in-
ductors connected to a common filter capacitor and load. The switches are operated
180 out of phase, producing inductor currents that are also 180 out of phase. The
current entering the capacitor and load resistance is the sum of the inductor cur-
rents, which has a smaller peak-to-peak variation and a frequency twice as large as
individual inductor currents. This results in a smaller peak-to-peak variation in ca-
pacitor current than would be achieved with a single buck converter, requiring less
capacitance for the same output ripple voltage. The variation in current coming
from the source is also reduced. Figure 6-17b shows the current waveforms.
The output voltage is obtained by taking Kirchhoff’s voltage law around
either path containing the voltage source, a switch, an inductor, and the output
voltage. The voltage across the inductor is Vs Vo with the switch closed and
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 238
L1
+
S1
Vo
Vs +
-
L2
S2
(a)
iL1 + iL2
iL1
iL2
S2 Open
Closed
S1
Closed Open
(b)
Figure 6-17 (a) An interleaved buck converter; (b) The switching scheme and
current waveforms.
is Vo with the switch open. These are the same as for the buck converter of
Fig. 6-3a discussed previously, resulting in
Vo Vs D
where D is the duty ratio of each switch.

Each inductor supplies one-half of the load current and output power, so
the average inductor current is one-half of what it would be for a single buck
converter.
More than two converters can be interleaved. The phase shift between
switch closing is 360/n, where n is the number of converters in the parallel con-
figuration. Interleaving can be done with the other converters in this chapter and
with the converters that are described in Chap. 7. Figure 6-18 shows an inter-
leaved boost converter.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 239
6.10 Nonideal Switches and Converter Performance 239
L1
+
+
Vs S1 Vo
−
L2
S2
Figure 6-18 An interleaved boost converter.
6.10 NONIDEAL SWITCHES AND CONVERTER

PERFORMANCE
Switch Voltage Drops
All the preceding calculations were made with the assumption that the switches
were ideal. Voltage drops across conducting transistors and diodes may have a
significant effect on converter performance, particularly when the input and
output voltages are low. Design of dc-dc converters must account for nonideal
components. The buck converter is used to illustrate the effects of switch volt-
age drops.
Referring again to the analysis of the buck converter of Fig. 6-3a, the input-
output voltage relationship was determined using the inductor voltage and cur-
rent. With nonzero voltage drops across conducting switches, the voltage across
the inductor with the switch closed becomes
vL Vs Vo VQ (6-86)
where VQ is the voltage across the conducting switch. With the switch open, the
voltage across the diode is VD and the voltage across the inductor is
vL Vo VD (6-87)
The average voltage across the inductor is zero for the switching period.
VL (Vs Vo VQ)D ( Vo VD)(1 D) 0
Solving for Vo,
Vo Vs D VQ D VD (1 D) (6-88)
which is lower than Vo Vs D for the ideal case.

har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 240
Switching Losses
In addition to the on-state voltage drops and associated power losses of the
switches, other losses occur in the switches as they turn on and off. Figure 6-19a
illustrates switch on-off transitions. For this case, it is assumed that the changes
in voltage and current are linear and that the timing sequence is as shown. The
instantaneous power dissipated in the switch is shown in Fig. 6-19a. Another
possible switch on-off transition is shown in Fig. 6-12b. In this case, the volt-
age and current transitions do not occur simultaneously. This may be closer to
actual switching situations, and switching power loss is larger for this case.
(See Chap. 10 for additional information.)
The energy loss in one switching transition is the area under the power
curve. Since the average power is energy divided by the period, higher switch-
ing frequencies result in higher switching losses. One way to reduce switching
losses is to modify the circuit to make switching occur at zero voltage and/or
zero current. This is the approach of the resonant converter, which is discussed
in Chap. 9.
v(t)
i(t)
p(t)
(a)
v(t) i(t)
p(t)
(b)
Figure 6-19 Switch voltage, current, and

instantaneous power. (a) Simultaneous voltage
and current transition; (b) Worst-case transition.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 241
6.11 Discontinuous-Current Operation 241
6.11 DISCONTINUOUS-CURRENT OPERATION

Continuous current in the inductor was an important assumption in the previous
analyses for dc-dc converters. Recall that continuous current means that the cur-
rent in the inductor remains positive for the entire switching period. Continuous
current is not a necessary condition for a converter to operate, but a different
analysis is required for the discontinuous-current case.
Buck Converter with Discontinuous Current

Figure 6-20 shows the inductor and source currents for discontinuous-current
operation for the buck converter of Fig 6-3a. The relationship between output and
input voltages is determined by first recognizing that the average inductor voltage
is zero for periodic operation. From the inductor voltage shown in Fig. 6-20c,
(Vs Vo) DT Vo D 1 T 0
which is rearranged to get
(Vs Vo)D Vo D 1 (6-89)
iL
Imax
DT T t
D1T
(a)
is
Imax
DT T t
(b)
vL
Vs - Vo
DT T t
D1T
-Vo
(c)
Figure 6-20 Buck converter discontinuous current.

(a) Inductor current; (b) Source current; (c) Inductor voltage.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 242
Vo D
a b (6-90)
Vs D D1
Next, the average inductor current equals the average resistor current because the
average capacitor current is zero. With the output voltage assumed constant,
Vo
IL IR
R
Computing the average inductor current from Fig. 6-20a,
1 1 1 1
IL a I max DT I max D1Tb I max (D D1)
T 2 2 2
which results in
1 V
Imax (D D1 ) o (6-91)
2 R
Since the current starts at zero, the maximum current is the same as the change
in current over the time that the switch is closed. With the switch closed, the volt-
age across the inductor is
vL Vs Vo
which results in
di L Vs Vo i L i L I max
(6-92)
dt L t DT DT
Solving for Imax and using Eq. (6-89) for (Vs Vo)D,
Vs Vo VDT
I max i L a b DT o 1 (6-93)
L L
Substituting for Imax in Eq. (6-91),
1 1 VD T V
I max (D D1 ) a o 1 b (D D1) o (6-94)
2 2 L R
which gives
2L
D 12 DD1 0
RT
Solving for D1,
D 2D 2 8L>RT
D1 (6-95)
2
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 243
Substituting for D1 in Eq. (6-90),
D 2D
Vo Vs a b Vs c d (6-96)
D D1 D 1D 2 8L>RT
The boundary between continuous and discontinuous current occurs when

D1 1 D. Recall that another condition that occurs at the boundary between
continuous and discontinuous current is Imin 0 in Eq. (6-12).
EXAMPLE 6-9
Buck Converter with Discontinuous Current

For the buck converter of Fig. 6-3a,
Vs 24 V
L 200 H
R 20
C 1000 F
f 10 kHz switching frequency
D 0.4
(a) Show that the inductor current is discontinuous, (b) Determine the output voltage Vo.
■ Solution
(a) For discontinuous current, D1 1 D, and D1 is calculated from Eq. (6-95).
D 2D 2 8L>RT
D1
2
1 8(200)(10)6 (10,000)
a 0.4 0.42 b 0.29
2 A 20
Comparing D1 to 1 D, 0.29 (1 0.4) shows that the inductor current is discontin-

uous. Alternatively, the minimum inductor current computed from Eq. (6-12) is Imin
0.96 A. Since negative inductor current is not possible, inductor current must be
discontinuous.
(b) Since D1 is calculated and discontinuous current is verified, the output voltage can be
0.4
Vo Vs a
D
b 20 a b 13.9 V
D D1 0.4 0.29
Figure 6-21 shows the relationship between output voltage and duty ratio for
the buck converter of Example 6-9. All parameters except D are those of Exam-
ple 6-9. Note the linear relationship between input and output for continuous cur-
rent and the nonlinear relationship for discontinuous current. For a given duty
ratio, the output voltage is greater for discontinuous-current operation than it
would be if current were continuous.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 244
25
Discontinuous Continuous
20
15
Vo
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

D
Figure 6-21 Vo versus duty ratio for the buck converter of

Example 6-9.
Boost Converter with Discontinuous Current

The boost converter will also operate for discontinuous inductor current. In some
cases, the discontinuous-current mode is desirable for control reasons in the case
of a regulated output. The relationship between output and input voltages is de-
termined from two relationships:
1. The average inductor voltage is zero.
2. The average current in the diode is the same as the load current.
The inductor and diode currents for discontinuous current have the basic wave-
forms as shown in Fig. 6-22a and c. When the switch is on, the voltage across
the inductor is Vs. When the switch is off and the inductor current is positive,
the inductor voltage is Vs Vo. The inductor current decreases until it reaches
zero and is prevented from going negative by the diode. With the switch open
and the diode off, the inductor current is zero. The average voltage across the
inductor is
Vs DT (Vs Vo)D1 T 0
which results in
D D1
Vo Vs a b (6-97)
D1
The average diode current (Fig. 6-22c) is
1 1 1
ID a I D T b I max D 1 (6-98)
T 2 max 1 2
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 245
iL
Imax
ΔIL
DT D1T T t
(a)
vL
Vs
D1T t
DT
Vs − V o
(b)
iD
Imax
D1T t
(c)
Figure 6-22 Discontinuous current in the boost converter.

(a) Inductor current; (b) Inductor voltage; (c) Diode current.
Current Imax is the same as the change in inductor current when the switch is
closed.
Vs DT
Imax i L (6-99)
L
Substituting for Imax in Eq. (6-98) and setting the result equal to the load current,
1 Vs DT
a bD1 o
V
ID (6-100)
2 L R
Solving for D1,

2L
D1 a
Vo
ba b (6-101)
Vs RDT
Substituting the preceding expression for D1 into Eq. (6-97) results in the qua-
dratic equation
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 246
400
300
200
vo
Discontinuous
100 Current Continuous
0 0.2 0.4 0.6 0.8 1.0

D
Figure 6-23 Output voltage of boost converter.
Vo 2 Vo D 2 RT
a b 0
Vs Vs 2L
Solving for Vo/Vs ,

Vo 1 2D 2RT
a1 1 b (6-102)
Vs 2 B L
The boundary between continuous and discontinuous current occurs when D1
1 D. Another condition at the boundary is when I min in Eq. (6-30) is zero.
Whether the boost converter is operating in the continuous or discontinuous
mode depends on the combination of circuit parameters, including the duty ratio.
As the duty ratio for a given boost converter is varied, the converter may go into
and out of the discontinuous mode. Figure 6-23 shows the output voltage for a
boost converter as the duty ratio is varied.
EXAMPLE 6-10
Boost Converter with Discontinuous Current

The boost converter of Fig. 6-8a has parameters
Vs 20 V
D 0.6
L 100 H
R 50
C 100 F
f 15 kHz
(a) Verify that the inductor current is discontinuous, (b) determine the output voltage, and
(c) determine the maximum inductor current.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 247
6.12 Switched-Capacitor Converters 247
■ Solution
(a) First assume that the inductor current is continuous and compute the minimum from
Eq. (6-30), resulting in Imin 1.5 A. Negative inductor current is not possible, in-
dicating discontinuous current.
(b) Equation (6-102) gives the output voltage
Vs 2D 2R 20 2(0.6)2(50)
Vo a1 1 b B1 1 R 60 V
2 B Lf 2 B 100(10)6(15,000)
Note that a boost converter with the same duty ratio operating with continuous cur-
rent would have an output of 50 V.
(c) The maximum inductor current is determined from Eq. (6-99).
Vs D (20)(0.6)
I max 8A
Lf 100(10)6(15,000)
6.12 SWITCHED-CAPACITOR CONVERTERS

In switched-capacitor converters, capacitors are charged in one circuit configura-
tion and then reconnected in a different configuration, producing an output voltage
different from the input. Switched-capacitor converters do not require an inductor
and are also known as inductorless converters or charge pumps. Switched-capacitor
converters are useful for applications that require small currents, usually less
than 100 MA. Applications include use in RS-232 data signals that require both
positive and negative voltages for logic levels; in flash memory circuits, where
large voltages are needed to erase stored information; and in drivers for LEDs
and LCD displays.
The basic types of switched-capacitor converters are the step-up (boost), the
inverting, and the step-down (buck) circuits. The following discussion intro-
duces the concepts of switched-capacitor converters.
The Step-Up Switched-Capacitor Converter

A common application of a switched-capacitor converter is the step-up (boost)
converter. The basic principle is shown in Fig. 6-24a. A capacitor is first con-
nected across the source to charge it to Vs. The charged capacitor is then con-
nected in series with the source, producing an output voltage of 2Vs.
A switching scheme to accomplish this is shown in Fig. 6-24b. The switch
pair labeled 1 is closed and opened in a phase sequence opposite to that of switch
pair 2. Switch pair 1 closes to charge the capacitor and then opens. Switch pair 2
then closes to produce an output of 2Vs.
The switches can be implemented with transistors, or they can be imple-
mented with transistors and diodes, as shown in Fig. 6-24c. Transistor M1 is
turned on, and C1 is charged to Vs through D1. Next, M1 is turned off and M2 is
turned on. Kirchhoff’s voltage law around the path of the source, the charged
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 248
Vs
- +
+ b a +
a
Vs +
-
Vs Vs +
-
2Vs
b
- -
(a)
1
2 2
b a
Vs +
-
1
(b)
D1
M2 C1 D2
b a
+
Vs +
-
C2 R Vo = 2Vs
M1
-
(c)
Figure 6-24 A switched-capacitor step-up converter. (a) A capacitor is

charged and then reconnected to produce a voltage of twice that of the
source; (b) A switch arrangement; (c) An implementation using transistors
and diodes and showing a second capacitor C2 to sustain the output voltage
during switching.
capacitor C1, and Vo shows that Vo 2Vs. The capacitor C2 on the output is
required to sustain the output voltage and to supply load current when C1 is dis-
connected from the load. With C2 included, it will take several switching cycles
to charge it and achieve the final output voltage. With the resistor connected, cur-
rent will flow from the capacitors, but the output voltage will be largely unaffected
if the switching frequency is sufficiently high and capacitor charges are replenished
in short time intervals. The output will be less than 2Vs for real devices because of
voltage drops in the circuit.
Converters can be made to step up the input voltage to values greater than
2Vs. In Fig. 6-25a, two capacitors are charged and then reconnected to create a
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 249
6.12 Switched-Capacitor Converters 249
Vs Vs
- + - +
+ b a d c +
a c
Vs + Vs Vs +
- - 3Vs
b d
-
-
(a)
2 2
2
c +
b a d
Vs +
- 1 1
C3 Vo = 3Vs
-
(b)
Figure 6-25 A step-up switched-capacitor converter to produce 3 times the source

voltage. (a) Each capacitor is charged to Vs and reconnected to produce an output of
3Vs; (b) A switch arrangement also shows an output capacitor to sustain the output
voltage during switching.
voltage of 3Vs. A switching arrangement to implement this circuit is shown in

Fig. 6-25b. Switch sets 1 and 2 open and close alternately. The circuit includes
an output capacitor C3 to sustain the voltage across the load during the switch-
ing cycle.
The Inverting Switched-Capacitor Converter

The inverting switched-capacitor converter is useful for producing a negative
voltage from a single voltage source. For example, 5 V can be made from a
5-V source, thereby creating a +/ 5-V supply. The basic concept is shown in
Fig. 6-26a. A capacitor is charged to the source voltage and then connected to the
output with opposite polarity.
A switching scheme to accomplish this is shown in Fig. 6-26b. Switch pairs 1
and 2 open and close in opposite phase sequence. Switch pair 1 closes to charge the
capacitor and then opens. Switch pair 2 then closes to produce an output of Vs.
A switch configuration to implement the inverting circuit is shown in Fig. 6-26c.
An output capacitor C2 is included to sustain the output and supply current to the
load during the switching cycle. Transistor M1 is turned on, charging C1 to Vs
through D1. Transistor M1 is turned off and M2 is turned on, charging C2 with a
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 250
+
a +
b -
Vs +
-
Vs Vs +
-
Vo = -Vs
b Vs
a + -
-
(a)
1 2
a b
Vs +
-
2 1
(b)
+
C1 D2
M1
Vs +
- D1 C2 R Vo = -Vs
M2
-
(c)
Figure 6-26 The inverting switched-capacitor converter. (a) The

capacitor is charged to Vs and then reconnected to produce an output of
Vs; (b) A switch arrangement; (c) An implementation using transistors
and diodes and showing a second capacitor to sustain the output voltage
during switching.
polarity that is positive on the bottom. After several switching cycles, the output
voltage is Vs.
The Step-Down Switched-Capacitor Converter

A step-down (buck) switched-capacitor converter is shown in Fig. 6-27. In
Fig. 6-27a, two capacitors of equal value are connected in series, resulting in a
voltage of Vs /2 across each. The capacitors are then reconnected in parallel, mak-
ing the output voltage Vs /2. A switching scheme to accomplish this is shown in
Fig. 6-27b. Switch pairs 1 and 2 open and close in opposite phase sequence. With
the resistor connected, current will flow from the capacitors, but the output voltage
will be unaffected if the switching frequency is sufficiently high and capacitor
charges are replenished in short time intervals.
A switch configuration to implement the inverting circuit is shown in
Fig. 6-27c. Transistor M1 is turned on, and both capacitors charge through D1.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 251
6.13 PSpice Simulation of DC-DC Converters 251
a + +
V /2 a c
Vs + b - s +
- Vs + Vs /2 Vs /2
c + -
-
V /2 b d
d - s -
(a)
1 2
a c
1
Vs +
- b
2 d
(b)
M1 M2
+
Vs + D1 Vo = Vs /2
- R
D2 -
(c)
Figure 6-27 The step-down switched-capacitor converter.

(a) The capacitors are in series and each is charged to Vs /2,
followed by the capacitors in parallel, with the output
voltage at Vs /2; (b) A switch arrangement; (c) An
implementation using transistors and diodes.
Transistor M1 is turned off, and M2 is turned on, connecting the capacitors in

parallel through D2. And D2 is forward-biased as the capacitors discharge into
the load resistor.
6.13 PSPICE SIMULATION OF DC-DC CONVERTERS

The circuit model to be used for PSpice simulation of the dc-dc converters dis-
cussed in this chapter depends on the ultimate goal of the simulation. To predict the
behavior of a circuit with the goal of producing the periodic voltage and current
waveforms requires a circuit model that includes a switch. A voltage-controlled
switch is convenient for this application. If the circuit includes an ideal diode and
lossless inductors and capacitors, the simulation results will be first-order approxi-
mations of circuit behavior, much the same as the analytical work done previously
in this chapter. By including parasitic elements and using nonideal switching
devices in the circuit model, the simulation will be useful to investigate how a real
circuit is expected to depart from the ideal.
Another simulation goal may be to predict the dynamic behavior of a dc-dc
converter for changes in the source voltage or load current. A disadvantage of
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 252
using the cycle-to-cycle switched model is that the time for overall circuit tran-
sients may be orders of magnitude larger than the switching period, thereby mak-
ing the program execution time quite long. A circuit model that does not include
the cycle-by-cycle details but does simulate the large-scale dynamic behavior by
using averaging techniques may be preferred. PSpice simulations for both cycle-
to-cycle and large-scale dynamic behavior are discussed in this section.
A Switched PSpice Model
A voltage-controlled switch is a simple way to model a transistor switch that
would actually be used in a physical converter. The voltage-controlled switch has
an on resistance that could be selected to match the transistor’s, or the on resis-
tance could be chosen negligibly small to simulate an ideal switch. A pulse volt-
age source acts as the control for the switch.
When periodic closing and opening of the switch in a dc-dc converter begins,
a transient response precedes the steady-state voltages and currents described ear-
lier in this chapter. The following example illustrates a PSpice simulation for a
buck converter using idealized models for circuit components.
EXAMPLE 6-11
Buck Converter Simulation Using Idealized Components

Use PSpice to verify the buck converter design in Example 6-3.
The buck converter has the following parameters:
Vs 3.3 V
L 1 H
C 667 F with an ESR of 15 m
R 0.3 for a load current of 4 A
D 0.364 for an output of 1.2 V
Switching frequency 500 kHz
■ Solution
A PSpice model for the buck converter is shown in Fig. 6-28. A voltage-controlled switch
(Sbreak) is used for the switching transistor, with the on resistance Ron set to 1 m to
approximate an ideal device. An ideal diode is simulated by letting the diode parameter n
(the emission coefficient in the diode equation) be 0.001. The switch is controlled by a
pulse voltage source. The parameter statements file facilitates modification of the circuit
file for other buck converters. Initial conditions for the inductor current and capacitor
voltage are assumed to be zero to demonstrate the transient behavior of the circuit.
Figure 6-29a shows the Probe output for inductor current and capacitor voltage.
Note that there is a transient response of the circuit before the steady-state periodic con-
dition is reached. From the steady-state portion of the Probe output shown in Fig. 6-29b,
the maximum and minimum values of the output voltage are 1.213 and 1.1911 V, respec-
tively, for a peak-to-peak variation of about 22 mV, agreeing well with the 24-mV design
objective. The maximum and minimum inductor currents are about 4.77 and 3.24 A,
agreeing well with the 4.8- and 3.2-A design objectives.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 253
BUCK CONVERTER
Ideal switch and diode
Input vx L1 1u Output
1 2
+ S1
+−
+ Vs Sbreak
3.3 667u C1 RL
− D1 0.3
Dbreak
15m Resr
PARAMETERS:
V1 = 0 Vcontrol Duty = 0.364
+
V2 = 5 Freq = 500k
−
TD = 0
TR = 1n
TF = 1n
PW = {Duty/Freq} .model Dbreak D n=0.001
PER = {1/Freq} .model Sbreak VSWITCH Roff =1e6 Ron=0.001 Voff=0.0 Von=1.0
Figure 6-28 PSpice circuit for the buck converter.
30
BUCK TRANSIENTS AT START UP

20
10
INDUCTOR CURRENT
OUTPUT VOLTAGE
0
0s 0.2 ms 0.4 ms 0.6 ms 0.8 ms 1.0 ms
V(OUTPUT) I (L1)
Time
(a)
Figure 6-29 Probe output for Example 6-11 (a) showing the transient at start-up and (b) in
steady state.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 254

(982.730u, 4.7721) INDUCTOR CURRENT

5.0 A
2.5 A
(988.000u, 3.2438)
SEL>>
0A
I (L1)
1.250 V
(982.730u, 1.2130) OUTPUT VOLTAGE
1.225 V
1.200 V
1.175 V
(988.000u, 1.1911)
1.150 V
0.980 ms 0.985 ms 0.990 ms 0.995 ms 1.000 ms
V(OUTPUT)
Time
(b)
An Averaged Circuit Model

PSpice simulation of the dc-dc buck converter in Example 6-11 includes both the
large scale transient behavior and the cycle-to-cycle waveforms of voltage and
current. If the goal of a simulation is to determine the large-scale transient behav-
ior, the cycle-to-cycle response merely adds to the execution time of the program.
A more time-efficient way to simulate the transient behavior of dc-dc converters
is to use a circuit model that produces the average values of voltages and currents
only, rather than including the detailed variations around the averages. In general,
transient behavior for dc-dc converters can be predicted by analyzing linear
networks, with the response equal to the average value of the switching wave-
forms. The discussion that follows is focused on the buck converter operating in
the continuous-current mode.
The transient behavior of the average output voltage can be described using
linear circuit analysis. The input vx to the RLC circuit of the buck converter of
Fig. 6-3a has an average value of Vx VsD. The response of the RLC circuit to a
step input voltage of vx(t) (VsD)u(t) represents the average of the output voltage
and current waveforms when the converter is turned on. This represents the same
large-scale transient that was present in the PSpice simulation shown in Fig. 6-29a.
For complete simulation of the large-scale behavior of a dc-dc converter, it
is desirable to include the proper voltage and current relationships between the
source and the load. Taking the buck converter as an example, the relationship
between average voltage and current at the input and output for continuous
inductor current is given by
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 255
+
Vs
-
(a)
1:D
+
Vs
-
(b)
DiC iC
+-
a
0V
+ +
Vs Vap + DV
- ap
-
-
p
(c)
Figure 6-30 (a) Buck converter with switch;

(b) Circuit model for averaged buck
converter; (c) PSpice circuit.
Vo Is
D (6-103)
Vs Io
Since Vo Vs D and Io Is /D, the switch in a model for computing average voltage
and current is the same as a “transformer” which has a turns ratio of 1:D. Circuit
models for a buck converter using a 1:D transformer and a PSpice circuit for imple-
menting the averaged model are shown in Fig. 6-30. The circuit symbol for the
transformer indicates that the model is valid for both ac and dc signals.
The following example illustrates the use of the PSpice model to simulate
the response of average voltage and current for a buck converter.
EXAMPLE 6-12
Averaged Buck Converter

Use the averaged circuit of Fig. 6-30c to simulate the buck converter having parameters
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 256
Vs 10 V
D 0.2
L 400 H
C 400 F
R2
f 5 kHz
Use initial conditions of zero for inductor current and capacitor voltage.
■ Solution
The PSpice implementation of the averaged model is shown in Fig. 6-31a. The simulation
results from both a switched model and for the averaged model are shown in Fig. 6-31b.
Note that the switched model shows the cycle-to-cycle variation, while the average model
shows only the averaged values.
Buck Converter
Averaged Model
F
A C 1 2
400u
+ + {+{ 400u 2
10 - -
- P
E
Set gain = Duty ratio
for E and F
0
(a)
4.0
SWITCHED MODEL
OUTPUT VOLTAGE
2.0
INDUCTOR CURRENT
0
I (L2) V(Output_Switched)
4.0
AVERAGED MODEL
OUTPUT VOLTAGE
2.0
SEL >> INDUCTOR CURRENT

0
0s 2.0 ms 4.0 ms 6.0 ms 8.0 ms
I (L1) V(Output_Avg)
Time
(b)
Figure 6-31 (a) PSpice implementation of the averaged buck converter model; (b) Probe
output for both the switched model and the averaged model.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 257
The averaged model can be quite useful in investigating the dynamic behav-
ior of the converter when it is subjected to changes in operating parameters. Such
an analysis is essential when the output is regulated through a feedback loop
which is designed to keep the output at a set level by adjusting the duty ratio of
the switch to accommodate variations in the source or the load. Closed-loop re-
sponse is discussed in Chap. 7 on dc power supplies.
The following example illustrates the use of the averaged circuit model to
simulate a step change in load resistance.
EXAMPLE 6-13
Step Change in Load

Use the averaged buck converter model to determine the dynamic response when the load
resistance is changed. The circuit parameters are
Vs 50 V
L 1 mH with a series resistance of 0.4
C 100 F with an equivalent series resistance of 0.5
R 4 , stepped to 2 and back to 4
D 0.4
Switching frequency 5 kHz
■ Solution
Step changes in load are achieved by switching a second 4- resistor across the output at
6 ms and disconnecting it at 16 ms. The averaged model shows the transients associated
with output voltage and inductor current (Fig. 6-32b). Also shown for comparison are the
results of a different simulation using a switch, showing the cycle-to-cycle variations in
voltage and current.
Buck Converter
Averaged Model
F 1 2
1m
4
+ 100u 4
+ {-+{ ++
10 - TD = 6m
- - +
0.5 TF = 1n
E Set gain = Duty ratio -
PW = 10m
for E1 and F1 PER = 20m
0 V1 = 0
TR = 1n
(a) V2 = 5
Figure 6-32 (a) PSpice implementation of the averaged model with a switched load;
(b) Probe results for both the switched model and the averaged model.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 258
SWITCHED MODEL
5.0
OUTPUT VOLTAGE
2.5
INDUCTOR CURRENT
0
V(Output_Switched) I (L2)
AVERAGED MODEL
5.0
OUTPUT VOLTAGE
2.5
INDUCTOR CURRENT
SEL >>
0
0s 5 ms 10 ms 15 ms 20 ms
V(Output_Avg) I (L1)
Time
(b)
DiC iC
a c
+ −
0V
+
Dvap
−
p
(a)
a c c p
+ +
p a
− −
Figure 6-33
Averaged switch
model in dc-dc (b) (c)
converters. (a) PSpice
averaged model for a p
switch and diode;
+ + a p
(b) Buck equivalent; c
(c) Boost equivalent; − − c
(d) Buck-boost
equivalent; (e) Ćuk
equivalent. (d) (e)
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 259
The averaged switch model can be used to simulate the other dc-dc convert-
ers discussed in this chapter. Figure 6-33 shows how the average switch model is
used in the boost, buck-boost, and Ćuk converters for continuous-current opera-
tion. The designation of the switch terminals a, p, and c represents active, pas-
sive, and common terminals.
6.14 Summary
• A switched-mode dc-dc converter is much more efficient than a linear converter
because of reduced losses in the electronic switch.
• A buck converter has an output voltage less than the input.
• A boost converter has an output voltage greater than the input.
• Buck-boost and Ćuk converters can have output voltages greater than or less than
the input, but there is a polarity reversal.
• A SEPIC (single-ended primary-inductor converter) can have an output voltage
greater than or less than the input with no polarity reversal.
• Output voltage is generally reduced from the theoretical value when switch drops
and inductor resistances are included in the analysis.
• Capacitor equivalent series resistance (ESR) may produce an output voltage ripple
much greater than that of the capacitance alone.
• Interleaved converters have parallel switch/inductor paths to reduce the current
variation in the output capacitor.
• Discontinuous-current modes for dc-dc converters are possible and sometimes
desirable, but input-output relationships are different from those for the
continuous-current modes.
• Switched-capacitor converters charge capacitors in one configuration and then use
switches to reconnect the capacitors to produce an output voltage different from the
input.
• PSpice can be used to simulate dc-dc converters by using a voltage-controlled
switch or by using an averaged circuit model.
6.15 Bibliography
S. Ang and A. Oliva, Power-Switching Converters, 2d ed., Taylor & Francis, Boca
Raton, Fla., 2005.
C. Basso, Switch-Mode Power Supplies, McGraw-Hill, New York, 2008.
B. K. Bose, Power Electronics and Motor Drives: Advances and Trends,
Elsevier/Academic Press, Boston, 2006.
R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 2d ed.,
Kluwer Academic, Boston, 2001.
W. Gu, “Designing a SEPIC Converter,” National Semiconductor Application Note
1484, 2007, http://www.national.com/an/AN/AN-1484.pdf.
P. T. Krein, Elements of Power Electronics, Oxford University Press, New York, 1998.
D. Maksimović, and S. Dhar, “Switched-Capacitor DC-DC Converters for Low-Power
On-Chip Applications,” IEEE Annual Power Electronics Specialists Conference,
vol. 1, pp. 54–59, 1999.
R. D. Middlebrook and, S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I
and II, TESLAco, Pasadena, Calif., 1981.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 260
A. I. Pressman, K. Billings, and T. Morey, Switching Power Supply Design, McGraw-

Hill, New York, 2009.
“SEPIC Equations and Component Ratings,” MAXIM Application Note 1051, 2002,
http://www.maxim-ic.com/an1051.
V. Vorperian, “Simplified Analysis of PWM Converters Using Model of PWM Switch”,
IEEE Transactions on Aerospace and Electronic Systems, May 1990.
Problems
Linear Converters
6-1. What is the relationship between Vo/Vs and efficiency for the linear converter
described in Sec. 6.1?
6-2. A dc power supply must step down a 100-V. source to 30 V. The output power is
100 W. (a) Determine the efficiency of the linear converter of Fig. 6-1 when it is
used for this application. (b) How much energy is lost in the transistor in 1 yr?
(c) Using the electric rate in your area, what is the cost of the energy loss for 1 yr?
Basic Switched Converter
6-3. The basic dc-dc converter of Fig. 6-2a has a source of 100 V and a load
resistance of 10 . The duty ratio of the switch is D 0.6, and the switching
frequency is 1 kHz. Determine (a) the average voltage across the load, (b) the
rms voltage across the load, and (c) the average power absorbed by the load.
(d) What would happen if the switching frequency were increased to 2 kHz?
Buck Converter
6-4. The buck converter of Fig. 6-3a has the following parameters: Vs 24 V, D 0.65,
L 25 H, C 15 F, and R 10 . The switching frequency is 100 kHz.
Determine (a) the output voltage, (b) the maximum and minimum inductor currents,
and (c) the output voltage ripple.
6-5. The buck converter of Fig. 6-3a has the following parameters: Vs 15 V, D 0.6,
L 10 H, C 50 F, and R 5 . The switching frequency is 150 kHz.
Determine (a) the output voltage, (b) the maximum and minimum inductor
currents, and (c) the output voltage ripple.
6-6. The buck converter of Fig. 6-3a has an input of 50 V and an output of 25 V. The
switching frequency is 100 kHz, and the output power to a load resistor is 125 W.
(a) Determine the duty ratio. (b) Determine the value of inductance to limit the
peak inductor current to 6.25 A. (c) Determine the value of capacitance to limit
the output voltage ripple to 0.5 percent.
6-7. A buck converter has an input of 6 V and an output of 1.5 V. The load resistor
is 3 , the switching frequency is 400 kHz, L 5 H, and C 10 F.
(a) Determine the duty ratio. (b) Determine the average, peak, and rms inductor
currents. (c) Determine the average source current. (d) Determine the peak and
average diode current.
6-8. The buck converter of Fig. 6-3a has Vs 30 V, Vo 20 V, and a switching
frequency of 40 kHz. The output power is 25 W. Determine the size of the inductor
such that the minimum inductor current is 25 percent of the average inductor current.
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 261
Problems 261
6-9. A buck converter has an input voltage that varies between 50 and 60 V and a load
that varies between 75 and 125 W. The output voltage is 20 V. For a switching
frequency of 100 kHz, determine the minimum inductance to provide for
continuous current for every operating possibility.
6-10. A buck converter has an input voltage that varies between 10 and 15 V and a load
current that varies between 0.5 A and 1.0 A. The output voltage is 5 V. For a
switching frequency of 200 kHz, determine the minimum inductance to provide
for continuous current for every operating possibility.
6-11. Design a buck converter such that the output voltage is 15 V when the input is 48 V.
The load is 8 . Design for continuous inductor current. The output voltage
ripple must be no greater than 0.5 percent. Specify the switching frequency and
the value of each of the components. Assume ideal components.
6-12. Specify the voltage and current ratings for each of the components in the design
of Prob. 6-11.
6-13. Design a buck converter to produce an output of 15 V from a 24-V source. The
load is 2 A. Design for continuous inductor current. Specify the switching
frequency and the values of each of the components. Assume ideal components.
6-14. Design a buck converter that has an output of 12 V from an input of 18 V. The
output power is 10 W. The output voltage ripple must be no more than 100 mV
p-p. Specify the duty ratio, switching frequency, and inductor and capacitor
values. Design for continuous inductor current. Assume ideal components.
6-15. The voltage Vx in Fig. 6-3a for the buck converter with continuous inductor
current is the pulsed waveform of Fig. 6-2c. The Fourier series for this waveform
has a dc term of VsD. The ac terms have a fundamental frequency equal to the
switching frequency and amplitudes given by
22Vs
Vn 21 cos (2nD) n 1, 2, 3, . . .
n
Using ac circuit analysis, determine the amplitude of the first ac term of the
Fourier series for voltage across the load for the buck converter in Example 6-1.
Compare your result with the peak-to-peak voltage ripple determined in the
example. Comment on your results.
6-16. (a) If the equivalent series resistance of the capacitor in the buck converter in
Example 6-2 is 0.5 , recompute the output voltage ripple. (b) Recompute the
required capacitance to limit the output voltage ripple to 0.5 percent if the ESR
of the capacitor is given by rC 50(10)6/C, where C is in farads.
Boost Converter
6-17. The boost converter of Fig. 6-8 has parameter Vs 20 V, D 0.6, R 12.5 ,
L 10 H, C 40 F, and the switching frequency is 200 kHz. (a) Determine
the output voltage. (b) Determine the average, maximum, and minimum inductor
currents. (c) Determine the output voltage ripple. (d) Determine the average
current in the diode. Assume ideal components.
6-18. For the boost converter in Prob. 6-17, sketch the inductor and capacitor currents.
Determine the rms values of these currents.
6-19. A boost converter has an input of 5 V and an output of 25 W at 15 V. The
minimum inductor current must be no less than 50 percent of the average. The
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 262
output voltage ripple must be less than 1 percent. The switching frequency is
300 kHz. Determine the duty ratio, minimum inductor value, and minimum
capacitor value.
6-20. Design a boost converter to provide an output of 18 V from a 12-V source. The
load is 20 W. The output voltage ripple must be less than 0.5 percent. Specify the
duty ratio, the switching frequency, the inductor size and rms current rating, and
the capacitor size and rms current rating. Design for continuous current. Assume
ideal components.
6-21. The ripple of the output voltage of the boost converter was determined assuming
that the capacitor current was constant when the diode was off. In reality, the
current is a decaying exponential with a time constant RC. Using the capacitance
and resistance values in Example 6-4, determine the change in output voltage
while the switch is closed by evaluating the voltage decay in the RC circuit.
Compare it to that determined from Eq. (6-34).
6-22. For the boost converter with a nonideal inductor, produce a family of curves of
Vo/Vs similar to Fig. 6-10a for rL/R 0.1, 0.3, 0.5, and 0.7.
Buck-boost Converter
6-23. The buck-boost converter of Fig. 6-11 has parameters Vs 12 V, D 0.6, R 10 ,
L 10 H, C 20 F, and a switching frequency of 200 kHz. Determine
(a) the output voltage, (b) the average, maximum, and minimum inductor
6-24. Sketch the inductor and capacitor currents for the buck-boost converter in
Prob. 6-23. Determine the rms values of these currents.
6-25. The buck-boost converter of Fig. 6-11 has Vs 24 V, Vo 36 V, and a load
resistance of 10 . If the switching frequency is 100 kHz, (a) determine the induc-
tance such that the minimum current is 40 percent of the average and (b) determine
the capacitance required to limit the output voltage ripple to 0.5 percent.
6-26. Design a buck-boost converter to supply a load of 75 W at 50 V from a 40-V
source. The output ripple must be no more than 1 percent. Specify the duty ratio,
switching frequency, inductor size, and capacitor size.
6-27. Design a dc-dc converter to produce a 15-V output from a source that varies
from 12 to 18 V. The load is a 15- resistor.
6-28. Design a buck-boost converter that has a source that varies from 10 to 14 V. The
output is regulated at 12 V. The load varies from 10 to 15 W. The output
voltage ripple must be less than 1 percent for any operating condition. Determine
the range of the duty ratio of the switch. Specify values of the inductor and
capacitor, and explain how you made your design decisions.
Ćuk Converter
6-29. The Ćuk converter of Fig. 6-13a has parameters Vs 12 V, D 0.6, L1 200 H,
L2 100 H, C1 C2 2 F, and R 12 , and the switching frequency is
250 kHz. Determine (a) the output voltage, (b) the average and the peak-to-peak
variation of the currents in L1 and L2, and (c) the peak-to-peak variation in the
capacitor voltages.
6-30. The Ćuk converter of Fig. 6-13a has an input of 20 V and supplies an output of
1.0 A at 10 V. The switching frequency is 100 kHz. Determine the values of L1
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 263
Problems 263
and L2 such that the peak-to-peak variation in inductor currents is less than
10 percent of the average.
6-31. Design a Ćuk converter that has a in input of 25 V and an output of 30 V. The
load is 60 W. Specify the duty ratio, switching frequency, inductor values, and
capacitor values. The maximum change in inductor currents must be 20 percent
of the average currents. The ripple voltage across C1 must be less than 5 percent,
and the output ripple voltage must be less than 1 percent.
SEPIC Circuit
6-32. The SEPIC circuit of Fig. 6-14a has Vs 5 V, Vo 12 V, C1 C2 50 µF,
L1 10 H, and L2 20 H. The load resistor is 4 . Sketch the currents in
L1 and L2, indicating average, maximum, and minimum values. The switching
frequency is 100 kHz.
6-33. The SEPIC circuit of Fig. 6-14a has Vs 3.3 V, D 0.7, L1 4 H, and L2
10 H. The load resistor is 5 . The switching frequency is 300 kHz. (a) Determine
the maximum and minimum values of the currents in L1 and L2. (b) Determine
the variation in voltage across each capacitor.
6-34. The relationship between input and output voltages for the SEPIC circuit of
Fig. 6-14a expressed in Eq. (6-74) was developed using the average voltage
across L1. Derive the relationship using the average voltage across L2.
6-35. A SEPIC circuit has an input voltage of 15 V and is to have an output of 6 V. The
load resistance is 2 , and the switching frequency is 250 kHz. Determine values
of L1 and L2 such that the variation in inductor current is 40 percent of the
average value. Determine values of C1 and C2 such that the variation in capacitor
voltage is 2 percent.
6-36. A SEPIC circuit has an input voltage of 9 V and is to have an output of 2.7 V.
The output current is 1 A, and the switching frequency is 300 kHz. Determine
values of L1 and L2 such that the variation in inductor current is 40 percent of the
average value. Determine values of C1 and C2 such that the variation in capacitor
voltage is 2 percent.
Nonideal Effects
6-37. The boost converter of Example 6-4 has a capacitor with an equivalent series
resistance of 0.6 . All other parameters are unchanged. Determine the output
voltage ripple.
6-38. Equation (6-88) expresses the output voltage of a buck converter in terms of
input, duty ratio, and voltage drops across the nonideal switch and diode. Derive
an expression for the output voltage of a buck-boost converter for a nonideal
switch and diode.
Discontinuous Current
6-39. The buck converter of Example 6-2 was designed for a 10- load. (a) What is
the limitation on the load resistance for continuous-current operation? (b) What
would be the range of output voltage for a load resistance range of 5 to 20 ?
(c) Redesign the converter so inductor current remains continuous for a load
resistance range of 5 to 20 .
har80679_ch06_196-264.qxd 12/16/09 12:29 PM Page 264
6-40. The boost converter of Example 6-4 was designed for a 50- load. (a) What is
the limitation on the load resistance for continuous-current operation? (b) What
would be the range of output voltage for a load resistance range of 25 to 100 ?
(c) Redesign the converter so inductor current remains continuous for a load
resistance range of 25 to 100 .
6-41. Section 6.11 describes the buck and boost converters for discontinuous-current
operation. Derive an expression for the output voltage of a buck-boost converter
when operating in the discontinuous-current mode.
Switched-capacitor Converters
6-42. Capacitors C1 and C2 in Fig. P6-42 are equal in value. In the first part of the
switching cycle, the switches labeled 1 are closed while the switches labeled 2
are open. In the second part of the cycle, switches 1 are opened and then switches
2 are closed. Determine the output voltage Vo at the end of the switching cycle.
Note: A third capacitor would be placed from Vo to ground to sustain the output
voltage during subsequent switching cycles.
PSpice
6-43. Simulate the buck converter of Example 6-11, but use the IRF150 MOSFET
from the PSpice device library for the switch. Use an idealized gate drive circuit
of a pulsed voltage source and small resistance. Use the default model for the
diode. Use Probe to graph p(t) versus.t for the switch for steady-state conditions.
Determine the average power loss in the switch.
6-44. Simulate the buck converter of Example 6-1 using PSpice. (a) Use an ideal
switch and ideal diode. Determine the output ripple voltage. Compare your
PSpice results with the analytic results in Example 6-1. (b) Determine the steady-
state output voltage and voltage ripple using a switch with an on resistance of
2 and the default diode model.
6-45. Show that the equivalent circuits for the PSpice averaged models in Fig. 6-33
satisfy the average voltage and current input-output relationships for each of the
converters.
1 1 1
C1 C2
+
Vs 2
- 2 Vo
Figure P6-42
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 265
C H A P T E R 7
DC Power Supplies
7.1 INTRODUCTION
A basic disadvantage of the dc-dc converters discussed in Chap. 6 is the elec-
trical connection between the input and the output. If the input supply is
grounded, that same ground will be present on the output. A way to isolate the
output from the input electrically is with a transformer. If the dc-dc converter
has a first stage that rectifies an ac power source to dc, a transformer could be
used on the ac side. However, not all applications require ac to dc conversion
as a first stage. Moreover, a transformer operating at a low frequency (50 or
60 Hz) requires a large magnetic core and is therefore relatively large, heavy,
and expensive.
A more efficient method of providing electrical isolation between input
and output of a dc-dc converter is to use a transformer in the switching
scheme. The switching frequency is much greater than the ac power-source
frequency, enabling the transformer to be small. Additionally, the transformer
turns ratio provides increased design flexibility in the overall relationship
between the input and the output of the converter. With the use of multiple
transformer windings, switching converters can be designed to provide multi-
ple output voltages.
7.2 TRANSFORMER MODELS

Transformers have two basic functions: to provide electrical isolation and to step
up or step down time-varying voltages and currents. A two-winding transformer
265
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 266
266 C H A P T E R 7 DC Power Supplies
is depicted in Fig. 7-1a. An idealized model for the transformer, as shown in

Fig. 7-1b, has input-output relationships
v1 N1

v2 N 2
(7-1)
i 1 N2

i 2 N1
The dot convention is used to indicate relative polarity between the two
windings. When the voltage at the dotted terminal on one winding is positive, the
voltage at the dotted terminal on the other winding is also positive. When current
enters the dotted terminal on one winding, current leaves the dotted terminal on
the other winding.
A more complete transformer model is shown in Fig. 7-1c. Resistors r1
and r2 represent resistances of the conductors, L1 and L2 represent leakage
inductances of the windings, Lm represents magnetizing inductance, and rm
represents core loss. The ideal transformer is incorporated into this model
to represent the voltage and current transformation between primary and
secondary.
In some applications in this chapter, the ideal transformer representation is
sufficient for preliminary investigation of a circuit. The ideal model assumes that
the series resistances and inductances are zero and that the shunt elements are
infinite. A somewhat better approximation for power supply applications includes
the magnetizing inductance Lm, as shown in Fig. 7-1d. The value of Lm is an
important design parameter for the flyback converter.
i1 N1 N2 i2
i1 i2 + +
+ N1 +
v1 v2 v1 v2
− N2 −
− −
(a) (b)
r1 L1 N1 N2 r2 L2 i1 N1 N2 i2
+ +
rm Lm v 1 Lm v2
− −
(c) (d)
Figure 7-1 (a) Transformer; (b) Ideal model; (c) Complete model; (d) Model used for most power
electronics circuits.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 267
The leakage inductances L1 and L2 are usually not crucial to the general
operation of the power electronics circuits described in this chapter, but they are
important when considering switching transients. Note that in ac power system
applications, the leakage inductance is normally the important analysis and
design parameter.
For periodic voltage and current operation for a transformer circuit, the
magnetic flux in the core must return to its starting value at the end of each
switching period. Otherwise, flux will increase in the core and eventually
cause saturation. A saturated core cannot support a voltage across a trans-
former winding, and this will lead to device currents that are beyond the
design limits of the circuit.
7.3 THE FLYBACK CONVERTER

Continuous-Current Mode
A dc-dc converter that provides isolation between input and output is the flyback
circuit of Fig. 7-2a. In a first analysis, Fig. 7-2b uses the transformer model
which includes the magnetizing inductance Lm, as in Fig. 7-1d. The effects of
+
Vo
+ −
Vs
−
(a)
iD
is i1
N1 N2
+
+ − + vD − i
C iR
iLm Lm v1 v2 C R Vo
+ − +
Vs
− −
i2
+
vSW Transformer
−
(b)
Figure 7-2 (a) Flyback converter; (b) Equivalent circuit using

a transformer model that includes the magnetizing inductance;
(c) Circuit for the switch on; (d) Circuit for the switch off.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 268
is = iLm iD
0 N1 N2 N1 N2
+
+ + −
iLm N1
v1 = Vs v1 = −Vo v2 = −Vs Vo
N2
− iLm −
Vs + +
Vs −
+
− −
0
+ N
vSW = Vs + Vo 1
N2
−
(c) (d)
losses and leakage inductances are important when considering switch perfor-
mance and protection, but the overall operation of the circuit is best understood
with this simplified transformer model. Note the polarity of the transformer
windings in Fig. 7-2.
Additional assumptions for the analysis are made:
1. The output capacitor is very large, resulting in a constant output
voltage Vo.
2. The circuit is operating in the steady state, implying that all voltages and
currents are periodic, beginning and ending at the same points over one
switching period.
3. The duty ratio of the switch is D, being closed for time DT and open for
(1 D)T.
4. The switch and diode are ideal.
The basic operation of the flyback converter is similar to that of the buck-
boost converter described in Chap. 6. Energy is stored in Lm when the switch is
closed and is then transferred to the load when the switch is open. The circuit is
analyzed for both switch positions to determine the relationship between input
and output.
Analysis for the Switch Closed On the source side of the transformer
(Fig. 7-2c),
di Lm
v1 Vs L m
dt
di Lm i Lm i Lm V
s
dt t DT Lm
Solving for the change in current in the transformer magnetizing inductance,
Vs DT
( i Lm)closed (7-2)
Lm
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 269
On the load side of the transformer,

N2 N
v2 v1 a b Vs a 2 b
N1 N1
N2
vD Vo Vs a b0
N1
i2 0
i1 0
Since the diode is off, i2 0, which means that i1 0. So while the switch is
closed, current is increasing linearly in the magnetizing inductance Lm, and
there is no current in the windings of the ideal transformer in the model.
Remember that in the actual transformer, this means that the current is
increasing linearly in the physical primary winding, and no current exists in
the secondary winding.
Analysis for the Switch Open When the switch opens (Fig. 7-2d), the current
cannot change instantaneously in the inductance Lm, so the conduction path must
be through the primary turns of the ideal transformer. The current iLm enters the
undotted terminal of the primary and must exit the undotted terminal of the sec-
ondary. This is allowable since the diode current is positive. Assuming that the
output voltage remains constant at Vo, the transformer secondary voltage v2
becomes Vo. The secondary voltage transforms back to the primary, establish-
ing the voltage across Lm at
N1
v1 Vo a b
N2
Voltages and currents for an open switch are

v2 Vo
N1 N
v1 v2 a b Vo a 1 b
N2 N2
di Lm N
Lm v1 Vo a 1 b
dt N2
di Lm i Lm i Lm Vo N1
a b
dt t (1 D)T L m N2
Solving for the change in transformer magnetizing inductance with the switch
open,
Vo(1 D)T N1
( i Lm)open a b (7-3)
Lm N2
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Since the net change in inductor current must be zero over one period for
steady-state operation, Eqs. (7-2) and (7-3) show
( i Lm)closed ( i Lm)open 0
Vs DT Vo(1 D)T N1
a b 0
Lm Lm N2
Solving for Vo,
D N
Vo Vs a b a 2b (7-4)
1 D N1
Note that the relation between input and output for the flyback converter is sim-
ilar to that of the buck-boost converter but includes the additional term for the
transformer ratio.
Other currents and voltages of interest while the switch is open are
N1 N
iD i1 a b i Lm a 1 b
N2 N2
N1
vsw Vs v1 Vs Vo a b
N2
(7-5)
V
iR o
R
N1 V
i C i D i R i Lm a b o
N2 R
Note that vsw, the voltage across the open switch, is greater than the source volt-
age. If the output voltage is the same as the input and the turns ratio is 1, for
example, the voltage across the switch will be twice the source voltage. Circuit
currents are shown in Fig. 7-3.
The power absorbed by the load resistor must be the same as that supplied
by the source for the ideal case, resulting in
Ps Po
V 2o
or Vs Is (7-6)
R
The average source current Is is related to the average of the magnetizing induc-
tance current ILm by
(ILm)DT
Is ILmD (7-7)
T
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 271
iLm
ΔiLm
DT T t
(a)
is
DT T t
(b)
iD
DT T t
(c)
iC
Vo
−
R
(d)
v1
Vs
t
N1
−Vo
N2
(e)
Figure 7-3 Flyback converter current and voltage waveforms.

(a) Magnetizing inductance current; (b) Source current; (c) Diode
current; (d) Capacitor current; (e) Transformer primary voltage.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 272
Substituting for Is in Eq. (7-6) and solving for ILm,

V 2o
Vs ILmD
R
(7-8)
V 2o
ILm
Vs DR
Using Eq. (7-4) for Vs, the average inductor current is also expressed as
Vs D N2 2 Vo N
ILm 2 a b a 2b (7-9)
(1 D) R N1 (1 D)R N1
The maximum and minimum values of inductor current are obtained from
Eqs. (7-9) and (7-2).
i Lm
ILm, max ILm
2
(7-10)
Vs D N2 2 Vs DT
a b
(1 D)2R N1 2L m
i Lm
ILm, min ILm
2 (7-11)
Vs D N2 2 Vs DT
a b
(1 D)2R N1 2L m
Continuous-current operation requires that ILm,min 0 in Eq. (7-11). At the

boundary between continuous and discontinuous current,
ILm, min 0
VsD N2 2 Vs DT VD
2 a b s
(1 D) R N1 2L m 2L m f
where f is the switching frequency. Solving for the minimum value of Lm that will
allow continuous current,
(1 D)2R N1 2
(L m)min a b (7-12)
2f N2
In a flyback converter design, Lm is selected to be larger than Lm,min to ensure

continuous current operation. A convenient expression relating inductance and
current variation is found from Eq. (7-2).
Vs DT Vs D
Lm (7-13)
i Lm i Lm f
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 273
The output configuration for the flyback converter is the same as for the buck-
boost converter, so the output ripple voltages for the two converters are also
the same.
Vo D
(7-14)
Vo RCf
As with the converters described in Chap. 6, the equivalent series resistance of

the capacitor can contribute significantly to the output voltage ripple. The peak-to-
peak variation in capacitor current is the same as the maximum current in the diode
and the transformer secondary. Using Eq. (7-5), the voltage ripple due to the ESR is
N1
Vo, ESR i C rC ILm, max a br (7-15)
N2 C
EXAMPLE 7-1
Flyback Converter
A flyback converter of Fig. 7-2 has the following circuit parameters:
Vs 24 V
N1/N2 3.0
Lm 500 H
R5
C 200 F
f 40 kHz
Vo 5 V
Determine (a) the required duty ratio D; (b) the average, maximum, and minimum values
for the current in Lm; and (c) the output voltage ripple. Assume that all components are ideal.
■ Solution
(a) Rearranging Eq. (7-4) yields
Vo Vs a
D
b a 2b
N
1 D N1
1 1
D 0.385
(Vs>Vo)(N2>N1) 1 (24>5)(1>3) 1
(b) Average current in Lm is determined from Eq. (7-8).
V 2o 52
ILm 540 mA
Vs DR (24)(0.385)(5)
The change in iLm can be calculated from Eq. (7-2).
Vs D (24)(0.385)
i Lm 460 mA
L m f 500 (10)6(40,000)
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 274
Maximum and minimum inductor currents can be computed from

i Lm 460
ILm, max ILm 540 770 mA
2 2
i Lm 460
ILm, min ILm 540 310 mA
2 2
Equations (7-10) and (7-11), which are derived from the above computation, could
also be used directly to obtain the maximum and minimum currents. Note that a
positive ILm, min verifies continuous current in Lm.
(c) Output voltage ripple is computed from Eq. (7-14).
Vo D 0.385
0.0096 0.96%
Vo RCf (5)3200(10)64(40,000)
EXAMPLE 7-2
Flyback Converter Design, Continuous-Current Mode

Design a converter to produce an output voltage of 36 V from a 3.3-V source. The output
current is 0.1 A. Design for an output ripple voltage of 2 percent. Include ESR when
choosing a capacitor. Assume for this problem that the ESR is related to the capacitor
value by rC 105/C.
■ Solution
Considering a boost converter for this application and calculating the required duty ratio
from Eq. (6-27),
Vs 3.3
D1 1 0.908
Vo 36
The result of a high duty ratio will likely be that the converter will not function as desired
because of losses in the circuit (Fig. 6-10). Therefore, a boost converter would not be a
good choice. A flyback converter is much better suited for this application.
As a somewhat arbitrary design decision, start by letting the duty ratio be 0.4. From
Eq. (7-4), the transformer turns ratio is calculated to be
V 1D 36 1 0.4
a
N2
b oa b a b 16.36
N1 Vs D 3.3 0.4
Rounding, let N2/N1 16. Recalculating the duty ratio using a turns ratio of 16 gives
D 0.405.
To determine Lm, first compute the average current in Lm from Eq. (7-9), using
Io Vo /R.
Vo 0.1
a 2b o a 2b a
N I N
ILm b16 2.69 A
(1 D)R N1 1 D N1 1 0.405
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 275
Let the current variation in Lm be 40 percent of the average current: iLm 0.4(2.69) 1.08 A.
As another somewhat arbitrary choice, let the switching frequency be 100 kHz. Using
Eq. (7-13),
Vs D 3.3(0.405)
Lm 12.4 H
i Lm f 1.08(100,000)
Maximum and minimum currents in Lm are found from Eqs. (7-10) and (7-11) as 3.23 and
2.15 A, respectively.
The output voltage ripple is to be limited to 2 percent, which is 0.02(36) 0.72 V.
Assume that the primary cause of the voltage ripple will be the voltage drop across the
equivalent series resistance iC rC. The peak-to-peak variation in capacitor current is the
same as in the diode and the transformer secondary and is related to current in Lm by
1
i C ILm, max a
N1
b (3.23 A)a b 0.202 A
N2 16
Using Eq. (7-15),

Vo, ESR 0.72 V
rC 3.56 Æ
i C 0.202 A
Using the relationship between ESR and capacitance given in this problem,
10 5 10 5
C 2.8 F
rC 3.56
The ripple voltage due to the capacitance only is obtained from Eq. (7-14) as
Vo D 0.405
0.004 0.04%
Vo RCf (36 V>0.1 A)32.8(10)64(100,000)
showing that the assumption that the voltage ripple is primarily due to the ESR was cor-
rect. A standard value of 3.3 F would be a good choice. Note that the designer should
consult manufacturers’ specifications for ESR when selecting a capacitor.
The turns ratio of the transformer, current variation, and switching frequency were
selected somewhat arbitrarily, and many other combinations are suitable.
Discontinuous-Current Mode in the Flyback Converter

For the discontinuous-current mode for the flyback converter, the current in
the transformer increases linearly when the switch is closed, just as it did for the
continuous-current mode. However, when the switch is open, the current in the
transformer magnetizing inductance decreases to zero before the start of the next
switching cycle, as shown in Fig. 7-4. While the switch is closed, the increase in
inductor current is described by Eq. (7-2). Since the current starts at zero, the
maximum value is also determined from Eq. (7-2).
Vs DT
ILm, max (7-16)
Lm
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 276
iLm
DT T t
is
DT T t
Figure 7-4 Discontinuous current for the flyback converter.
The output voltage for discontinuous-current operation can be determined

by analyzing the power relationships in the circuit. If the components are ideal,
the power supplied by the dc source is the same as the power absorbed by the
load resistor. Power supplied by the source is the dc voltage times average source
current, and load power is Vo2/R:
Ps Po
V 2o (7-17)
Vs Is
R
Average source current is the area under the triangular waveform of Fig. 7-4b
divided by the period, resulting in
1 V DT 1 V D 2T
Is a b a s b (DT)a b s (7-18)
2 Lm T 2L m
Equating source power and load power [Eq. (7-17)],
V 2s D 2T V 2o
(7-19)
2L m R
Solving for Vo for discontinuous-current operation in the flyback converter,
TR R
Vo Vs D Vs D (7-20)
A 2L m A 2L m f
EXAMPLE 7-3
Flyback Converter, Discontinuous Current

For the flyback converter in Example 7-1, the load resistance is increased from 5 to 20
with all other parameters remaining unchanged. Show that the magnetizing inductance
current is discontinuous, and determine the output voltage.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 277
7.4 The Forward Converter 277
■ Solution
Using Lm 500 H, f 40 kHz, N1/N2 3, D 0.385, and R 20 , the minimum
inductor current from Eq. (7-11) is calculated as
Vs D N2 2 Vs DT
ILm, min 2 a b
(1 D) R N1 2L m
(24) (0.385) 1 2 (24) (0.385)
a b 95 mA
2
(1 0.385) (20) 3 2(500)(10)6(40,000)
Since negative current in Lm is not possible, iLm must be discontinuous. Equivalently, the
minimum inductance for continuous current can be calculated from Eq. (7-12).
(1 D)2R N1 2 (1 0.385)220 2
(L m) min a b (3) 850 H
2f N2 2(40,000)
which is more than the 500 H specified, also indicating discontinuous current.
Using Eq. (7-20),
R 20
Vo Vs D (24)(0.385) 6.53 V
A 2L m f A 2(500)(10)6(40,000)
For the current in Lm in the discontinuous-current mode, the output voltage is no longer
5 V but increases to 6.53 V. Note that for any load that causes the current to be continu-
ous, the output would remain at 5 V.
Summary of Flyback Converter Operation

When the switch is closed in the flyback converter of Fig. 7-2a, the source volt-
age is across the transformer magnetizing inductance Lm and causes iLm to
increase linearly. Also while the switch is closed, the diode on the output is
reverse-biased, and load current is supplied by the output capacitor. When the
switch is open, energy stored in the magnetizing inductance is transferred
through the transformer to the output, forward-biasing the diode and supplying
current to the load and to the output capacitor. The input-output voltage relation-
ship in the continuous-current mode of operation is like that of the buck-boost
dc-dc converter but includes a factor for the turns ratio.
7.4 THE FORWARD CONVERTER

The forward converter, shown in Fig. 7-5a, is another magnetically coupled dc-
dc converter. The switching period is T, the switch is closed for time DT and
open for (1 D)T. Steady-state operation is assumed for the analysis of the cir-
cuit, and the current in inductance Lx is assumed to be continuous.
The transformer has three windings: windings 1 and 2 transfer energy from
the source to the load when the switch is closed; winding 3 is used to provide a
path for the magnetizing current when the switch is open and to reduce the mag-
netizing current to zero before the start of each switching period. The transformer
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 278
D3 i3
N3
+ vD3 - iLx
+ D1 Lx
v3 +
N2 + vLx -
is i2
-
+ +
N1 D2 C R Vo
v2 vx
+
Lm
iLm v - -
1
i1 -
-
Vs +
-
+
vSW
-
(a)
N3 iLx
+
N2 + vLx -
+
N2 R Vo
N1 v2 = V s = vx
+ N1
iL m -
v1 = Vs
i1 -
-
Vs +
-
(b)
N3 iL
i3 x
+
N2 + vLx -
+
vx = 0 Vo
N1
-
iL m
-
Vs +
-
(c)
Figure 7-5 (a) Forward dc-dc converter; (b) Circuit for switch closed; (c) Circuit for switch
open.
278
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 279
is modeled as three ideal windings with a magnetizing inductance Lm, which is

placed across winding 1. Leakage inductance and losses are not included in this
simplified transformer model.
For the forward converter, energy is transferred from the source to the load
while the switch is closed. Recall that for the flyback converter, energy was
stored in Lm when the switch was closed and transferred to the load when the
switch was open. In the forward converter, Lm is not a parameter that is included
in the input-output relationship and is generally made large.
Analysis for the Switch Closed The equivalent circuit for the forward con-
verter with the switch closed is shown in Fig. 7-5b. Closing the switch estab-
lishes the voltage across transformer winding 1, resulting in
v1 Vs
N2 N
v2 v1 a b Vs a 2 b (7-21)
N1 N1
N3 N
v3 v1 a b Vs a 3 b
N1 N1
The voltage across D3 is
VD3 Vs v3 0
showing that D3 is off. A positive v2 forward-biases D1 and reverse-biases D2.
The relationship between input and output voltages can be determined by
examining the current in inductor Lx. Assuming the output is held at a constant Vo,
N2 di Lx
vLx v2 Vo Vs ab Vo L x
N1 dt
di Lx Vs(N2>N1) Vo i Lx i Lx

dt Lx t DT
N2 DT
( i Lx)closed c Vs a b Vo d (7-22)
N1 Lx
The voltage across the magnetizing inductance Lm is also Vs, resulting in
Vs DT
i Lm (7-23)
Lm
Equations (7-22) and (7-23) show that the current is increasing linearly in both
Lx and Lm while the switch is closed. The current in the switch and in the physi-
cal transformer primary is
i sw i 1 i Lm (7-24)
Analysis for the Switch Open Figure 7-5c shows the circuit with the switch
open. The currents in Lx and Lm do not change instantaneously when the switch
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 280
is opened. Continuity of iLm establishes i1 iLm. Looking at the transformation

from winding 1 to 2, current out of the dotted terminal on 1 would establish cur-
rent into the dotted terminal on 2, but diode D1 prevents current in that direction.
For the transformation from winding 1 to 3, current out of the dotted termi-
nal of winding 1 forces current into the dotted terminal of winding 3. Diode D3
is then forward-biased to provide a path for winding 3 current, which must go
back to the source.
When D3 is on, the voltage across winding 3 is established at
v3 Vs
With v3 established, v1 and v2 become
N1 N1
v1 v3 a b Vs a b
N3 N3
(7-25)
N2 N2
v2 v3 a b Vs a b
N3 N3
With D1 off and positive current in Lx, D2 must be on. With D2 on, the voltage
across Lx is
di
vLx Vo L x Lx
dt
resulting in
di Lx Vo i Lx i Lx

dt L t (1 D)T
(7-26)
Vo(1 D)T
( i Lx)open
Lx
Therefore, the inductor current decreases linearly when the switch is open.
For steady-state operation, the net change in inductor current over one
period must be zero. From Eq. (7-22) and (7-26),
( i Lx)closed ( i Lx)open 0
N2 DT Vo(1 D)T
c Vs a b Vo d 0
N1 Lx Lx
Solving for Vo,
N2
Vo Vs D a b (7-27)
N1
Note that the relationship between input and output voltage is similar to that for
the buck dc-dc converter except for the added term for the turns ratio. Current in
Lx must be continuous for Eq. (7-27) to be valid.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 281
Meanwhile, the voltage across Lm is v1, which is negative, resulting in

N1 di
vLm v1 Vs a b L m Lm
N3 dt
(7-28)
di Lm V N
s a 1b
dt L m N3
The current in Lm should return to zero before the start of the next period
to reset the transformer core (return the magnetic flux to zero). When the
switch opens, Eq. (7-28) shows that iLm decreases linearly. Since D3 will pre-
vent iLm from going negative, Eq. (7-28) is valid as long as iLm is positive. From
Eq. (7-28),
i Lm Vs N1
a b (7-29)
t L m N3
For iLm to return to zero after the switch is opened, the decrease in current must
equal the increase in current given by Eq. (7-22). Letting Tx be the time for iLm
to decrease from the peak back to zero,
i Lm Vs DT Vs N1
a b (7-30)
Tx Lm L m N3
Solving for Tx,
N3
Tx DT a b (7-31)
N1
The time at which the current iLm reaches zero t0, is
N3 N3
t 0 DT Tx DT DT a b DT a 1 b (7-32)
N1 N1
Because the current must reach zero before the start of the next period,
t0 T
N3
sDT a 1 b T (7-33)
N1
N3
D a1 b 1
N1
For example, if the ratio N3/N1 1 (a common practice), then the duty ratio D
must be less than 0.5. The voltage across the open switch is Vs v1, resulting in
N1 N1
Vs v1 Vs aVs b Vs a1 b for DT t t 0
L
vsw N3 N3 (7-34)
Vs for t 0 t T
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 282
iLx
ΔiLx
DT T
iLm
ΔiLm
DT t0 T
ΔTx
i1
i2
i3
DT t0 T
vx
N2
Vs
N1
DT T
Figure 7-6 Current and voltage waveforms for the forward converter.
Forward converter current and voltage waveforms are shown in Fig. (7-6).
The circuit configuration on the output of the forward converter is the same
as that for the buck converter, so the output voltage ripple based on an ideal
capacitance is also the same.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 283
Vo 1D
(7-35)
Vo 8L x Cf 2
The equivalent series resistance of the capacitor often dominates the output volt-
age ripple. The peak-to-peak voltage variation due to the ESR is
Vo (1 D)
Vo, ESR i C rC i Lx rC c d rC (7-36)
Lx f
where Eq. (7-26) is used for iLx.
Summary of Forward Converter Operation

When the switch is closed, energy is transferred from the source to the load
through the transformer. The voltage on the transformer secondary is a pulsed
waveform, and the output is analyzed like that of the buck dc-dc converter.
Energy stored in the magnetizing inductance while the switch is closed can be
returned to the input source via a third transformer winding while the switch
is open.
EXAMPLE 7-4
Forward Converter
The forward converter of Fig. 7-5a has the following parameters:
Vs 48 V
R 10
Lx 0.4 mH, Lm 5 mH
C 100 F
f 35 kHz
N1/N2 1.5, N1/N3 1
D 0.4
(a) Determine the output voltage, the maximum and minimum currents in Lx, and the out-
put voltage ripple. (b) Determine the peak current in the transformer primary winding.
Verify that the magnetizing current is reset to zero during each switching period. Assume
all components are ideal.
■ Solution
(a) The output voltage is determined from Eq. (7-27).
N2 1
Vo Vs Da b 48(0.4)a b 12.8 V
N1 1.5
Average current in Lx is the same as the current in the load.
Vo 12.8
ILx 1.28 A
R 10
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 284
The change in iLx is determined from Eq. (7-22) or (7-26). Using Eq. (7-26),
Vo(1 D) 12.8(1 0.4)
i Lx 0.55 A
Lx f 0.4(10)3(35,000)
Maximum and minimum currents in Lx are then
i Lx 0.55
ILx, max ILx 1.28 1.56 A
2 2
i Lx 0.55
ILx, min ILx 1.28 1.01 A
2 2
(b) Current in the primary winding of the transformer is the sum of the reflected current
from the secondary and the magnetizing currents. The peak secondary current is the
same as ILx,max. The peak magnetizing current is obtained from Eq. (7-23).
Vs DT 48(0.4)
ILm, max i Lm 0.11 A
Lm 5(10)3(35,000)
The peak current in the transformer primary is therefore
1
Imax ILx, max a
N2
b ILm, max 1.56 a b 0.11 1.15 A
N1 1.5
The time for the magnetizing current to return to zero after the switch is opened is
0.4(1)
Tx DT a
N3
b 11.4 s
N1 35,000
Since the switch is closed for DT 11.4 s, the time at which the magnetizing current
reaches zero is 22.8 s [Eq. (7-32)], which is less than the switching period of 28.6 s.
EXAMPLE 7-5
Forward Converter Design

Design a forward converter such that the output is 5 V when the input is 170 V. The
output current is 5 A. The output voltage ripple must not exceed 1 percent. Choose the
transformer turns ratio, duty ratio, and switching frequency. Choose Lx such that the cur-
rent in it is continuous. Include the ESR when choosing a capacitor. For this problem, use
rC 105/C.
■ Solution
Let the turns ratio N1/N3 1. This results in a maximum duty ratio of 0.5 for the switch.
For margin, let D 0.35. From Eq. (7-27),
N1 Vs D 170 (0.35)
11.9
N2 Vo 5
Rounding, let N1/N2 12. Recalculating D for N1/N2 12 yields
Vo N1 5
D a ba b(12) 0.353
Vs N2 170
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 285
7.5 The Double-Ended (Two-Switch) Forward Converter 285
The inductor Lx and the capacitor are selected using the same design criteria as discussed
for the buck converter in Chap. 6. For this design, let f 300 kHz. The average current
in Lx is 5 A, the same as average current in the load since the average current in the capac-
itor is zero. Let the variation in inductor current be 2 A, which is 40 percent of the aver-
age value. From Eq. (7-26),
Vo(1 D)T Vo(1 D) 5(1 0.353)
Lx 5.39 H
i Lx 0.4ILx f 0.4(5)(300,000)
A standard value of 5.6 H is suitable for this design and would result in a slightly
smaller iLx.
For a 1 percent output voltage ripple,
vo
(0.01)(5) 0.05 V
The capacitor size is determined by assuming that the voltage ripple is produced primar-
ily by the equivalent series resistance, or
Vo L Vo, ESR i C rC (2 A)(rC) 0.05 V

0.05 V
rC 0.025 Æ 25 mÆ
2A
The designer would now search for a capacitor having a 25-m or lower ESR. Using
rC 105/C given in this problem,
10 5
C 400 F
0.025
A standard value of 470 F is suitable.
7.5 THE DOUBLE-ENDED (TWO-SWITCH)

FORWARD CONVERTER
The forward converter discussed in Sec. 7.4 has a single transistor switch and is
referred to as a single-ended converter. The double-ended (two-switch) forward
converter shown in Fig. 7-7 is a variation of the forward converter. In this circuit,
the switching transistors are turned on and off simultaneously. When the
switches are on, the voltage across the primary transformer winding is Vs. The
voltage across the secondary winding is positive, and energy is transferred to
the load, as it was for the forward converter discussed in Sec. 7.4. Also when the
switches are on, the current in the magnetizing inductance is increasing. When
the switches turn off, diode D1 prevents iLm from flowing in the secondary (and
hence primary) winding of the transformer and forces the magnetizing current to
flow in diodes D3 and D4 and back to the source. This establishes the primary
voltage at Vs, causing a linear decrease in magnetizing current. If the duty ratio
of the switches is less than 0.5, the transformer core resets (the magnetic flux
returns to zero) during every cycle.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 286
D3 iLx
D1 Lx
+
N1 N2 + vL −
x
iL
m
+ Lm D2 C R Vo
Vs −
D4
(a)
iLx
+
N1 N2 +
iLm +
N2
Vs + Vs Vs C R Vo
− N1
−
−
−
(b)
iLx
iLm +
0 0 +
Vs +
− 0 Vo
−
(c)
Figure 7-7 (a) Double-ended forward converter; (b) Circuit for the switches
closed; (c) Circuit for the switches open.
The output voltage is the same as for the single-ended forward converter
[Eq. (7-27)]. An advantage of the double-ended forward converter is that
the voltage across an off transistor is Vs rather than Vs(1 + N1/N3) as it was for
the single-ended forward converter. This is an important feature for high-voltage
applications.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 287
7.6 The Push-Pull Converter 287
7.6 THE PUSH-PULL CONVERTER

Another dc-dc converter that has transformer isolation is the push-pull converter
shown in Fig. 7-8a. As with the forward converter, the transformer magnetizing
inductance is not a design parameter. The transformer is assumed to be ideal for
iLx
Np : Ns D1 Lx
+
+ + + vLx −
+
vP2 P2 S2 vS2 C R Vo
vx
− − −
−
+ +
v P1 P1 S1 vS
1
− −
+
Vs
−
D2
+
vSW
Sw2 Sw1
−
(a)
Sw1
On
DT T
Sw2
T T + DT
2 2
(b)
vx
DT T T T
+ DT
2 2
(c)
iLx
ΔiL
x
(d )
Figure 7-8 (a) Push-pull converter; (b) Switching sequence; (c) Voltage vx;
(d) Current in Lx.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 288
this analysis. Switches Sw1 and Sw2 turn on and off with the switching sequence
shown in Fig. 7-8b. Analysis proceeds by analyzing the circuit with either switch
closed and then with both switches open.
Switch Sw1 Closed Closing Sw1 establishes the voltage across primary wind-
ing P1 at
vP1 Vs (7-37)
The voltage across P1 is transformed to the three other windings, resulting in
NS
vS1 Vs a b
NP
NS
vS2 Vs a b (7-38)
NP
vP2 Vs
vSw2 2Vs
Diode D1 is forward-biased, D2 is reverse-biased, and
NS
vx vS2 Vs a b (7-39)
NP
NS
vLx vx Vo Vs a b Vo
NP
Assuming a constant output voltage Vo, the voltage across Lx is a constant, result-
ing in a linearly increasing current in Lx. In the interval when Sw1 is closed, the
change in current in Lx is
i Lx i Lx Vs(NS>NP) Vo

t DT Lx
Vs(NS>NP) Vo
( i Lx)closed c d DT (7-40)
Lx
Switch Sw2 Closed Closing Sw2 establishes the voltage across primary winding
P2 at
vP2 Vs (7-41)
The voltage across P2 is transformed to the three other windings, resulting in
vP1 Vs
NS
vS1 Vs a b
NP
(7-42)
N
vS2 Vs a S b
NP
vS1 2Vs
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 289
7.6 The Push-Pull Converter 289
Diode D2 is forward-biased, D1 is reverse-biased, and

N
vx vS2 Vs a S b
NP
(7-43)
NS
vLx vx Vo Vs a b Vo
NP
which is a positive pulse. The current in Lx increases linearly while Sw2 is closed,
and Eq. (7-40) applies.
Both Switches Open With both switches open, the current in each of the
primary windings is zero. The current in the filter inductor Lx must maintain con-
tinuity, resulting in both D1 and D2 becoming forward-biased. Inductor current
divides evenly between the transformer secondary windings. The voltage across
each secondary winding is zero, and
vx 0
(7-44)
vLx vx Vo Vo
The voltage across Lx is Vo, resulting in a linearly decreasing current in Lx. The
change in current while both switches are open is
i Lx iL x Vo

t T>2 DT Lx
Solving for iLx,
Vo 1
(i Lx)open ab a D bT (7-45)
Lx 2
Since the net change in inductor current over one period must be zero for steady-
state operation,
(i Lx)closed ( i Lx)open 0

(7-46)
Vs(NS>NP) Vo V 1
c d DT a o b a D b T 0
Lx Lx 2
Solving for Vo,
NS
Vo 2Vs a bD (7-47)
NP
where D is the duty ratio of each switch. The above analysis assumes continuous
current in the inductor. Note that the result is similar to that for the buck con-
verter, discussed in Chap. 6. Ripple voltage on the output is derived in a manner
similar to the buck converter. The output ripple for the push-pull converter is
Vo 1 2D
(7-48)
Vo 32L xCf 2
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 290
As with the other converters analyzed previously, the equivalent series resistance
of the capacitor is usually responsible for most of the voltage output ripple.
Recognizing that iC iLx and using Eq. (7-45),
Vo A12 DB
Vo, ESR i CrC i Lx rC B R rC (7-49)
Lx f
The preceding analysis neglected the magnetizing inductance of the trans-
former. If Lm were included in the equivalent circuit, iLm would increase linearly
when Sw1 was closed, circulate while both Sw1 and Sw2 were open, and decrease
linearly when Sw2 was closed. Because Sw1 and Sw2 are closed for equal inter-
vals, the net change in iLm is zero, and the transformer core is reset during each
period in the ideal case. In actual applications of the push-pull converter, control
techniques are used to ensure that the core is reset.
Summary of Push-Pull Operation

Pulses of opposite polarity are produced on the primary and secondary windings
of the transformer by switching Sw1 and Sw2 (Fig. 7-8). The diodes on the sec-
ondary rectify the pulse waveform and produce a waveform vx at the input of the
low-pass filter, as shown in Fig. 7-8c. The output is analyzed like that of the buck
converter discussed in Chap. 6.
EXAMPLE 7-6
Push-Pull Converter
A push-pull converter has the following parameters:
Vs 30 V
NP /NS 2
D 0.3
Lx 0.5 mH
R6
C 50 F
f 10 kHz
Determine Vo, the maximum and minimum values of iLx, and the output ripple voltage.
Assume all components are ideal.
■ Solution
Using Eq. (7-47), the output voltage is
1
Vo 2Vs a
NS
b D (2)(30)a b(0.3) 9.0 V
NP 2
Average inductor current is the same as average load current,
V 9
ILx o 1.5 A
R 6
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 291
7.7 Full-Bridge and Half-Bridge DC-DC Converters 291
The change in iLx is determined from Eq. (7-45).
Vo A12 DB T 9 (0.5 0.3)

i Lx 0.36 A
Lx 0.5(10)3(10,000)
resulting in maximum and minimum currents of
i Lx
ILx, max ILx 1.68 A
2
i Lx
ILx, min ILx 1.32 A
2
Output voltage ripple is determined from Eq. (7-48).
Vo 1 2D 1 2(0.3)

Vo 32f L xC 32(10,000) (0.5)(10)3(50)(10)6
2 2
0.005 0.5%
7.7 FULL-BRIDGE AND HALF-BRIDGE

DC-DC CONVERTERS
The full-bridge and half-bridge converters shown in Figs. 7-9 and 7-10 are simi-
lar in operation to the push-pull converter. Assuming that the transformer is
ideal, the full-bridge converter of Fig. 7-9a has switch pairs (Sw1, Sw2) and (Sw3,
Sw4) alternate closing. When Sw1 and Sw2 are closed, the voltage across the
transformer primary is Vs. When Sw3 and Sw4 are closed, the transformer pri-
mary voltage is Vs. For an ideal transformer, having all switches open will
make vp 0. With a proper switching sequence, the voltage vp across the trans-
former primary is the alternating pulse waveform shown in Fig. 7-9c. Diodes D1
and D2 on the transformer secondary rectify this waveform to produce the volt-
age vx as shown in Fig. 7-9d. This vx is identical to the vx shown in Fig. 7-8c for
the push-pull converter. Hence the output of the full-bridge converter is analyzed
as for the push-pull converter, resulting in
NS
Vo 2Vs a bD (7-50)
VP
where D is the duty ratio of each switch pair.

Note that the maximum voltage across an open switch for the full-bridge
converter is Vs, rather than 2Vs as for the push-pull and single-ended forward
converters. Reduced voltage stress across an open switch is important when
the input voltage is high, giving the full-bridge converter an advantage.
The half-bridge converter of Fig. 7-10a has capacitors C1 and C2 which are
large and equal in value. The input voltage is equally divided between the
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 292
Sw1 Sw3
D1 Lx
+
+
+
NP NS vx C R Vo
+ −
Vs
− vP −
NS
−
D2
Sw4 Sw2
(a)
Sw1, Sw2
Closed
DT T
Sw3, Sw4
T T
+ DT
2 2
(b)
vP
Vs
−Vs
(c)
vx
NS
Vs
NP
DT T T T
+ DT
2 2
(d )
Figure 7-9 (a) Full-bridge converter; (b) Switching sequence; (c) Voltage
on the transformer primary; (d) Voltage vx.
292
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 293
+
Vs
C1 Sw1
2
− D1 Lx
NP +
+
+
NS vx C R Vo
+ −
Vs
− vP −
NS
−
+ D2
Vs
C2
2 Sw2
−
(a)
Sw1
Closed
DT T
Sw2
T T + DT
2 2
(b)
vP
Vs
2
Vs
−
2
(c)
vx
Vs NS
2 NP
DT T T T
+ DT
2 2
(d)
Figure 7-10 (a) Half-bridge converter; (b) Switching sequence; (c) Voltage
on the transformer primary; (d) Voltage vx.
293
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 294
capacitors. Switches Sw1 and Sw2 close with the sequence shown, producing
an alternating voltage pulse vP on the transformer primary. The rectified sec-
ondary voltage vx has the waveform shown in Fig. 7-10d. Voltage vx is the same
form as for the push-pull and the full-bridge converters, but the amplitude is
one-half the value. The relationship between the input and output voltages for
the half-bridge converter is
NS
Vo Vs a bD (7-51)
NP
where D is the duty ratio of each switch. The voltage across an open switch for
the half-bridge converter is Vs.
7.8 CURRENT-FED CONVERTERS

The converters described thus far in this chapter are called voltage-fed con-
verters. Another method of controlling output is to establish a constant source
current and use the switches to direct the current. Current control has advan-
tages over voltage control for some converters. A circuit that operates by
switching current rather than voltage is called a current-fed converter.
Figure 7-11 shows a circuit that is a modification of the push-pull converter.
The inductor Lx has been moved from the output side of the transformer to the
input side. A large inductor in this position establishes a nearly constant
source current. Switch Sw1 directs the current through winding P1, and switch
Sw2 directs the current through winding P2. With both switches closed, the
current divides evenly between the windings. At least one switch must be
closed to provide a current path.
The switching sequence and waveforms are shown in Fig. 7-11. The follow-
ing analysis assumes that Lx is large and the current in it is a constant ILx. The
transformer is assumed to be ideal.
Sw1 Closed and Sw2 Open The inductor current ILx flows through primary
winding P1 and through D1 on the secondary when switch 1 is closed and switch 2
is open. D1 is on, D2 is off, and the following equations apply:
NP
i D1 ILx a b
NS
NP
vP1 Vo a b
NS
(7-52)
NP
vLx Vs vP1 Vs Vo a b
NS
NP
vSw2 vP1 vP2 2Vo a b
NS
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 295
D1 ix
NP : NS
+
+
iD1
vP P2 C R Vo
2
Lx iLx −
N1 −
+ vLx − +
vP P1
1
− iD2
+
Vs
−
D2
+ +
vSw1 vSw2
− −
(a)
S1
Closed
DT T
S2
(b)
iD1
iD2
ix
vLx
(1 − D)T (1 − D)T
(c)
Figure 7-11 (a) A current-fed converter; (b) Switching sequence; (c) Current and
voltage waveforms. 295
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 296
Sw1 Open and Sw2 Closed With switch 1 open and switch 2 closed, ILx flows
through primary winding P2 and through D2 on the secondary. D1 is off and D2 is
on, and the following equations apply:
NP
i D2 ILx a b
NS
NP
vP2 Vo a b
NS
(7-53)
NP
vLx Vs Vo a b
NS
NP
vSw1 vP1 vP2 2Vo a b
NS
Both Sw1 and Sw2 Closed With both switches closed, ILx divides evenly be-
tween the two primary windings, and both D1 and D2 are off. The voltage on each
primary winding is zero:
vP1 vP2 0
Inductor Lx then has the source voltage across it:
vLx Vs (7-54)
The average voltage across Lx must be zero for steady-state operation. During
one switching period, vLx Vs Vo(NP/NS) for two intervals of (1 D)T when
only one switch is closed, and vLx Vs for the remaining time, which is
T 2(1 D)T (2D 1)T. The average inductor voltage is thus expressed as
NP
VLx Vs(2D 1)T c Vs Vo a b d 2(1 D)T 0 (7-55)
NS
Solving for Vo,
Vs N
Vo a Sb (7-56)
2(1 D) NP
where D is the duty ratio of each switch. This result is similar to that of the boost
converter. Note that the duty ratio of each switch must be greater than 0.5 to pre-
vent an open circuit in the path of the inductor current.
EXAMPLE 7-7
Current-Fed Converter
The current-fed converter of Fig. 7-11 has an input inductor Lx that is large enough to
assume that the source current is essentially constant. The source voltage is 30 V, and the
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 297
7.9 Multiple Outputs 297
load resistor is 6 . The duty ratio of each switch is 0.7, and the transformer has a turns
ratio of NP /NS 2. Determine (a) the output voltage, (b) the current in Lx, and (c) the
maximum voltage across each switch.
■ Solution
(a) The output voltage is determined by using Eq. (7-56).
Vs 30 1
a Sb
N
Vo a b 25 V
2(1 D) NP 2(1 0.7) 2
(b) To determine ILx, recognize that the power delivered to the load must be the same as
that supplied by the source in the ideal case:
Ps Po
V 2o
ILxVs
R
Solving for ILx,

V 2o 252
ILx 3.47 A
Vs R 30(6)
(c) The maximum voltage across each switch is determined from Eqs. (7-52) and
(7-53).
Vsw, max 2Vo a

NP
b 2(25)(2) 100 V
NS
7.9 MULTIPLE OUTPUTS

The dc power supply circuits discussed thus far in this chapter have only one
output voltage. With additional transformer windings, multiple outputs
are possible. Flyback and forward converters with two outputs are shown in
Fig. 7-12.
Multiple outputs are useful when different output voltages are necessary.
The duty ratio of the switch and the turns ratio of the primary to the specific
secondary winding determine the output/input voltage ratio. An example is a
single converter with three windings on the output producing voltages of 12,
5, and 5 V with respect to a common ground on the output side. Multiple
outputs are possible with all the dc power supply topologies discussed in this
chapter. Note, however, that only one of the outputs can be regulated with a
feedback control loop. Other outputs will follow according to the duty ratio
and the load.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 298
Vo1
−
Lm
+
+
Vs −
Vo2
(a)
Vo1
Vo2
+
Vs −
−
(b)
Figure 7-12 (a) Flyback and (b) forward converters with two outputs.
7.10 CONVERTER SELECTION

In theory, any power supply circuit can be designed for any application, depend-
ing on how much the designer is willing to spend for components and control
circuitry. In practice, some circuits are much more suited to particular applica-
tions than others.
The flyback converter, having a low parts count, is a simple circuit to implement
and is very popular for low-power applications. The main disadvantages are that the
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 299
7.11 Power Factor Correction 299
transformer core must be made large as power requirements increase, and the voltage
stress across the switch is high (2Vs). Typical applications can go up to about 150 W,
but the flyback converter is used most often for an output power of 10 W or less.
The forward converter is a popular circuit for low and medium power levels,
up to about 500 W. It has one transistor as does the flyback, but it requires a
smaller transformer core. Disadvantages are high voltage stress for the transistor
and the extra cost of the filter inductor. The double-ended forward converter can
be used to reduce the switch voltage stress, but the drive circuit for one of the
transistors must be floating with respect to ground.
The push-pull converter is used for medium to high power requirements,
typically up to 1000 W. Advantages include transistor drive circuits that have a
common point and a relatively small transformer core because it is excited in both
directions. Disadvantages include a high voltage stress for the transistors and
potential core saturation problems caused by a dc imbalance in nonideal circuits.
The half-bridge converter is also used for medium power requirements, up to
about 500 W, and has some of the same advantages as the push-pull. The voltage
stress on the switches is limited to Vs.
The full-bridge converter is often the circuit of choice for high-power appli-
cations, up to about 2000 W. The voltage stress on the transistors is limited to Vs.
Extra transistors and floating drive circuits are disadvantages.
A method of reducing switching losses is to use a resonant converter topol-
ogy. Resonant converters switch at voltage or current zeros, thus reducing the
switch power loss, enabling high switching frequencies and reduced component
sizes. Resonant converters are discussed in Chap. 9.
7.11 POWER FACTOR CORRECTION

Power supplies often have an ac source as the input, and the first stage is a full-
wave rectifier that converts the ac input to a dc voltage. Figure 7-13, as discussed
in Chap. 4, is one such arrangement. The diodes conduct for only a small amount
of time during each cycle, resulting in currents that are highly nonsinusoidal. The
result is a large total harmonic distortion (THD) of current coming from the ac
is
is
+
vs vo
(a)
Figure 7-13 (a) Fullwave rectifier and

(b) voltage and current waveforms. The
source current is highly nonsinusoidal because
the diodes conduct for a short time interval.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 300
vo
vs
is
is
(b)
iL
is
+
vs Vo
−
(a)
iL
(b)
is
vs . k
(c)
Figure 7-14 (a) A rectifier circuit used to produce a

high power factor and low THD; (b) Current in the
inductor for continuous-current mode (CCM)
operation; (c) Current from the ac source.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 301
7.12 PSpice Simulation of DC Power Supplies 301
iL
v s. k
Figure 7-15 Discontinuous-current mode

(DCM) power factor correction.
source. A large THD corresponds to a low power factor (see Chap. 2). The resis-
tor represents any load on the output, which may be a dc-dc converter.
A way to improve the power factor (and reduce the THD) is with a power
factor correction circuit, as shown in Fig. 7-14a. A boost converter is used to
make the current in the inductor approximate a sinusoid. When the switch is
closed, the inductor current increases. When the switch is open, the inductor cur-
rent decreases. By using appropriate switching intervals, the inductor current can
be made to follow the sinusoidal shape of the full-wave rectified input voltage.
The voltage on the output of the diode bridge is a full-wave rectified sinusoid.
The current in the inductor is of the general form as shown in Fig. 7-14b, and the
resulting current from the ac source is shown in Fig. 7-14c. This current is pre-
dominantly at the same frequency and phase angle as the voltage, making the
power factor quite high and the THD quite low. This type of switching scheme is
called continuous-current mode (CCM) power factor correction (PFC). In an
actual implementation, the switching frequency would be much greater than is
shown in the figure.
Another type of switching scheme produces a current like that shown
in Fig. 7-15. In this scheme, the inductor current varies between zero and a
peak that follows a sinusoidal shape. This type of switching scheme is called
discontinuous-current mode (DCM) power factor correction. DCM is used with
low-power circuits, while CCM is more suitable for high-power applications.
In both the CCM and DCM schemes, the output of the power factor correc-
tion (PFC) stage is a large dc voltage, usually on the order of 400 V. The output
of the PFC stage will go to a dc-dc converter. For example, a forward converter
can be used to step down the 400-V output of the PFC stage to 5 V.
Other converter topologies in addition to the boost converter can be used for
power factor correction. The SEPIC and Ćuk converters are well suited for this
purpose.
7.12 PSPICE SIMULATION OF DC POWER SUPPLIES

PSpice simulations of the magnetically coupled dc-dc converters discussed in
this chapter are similar to those of the dc-dc converters of Chap. 6. For initial
investigation, the switches can be implemented with voltage-controlled switches
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 302
FLYBACK CONVERTER
N1 N2 Output
PARAMETERS:
Duty = 0.385
Freq = 40k + Vs
N1overN2 = 3 24
Lm = 500u − C R
control 200u 5
+ +
V1 = 0
+ − − TX1
V2 = 5
TD = 0 − V2
TR = 1n 0 Ron=0.01
TF = 1n .model Dbreak D n=0.01
PW = {Duty/Freq}
PER = {1/Freq}
(a) (b)
Figure 7-16 (a) The flyback converter circuit for simulation; (b) Probe output showing
the transient and steady-state output voltage.
rather than with transistors, simplifying the switching and allowing examination
of the overall circuit behavior.
Transformers can be modeled in PSpice as two or more inductances with
ideal coupling. Since inductance is proportional to the square of the turns in a
winding, the transformer turns ratio is
N1 L1
(7-57)
N2 A L 2
For the flyback converter, let L1 Lm and determine L2 from Eq. (7-57). For
other converters where Lm is not a design parameter, let L1 be any large value
and determine L2 accordingly. For two-winding transformers, the part XFRM_
LINEAR can serve as a template.
Figures 7-16 and 7-17 show circuits for the flyback and forward converter
topologies. The flyback simulation uses the XFRM_LINEAR part, and the forward
simulation uses mutually coupled inductors. The switches and diodes are ideal-
ized by setting Ron 0.01 for the switches and n 0.01 for the diodes. Just as
with the dc-dc converters in Chap. 6, transient voltages and currents precede the
steady-state waveforms that were presented in the earlier discussion of the con-
verters in this chapter.
7.13 POWER SUPPLY CONTROL

In ideal switching dc-dc converters, the output voltage is a function of the input
voltage and duty ratio. In real circuits with nonideal components, the output is
also a function of the load current because of resistances in the components. A
power supply output is regulated by modulating the duty ratio to compensate for
variations in the input or load. A feedback control system for power supply con-
trol compares output voltage to a reference and converts the error to a duty ratio.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 303
FORWARD CONVERTER PARAMETERS:

Freq = 200k
Duty = 0.3
1 N1overN2 = 2
L3 N1overN3 = 1
{Lt} Lm = 1m
secondary vx Lx Output
2 1 2
primary
D1 80u
1 1
+ L2 D2 C1 R1
Vs {Lm} L1 {Ls} 20u 10
− 2
100
2
D3
K
S1
control + + Switch K_Linear
− − COUPLING = .999
+
V1 = 0 Vcontrol
V2 = 5 −
TD = 0
TR = 1n
TF = 1n
PW = {Duty/Freq}
PER = {1/Freq}
Figure 7-17 The forward converter circuit for simulation.
The buck converter operating in the continuous-current mode is used to

illustrate the basics of power supply control. Figure 7-18a shows the converter
and feedback loop consisting of
1. The switch, including the diode and drive circuit
2. The output filter
3. A compensated error amplifier
4. A pulse-width modulating circuit that converts the output of the compensated
error amplifier to a duty ratio to drive the switch
The regulated converter is represented by the closed-loop system of Fig. 7-18b.
Control Loop Stability

Performance and stability of the control loop for regulating the output voltage for
a converter can be determined from the open-loop characteristics:
1. The gain at low frequencies should be large so the steady-state error
between the output and the reference signal is small.
2. The gain at the converter’s switching frequency should be small.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 304
Switch Filter and Load

Vo
+ Driver
VS
−
+
+
PWM
Vref −
−
(a)
Vs
Compensated vc d Vs d vo
Vref Filter and
+− Error PWM Switch
Load
Amplifier
(b)
Figure 7-18 (a) Buck converter with feedback; (b) Control representation.
3. The open-loop phase shift at the crossover frequency (the frequency where
the open-loop gain is unity) must lag by less than 180. If the phase lag
were 180(or 180), negative feedback provides a shift of another 180,
resulting in a total of 360 (or zero). A gain of magnitude 1 and phase of
360 around the loop make the loop unstable. The open-loop phase shift
less than 180 at crossover is called the phase margin. A phase margin of
at least 45 is a commonly used criterion for stability. Figure 7-19
illustrates the concept of phase margin. Note that phase margin is the angle
between the phase shift and zero when the 180 phase angle of the inverting
operational amplifier is included, which is convenient for use with PSpice
analysis.
The transfer function of each block of the system in Fig. 7-18b must be devel-
oped to describe the control properties.
Small-Signal Analysis
Control loop analysis is based on the dynamic behavior of voltages, currents, and
switching, unlike the steady-state analysis where the averaged circuit quantities
are constants. Dynamic behavior can be described in terms of small-signal
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 305
Gain Phase Phase

Phase Margin 0°
Gain
0 dB −180°
Gain Phase Phase

Phase
Margin −180°
Gain
0 dB 0°
Figure 7-19 Phase margin. (a) In classical control theory,

the phase margin is the angle difference between 180
and the open-loop phase angle at the crossover frequency,
where the open-loop gain magnitude is 0 dB; (b) The phase
margin is between zero and the phase angle when the 180
phase angle of the inverting operational amplifier is
included, which is convenient for PSpice simulation.
variations around a steady-state operating point. Output voltage, duty ratio,

inductor current, source voltage, and other quantities are represented as
v V ~v
o o o
~
dDd
~ (7-58)
i L IL i L
v V ~v
s s s
In these equations, the steady-state or dc term is represented by the uppercase let-

ters, the ~ (tilde) quantity represents the ac term or small-signal perturbation, and
the sum is the total quantity, represented by the lowercase letters.
Switch Transfer Function

For control purposes, the average values of voltages and currents are of greater
interest than the instantaneous values that occur during the switching period.
Equivalent representations of the switch in a buck converter are shown in Fig. 7-20.
The relationship between input and output for the switch for a time-varying duty
ratio is represented by the ideal transformation of 1 : d shown in Fig. 7-20b. Here,
d represents a time-varying duty ratio consisting of a dc (constant) component D
~
plus a small-signal component d.
~
dDd (7-59)
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 306
Vs ~
iLd iL d
D
1:d − + 1:D
+ + + + +
Vs vx Vs ~
Vs d ILd
− − − − −
(a) (b) (c)
Figure 7-20 Switch models. (a) Switch and diode; (b) Model representing the transformation of
average voltage and average current; (c) Model that separates steady-state and small-signal
components.
An alternative representation of the switch shown in Fig. 7-20c separates the

steady-state and small-signal components. The transformer secondary voltage vx
is related to the source voltage by
vx vsd (Vs ~v s)(D ~

d ) Vs D ~v s D Vs ~
d ~v s ~d (7-60)
Neglecting the product of the small-signal terms,
vx ⬟ VsD ~v sD Vs ~d vsD Vs~d (7-61)
Similarly, the current on the source side of the transformer is related to the
secondary current by
~
i s i Ld (IL i L )(D ~
d ) ⬟ i LD IL~
d (7-62)
The circuit of Fig. 7-20c, with the transformer ratio fixed at D and the small-
signal terms included with the dependent sources, satisfies the voltage and cur-
rent requirements of the switch expressed in Eqs. (7-61) and (7-62).
Filter Transfer Function

The input to the buck converter filter is the switch output, which is vx vs d on
an averaged circuit basis in the continuous current mode. The RLC filter of the
buck converter has a transfer function developed from a straightforward applica-
tion of circuit analysis in the s domain. From Fig. 7-21a, the transfer function of
the filter with the load resistor is
vo(s) v (s) 1
o 2 (7-63)
vx(s) Vs d(s) LC3s s(1>RC) 1>LC4
vo(s) Vs
or 2 (7-64)
d(s) LC3s s(1>RC) 1>LC4
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 307
sL sL
+ + + +
1
sC
1
vx (s) sC R vo(s) vx (s) R vo (s)
rC
− − − −
(a) (b)
Figure 7-21 Circuits for deriving the filter transfer

function (a) with an ideal capacitor and (b) with the ESR
of the capacitor.
The above transfer function is based on ideal filter components. An equivalent

series resistance (ESR) of rC for a nonideal capacitor in Fig. 7-21b results in a fil-
ter transfer function of
vo(s) V 1 srCR
sc d (7-65)
d(s) LC s 2(1 rC>R) s(1>RC rC>L) 1>LC
Since rC R in practical circuits, the transfer function becomes approximately
vo(s) Vs 1 srCR
c 2 d
LC s s(1>RC rC>L) 1>LC
L (7-66)
d(s)
The numerator of Eq. (7-66) shows that the ESR of the capacitor produces a
zero in the transfer function, which may be important in determining system
stability.
A general technique for establishing the switch and filter transfer function is
state-space averaging. A development of this method is shown in App. B.
Pulse-Width Modulation Transfer Function

The pulse-width modulation (PWM) circuit converts the output from the com-
pensated error amplifier to a duty ratio. The error amplifier output voltage vc is
compared to a sawtooth waveform with amplitude Vp, as shown in Fig. 7-22. The
output of the PWM circuit is high while vc is larger than the sawtooth and is zero
when vc is less than the sawtooth. If the output voltage falls below the reference,
the error between the converter output and the reference signal increases, caus-
ing vc to increase and the duty ratio to increase. Conversely, a rise in output volt-
age reduces the duty ratio. A transfer function for the PWM process is derived
from the linear relation
vc
d (7-67)
Vp
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 308
vp
vc
Figure 7-22 The PWM process. The output is high when

vc from the compensated error amplifier is higher than the
sawtooth waveform.
The transfer function of the PWM circuit is therefore
d(s) 1
(7-68)
vc(s) Vp
Type 2 Error Amplifier with Compensation

The error amplifier compares the converter output voltage with a reference volt-
age to produce an error signal that is used to adjust the duty ratio of the switch.
Compensation associated with the amplifier determines control loop perfor-
mance and provides for a stable control system.
The transfer function of the compensated error amplifier should give a total
loop characteristic consistent with the stability criteria described previously.
Namely, the amplifier should have a high gain at low frequencies, a low gain at
high frequencies, and an appropriate phase shift at the crossover frequency.
An amplifier that suits this purpose for many applications is shown in
Fig. 7-23a. This is commonly referer to as a type 2 compensated error amplifier.
(A type 1 amplifier is a simple integrator with one resistor on the input and one
capacitor as feedback.). The amplifier is analyzed for the small-signal transfer
function, so the dc reference voltage Vref has no effect on the small-signal portion
of the analysis. Furthermore, a resistor can be placed between the inverting input
terminal and ground to act as a voltage divider to adjust the converter output
voltage, and that resistor will have no effect on the small-signal analysis because
the small-signal voltage at the noninverting terminal, and therefore at the invert-
ing terminal, is zero.
The small-signal transfer function (with dc terms set to zero) of the amplifier
is expressed in terms of input and feedback impedances Zi and Zf, where
1 1 (R 1>sC1)(1>sC2)
Zf a R2 b || 2
sC1 sC2 R2 1>sC1 1>sC2 (7-69)
Zi R1
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 309
C2
Vc / Vo
R2 C1
R2
R1 R1
vo −
vc
+ ωz ωp
Vref
(a) (b)
Figure 7-23 (a) Type 2 compensated error amplifier; (b) Frequency response.
The gain function G(s) is expressed as the ratio of the compensated error ampli-
fier small-signal output ~v c to the input, which is the converter output ~v o.
~v (s) Z (R2 1>sC1)(1>sC2)
G(s) ~c f (7-70)
v o(s) Zi R1(R2 1>sC1 1>sC2)
Rearranging terms and assuming C2 C1,
~v (s) s 1>R2C2 s 1>R2C1

G(s) ~c L (7-71)
v o(s) R1C2s3s (C1 C2 )>R2C1C24 R1C2s(s 1>R2C2)
The above transfer function has a pole at the origin and a zero and pole at
1
z (7-72)
R2C1
C1 C2 1
p L (7-73)
R2C1C2 R2C2
The frequency response of this amplifier has the form shown in Fig. 7-23b.
The values of R1, R2, C1, and C2 are chosen to make the overall control system
have the desired attributes.
The combined frequency response of the transfer functions of the PWM cir-
cuit, the switch, and the output filter of a converter is shown in Fig. 7-24. The
ESR of the filter capacitor puts a zero at 1/rcC. A simulation program such
as PSpice is useful to determine the frequency response. Otherwise, the transfer
function may be evaluated with s j.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 310
Compensated Error Amplifier

Ov
era
ll G
ain
0 dB
Filter
Filter & PWM
Figure 7-24 The control loop transfer function

frequency response.
EXAMPLE 7-8
A Type 2 Amplifier Control Loop for a Buck Converter

The source voltage for a buck converter is Vs 6 V, and the output voltage is to be regu-
lated at 3.3 V. The load resistance is 2 , L 100 H with negligible internal resistance,
and C 75 F with an ESR of 0.4 . The PWM circuit has a sawtooth voltage with peak
value Vp 1.5 V. A type 2 compensated error amplifier has R1 1 k , R2 2.54 k ,
C1 48.2 nF, and C2 1.66 nF. The switching frequency is 50 kHz. Use PSpice to deter-
mine the crossover frequency and the phase margin.
C2
1.66n
BUCK CONVERTER OPEN LOOP C1
TYPE 2 R2
V(%IN+, %IN-)/(Vp) 2.54K 48.2n

1L L R1
1 2 FILTER PWM
IN + OUT+ 0p Amp
0.1 100u IN - OUT- 1K Loop
C Rload +
1Np -
Vs 75u GAIN = 2E5
+ 2
ACMAG = 6V C
- 0.4
PARAMETERS:
Vp = 1.5
(a)
Figure 7-25 (a) PSpice circuit for simulating the open-loop response of a buck converter;
(b) Probe output for Example 7-8 showing a crossover frequency of 6.83 kHz and a phase margin
of approximately 45.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 311
200
100
Phase Angle
(6.8303K, 45.285)
Gain, dB
Phase Margin
0
(6.8303K, 37.039m)
-100
100 Hz 1.0 KHz 10 KHz 100 KHz
vdb (loop) vp (loop) 0 Frequency
(b)
Figure 7-25 (continued).
■ Solution
A PSpice circuit for the filter, compensated error amplifier, and PWM converter is shown
in Fig. 7-25a. The input voltage source is the ac source Vac, the PWM function of 1/Vp is
implemented with the dependent source EVALUE, and the ideal op-amp is implemented
with a high-gain voltage-controlled voltage source.
The Probe output shown in Fig. 7-25b reveals the crossover frequency to be 6.83 kHz.
The phase margin is the angle greater than zero (or 360) because the operational ampli-
fier contains the inversion (180) for negative feedback (Fig. 7-19a). The Probe output
shows the phase margin to be slightly larger than 45. The gain is low, 23.8 dB, at the
50-kHz switching frequency. Therefore, this circuit meets the criteria for a stable control
system.
Design of a Type 2 Compensated Error Amplifier

The midfrequency gain and the location of the pole and zero of the transfer func-
tion of the compensated error amplifier must be selected to provide the desired
total open-loop crossover frequency and phase margin required for stability.
The transfer function of the compensated error amplifier in Eq. (7-71) can be
expressed for s j as
~v ( j) j z
c
G( j) ~ (7-74)
v ( j)
o R C j( j )
1 2 p
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 312
For the middle frequencies, z p, resulting in

~v ( j) j 1 R
G( j) ~c L 2 (7-75)
v o( j) R1C2 jp R1C2(1>R2C2) R1
The phase angle comp of the compensated error amplifier transfer function of
Eq. (7-74) is

comp 180° tan1 a b 90° tan1 a b
z p

270° tan1 a b tan1 a b (7-76)
z p
The 180 is from the negative sign, and the 90 is from the pole at the origin.
Note that in this development the inverting amplifier phase shift of 180 is
included in Eq. (7-76). In some developments of this method, the inverting
amplifier phase shift is omitted at this point and then included later.
The following is a design procedure for the type 2 compensated error amplifier.
1. Choose the desired crossover frequency of the total open-loop transfer
function. This is usually around an order of magnitude less than the
converter switching frequency. Some designers go as high as 25 percent of
the switching frequency.
2. Determine the transfer function and frequency response of all elements in
the control circuit except for the compensated error amplifier.
3. Determine the midfrequency gain of the compensated error amplifier
required to achieve the overall desired crossover frequency. This establishes
the R2/R1 ratio as in Eq. (7-75).
4. Choose the desired phase margin needed to ensure stability, typically greater
than 45. Having established R1 and R2 for the midfrequency gain, the pole
and zero, p and z, are determined by C1 and C2. The phase angle comp of
the compensated error amplifier at the crossover frequency co is
co
comp 270° tan1 a b tan1 a co b (7-77)
z p
A procedure for selecting the pole and zero frequencies is the K factor
method [see Venable (1983) and Basso (2008) in the Bibliography]. Using the K
factor method, the value of K is determined as follows:
Let the zero and pole of the transfer function be at

z co (7-78)
K
and
p Kco (7-79)
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 313
Then
co p
K (7-80)
z co
The phase angle of the compensated error amplifier at crossover in Eq. (7-77) is
then
1
comp 270° tan1K tan1 a b (7-81)
K
Using the trigonometric identity
1
tan1(x) tan1 a b 90° (7-82)
x
gives
1
tan1 a b 90° tan1(K) (7-83)
K
Equation (7-81) becomes
1
comp 270° tan1(K) tan1 a b 2 tan1(K) 360° 2 tan1(K) (7-84)
K
Solving for K,
comp
K tan a b (7-85)
2
The angle comp is the desired phase angle of the compensated error amplifier at
the crossover frequency. From Eq. (7-84), the phase angle of the compensated
error amplifier can range from 0 to 180 for 0 K q.
The required phase angle of the compensated error amplifier to obtain the
desired phase margin is determined, establishing the value of K. If the desired
crossover frequency co is known, then z and p are obtained from Eqs. (7-78)
and (7-79). Then C1 and C2 are determined from Eqs. (7-71) and (7-72).
1
z co
R2C1 K
(7-86)
K K
C1
co R2 2 fco R2
1
p Kco
R2C2
(7-87)
1 1
C2
Kco R2 K2 fco R2
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 314
EXAMPLE 7-9

For a buck converter shown in Fig. 7-26a,
Vs 10 V with an output of 5 V
f 100 kHz
L 100 H with a series resistance of 0.1
R5
Vp 3 V in PWM circuit
Design a type 2 compensated error amplifier that results in a stable control system.
■ Solution
1. The crossover frequency of the total open-loop transfer function (the frequency
where the gain is 1, or 0 dB) should be well below the switching frequency. Let
fco 10 kHz.
2. A PSpice simulation of the frequency response of the filter with load resistor
(Fig. 7-26b) shows that the converter (Vs and the filter) gain at 10 kHz is 2.24 dB
and the phase angle is 101. The PWM converter has a gain of 1/Vp 1/3
9.5 dB. The combined gain of the filter and PWM converter is then 2.24 dB
9.54 dB 11.78 dB.
0.1 100uH
+ 100uF
10V
−
5
0.5
(a)
1 2
0.1 100u
100u
+
10
−
0.5 5
(b)
Figure 7-26 (a) Buck converter circuit; (b) The ac circuit

for determining the frequency response of the converter.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 315
3. The compensated error amplifier should therefore have a gain of +11.78 dB at 10 kHz
to make the loop gain 0 dB. Converting the gain in decibels to a ratio of vo/vi,
~v
11.78 dB 20log a ~ b
c
v o
~v
c 11.78/20
~v 10 3.88
o
Using Eq. (7-75), the magnitude of the midfrequency gain is

R2
3.88
R1
Letting R1 1 k , R2 is then 3.88 k .
4. The phase angle of the compensated error amplifier at crossover must be adequate
to give a phase margin of at least 45. The required phase angle of the amplifier is
comp phase margin converter 45° ( 101°) 146°
A K factor of 3.27 is obtained from Eq. (7-85).

comp 146°
K tan a b tan a b tan(73°) 3.27
2 2
Using Eq. (7-86) to get C1,
K 3.27
C1 13.4 nF
2 fcoR2 2(10,000)(3880)
Using Eq. (7-87) to get C2,
1 1
C2 1.25 nF
K2 fco R2 3.27(2)(10,000)(3880)
A PSpice simulation of the control loop gives a crossover frequency of 9.41 kHz
and a phase margin of 46, verifying the design.
PSpice Simulation of Feedback Control

Simulation is a valuable tool in the design and verification of a closed-loop con-
trol system for dc power supplies. Figure 7.27a shows a PSpice implementation
using idealized switches and ETABLE sources for the op-amp and for the com-
parator in the PWM function. The input is 6 V, and the output is to be regulated
at 3.3 V. The phase margin of this circuit is 45 when the load is 2 , and slightly
greater than 45 when the load changes to 2||4 . The switching frequency is
100 kHz. A step change in load occurs at t 1.5 ms. If the circuit were unregu-
lated, the output voltage would change as the load current changed because of
the inductor resistance. The control circuit adjusts the duty ratio to compensate
for changes in operating conditions.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 316
C2
1.5n
R2 C1
BUCK CONVERTER WITH TYPE
2 COMPENSATION 13.4n
3.88k
input rL L1 output R1
vx 1 2
0.1 100u 0P AMP
+ S1 2 1k
+ 100u Co IN+ OUT+ error
+ Vs Sbreak IN- OUT-
Rload TCLOSE = 1.5m
6V D1 ETABLE
- 0 Ideal Dbreak 2 V(%IN+, %IN-)
Switches 0.5 rC 1
+
2 Rload2 3.3V Vref
-
0 Step change in load at t = 1.5ms
PWN Comparator
Control
OUT+ IN+
Ecomp OUT- IN- PARAMETERS:
+ Freq = 100k
Vramp
ETABLE - Vp = 1.5
V(%IN+, %IN-) TD = 0
TF = 1n
0 PW = 1n
PER = {1/(Freq)}
V1 = 0
TR = (1/Freq-2n)
V2 = {Vp}
(a)
5.0
Output Voltage
2.5
Inductor Current
Load Step Change
0
1.0 ms 1.5 ms 2.0 ms 2.5 ms 3.0 ms
V (OUTPUT) I(L1) Time
(b)
Figure 7-27 (a) PSpice circuit for a regulated buck converter; (b) Output voltage and inductor current for a
step change in load.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 317
Figure 7-27b shows the output voltage and inductor current, verifying that
the control circuit is stable.
Type 3 Error Amplifier with Compensation

The type 2 compensation circuit described previously is sometimes not capable
of providing sufficient phase angle difference to meet the stability criterion of a
45 phase margin. Another compensation circuit, known as the type 3 amplifier,
is shown in Fig. 7-28a. The type 3 amplifier provides an additional phase angle
boost compared to the type 2 circuit and is used when an adequate phase margin
is not achievable using the type 2 amplifier.
The small-signal transfer function is expressed in terms of input and feed-
back impedances Zi and Zf,
~v (s) Zf (R 1>sC1) ||1>sC2
G(s) ~c 2 (7-88)
v o(s) Zi R1 || (R3 1>sC3)
C2
R3 C3 R2 C1
R1
vo −
vC
+
+
Vref
−
(a)
vc
vo
ω
ωp = 0 ωz1 ωz2 ωp1 ωp2
1
(b)
Figure 7-28 (a) Type 3 compensated error amplifier;

(b) Bode magnitude plot.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 318
resulting in
R1 R3 As R2C1B As (R1 R3)C3B
1 1
R1R3C3 s As C1 C2B As R 1C B
G(s) (7-89)
RCC 2 1 2 3 3
The reference voltage Vref is purely dc and has no effect on the small-signal trans-
fer function. Assuming C2 C1 and R3 R1,
1 (s 1>R2C1)(s 1>R1C3)
G(s) L (7-90)
R3C2 s(s 1>R2C2)(s 1>R3C3)
An inspection of the transfer function of Eq. (7-90) shows that there are two
zeros and three poles, including the pole at the origin. A particular placement of the
poles and zeros produces the Bode plot of the transfer function shown in Fig. 7-28b.
1 ( j z1)( j z2)
G( j) (7-91)
R3C2 j( j p2)( j p3)
The zeros and poles of the transfer function are
1
z1
R2C2
1 1
z2 L
(R1 R3)C3 R1C3
p1 0 (7-92)
C1 C2 1
p2 L
R2C1C2 R2C2
1
p3
R3C3
The phase angle of the compensated error amplifier is

comp 180° tan1 a b tan1 a b 90° tan1 a b tan1 a b
z1 z2 p2 p3

270° tan1 a b tan1 a b tan1 a b tan1 a b (7-93)
z1 z2 p2 p3
The 180 is from the negative sign, and the 90 is from the pole at the origin.

The K factor method can be used for the type 3 amplifier in a similar way as it
was used in the type 2 circuit. Using the K factor method, the zeros are placed at
the same frequency to form a double zero, and the second and third poles are
placed at the same frequency to form a double pole:
z z1 z2
(7-94)
p p2 p3
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 319
The first pole remains at the origin.

The double zeros and poles are placed at frequencies

z co
1K
(7-95)
p co 1K
The amplifier transfer function from Eq. (7-91) can then be written as
1 ( j z)2
G( j) (7-96)
R3C2 j( j p)2
At the crossover frequency co, the gain is
1 ( jco z)2
G(jco) (7-97)
R3C2 jco( jco p)2
The phase angle of the amplifier at the crossover frequency is then
co
comp 270° 2 tan1 a b 2 tan1 a co b (7-98)
z p
Using Eq. (7-95) for z and p,
co co
comp 270° 2tan1 a b 2tan1 a b (7-99)
co> 1K co 1K
resulting in
1
comp 270° 2 tan1 2K 2 tan1 a b
1K
(7-100)
1
270° 2c tan 1
2K tan 1
a bd
1K
By using the identity
1
tan1(x) tan1 a b 90° (7-101)
x
making
b 90° tan1 A 1K B
1
tan1 a (7-102)
1K
Eq. (7-100) becomes
comp 270° 23tan1 1K ( 90° tan1 1K)4

(7-103)
comp 450° 4tan1 2K 90° 4 tan1 1K
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 320
Solving for K,
comp 90° 2
K tan a b (7-104)
4
From Eq. (7-103), the maximum angle of the compensated error amplifier is
270. Recall that the maximum phase angle of the type 2 amplifier is 180.
The phase angle of the compensated error amplifier is
comp phase margin converter (7-105)
The minimum phase margin is usually 45, and the phase angle of the converter
at the desired crossover frequency can be determined from a PSpice simulation.
At the crossover frequency co,
1 ( jco z)2
G( jco)
R3C2 jco( jco p)2
(7-106)
2
1 ( jco) 1 jco
L
R3C2 jco(p)2 R3C2 (p)2
Using Eqs. (7-95) and (7-92),
2K
co 2Kz (7-107)
R1C3
1 1 1
p Q 2p (7-108)
R2C2 R3C3 R2C2R3C3
Equation (7-106) becomes
1 jco 1 j 1K>R1C3 j 1K R2
G( jco) (7-109)
R3C2 (p)2 R3C2 1>R2C2R3C3 R1
In the design of a type 3 compensated error amplifier, first choose R1 and

then compute R2 from Eq. (7-109). Other component values can then be deter-
mined from
co 1 1
z (7-110)
1K R2C1 R1C3
1 1
and p co 1K (7-111)
R2C2 R3C3
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 321
The resulting equations are

ƒ G( jco) ƒ R1
R2
1K
1K 1K
C1
co R2 2fcoR2
1 1
C2 (7-112)
coR2 1K 2fcoR2 1K
1K 1K
C3
coR1 2fcoR1
1 1
R3
co 1KC3 2fco 1KC3
EXAMPLE 7-10

For the buck converter shown in Fig.7-29a,
Vs 10 V with an output of 5 V
f 100 kHz
L 100 H with a series resistance of 0.1
R5
Vp 3 V in PWM circuit
Design a type 3 compensated error amplifier that results in a stable control system.
Design for a crossover frequency of 10 kHz and a phase margin of 45. Note that all para-
meters are the same as in Example 7-8 except that the ESR of the capacitor is much
smaller.
■ Solution
A PSpice ac frequency sweep shows that the output voltage is 10.5 dB at 10 kHz and
the phase angle is 144. The PWM circuit produces an additional gain of 9.5 dB.
Therefore, the compensating error amplifier must have a gain of 10.5 + 9.5 20 dB at
10 kHz. A gain of 20 dB corresponds to a gain of 10.
The required phase angle of the amplifier is determined from Eq. (7-105),
comp phase margin converter 45° ( 144°) 189°
Solving for K in Eq. (7-104) yields.
189° 90° 2
K ctan a b d 3tan(69.75°)42 7.35
4
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 322
0.1 100uH
+ 100uF
10V 5
-
0.1
(a)
rL L1
1 2 FILTER
0.1 100u
V1 100u Co R1
+
10 5
-
0.1
rC
0 (b)
Figure 7-29 (a) Buck converter circuit; (b) The ac circuit

used to determine the frequency response.
Letting R1 1 k , the other component values are computed from Eq. (7-112).
ƒ G(jco) ƒ R1 10(1000)

R2 3.7 kÆ
1K 17.35
1K 17.35
C1 11.6 nF
2fco R2 2(10,000)(3700)
1 1
C2 1.58 nF
2fco R2 1K 2(10,000)(3700) 17.35
1K 17.35
C3 43.1 nF
2fco R1 2(10,000)(1000)
1 1
R3 136 Æ
2fco 1KC3 2(10,000)17.35(43.1)(10)9
A PSpice simulation of the converter, compensated error amplifier, and PWM circuit
gives a crossover frequency of 10 kHz with a phase margin of 49.
Note that attempting to use a type 2 compensated error amplifier for this circuit is
unsuccessful because the required phase angle at the crossover frequency is greater than
180. Comparing this converter with that of Example 7-8, the ESR of the capacitor here
is smaller. Low capacitor ESR values often necessitate use of the type 3 rather than the
type 2 circuit.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 323
7.15 The AC Line Filter 323
Table 7-1 Type 3 Compensating error amplifier zeros and poles and frequency placement
Zero or Pole Expression Placement
1
First zero z1 50% to 100% of LC
R2C2
1 1
Second zero z2 L At LC
(R1 R3)C3 R1C3
First pole p1 0 —
C1 C2 1
Second pole p2 L At the ESR zero 1/rCC
R2C1C2 R2C2
1
Third pole p3 At one-half the switching
R3C3 frequency, 2 fsw /2
Manual Placement of Poles and Zeros in the Type 3 Amplifier

As an alternative to the K factor method described previously, some designers
place the poles and zeros of the type 3 amplifier at specified frequencies. In plac-
ing the poles and zeros, a frequency of particular interest is the resonant fre-
quency of the LC filter in the converter. Neglecting any resistance in the inductor
and capacitor,
1 1
LC fLC (7-113)
1LC 2 1LC
The first zero is commonly placed at 50 to 100 percent of fLC, the second zero is
placed at fLC, the second pole is placed at the ESR zero in the filter transfer func-
tion (1/rCC), and the third pole is placed at one-half the switching frequency.
Table 7-1 indicates placement of the type 3 error amplifier poles and zeros.
7.14 PWM CONTROL CIRCUITS

The major elements of the feedback control of dc power supplies are available in
a single integrated circuit (IC). The National Semiconductor LM2743 is one
example of an integrated circuit for dc power supply control. The IC contains the
error amplifier op-amp, PWM circuit, and driver circuits for the MOSFETs in a
dc-dc converter using synchronous rectification. The block diagram of the IC is
shown in Fig. 7-30a, and a typical application is shown in Fig. 7-30b.
7.15 THE AC LINE FILTER

In many dc power supply applications, the power source is the ac power system. The
voltage and current from the ac system are often contaminated by high-frequency
electrical noise. An ac line filter suppresses conductive radio-frequency interfer-
ence (RFI) noise from entering or leaving the power supply.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 324
FREQ SD VDC PGND SGND PGND
CLOCK & UVLO

RAMP
SHUT DOWN BOOT
LOGIC
10
DELAY HG
PWGD SSDONE
SYNCHRONOUS
DRIVER LOGIC
OV UV
LG
0.71 V 0.134 V
10 μA
SS/TRACK 2V
PWM LOGIC
0.85 V PWM 40 μA
Solt Start
Comparator REF
Logic + − ISEN
90 μA
EA IUM
− +
VREF = 0.6 V
FE EAO
(a)
VCC = 3.3V VIN = 3.3 V

D1 CBOOT
RCC RPULL-UP Q1
CIN1,2
VCC HG
CCC SD BOOT RCS L1 VOUT = 1.2V@4A
PWGD ISEN
LM2743
FREQ LG
RFADJ +
SS/TRACK PGND RFB2 CO 1,2
CSS SGND PGND
EAO FB RC2 CC3
RFB1
CC1
CC2 RC1
(b)
Figure 7-30 (a) The National Semiconductor LM2743 block diagram; (b) An application in a buck converter circuit
(with permission from National Semiconductor Corporation1).
1
Copyright © 2003 National Semiconductor Corporation, 2900 Semiconductor Drive, Santa Clara, CA 95051. All rights reserved,
http://www.national.com.
324
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 325
7.16 The Complete DC Power Supply 325
Line
Y capacitors
X capacitor
Ground
Neutral Common-mode filter Differential-mode filter
Figure 7-31 A typical ac line filter.
A single-phase ac input to a power supply has a line (or phase) wire, a neu-
tral wire, and a ground wire. Common-mode noise consists of currents in the
line and neutral conductors that are in phase and return through the ground path.
Differential-mode noise consists of high-frequency currents that are 180 out of
phase in the line and neutral conductors, which means that current enters from
the line and returns in the neutral.
A typical ac line filter circuit is shown in Fig. 7-31. The first stage is a common-
mode filter, consisting of a transformer with adjacent polarity markings and a
capacitor connected from each line to ground. The capacitors in this stage are
referred to as the Y capacitors. The second stage of the filter, consisting of a
transformer with opposite polarity markings and a single capacitor connected
across the ac lines, removes differential-mode noise from the ac signal. The
capacitor in this stage is referred to as the X capacitor.
7.16 THE COMPLETE DC POWER SUPPLY

A complete dc power supply consists of an input ac line filter, a power factor cor-
rection stage, and a dc-dc converter, as illustrated in the block diagram of Fig. 7-32.
The power factor correction stage is discussed in Sec. 7.11, and the dc-dc con-
verter could be any of the converters discussed in this chapter or in Chap. 6.
Low-power applications such as cell phone chargers can be implemented
with a topology like that shown in Fig. 7-33. A full-wave rectifier with a capaci-
tor filter (Chap. 4) produces a dc voltage from the ac line voltage source, and a
flyback dc-dc converter reduces the dc voltage to the appropriate level for the
application. An optically coupled feedback loop preserves electrical isolation
between the source and the load, and a control circuit adjusts the duty ratio of the
switch for a regulated output. Integrated-circuit packages include the control
Rectifier with DC-DC Converter

AC Source AC Line Filter Power Factor (e.g., Forward) DC Output
Correction with Control
Figure 7-32 A complete power supply when the source is the ac power system.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 326
DC output
AC source +
− −
Optical isolation
Control
Figure 7-33 An off-line power supply for low-power applications.
function and the switching transistor. Some such integrated circuits can be pow-
ered directly from the high-voltage output of the rectifier, and others require
another winding on the flyback converter to produce the IC supply voltage. This
type of power supply is often called an off-line converter.
7.17 Bibliography
Raton, Fla., 2005.
C. Basso, Switch-Mode Power Supplies, McGraw-Hill, New York, 2008.
B. K. Bose, Power Electronics and Motor Drives: Advances and Trends,
Elsevier/Academic Press, Boston, 2006.
M. Day, “Optimizing Low-Power DC/DC Designs—External versus Internal
Compensation,” Texas Instruments, Incorporated, 2004.
R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 2d ed., Kluwer
Academic, 2001.
A. J. Forsyth and S. V. Mollov, “Modeling and Control of DC-DC converters,” Power
Engineering Journal, vol. 12, no. 5, 1998, pp. 229–236.
Y. M. Lai, Power Electronics Handbook, edited by M. H. Rashid, Academic Press,
Calif., San Diego, 2001, Chapter 20.
LM2743 Low Voltage N-Channel MOSFET Synchronous Buck Regulator Controller,
National Semiconductor, 2005.
D. Mattingly, “Designing Stable Compensation Networks for Single Phase Voltage
Mode Buck Regulators,” Intersil Technical Brief TB417.1, Milpitas, Calif., 2003.
G. Moschopoulos and P. Jain, “Single-Phase Single-Stage Power-Factor-Corrected
Converter Topologies,” IEEE Transactions on Industrial Electronics, vol. 52, no. 1,
February 2005, pp. 23–35.
M. Nave, Power Line Filter Design for Switched-Mode Power Supplies, Van Nostrand
Reinhold, Princeton, N.J., 1991.
A. I. Pressman, K. Billings, and T. Morey, Switching Power Supply Design, McGraw-Hill,
New York, 2009.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 327
Problems 327

M. Qiao, P. Parto, and R. Amirani, “Stabilize the Buck Converter with Transconductance
Amplifier,” International Rectifier Application Note AN-1043, 2002.
D. Venable, “The K Factor: A New Mathematical Tool for Stability Analysis and
Synthesis,” Proceedings Powercon 10, 1983.
V. Vorperian, “Simplified Analysis of PWM Converters Using Model of PWM Switch,”
IEEE Transactions on Aerospace and Electronic Systems, May 1990.
“8-Pin Synchronous PWM Controller,” International Rectifier Data Sheet No. PD94173
revD, 2005.
Problems
Flyback Converter
7.1 The flyback converter of Fig. 7-2 has parameters Vs 36 V, D 0.4, N1/N2 2,
R 20 , Lm 100 H, and C 50 F, and the switching frequency is
100 kHz. Determine (a) the output voltage; (b) the average, maximum, and
minimum inductor currents; and (c) the output voltage ripple.
7.2 The flyback converter of Fig. 7-2 has parameters Vs 4.5 V, D 0.6, N1/N2 0.4,
R 15 , Lm 10 H, and C 10 F, and the switching frequency is 250 kHz.
Determine (a) the output voltage; (b) the average, maximum, and minimum
inductor currents; and (c) the output voltage ripple.
7.3 The flyback converter of Fig. 7-2 has an input of 44 V, an output of 3 V, a duty
ratio of 0.32, and a switching frequency of 300 kHz. The load resistor is 1 .
(a) Determine the transformer turns ratio. (b) Determine the transformer
magnetizing inductance Lm such that the minimum inductor current is 40 percent
of the average.
7.4 Design a flyback converter for an input of 24 V and an output of 40 W at 40 V.
Specify the transformer turns ratio and magnetizing inductance, switching
frequency, and capacitor to limit the ripple to less than 0.5 percent.
7.5 (a) What is the value of load resistance that separates continuous and
discontinuous magnetizing inductance current in the flyback converter of
Example 7-1? (b) Graph Vo/Vs as the load changes from 5 to 20 .
7.6 For the flyback converter operating in the discontinuous-current mode, derive an
expression for the time at which the magnetizing current iLm returns to zero.
Forward Converter
7.7 The forward converter of Fig. 7-5a has parameters Vs 100 V, N1/N2 N1/N3 1,
Lm 1 mH, Lx 70 H, R 20 , C 33 F, and D 0.35, and the
switching frequency is 150 kHz. Determine (a) the output voltage and output
voltage ripple; (b) the average, maximum, and minimum values of the current in
Lx; (c) the peak current in Lm in the transformer model; and (d) the peak current
in the switch and the physical transformer primary.
7.8 The forward converter of Fig. 7-5a has parameters Vs 170 V, N1/N2 10,
N1/N3 1, Lm 340 H, Lx 20 H, R 10 , C 10 F, D 0.3, and the
switching frequency is 500 kHz. (a) Determine the output voltage and output
voltage ripple. (b) Sketch the currents in Lx, Lm, each transformer winding, and Vs.
har80679_ch07_265-330.qxd 12/17/09 2:54 PM Page 328
(c) Determine the power returned to the source by the tertiary (third) transformer
winding from the recovered stored energy in Lm.
7.9 A forward converter has a source of 80 V and a load of 250 W at 50 V. The output
filter has Lx 100 H and C 150 F. The switching frequency is 100 kHz.
(a) Select a duty ratio and transformer turns ratios N1/N2 and N1/N3 to provide the
required output voltage. Verify continuous current in Lx. (b) Determine the output
voltage ripple.
7.10 The forward converter of Fig. 7-5a has parameters Vs 100 V, N1/N2 5,
N1/N3 1, Lm 333 H, R 2.5 , C 10 F, and D 0.25, and the
switching frequency is 375 kHz. (a) Determine the output voltage and output
voltage ripple. (b) Sketch the currents iLx, I1, i2, i3, iLm, and is. Determine the
power returned to the source by the tertiary (third) transformer winding from the
recovery storage energy in Lm.
7.11 A forward converter has parameters Vs 125 V, Vo 50 V, and R 25 , and
the switching frequency is 250 kHz. Determine (a) the transformer turns ratio
N1/N2 such that the duty ratio is 0.3, (b) the inductance Lx such that the minimum
current in Lx is 40 percent of the average current, and (c) the capacitance required
to limit the output ripple voltage to 0.5 percent.
7.12 Design a forward converter to meet these specifications: Vs 170 V, Vo 48 V,
output power-150 W, and the output voltage ripple must be less than 1 percent.
Specify the transformer turns ratios, the duty ratio of the switch, the switching
frequency, the value of Lx to provide continuous current, and the output capacitance.
7.13 Design a forward converter to produce an output voltage of 30 V when the input
dc voltage is unregulated and varies from 150 to 175 V. The output power varies
from 20 to 50 W. The duty ratio of the switch is varied to compensate for the
fluctuations in the source to regulate the output at 30 V. Specify the switching
frequency and range of required duty ratio of the switch, the turns ratios of the
transformer, the value of Lx, and the capacitance required to limit the output
ripple to less than 0.2 percent. Your design must work for all operating conditions.
7.14 The current waveforms in Fig. 7-6 for the forward converter show the
transformer currents based on the transformer model of Fig. 7-1d. Sketch the
currents that exist in the three windings of the physical three-winding
transformer. Assume that N1/N2 N1/N3 1.
Push-Pull Converter
7.15 The push-pull converter of Fig. 7-8a has the following parameters: Vs 50 V,
Np/Ns 2, Lx 60 H, C 39 F, R 8 , f 150 kHz, and D 0.35.
Determine (a) the output voltage, (b) the maximum and minimun inductor
7.16 For the push-pull converter in Prob. 7-12, sketch the current in Lx, D1, D2, Sw1,
Sw2, and the source.
7.17 The push-pull converter of Fig. 7-8a has a transformer with a magnetizing
inductance Lm 2 mH which is placed across winding P1 in the model. Sketch
the current in Lm for the circuit parameters given in Prob. 7-11.
7.18 For the push-pull converter of Fig. 7-8a, (a) sketch the voltage waveform vLx,
and (b) derive the expression for output voltage [Eq. (7-44)] on the basis that the
average inductor voltage is zero.
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Problems 329
Current-Fed Converter
7.19 The current-fed converter of Fig. 7-11a has an input voltage of 24 V and a turns
ratio Np/Ns 2. The load resistance is 10 , and the duty ratio of each switch is
0.65. Determine the output voltage and the input current. Assume that the input
inductor is very large. Determine the maximum voltage across each switch.
7.20 The current-fed converter of Fig. 7-11a has an input voltage of 30 V and supplies
a load of 40 W at 50 V. Specify a transformer turns ratio and a switch duty ratio.
Determine the average current in the inductor.
7.21 The output voltage for the current-fed converter of Fig. 7-11a was derived on
the basis of the average inductor voltage being zero. Derive the output voltage
[Eq. (7-56)] on the basis that the power supplied by the source must equal the
power absorbed by the load for an ideal converter.
PSpice
7.22 Run a PSpice simulation for the flyback converter in Example 7-2. Use the
voltage-controlled switch Sbreak with Ron 0.2 , and use the default diode
model Dbreak. Display the output for voltage for steady-state conditions. Compare
output voltage and output voltage ripple to the results from Example 7-2. Display
the transformer primary and secondary current, and determine the average value
of each. Comment on the results.
7.23 Run a PSpice simulation for the forward converter of Example 7-4. Use the
voltage-controlled switch Sbreak with Ron 0.2 and use the default diode
model Dbreak. Let the capacitance be 20 F. Display the steady-state currents in
Lx and each of the transformer windings. Comment on the results.
Control
7.24 Design a type 2 compensated error amplifier (Fig. 7-23a) that will give a phase
angle at crossover co 210 and a gain of 20 dB for a crossover frequency of
12 kHz.
7.25 A buck converter has a filter transfer function that has a magnitude of 15 dB
and phase angle of 105 at 5 kHz. The gain of the PWM circuit is 9.5 dB.
Design a type 2 compensated error amplifier (Fig. 7-23a) that will give a phase
margin of at least 45 for a crossover frequency of 5 kHz.
7.26 A buck converter has L 50 H, C 20 F, rc 0.5 , and a load resistance
R 4 . The PWM converter has Vp 3 V. A type 2 error amplifier has R1
1 k , R2 5.3 k , C1 11.4 nF, and C2 1.26 nF. Use PSpice to determine
the phase margin of the control loop (as in Example 7-8) and comment on the
stability. Run a PSpice control loop simulation as in Example 7-10.
7.27 A buck converter has L 200 H with a series resistance rL 0.2 , C
100 F with rc 0.5 , and a load R 4 . The PWM converter has Vp 3 V.
(a) Use PSpice to determine the magnitude and phase angle of the filter and load
at 10 kHz. (b) Design a type 2 compensated error amplifier (Fig. 7-23a) that will
give a phase margin of at least 45 at a crossover frequency of 10 kHz. Verify
your results with a PSpice simulation of a step change in load resistance from
4 to 2 as in Example 7-10. Let Vs 20 V and Vref 8 V.
har80679_ch07_265-330.qxd 12/17/09 2:55 PM Page 330
7.28 A buck converter has L 200 H with a series resistance rL 0.1 , C

200 F with rc 0.4 , and a load R 5 . The PWM converter has Vp 3 V.
(a) Use PSpice to determine the magnitude and phase angle of the filter and load
at 8 kHz. (b) Design a type 2 compensated error amplifier (Fig. 7-23a) that will
give a phase margin of at least 45 at a crossover frequency of 10 kHz. Verify
your results with a PSpice simulation of a step change in load resistance as in
Fig. 7-27. Let Vs 20 V and Vref 8 V.
7.29 For the type 3 compensated error amplifier of Fig. 7-28a, determine the K factor
for an error amplifier phase angle of 195. For a gain of 15 dB at a crossover
frequency of 15 kHz, determine the resistance and capacitance values for the
amplifier.
7.30 The frequency response of a buck converter shows that the output voltage is
8 dB, and the phase angle is 140 at 15 kHz. The ramp function in the PWM
control circuit has a peak value of 3 V. Use the K factor method to determine
values of the resistors and capacitors for the type 3 error amplifier of Fig. 7-28a
for a crossover frequency of 15 kHz.
7.31 The buck converter circuit of Fig. 7-29 has L 40 H, rL 0.1 , Co
500 F, rC 30 m , and RL 3 . The ramp function in the PWM control
circuit has a peak value of 3 V. Use the K factor method to design a type 3
compensated error amplifier for a stable control system with a crossover
frequency of 10 kHz. Specify the resistor and capacitor values in the error
amplifier.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 331
C H A P T E R 8
Inverters
Converting dc to ac
8.1 INTRODUCTION
Inverters are circuits that convert dc to ac. More precisely, inverters transfer
power from a dc source to an ac load. The controlled full-wave bridge converters
in Chap. 4 can function as inverters in some instances, but an ac source must pre-
exist in those cases. In other applications, the objective is to create an ac voltage
when only a dc voltage source is available. The focus of this chapter is on invert-
ers that produce an ac output from a dc input. Inverters are used in applications
such as adjustable-speed ac motor drives, uninterruptible power supplies (UPS),
and running ac appliances from an automobile battery.
8.2 THE FULL-BRIDGE CONVERTER

The full-bridge converter of Fig 8-1a is the basic circuit used to convert dc to ac.
The full-bridge converter was introduced as part of a dc power supply circuit in
Chap. 7. In this application, an ac output is synthesized from a dc input by clos-
ing and opening the switches in an appropriate sequence. The output voltage vo
can be Vdc, Vdc, or zero, depending on which switches are closed. Figure 8-1b
to e shows the equivalent circuits for switch combinations.
Switches Closed Output Voltage vo

S1 and S2 Vdc
S3 and S4 Vdc
S1 and S3 0
S2 and S4 0
331
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332 C H A P T E R 8 Inverters
is
iS1 iS3
S1 S3
+ vo
+ –
Vdc
– iS4 io iS2
S4 S2
(a)
S1 S3
+ Vdc + –Vdc
+ – + –
Vdc Vdc
– –
S2 S4
(b) (c)
S1 S3
0 0
+ – + –
S4 S2
(d) (e)
Figure 8-1 (a) Full-bridge converter; (b) S1 and S2 closed; (c) S3 and S4
closed; (d ) S1 and S3 closed; (e) S2 and S4 closed.
Note that S1 and S4 should not be closed at the same time, nor should S2 and S3.
Otherwise, a short circuit would exist across the dc source. Real switches do
not turn on or off instantaneously, as was discussed in Chap. 6. Therefore,
switching transition times must be accommodated in the control of the switches.
Overlap of switch “on” times will result in a short circuit, sometimes called a
shoot-through fault, across the dc voltage source. The time allowed for switching
is called blanking time.
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8.3 The Square-Wave Inverter 333
8.3 THE SQUARE-WAVE INVERTER

The simplest switching scheme for the full-bridge converter produces a square wave
output voltage. The switches connect the load to Vdc when S1 and S2 are closed or
to Vdc when S3 and S4 are closed. The periodic switching of the load voltage
between Vdc and Vdc produces a square wave voltage across the load. Although
this alternating output is nonsinusoidal, it may be an adequate ac waveform for
some applications.
The current waveform in the load depends on the load components. For the
resistive load, the current waveform matches the shape of the output voltage. An
inductive load will have a current that has more of a sinusoidal quality than the
voltage because of the filtering property of the inductance. An inductive load pre-
sents some considerations in designing the switches in the full-bridge circuit
because the switch currents must be bidirectional.
For a series RL load and a square wave output voltage, assume switches S1
and S2 in Fig. 8-1a close at t 0. The voltage across the load is Vdc, and cur-
rent begins to increase in the load and in S1 and S2. The current is expressed as
the sum of the forced and natural responses
i o(t) i f (t) i n(t)

(8-1)
Vdc
Ae t> for 0 t T>2
R
where A is a constant evaluated from the initial condition and L/R.

At t T/2, S1 and S2 open, and S3 and S4 close. The voltage across the RL load
becomes Vdc, and the current has the form
Vdc
i o(t) Be (tT>2)> for T>2 t T (8-2)
R
where the constant B is evaluated from the initial condition.

When the circuit is first energized and the initial inductor current is zero, a
transient occurs before the load current reaches a steady-state condition. At
steady state, io is periodic and symmetric about zero, as illustrated in Fig. 8-2. Let
the initial condition for the current described in Eq. (8-1) be Imin, and let the ini-
tial condition for the current described in Eq. (8-2) be Imax.
Evaluating Eq. (8-1) at t 0,
Vdc
i o(0) Ae0 Imin
R
or
Vdc
A Imin (8-3)
R
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Vdc
vo 0
–T T t
2
–Vdc
Imax
io
t
Imin –T T
2
Imax
i S , iS
1 2 t
Imin –T T
2
Imax
i S , iS
3 4 t
Imin –T T
2
Imax
is
t
Imin –T T
2
Figure 8-2 Square wave output voltage and steady-state current

waveform for an RL load.
Likewise, Eq. (8-2) is evaluated at t T2.
Vdc
i o(T>2) Be0 Imax
R
or
Vdc
B Imax (8-4)
R
In steady state, the current waveforms described by Eqs. (8-1) and (8-2) then
become
Vdc V T
aImin dc b e t> for 0 t
R R 2
i o(t) e (8-5)
Vdc V T
a Imax dc b e(tT>2)> for tT
R R 2
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8.3 The Square-Wave Inverter 335
An expression is obtained for Imax by evaluating the first part of Eq. (8-5) at t T2
Vdc V
i(T>2) Imax aImin dc b e (T>2) (8-6)
R R
and by symmetry,
Imin Imax (8-7)
Substituting Imax for Imin in Eq. (8-6) and solving for Imax,
Vdc 1 e T>2
Imax Imin a b (8-8)
R 1 e T>2
Thus, Eqs. (8-5) and (8-8) describe the current in an RL load in the steady state
when a square wave voltage is applied. Figure 8-2 shows the resulting currents
in the load, source, and switches.
2
Power absorbed by the load can be determined from I rms R, where rms load
current is determined from the defining equation from Chap. 2. The integration
may be simplified by taking advantage of the symmetry of the waveform. Since
the square each of the current half-periods is identical, only the first half-period
needs to be evaluated:
T T/2
2
1 2 Vdc V
Irms i 2(t) d(t) c aImin dc b e t/ d dt (8-9)
FT L FT L R R
0 0
If the switches are ideal, the power supplied by the source must be the same as
absorbed by the load. Power from a dc source is determined from
Pdc Vdc Is (8-10)
as was derived in Chap. 2.
EXAMPLE 8-1
Square-Wave Inverter with RL Load

The full-bridge inverter of Fig. 8-1 has a switching sequence that produces a square wave
voltage across a series RL load. The switching frequency is 60 Hz, Vdc 100 V, R 10 ,
and L 25 mH. Determine (a) an expression for load current, (b) the power absorbed by
the load, and (c) the average current in the dc source.
■ Solution
(a) From the parameters given,
T 1f 160 0.0167 s
L/R 0.02510 0.0025 s
T2 3.33
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Equation (8-8) is used to determine the maximum and minimum current.
100 1 e 3.33
Imax Imin a b 9.31 A
10 1 e 3.33
Equation (8-5) is then evaluated to give load current.
100 100 t>0.0025

i o(t) a 9.31 be
10 10
1
10 19.31e t>0.0025 0t
120
100 100 (t0.0167>2)>0.0025

i o(t) a9.31 be
10 10
1 1
10 19.31e (t0.00835)0.0025 t
120 60
2
(b) Power is computed from Irms R, where Irms is computed from Eq. (8-9).
1/120
1
Irms 3 ( 10 19.31)e t/0.00254 2dt 6.64 A
F 120 L
0
Power absorbed by the load is

P I 2rms R (6.64)2(10) 441 W
(c) Average source current can also be computed by equating source and load power,
assuming a lossless converter. Using Eq. (8-10),
Pdc 441
Is 4.41 A
Vdc 100
Average power could also be computed from the average of the current
expression in part (a).
The switch currents in Fig. 8-2 show that the switches in the full-bridge cir-
cuit must be capable of carrying both positive and negative currents for RL loads.
However, real electronic devices may conduct current in one direction only. This
problem is solved by placing feedback diodes in parallel (anitparallel) with each
switch. During the time interval when the current in the switch must be negative,
the feedback diode carries the current. The diodes are reverse-biased when cur-
rent is positive in the switch. Figure 8-3a shows the full-bridge inverter with
switches implemented as insulated gate bipolar transistors (IGBTs) with feed-
back diodes. Transistor and diode currents for a square wave voltage and an RL
load are indicated in Fig 8-3b. Power semiconductor modules often include feed-
back diodes with the switches.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 337
8.4 Fourier Series Analysis 337
Q1 D1 D3 Q3
io + vo –
+
Vdc
–
Q4 D4 D2 Q2
(a)
vo
io
D1 Q1 D3 Q3
D2 Q2 D4 Q4
(b)
Figure 8-3 (a) Full-bridge inverter using IGBTs;

(b) Steady-state current for an RL load.
When IGBTs Q1 and Q2 are turned off in Fig. 8-3a, the load current must be
continuous and will transfer to diodes D3 and D4, making the output voltage Vdc,
effectively turning on the switch paths 3 and 4 before Q3 and Q4 are turned on.
IGBTs Q3 and Q4 must be turned on before the load current decays to zero.
8.4 FOURIER SERIES ANALYSIS

The Fourier series method is often the most practical way to analyze load current
and to compute power absorbed in a load, especially when the load is more com-
plex than a simple resistive or RL load. A useful approach for inverter analysis is
to express the output voltage and load current in terms of a Fourier series. With
no dc component in the output,
q
vo(t) a Vn sin (n
0t n) (8-11)
n1
and
q
i o(t) a In sin (n
0t n) (8-12)
n1
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 338
Power absorbed by a load with a series resistance is determined from I 2rmsR,

where the rms current can be determined from the rms currents at each of the
components in the Fourier series by
In 2
aa b
q q
2
Irms a I n, rms (8-13)
A n1 C n1 12
where
Vn
In (8-14)
Zn
and Zn is the load impedance at harmonic n.
Equivalently, the power absorbed in the load resistor can be determined for
each frequency in the Fourier series. Total power can be determined from
q q
P a Pn a I 2n, rms R (8-15)

n1 n1
where I n,rms is In/ 12.

In the case of the square wave, the Fourier series contains the odd harmonics
and can be represented as
4V
vo(t) a dc sin n
0t (8-16)
n odd n
EXAMPLE 8-2
Fourier Series Solution for the Square-Wave Inverter

For the inverter in Example 8-1 (Vdc 100 V, R 10 , L 25 mH, f 60 Hz), deter-
mine the amplitudes of the Fourier series terms for the square wave load voltage, the ampli-
tudes of the Fourier series terms for load current, and the power absorbed by the load.
■ Solution
The load voltage is represented as the Fourier series in Eq. (8-16). The amplitude of each
voltage term is
4Vdc 4(400)
Vn
n n
The amplitude of each current term is determined from Eq. (8-14),
Vn Vn 4(400)/n
In
Zn 2R2 (n
L)2 210 2 [n(2 60)(0.025)]2
0
Power at each frequency is determined from Eq. (8-15).
In 2
Pn I 2n, rms R a b R
12
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8.5 Total Harmonic Distortion 339
Table 8-1 Fourier Series Quantities for Example 8-2

n fn (Hz) Vn (V) Zn ( ) In (A) Pn (W)
1 60 127.3 13.7 9.27 429.3
3 180 42.4 30.0 1.42 10.0
5 300 25.5 48.2 0.53 1.40
7 420 18.2 66.7 0.27 0.37
9 540 14.1 85.4 0.17 0.14
Table 8-1 summarizes the Fourier series quantities for the circuit of Example 8-1.
As the harmonic number n increases, the amplitude of the Fourier voltage component
decreases and the magnitude of the corresponding impedance increases, both resulting
in small currents for higher-order harmonics. Therefore, only the first few terms of the
series are of practical interest. Note how the current and power terms become vanish-
ingly small for all but the first few frequencies.
Power absorbed by the load is computed from Eq. (8-15).
P a Pn 429.3 10.0 1.40 0.37 0.14 Á L 441 W
which agrees with the result in Example 8-1.
8.5 TOTAL HARMONIC DISTORTION

Since the objective of the inverter is to use a dc voltage source to supply a load
requiring ac, it is useful to describe the quality of the ac output voltage or current.
The quality of a nonsinusoidal wave can be expressed in terms of total harmonic
distortion (THD), defined in Chap. 2. Assuming no dc component in the output,
q
2
(V )
A a n, rms
n2 2V 2rms V 21, rms
THD (8-17)
V1, rms V1, rms
The THD of current is determined by substituting current for voltage in the

above equation. The THD of load current is often of greater interest than that
of output voltage. This definition for THD is based on the Fourier series, so
there is some benefit in using the Fourier series method for analysis when the
THD must be determined. Other measures of distortion such as distortion factor,
as presented in Chap. 2, can also be applied to describe the output waveform for
inverters.
EXAMPLE 8-3
THD for a Square-Wave Inverter

Determine the total harmonic distortion of the load voltage and the load current for the
square-wave inverter in Examples 8-1 and 8-2.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 340
■ Solution
Use the Fourier series for the square wave in Eq. (8-16) and the definition of THD in
Eq. (8-17). The rms value of the square wave voltage is the same as the peak value, and
the fundamental frequency component is the first term in Eq. (8-16),
Vrms Vdc
V1 4Vdc
V1, rms
12 12
Using Eq. (8-17) to compute the total harmonic distortion for voltage,
2V 2rms V 21, rms 2V 2dc (4Vdc> 12 )2

THDV 0.483 48.3%
V1, rms 4Vdc> 12
The THD of the current is computed using the truncated Fourier series which was deter-
mined in Example 8-2.
q
(I )2
A a n, rms
n2
THDI
I1, rms
2(1.42> 12)2 (0.53> 12)2 (0.27> 12)2 (0.17> 12)2

L 0.167 16.7%
9.27> 12
8.6 PSPICE SIMULATION OF SQUARE-WAVE

INVERTERS
Computer simulation of inverter circuits can include various levels of circuit
detail. If only the current waveform in the load is desired, it is sufficient to provide
a source that will produce the appropriate voltage that would be expected on the
inverter output. For example, a full-bridge inverter producing a square wave out-
put might be replaced with a square wave voltage source using the VPULSE
source. This simplified simulation will predict the behavior of the current in the
load but will give no direct information about the switches. Also, this approach
assumes that the switching operation correctly produces the desired output.
EXAMPLE 8-4
PSpice Simulation for Example 8-1

For a series (RL) load in a full-bridge inverter circuit with a square wave output, the dc
supply is 100 V, R 10 , L 25 mH, and the switching frequency is 60 Hz (Example 8-1).
(a) Assuming ideal switches, use PSpice to determine the maximum and minimum
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8.6 PSpice Simulation of Square-Wave Inverters 341
SQUARE–WAVE INVERTER
PARAMETERS:
Vdc = 100 R
out
freq = 60
10 1
V1 = {Vdc} V1
+
V2 = {–Vdc}
– L 25m
TD = 0
TR = 1n
TF = 1n
2
PW = {1/(2*freq)}
PER = {1/freq}
(a)
Inverter with Switches and Diodes

Ideal Switches and Diodes
S1 S3
Control12 + + + + Control34
– D1 D3 –
+ Out+ R L Out–
Vdc 1 2
100 25m
10
– V+ V–
S4 S2
Control34 Control12
+ + + +
–
D4 D2 –
E
Control12 Control34
+
PARAMETERS: V1 = –1
{{
Vsqr {{
+ –
freq = 60 V2 = 1
– GAIN = –1
TD = 0
TR = 1n
TF = 1n
PW = {1/(2*freq)}
PER = {1/freq}
(b)
Figure 8-4 (a) Square-wave inverter simulation using an ideal source;

(b) Square-wave inverter using switches and diodes.
current in the load in the steady state. (b) Determine the power absorbed by the load.
(c) Determine the total harmonic distortion of the load current.
■ Solution 1
Since individual switch currents are not of concern in this problem, a square wave volt-
age source (VPULSE), as shown in Fig. 8-4a, across the load can simulate the converter
output.
Set up a simulation profile for a transient analysis having a run time of 50 ms (three
periods), and start saving data after 16.67 ms (one period) so the output represents steady-
state current.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 342
Fourier analysis is performed under Simulation Settings, Output File Options, Perform
Fourier Analysis, Center Frequency: 60 Hz, Number of Harmonics: 15, Output Variables:
V(OUT) I(R).
(a) When in Probe, enter the expression I(R) to obtain a display of the current in the
load resistor. The first period contains the start-up transient, but steady-state current
like that in Fig. 8-2 is displayed thereafter. The maximum and minimum steady-
state current values are approximately 9.31 and 9.31 A, which can be obtained
precisely by using the cursor option.
(b) Average power can be obtained from Probe by displaying load current, making sure that
the data represent the steady-state condition and entering the expression AVG(W(R))
or AVG(V(OUT)*I(R)). This shows that the resistor absorbs approximately 441 W.
The rms current is determined by entering RMS(I(R)), resulting in 6.64 A, as read
from the end of the trace. These results agree with the analysis in Example 8-1.
(c) The THD is obtained from the Fourier series for I(R) in the output file as 16.7 percent,
agreeing with the Fourier analysis in Examples 8-2 and 8-3. Note that the THD for
the square wave in the output file is 45 percent, which is lower than the 48.3 percent
computed in Example 8-3. The THD in PSpice is based on the truncated Fourier
series through n 15. The magnitudes of higher-order harmonics are not
insignificant for the square wave, and omitting them underestimates the THD. The
higher-order current harmonics are small, so there is little error in omitting them from
the analysis. The number of harmonics in the output file can be increased if desired.
■ Solution 2
The inverter is simulated using the full-bridge circuit of Fig. 8-4b. (This requires the full
version of PSpice.) The result of this simulation gives information about the currents and
voltages for the switching devices. Voltage-controlled switches (Sbreak) and the default
diode (Dbreak) are used. Diodes are included in the switch model to make the switches
unidirectional. The model for Sbreak is changed so Ron 0.01 , and the model for
Dbreak is changed so n 0.01, approximating an ideal diode. The output voltage is
between nodes out and out. Models for the switches and diodes can be changed to
determine the behavior of the circuit using realistic switching devices.
8.7 AMPLITUDE AND HARMONIC CONTROL

The amplitude of the fundamental frequency for a square wave output from of
the full-bridge inverter is determined by the dc input voltage [Eq. (8-16)]. A con-
trolled output can be produced by modifying the switching scheme. An output
voltage of the form shown in Fig. 8-5a has intervals when the output is zero as
well as Vdc and Vdc. This output voltage can be controlled by adjusting the
interval on each side of the pulse where the output is zero. The rms value of the
voltage waveform in Fig 8-5a is
1 2 2
Vrms V dc d(
t) Vdc 1 (8-18)
B A
L
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 343
8.7 Amplitude and Harmonic Control 343
+Vdc
α α α α
0
π 2π ωt
–Vdc
(a)
S1 Closed Open
S2
S3
S4
S2 S1 S1 S3 S2
S4 S2 S3 S4 S4
vo: 0 Vdc 0 –Vdc 0
(b)
Figure 8-5 (a) Inverter output for amplitude and harmonic control; (b) Switching
sequence for the full-bridge inverter of Fig. 8-1a.
The Fourier series of the waveform is expressed as
vo (t) a Vn sin(n
0t) (8-19)
n odd
Taking advantage of half-wave symmetry, the amplitudes are

2 4V
Vn V sin(n
0t) d(
0t) dc cos(n ) (8-20)
3 dc n

har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 344
where is the angle of zero voltage on each end of the pulse. The amplitude of
each frequency of the output is a function of . In particular, the amplitude of the
fundamental frequency (n 1) is controllable by adjusting :
4Vdc
V1 a b cos (8-21)

Harmonic content can also be controlled by adjusting . If 30, for
example, V3 0. This is significant because the third harmonic can be eliminated
from the output voltage and current. Other harmonics can be eliminated by
choosing a value of which makes the cosine term in Eq. (8-20) to go to zero.
Harmonic n is eliminated if
90°
(8-22)
n
The switching scheme required to produce an output like Fig. 8-5a must pro-
vide intervals when the output voltage is zero, as well as Vdc. The switching
sequence of Fig. 8-5b is a way to implement the required output waveform.
Amplitude control and harmonic reduction may not be compatible. For
example, establishing at 30 to eliminate the third harmonic fixes the amplitude
of the output fundamental frequency at V1 (4Vdc/ ) cos 30 1.1Vdc and
removes further controllability. To control both amplitude and harmonics using
this switching scheme, it is necessary to be able to control the dc input voltage to
the inverter. A dc-dc converter (Chap. 6 and 7) placed between the dc source and the
inverter can provide a controlled dc input to the inverter.
A graphical representation of the integration in the Fourier series coefficient
of Eq. (8-20) gives some insight into harmonic elimination. Recall from Chap. 2
that the Fourier coefficients are determined from the integral of the product of the
waveform and a sinusoid. Figure 8-6a shows the output waveform for 30
and the sinusoid of
3
o. The product of these two waveforms has an area of
zero, showing that the third harmonic is zero. Figure 8-6b shows the waveform
for 18 and the sinusoid of
5
o, showing that the fifth harmonic is elim-
inated for this value of .
Other switching schemes can eliminate multiple harmonics. For example,
the output waveform shown in Fig. 8-6c eliminates both the third and fifth har-
monics, as indicated by the areas of both being zero.
EXAMPLE 8-5
Harmonic Control of the Full-Bridge Inverter Output

Design an inverter that will supply the series RL load of the previous examples (R 10
and L 25 mH) with a fundamental-frequency current amplitude of 9.27 A, but with a
THD of less than 10 percent. A variable dc source is available.
■ Solution
A square-wave inverter produces a THD for current of 16.7 percent (Example 8-3), which
does not meet the specification. The dominant harmonic current is for n 3, so a switching
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 345
8.7 Amplitude and Harmonic Control 345
n=3
0 α = 30°
(a)
n=5
0 α = 18°
(b)
vo(t)
n=3
n=5
30° 54° 66° 114° 126° 150°

(c)
Figure 8-6 Harmonic elimination; (a) Third harmonic; (b) Fifth

harmonic; (c) Third and fifth harmonics.
scheme to eliminate the third harmonic will reduce the THD. The required voltage ampli-
tude at the fundamental frequency is
V1 I1Z1 I1 2R2 (
0 L)2 9.27 210 2 32 60 (0.025)42 127 V
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 346
Using the switching scheme of Fig. 8-5b, Eq. (8-21) describes the amplitude of the
fundamental-frequency voltage,
4Vdc
V1 a b cos

Solving for the required dc input with 30,
V1 127
Vdc 116 V
4 cos 4 cos 30°
Other harmonic voltages are described by Eq. (8-20), and currents for these harmon-
ics are determined from voltage amplitude and load impedance using the same tech-
nique as for the square-wave inverter of Example 8-2. The results are summarized in
Table 8-2.
Table 8-2 Fourier Series Quantities for Example 8-5

n fn (Hz) Vn (V) Zn ( ) In (A)
1 60 127 13.7 9.27
3 180 0 30.0 0
5 300 25.5 48.2 0.53
7 420 18.2 66.7 0.27
9 540 0 85.4 0
11 660 11.6 104 0.11
The THD of the load current is then
q
2
I n, rms
Aa n2 2(0.53> 12)2 (0.27> 12)2 (0.11> 12)2
THD1 L 0.066 6.6%
I1, rms 9.27> 12
which more than satisfies the design specifications.

A PSpice circuit for the full-bridge inverter with harmonic and amplitude control is
shown in Fig. 8-7a. The user must enter the parameters alpha, output fundamental fre-
quency, dc input voltage to the bridge, and load. The Probe output for voltage and current
is shown in Fig. 8-7b. The current is scaled by a factor of 10 to show its relationship to
the voltage waveform. The THD of the load current is obtained from the Fourier analysis
in the output file as 6.6 percent.
8.8 THE HALF-BRIDGE INVERTER

The half-bridge converter of Fig. 8-8 can be used as an inverter. This circuit was
introduced in Chap. 7 as applied to dc power supply circuits. In this circuit, the
number of switches is reduced to 2 by dividing the dc source voltage into two
parts with the capacitors. Each capacitor will be the same value and will have
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 347
8.8 The Half-Bridge Inverter 347
INVERTER WITH AMPLITUDE AND HARMONIC CONTROL
TABLE = (–2,–1)(–1,0)(1,0)(2,1) {V(%In+, %In–)*Vdc}

R
Out
IN+ OUT+ IN+ OUT+
IN– OUT– IN– OUT– 10 1
Vsqr Vsqr2 ETABLE EVALUE V L
+ +
– – 25M
2
V1 = –2 V1 = –2 PARAMETERS:
V2 = 2 V2 = 2 alpha = 30
TD = {Talpha} TD = {1/(2*freq)-Talpha} freq = 60
TR = 1n TR = 1n Vdc = 100
TF = 1n TF = 1n Talpha = {alpha/360/freq}
PW = {1/(2*freq–2n)} PW = {1/(2*freq)–2n}
PER = {1/(freq)} PER = {1/(freq)}
(a)
100 v
i
0
SEL>>
–150
30 ms 40 ms 50 ms 60 ms 70 ms
V(Out) I(R)*10
Time
100
FOURIER
50
0
0 Hz 200 Hz 400 Hz 600 Hz 800 Hz
V(Out) I(R)*10
Frequency
(b)
Figure 8-7 (a) A PSpice circuit for Example 8-5 to produce the voltage waveform in
Fig. 8-5a; (b) Probe output for showing harmonic elimination.
voltage Vdc/2 across it. When S1 is closed, the load voltage is Vdc/2. When S2 is
closed, the load voltage is Vdc/2. Thus, a square wave output or a bipolar pulse-
width-modulated output, as described in Sec. 8.10, can be produced.
The voltage across an open switch is twice the load voltage, or Vdc. As with
the full-bridge inverter, blanking time for the switches is required to prevent a
short circuit across the source, and feedback diodes are required to provide con-
tinuity of current for inductive loads.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 348
+
Vdc
2 – S1
+ vo –
+
Vdc
–
+
Vdc
2 –
S2
(a)
HALF–BRIDGE INVERTER
Ideal Switches and Diodes
S1
Control1 + +
C1 – – D1
10000u
+ Vdc Out– L Out+

2 1 R
100
– 25m 10
V− S2 V+
Control2 + +
C2 – – D2
10000u
E
Control1 + Control2
PARAMETERS: V1 = –1
+
V1 –{ {
freq = 60 V2 = 1
– GAIN = –1
TD = 0
TR = 1n
TF = 1n
PW = {1/(2*freq)}
PER = {1/(freq)}
(b)
Figure 8-8 (a) A half-bridge inverter using IGBTs. The

output is Vdc; (b) A PSpice implementation using voltage-
controlled switches and diodes.
8.9 MULTILEVEL INVERTERS

The H bridge inverter previously illustrated in Figs. 8-1 and 8-3 produces
output voltages of Vdc, 0, and –Vdc. The basic H bridge switching concept can be
expanded to other circuits that can produce additional output voltage levels.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 349
8.9 Multilevel Inverters 349
+
Vdc +
– v2 +
–
vo
+
Vdc +
– v1 –
–
Figure 8-9 An inverter with two dc sources, each with an

H bridge implemented with IGBTs.
These multilevel-output voltages are more sinelike in quality and thus reduce
harmonic content. The multilevel inverter is suitable for applications including
adjustable-speed motor drives and interfacing renewable energy sources such as
photovoltaics to the electric power grid.
Multilevel Converters with Independent DC Sources

One multilevel inverter method uses independent dc sources, each with an H bridge.
A circuit with two dc voltage sources is shown in Fig. 8-9. The output of each of
the H bridges is Vdc, Vdc, or 0, as was illustrated in Fig. 8-1. The total instan-
taneous voltage vo on the output of the multilevel converter is any combination
of individual bridge voltages. Thus, for a two-source inverter, vo can be any of
the five levels 2Vdc, Vdc, 0, Vdc, or 2Vdc.
Each H bridge operates with a switching scheme like that of Fig. 8.5 in
Sec. 8.7, which was used for amplitude or harmonic control. Each bridge oper-
ates at a different delay angle , resulting in bridge and total output voltages like
those shown in Fig. 8-10.
The Fourier series for the total output voltage vo for the two-source circuit
contains only the odd-numbered harmonics and is
4Vdc sin(n
0t)
3cos(n 1) cos(n 2)4
q
vo(t) a (8-23)
n 1,3,5,7, . . . n
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 350
2Vdc
Vdc
vo
0 α1 α2 ωt
–Vdc
–2Vdc
v2
0 α2 π – α2 π ωt
v1
0 α1 π – α1 π ωt
Figure 8-10 Voltage output of each of the H bridges and

the total voltage for the two-source multilevel inverter of
Fig. 8-9.
The Fourier coefficients for this series are
4Vdc
Vn 3cos(n 1) cos(n 2)4 (8-24)
n
The modulation index Mi is the ratio of the amplitude of the fundamental fre-
quency component of vo to the amplitude of the fundamental frequency compo-
nent of a square wave of amplitude 2Vdc, which is 2(4Vdc/ ).
V1 cos 1 cos 2
Mi (8-25)
2(4Vdc / ) 2
Some harmonics can be eliminated from the output voltage waveform with
the proper selection of 1 and 2 in Eq. (8-24). For the two-source converter, har-
monic m can be eliminated by using delay angles such that
cos(m 1) cos(m 2) 0 (8-26)
To eliminate the mth harmonic and also meet a specified modulation index
for the two-source inverter requires the simultaneous solution to Eq. (8-26) and
the additional equation derived from Eq. (8-25),
cos( 1) cos( 2) 2M i (8-27)
To solve Eqs. (8-26) and (8-27) simultaneously requires an iterative numerical

method such as the Newton-Raphson method.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 351
EXAMPLE 8-6
A Two-Source Multilevel Inverter

For the two-source multilevel inverter of Fig. 8-9 with Vdc 100 V: (a) Determine the
Fourier coefficients through n 9 and the modulation index for 1 20 and 2 40.
(b) Determine 1 and 2 such that the third harmonic (n 3) is eliminated and Mi 0.8.
■ Solution
Using Eq. 8-24 to evaluate the Fourier coefficients,
4Vdc 4(100)
Vn 3cos(n 1) cos(n 2)4 3cos(n20°) cos(n 40°)4
n n
resulting in V1 217, V3 0, V5 28.4, V7 10.8, and V9 0. Note that the third
and ninth harmonics are eliminated. The even harmonics are not present.
The modulation index Mi is evaluated from Eq. (8-25).
cos 1 cos 2 cos 20° cos 40°
Mi 0.853
2 2
The amplitude of the fundamental frequency voltage is therefore 85.3 percent of that
of a square wave of 200 V.
(b) To achieve simultaneous elimination of the third harmonic and a modulation index of
Mi 0.8 requires the solution to the equations
cos(3 1) cos(3 2) 0
and
cos( 1) cos( 2) 2M i 1.6
Using an iterative method, 1 7.6 and 2 52.4.
The preceding concept can be extended to a multilevel converter having several

dc sources. For k separate sources connected in cascade, there are 2k1 possible
voltage levels. As more dc sources and H bridges are added, the total output volt-
age has more steps, producing a staircase waveform that more closely
approaches a sinusoid. For a five-source system as shown in Fig. 8-11, there are
11 possible output voltage levels, as illustrated in Fig. 8-12.
The Fourier series for a staircase waveform such as that in Fig 8-12 for k sep-
arate dc sources each equal to Vdc is
4Vdc sin(n
0t)
3cos(n 1) cos(n 2) Á cos(n k)4
q
vo(t) a (8-28)
n1,3,5,7, . . . n
The magnitudes of the Fourier coefficients are thus
4Vdc
Vn 3cos(n 1) cos(n 2) Á cos(n k)4
n
(8-29)
for n 1, 3, 5, 7, . . .
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 352
+ +
Vdc v5
– –
+ +
Vdc v4
– –
+
+ +
Vdc v3 vo
– –
–
+ +
Vdc v2
– –
+ +
Vdc v1
– –
Figure 8-11 A five-source cascade

multilevel converter.
The modulation index Mi for k dc sources each equal to Vdc is

V1 cos( 1) cos( 2) Á cos( k)
Mi (8-30)
4kVdc/ k
5Vdc
4Vdc
3Vdc
2Vdc
Vdc
0
v5
α5
v4
α4
v3
α3
v2
α2
v1
α1
Figure 8-12 Voltages at each H bridge in Fig. 8-11 and the

total output voltage.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 353
Specific harmonics can be eliminated from the output voltage. To eliminate the
mth harmonic, the delay angles must satisfy the equation
cos(m 1) cos(m 2) Á cos(m k) 0 (8-31)
For k dc sources, k 1 harmonics can be eliminated while establishing a par-
ticular Mi.
EXAMPLE 8-7
A Five-Source Multilevel Inverter

Determine the delay angles required for a five-source cascade multilevel converter that
will eliminate harmonics 5, 7, 11, and 13 and will have a modulation index Mi 0.8.
■ Solution
The delay angles must satisfy these simultaneous equations:
cos(5 1) cos(5 2) cos(5 3) cos(5 4) cos(5 5) 0

cos( 1) cos( 2) cos( 3) cos( 4) cos( 5) 5M i 5(0.8) 4
An iteration method such as the Newton-Raphson method must be used to solve these
equations. The result is 1 6.57, 2 18.94, 3 27.18, 4 45.14, and 5
62.24. See the references in the Bibliography for information on the technique.
Equalizing Average Source Power with Pattern Swapping

In the two-source inverter of Fig. 8-9 using the switching scheme of Fig. 8-10,
the source and H bridge producing the voltage v1 supplies more average power
(and energy) than the source and H bridge producing v2 due to longer pulse
widths in both the positive and negative half cycles. If the dc sources are batter-
ies, one battery will discharge faster than the other. A technique known as pattern
swapping or duty swapping equalizes the average power supplied by each dc
source.
The principle of pattern swapping is to have each dc source conduct for an
equal amount of time on average. An alternate switching scheme for the two-
source circuit is shown in Fig. 8-13. In this scheme, the first source conducts for
a longer time in the first half-cycle while the second source conducts for more
time in the second half-cycle. Thus, over one complete period, the sources con-
duct equally, and average power from each source is the same.
For the five-source converter in Fig. 8-11, a switching scheme to equalize
average power is shown in Fig. 8-14. Note that five half cycles are required to
equalize power.
A variation of the H bridge multilevel inverter is to have the dc sources be of
different values. The output voltage would be a staircase waveform, but not in equal
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 354
v3
v2
v1
Figure 8-13 Pattern swapping to equalize

average power in each source for the two-
source inverter of Fig. 8-9.
voltage increments. The Fourier series of the output voltage would have different-
valued harmonic amplitudes which may be an advantage in some applications.
Because independent voltage sources are needed, the multiple-source imple-
mentation of multilevel converters is best suited in applications where batteries,
fuel cells, or photovoltaics are the sources.
Diode-Clamped Multilevel Inverters

A multilevel converter circuit that has the advantage of using a single dc source
rather than multiple sources is the diode-clamped multilevel converter shown in
Fig. 8-15a. In this circuit, the dc voltage source is connected to a pair of series
capacitors, each charged to Vdc/2. The following analysis shows how the output
voltage can have the levels of Vdc, Vdc/2, 0, Vdc/2, or –Vdc.
vo
v5
v4
v3
v2
v1
Figure 8-14 Pattern swapping to equalize average source power for the five-source
multilevel inverter of Fig. 8-11.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 355
S1 S5
S2 S6
Vdc + vo –
S3 S7
S8
S4
(a)
S1 S1 S1
+
Vdc/2
S2 S2 – S2
+ + +
Vdc Vdc Vdc
– + – + – +
S3 S3
S3 +
v1 = Vdc v1 = 0 v1 = Vdc/2
Vdc/2
S4 –
S4 S4
– – –
(b) (c) (d)
Figure 8-15 (a) A diode-clamped multilevel inverter implemented with IGBTs. (b) Analysis for
one-half of the circuit for v1 Vdc, (c) for v1 0, and (d) for v1 12Vdc.
For the analysis, consider only the left half of the bridge, as shown in Fig. 8-15b,
c, and d. With S1 and S2 closed and S3 and S4 open, V1 Vdc (Fig. 8-15b). The
diodes are off for this condition. With S1 and S2 open and S3 and S4 closed, V1 0
(Fig. 8-15c). The diodes are off for this condition also. To produce a voltage of
Vdc/2, S2 and S3 are closed, and S1 and S4 are open (Fig. 8-15d). The voltage v1 is
that of the lower capacitor, at voltage Vdc/2, connected through the antiparallel
diode path that can carry load current in either direction. Note that for each of
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 356
these circuits, two switches are open, and the voltage of the source divides
between the two, thus reducing the voltage stress across each switch compared to
the H bridge circuit of Fig. 8-1.
Using a similar analysis, the right half of the bridge can also produce the
voltages Vdc, 0, and Vdc/2. The output voltage is the difference of the voltages
between each half bridge, resulting in the five levels
1 1
vo H b Vdc, Vdc, 0, Vdc, Vdc r (8-32)
2 2
with multiple ways to achieve some of them. The switch control can establish
delay angles 1 and 2, to produce an output voltage like that in Fig. 8-10 for the
cascaded H bridge, except that the maximum value is Vdc instead of 2Vdc.
More output voltage levels are achieved with additional capacitors and
switches. Figure 8-16 shows the dc source divided across three series capacitors.
+
Vdc/3
–
+ + vo –
Vdc Vdc/3
–
+
Vdc/3
–
Figure 8-16 A diode-clamped multilevel inverter that produces

four voltage levels on each side of the bridge and seven output
voltage levels.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 357
8.10 Pulse-Width-Modulated Output 357
The voltage across each capacitor is 13 V, producing the four voltage levels on
each side of the bridge of Vdc, 32Vdc, 13Vdc, and 0. The output voltage can then have
the seven levels
2 1 1 2
vo H b Vdc, Vdc, Vdc, 0, Vdc, Vdc, Vdc r (8-33)
3 3 3 3
8.10 PULSE-WIDTH-MODULATED OUTPUT

Pulse-width modulation (PWM) provides a way to decrease the total harmonic
distortion of load current. A PWM inverter output, with some filtering, can gen-
erally meet THD requirements more easily than the square wave switching
scheme. The unfiltered PWM output will have a relatively high THD, but the har-
monics will be at much higher frequencies than for a square wave, making filter-
ing easier.
In PWM, the amplitude of the output voltage can be controlled with the
modulating waveforms. Reduced filter requirements to decrease harmonics and
the control of the output voltage amplitude are two distinct advantages of PWM.
Disadvantages include more complex control circuits for the switches and
increased losses due to more frequent switching.
Control of the switches for sinusoidal PWM output requires (1) a reference
signal, sometimes called a modulating or control signal, which is a sinusoid in
this case and (2) a carrier signal, which is a triangular wave that controls the
switching frequency. Bipolar and unipolar switching schemes are discussed next.
Bipolar Switching
Figure 8-17 illustrates the principle of sinusoidal bipolar pulse-width modula-
tion. Figure 8-17a shows a sinusoidal reference signal and a triangular carrier
signal. When the instantaneous value of the sine reference is larger than the tri-
angular carrier, the output is at Vdc, and when the reference is less than the car-
rier, the output is at Vdc:
vo Vdc for vsine v tri

(8-34)
vo Vdc for vsine v tri
This version of PWM is bipolar because the output alternates between plus and
minus the dc supply voltage.
The switching scheme that will implement bipolar switching using the full-
bridge inverter of Fig. 8-1 is determined by comparing the instantaneous refer-
ence and carrier signals:
S1 and S2 are on when vsine vtri (vo Vdc)

S3 and S4 are on when vsine vtri. (vo Vdc)
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 358
vtri vsine
(Carrier) (Reference)
(a)
Vdc
–Vdc
(b)
Figure 8-17 Bipolar pulse-width modulation. (a) Sinusoidal

reference and triangular carrier; (b) Output is Vdc when vsine
vtri and is Vdc when vsine vtri.
Unipolar Switching
In a unipolar switching scheme for pulse-width modulation, the output is switched
either from high to zero or from low to zero, rather than between high and low as in
bipolar switching. One unipolar switching scheme has switch controls in Fig. 8-1
as follows:
S1 is on when vsine vtri

Note that switch pairs (S1, S4) and (S2, S3) are complementary—when one switch
in a pair is closed, the other is open. The voltages va and vb in Fig. 8-18a alternate
between Vdc and zero. The output voltage vo vab va vb is as shown in
Fig. 8-18d.
Another unipolar switching scheme has only one pair of switches operating
at the carrier frequency while the other pair operates at the reference frequency,
thus having two high-frequency switches and two low-frequency switches. In
this switching scheme,
S1 is on when vsine vtri (high frequency)
S4 is on when vsine vtri (high frequency)
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8.11 PWM Definitions and Considerations 359
S1 S3
+ vo = vab
Vdc + –
–
+ +
va vb
S4 S2
– –
(a)
vsine –vsine
vtri
(b)
Vdc
va
0
Vdc
vb
0
(c)
Vdc
vab 0
–Vdc
(d)
Figure 8-18 (a) Full-bridge converter for unipolar PWM; (b) Reference
and carrier signals; (c) Bridge voltages va and vb; (d) Output voltage.
S2 is on when vsine 0 (low frequency)

S3 is on when vsine 0 (low frequency)
where the sine and triangular waves are as shown in Fig. 8-19a. Alternatively,
S2 and S3 could be the high-frequency switches, and S1 and S4 could be the low-
frequency switches.
8.11 PWM DEFINITIONS AND CONSIDERATIONS

At this point, some definitions and considerations relevant when using PWM
should be stated.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 360
(a)
+Vdc
va
0
(b)
+Vdc
vb
0
(c)
+Vdc
vo = vab 0
–Vdc
(d)
Figure 8-19 Unipolar PWM with high- and low-frequency

switches. (a) Reference and control signals; (b) va (Fig. 8-18a);
(c) vb ; (d) output va vb.
1. Frequency modulation ratio mf. The Fourier series of the PWM output
voltage has a fundamental frequency which is the same as the reference
signal. Harmonic frequencies exist at and around multiples of the switching
frequency. The magnitudes of some harmonics are quite large, sometimes
larger than the fundamental. However, because these harmonics are located
at high frequencies, a simple low-pass filter can be quite effective in
removing them. Details of the harmonics in PWM are given in the next
section. The frequency modulation ratio mf is defined as the ratio of the
frequencies of the carrier and reference signals,
fcarrier f
mf tri (8-35)
freference fsine
Increasing the carrier frequency (increasing mf) increases the frequencies at
which the harmonics occur. A disadvantage of high switching frequencies
is higher losses in the switches used to implement the inverter.
2. Amplitude modulation ratio ma. The amplitude modulation ratio ma is
defined as the ratio of the amplitudes of the reference and carrier signals:
Vm, reference Vm, sine
ma (8-36)
Vm, carrier Vm, tri
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 361
8.12 PWM Harmonics 361
If ma 1, the amplitude of the fundamental frequency of the output

voltage V1 is linearly proportional to ma. That is,
V1 m aVdc (8-37)
The amplitude of the fundamental frequency of the PWM output is thus
controlled by ma. This is significant in the case of an unregulated dc supply
voltage because the value of ma can be adjusted to compensate for
variations in the dc supply voltage, producing a constant-amplitude output.
Alternatively, ma can be varied to change the amplitude of the output. If ma is
greater than 1, the amplitude of the output increases with ma, but not linearly.
3. Switches. The switches in the full-bridge circuit must be capable of
carrying current in either direction for pulse-width modulation just as they
did for square wave operation. Feedback diodes across the switching
devices are necessary, as was done in the inverter in Fig. 8-3a. Another
consequence of real switches is that they do not turn on or off instantly.
Therefore, it is necessary to allow for switching times in the control of the
switches just as it was for the square-wave inverter.
4. Reference voltage. The sinusoidal reference voltage must be generated
within the control circuit of the inverter or taken from an outside reference.
It may seem as though the function of the inverter bridge is unnecessary
because a sinusoidal voltage must be present before the bridge can operate
to produce a sinusoidal output. However, there is very little power required
from the reference signal. The power supplied to the load is provided by
the dc power source, and this is the intended purpose of the inverter. The
reference signal is not restricted to a sinusoid, and other waveshapes can
function as the reference signal.
8.12 PWM HARMONICS

Bipolar Switching
The Fourier series of the bipolar PWM output illustrated in Fig. 8-17 is deter-
mined by examining each pulse. The triangular waveform is synchronized to the
reference as shown in Fig 8-17a, and mf is chosen to be an odd integer. The PWM
output then exhibits odd symmetry, and the Fourier series can then be expressed
q
vo(t) a Vn sin(n
0 t) (8-38)
n1
For the kth pulse of the PWM output in Fig. 8-20, the Fourier coefficient is
T
2
Vnk v(t) sin(n
0 t) d(
0 t)
3
0
k k k1
2
c V sin(n
0 t) d(
0 t) (Vdc)sin(n
0 t) (d(
0 t) d
3 dc 3
k k k
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 362
vtri vsine
+Vdc
–Vdc
αk δk
αk + δk
αk+1
Figure 8-20 Single PWM pulse for determining Fourier

series for bipolar PWM.
Performing the integration,

2Vdc
Vnk [cos n k cos n k1 2 cos n( k k)] (8-39)
n
Each Fourier coefficient Vn for the PWM waveform is the sum of Vnk for the p
pulses over one period,
p
Vn a Vnk (8-40)
k1
The normalized frequency spectrum for bipolar switching for ma1 is

shown in Fig. 8-21. The harmonic amplitudes are a function of ma because the
1.00
0.80
0.60
Vn
0.40
0.20
0
1 mf 2mf 3mf 4mf 5mf 6mf n
Figure 8-21 Frequency spectrum for bipolar PWM with ma 1.

har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 363
Table 8-3 Normalized Fourier Coefficients Vn/Vdc for Bipolar PWM

ma1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
n1 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10
nmf 0.60 0.71 0.82 0.92 1.01 1.08 1.15 1.20 1.24 1.27
nmf2 0.32 0.27 0.22 0.17 0.13 0.09 0.06 0.03 0.02 0.00
width of each pulse depends on the relative amplitudes of the sine and triangular
waves. The first harmonic frequencies in the output spectrum are at and around
m f. Table 8-3 indicates the first harmonics in the output for bipolar PWM. The
Fourier coefficients are not a function of mf if mf is large ( 9).
EXAMPLE 8-8
A PWM Inverter
The full-bridge inverter is used to produce a 60-Hz voltage across a series RL load using
bipolar PWM. The dc input to the bridge is 100 V, the amplitude modulation ratio ma is
0.8, and the frequency modulation ratio mf is 21 [ftri (21)(60) 1260 Hz]. The load has
a resistance of R 10 and series inductance L 20 mH. Determine (a) the amplitude
of the 60-Hz component of the output voltage and load current, (b) the power absorbed
by the load resistor, and (c) the THD of the load current.
■ Solution
(a) Using Eq. (8-38) and Table 8-3, the amplitude of the 60-Hz fundamental frequency is
V1 m aVdc (0.8)(100) 80 V
The current amplitudes are determined using phasor analysis:

Vn Vn
In (8-41)
Zn 2R (n
0L)2
2
For the fundamental frequency,

80
I1 6.39 A
210 [(1)(2 60)(0.02)]2
2
(b) With mf 21, the first harmonics are at n 21, 19, and 23. Using Table 8-3,
V21 (0.82)(100) 82 V
V19 V23 (0.22)(100) 22 V
Current at each of the harmonics is determined from Eq. (8-41).
Power at each frequency is determined from
In 2
Pn (In, rms)2R a b R
12
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 364
Table 8-4 Fourier Series Quantities for the PWM Inverter of Example 8-8
n fn (Hz) Vn (V) Zn ( ) In (A) In,rms (A) Pn (W)
1 60 80.0 12.5 6.39 4.52 204.0
19 1140 22.0 143.6 0.15 0.11 0.1
21 1260 81.8 158.7 0.52 0.36 1.3
23 1380 22.0 173.7 0.13 0.09 0.1
The resulting voltage amplitudes, currents, and powers at these frequencies are sum-
marized in Table 8-4.
Power absorbed by the load resistor is
P a Pn L 204.0 0.1 1.3 0.1 205.5 W
Higher-order harmonics contribute little power and can be neglected.

(c) The THD of the load current is determined using Eq. (8-17) with the rms current of
the harmonics approximated by the first few terms indicated in Table 8-4.
q
2
I n,
A a rms
n2 2(0.11)2 (0.36)2 (0.09)2
THD1 L 0.087 8.7%
I1, rms 4.52
By using the truncated Fourier series in Table 8-4, the THD will be underestimated.
However, since the impedance of the load increases and the amplitudes of the har-
monics generally decrease as n increases, the above approximation should be accept-
able. (Including currents through n 100 gives a THD of 9.1 percent.)
EXAMPLE 8-9
PWM Inverter Design

Design a bipolar PWM inverter that will produce a 75-V rms 60-Hz output from a 150-V
dc source. The load is a series RL combination with R 12 and L 60 mH. Select the
switching frequency such that the current THD is less than 10 percent.
■ Solution
The required amplitude modulation ratio is determined from Eq. (8-38),
V1 7522
ma 0.707
Vdc 150
The current amplitude at 60 Hz is
V1 7522
I1 4.14 A
Z1 2122 [(2 60)(0.06)]2
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 365
The rms value of the harmonic current has a limit imposed by the required THD,
4.14
(In, rms)2 0.1 I1, rms 0.1 a b 0.293 A
q
a
A n2 12
The term that will produce the dominant harmonic current is at the switching frequency.
As an approximation, assume that the harmonic content of the load current is the same as
the dominant harmonic at the carrier frequency:
q
I
a (In, rms)2 L Imf, rms mf
A n2 12
The amplitude of the current harmonic at the carrier frequency is then approximated as
Imf (0.1)(4.14) 0.414 A
Table 8-3 indicates that the normalized voltage harmonic for n mf and for ma 0.7 is
0.92. The voltage amplitude for n mf is then
Vmf 0.92 Vdc (0.92)(150) 138 V
The minimum load impedance at the carrier frequency is then
Vmf 138
Zmf 333 Æ
Imf 0.414
Because the impedance at the carrier frequency must be much larger than the 12- load
resistance, assume the impedance at the carrier frequency is entirely inductive reactance,
Zmf L
L m f
0L
For the load impedance to be greater than 333 ,
m f
0 L 333
333
mf 14.7
(377)(0.06)
Selecting mf to be at least 15 would marginally meet the design specifications. However,
the estimate of the harmonic content used in the calculations will be low, so a higher car-
rier frequency is a more prudent selection. Let mf 17, which is the next odd integer. The
carrier frequency is then
ftri m f fref (17)(60) 1020 Hz
Further increasing mf would reduce the current THD, but at the expense of larger switch-
ing losses. A PSpice simulation, as discussed later in this chapter, can be used to verify
that the design meets the specifications.
Unipolar Switching
With the unipolar switching scheme in Fig. 8-18, some harmonics that were in
the spectrum for the bipolar scheme are absent. The harmonics in the output
begin at around 2mf , and mf is chosen to be an even integer. Figure 8-22 shows
the frequency spectrum for unipolar switching with ma 1.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 366
1.00
0.80
0.60
Vn
0.40
0.20
0
1 2mf 4mf 6mf n
Figure 8-22 Frequency spectrum for unipolar PWM with ma 1.
Table 8-5 indicates the first harmonics in the output for unipolar PWM.
The unipolar PWM scheme using high- and low-frequency switches shown
in Fig. 8-19 will have similar results as indicated above, but the harmonics will
begin at around mf rather than 2mf .
Table 8-5 Normalized Fourier Coefficients Vn/Vdc for Unipolar PWM in Fig. 8-18
ma1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
n1 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10
n2mf1 0.18 0.25 0.31 0.35 0.37 0.36 0.33 0.27 0.19 0.10
n2mf3 0.21 0.18 0.14 0.10 0.07 0.04 0.02 0.01 0.00 0.00
8.13 CLASS D AUDIO AMPLIFIERS

The reference signal for the PWM control circuit can be an audio signal, and the
full-bridge circuit could be used as a PWM audio amplifier. A PWM audio ampli-
fier is referred to as a class D amplifier. The triangular wave carrier signal for this
application is typically 250 kHz to provide adequate sampling, and the PWM
waveform is low-pass filtered to recover the audio signal and deliver power to a
speaker. The spectrum of the PWM output signal is dynamic in this case.
Class D amplifiers are much more efficient than other types of audio power
amplifiers. The class AB amplifier, the traditional circuit for audio applications,
has a maximum theoretical efficiency of 78.5 percent for a sine wave of maximum
undistorted output. In practice, with real audio signals, class AB efficiency is
much lower, on the order of 20 percent. The theoretical efficiency of the class D
amplifier is 100 percent because the transistors are used as switches. Because
transistor switching and filtering are imperfect, practical class D amplifiers are
about 75 percent efficient.
Class D audio amplifiers are becoming more prevalent in consumer electron-
ics applications where greater efficiency results in reduced size and increased
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 367
8.14 Simulation of Pulse-Width-Modulated Inverters 367
battery life. In high-power applications such as at rock concerts, class D amplifiers

are used to reduce the size of the amplifier and for reduced heat requirements in
the equipment.
8.14 SIMULATION OF PULSE-WIDTH-MODULATED

INVERTERS
Bipolar PWM
PSpice can be used to simulate the PWM inverter switching schemes presented
previously in this chapter. As with other power electronics circuits, the level of
circuit detail depends on the objective of the simulation. If only the voltages and
currents in the load are desired, a PWM source may be created without modeling
the individual switches in the bridge circuit. Figure 8-23 shows two ways to pro-
duce a bipolar PWM voltage. The first uses an ABM2 block, and the second uses
BIPOLAR PWM FUNCTION
Sine IN1 L
PWM_1 1 2
VOFF = 0 Tri OUT
V1 IN2 20m
VAMPL = {ma} + V2
FREQ = {freq} – + EXP1 = {VDC}*(V(%IN1)–V(%IN2))/ABS((V(%IN1)–v(%IN2))+1n) R 10
PHASE = {–90/mf} –
V1 = –1
V2 = 1 PARAMETERS:
TD = 0
TR = {0.5/(freq*mf) – .5n} mf = 21
TF = {0.5/(freq*mf – .5n)} ma = 0.8
PW = 1n freq = 60
PER = {1/(freq*mf)} VDC = 100
(a)
TABLE = (–2,–1)(–10u,–1)(10u,1)(2,1) GAIN = {VDC}

Sine PWM_2 1 L1 2
IN+ OUT+ + {{
VOFF = 0 V3 Tri IN– OUT– – 20m
+ V4
VAMPL = {ma} – + E1 E E2
R1 10
FREQ = {freq} –
PHASE = {−90/mf}
V1 = –1
V2 = 1
TD = 0
TR = {0.5/(freq*mf) – .5n}
TF = {0.5/(freq*mf – .5n)}
PW = 1n
PER = {1/(freq*mf)}
(b)
Figure 8-23 PSpice functional circuits for producing a bipolar PWM voltage using (a) an ABM
block and (b) an ETABLE voltage source.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 368
a voltage-controlled voltage source ETABLE. Both methods compare a sine

wave to a triangular wave. Either method allows the behavior of a specific load
to a PWM input to be investigated.
If the load contains an inductance and/or capacitance, there will be an initial
transient in the load current. Since the steady-state load current is usually of interest,
one or more periods of the load current must be allowed to run before meaningful
output is obtained. One way to achieve this in PSpice is to delay output in the tran-
sient command, and another way is to restrict the data to steady-state results in
Probe. The reference signal is synchronized with the carrier signal as in Fig. 8-17a.
When the triangular carrier voltage has negative slope going through zero, the sinu-
soidal reference voltage must have positive slope going through zero. The triangu-
lar waveform starts at the positive peak with negative slope. The phase angle of the
reference sinusoid is adjusted to make the zero crossing correspond to that of the tri-
angular wave by using a phase angle of 90/mf . The following example illustrates
a PSpice simulation of a bipolar PWM application.
EXAMPLE 8-10
PSpice Simulation of PWM

Use PSpice to analyze the PWM inverter circuit of Example 8-8.
■ Solution
Using either PWM circuit in Fig. 8-23, the Probe output will be the waveforms shown in
Fig. 8-24a. The current is scaled by a factor of 10 to show more clearly its relationship
150
EXAMPLE 8–8: BIPOLAR PWM
100
–100
32 ms 36 ms 40 ms 44 ms 48 ms 51 ms
V(PWM) I(R)*10
Time
(a)
Figure 8-24 (a) Probe output for Example 8-10 showing PWM voltage and load current
(current is scaled for illustration); (b) Frequency spectra for voltage and current.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 369
100 V
VOLTAGE SPECTRUM
50 V
0V
V(PWM)
10.0 A
7.5 A CURRENT SPECTRUM
5.0 A
SEL>>
0A
0 Hz 1.0 KHz 2.0 KHz 3.0 KHz 4.0 KHz
I(R) Frequency
(b)
with output voltage. Note the sinelike quality of the current. The Fourier coefficients of
voltage and current are determined by using the Fourier option under the x axis menu or
by pressing the FFT icon. Figure 8-24b shows the frequency spectra of voltage and cur-
rent with the range on the x axis selected to show the lower frequencies. The cursor option
is used to determine the Fourier coefficients.
Table 8-6 summarizes the results. Note the close correspondence with the results of
Example 8-8.
Table 8-6 PSpice Results of Example 8-10
n fn (Hz) Vn (V) In (A)
1 60 79.8 6.37
19 1140 21.8 0.15
21 1260 82.0 0.52
23 1380 21.8 0.13
If the voltages and currents in the source and switches are desired, the
PSpice input file must include the switches. A somewhat idealized circuit using
voltage-controlled switches with feedback diodes is shown in Fig. 8-25. To sim-
ulate pulse-width modulation, the control for the switches in the inverter is the
voltage difference between a triangular carrier voltage and a sine reference volt-
age. While this does not represent a model for real switches, this circuit is useful
to simulate either bipolar or unipolar PWM. A more realistic bridge model would
include devices such as BJTs, MOSFETs, or IGBTs for the switches. The model
that is appropriate will depend on how completely switch performance must be
investigated.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 370
BIPOLAR PWM
PARAMETERS:
mf = 21
ma = 0.8
S1 S3
freq = 60 Cont12 + + + + Cont34
–– D1 D3 –
R L
+ Vdc Out+ 1 2 Out–
12 10 20m
–
S4 S2
Cont34 + + + + Cont12
–– D4 D2 –
(a)
Sine TABLE = (–2,–1)(–10u,–1)(10u,1)(2,1)

V1 = –1 E2 Cont34
VOFF = 0 Vs V2 = 1 Cont12
IN+ OUT+ + {{
VAMPL = {ma} + TD = 0 –
FREQ = {freq} – IN– OUT–
TR = {0.5/(freq*mf) – .5n} + E
PHASE = {–90/mf} TF = {0.5/(freq*mf – .5n)} E1
– Vt
PW = 1n
PER = {1/(freq*mf)}
(b)
Figure 8-25 PSpice circuits for a PWM inverter (a) using voltage-controlled
switches and diodes but requires the full PSpice version and (b) generating a
PWM function.
Unipolar PWM
Again, unipolar PWM can be simulated using various levels of switch models.
The input file shown in Fig. 8-26 utilizes dependent sources to produce a unipolar
PWM output.
UNIPOLAR PWM
R 1 L 2 B
IN+ OUT+ A OUT+ IN+
V1 = 1 IN– OUT– 1 2.65m OUT– IN–
V2 = –1 EVALUE + Vsin23
VOFF = 0 Vsin14 TD = 0 V+ V− EVALUE –
VAMPL = {ma} + TR = {1/(2*fc)} FREQ = {1}
– TF = {1/(2*fc)}
FREQ = {f}
PW = 1n + Vtri VAMPL = {ma}
PHASE = {–90/mf} PER = {1/(fc)} – VOFF = 0
PHASE = {–90/mf + 180}
PARAMETERS: EVALUE =
f = 60 Vdc/2*V(%IN+, %IN–)/(abs(V(%IN+, %IN–))+1n)+1
fc = {f*mf}
ma = 0.9
mf = 10
Vdc = 100
Figure 8-26 A PSpice circuit for generating a unipolar PWM voltage. The output voltage is between nodes
A and B.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 371
EXAMPLE 8-11
Pulse-Width Modulation PSpice Simulation

Pulse-width modulation is used to provide a 60-Hz voltage across a series RL load
with R 1 and L 2.65 mH. The dc supply voltage is 100 V. The amplitude of
the 60-Hz voltage is to be 90 V, requiring ma 0.9. Use PSpice to obtain the current
waveform in the load and the THD of the current waveform in the load. Use (a) bipo-
lar PWM with mf 21, (b) bipolar PWM with mf 41, and (c) unipolar PWM with
mf 10.
■ Solution
(a) The PSpice circuit for bipolar PWM (Fig. 8-25b) is run with ma 0.9 and mf 21.
The voltage across the load and the current in the load resistor are shown in
Fig. 8-27a. The currents for the 60-Hz fundamental and the lowest-order harmonics
are obtained from the Fourier option under x axis in Probe. The harmonic amplitudes
correspond to the peaks, and the cursor option determines precise values. The rms
current can be obtained from Probe by entering the expression RMS(I(R)). The
total harmonic distortion based on the truncated Fourier series is computed from
Eq. (8-17). Results are in the table in this example.
(b) The PSpice circuit is modified for mf 41. The voltage and current waveforms are
shown in Fig. 8-27b. The resulting harmonic currents are obtained from the Fourier
option in Probe.
BIPOLAR PWM, Ma = 0.9, MF = 21

100
–100
35.0 ms 40.0 ms 45.0 ms 50.0 ms

V(PWM) I(R)*10
Time
(a)
Figure 8-27 Voltage and current for Example 8-11 for (a) bipolar PWM with mf 21,
(b) bipolar PWM with mf 41, (c) Unipolar PWM with mf 10.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 372
BIPOLAR PWM, Ma = 0.9, Mf = 41

100
–100
35.0 ms 40.0 ms 45.0 ms 50.0 ms

V(PWM) I(R)*10
Time
(b)
UNIPOLAR PWM, Ma = 0.9, Mf = 10

100
–100
30 ms 35 ms 40 ms 45 ms 50 ms
V(A, B) I(R)
Time
(c)

har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 373
(c) The PSpice input file for unipolar switching in Fig. 8-26 is run with the parameter
mf 10. The output voltage and current are shown in Fig. 8-27c. The results of the
three simulations for this example are shown in the following table.
Bipolar mf 21 Bipolar mf 41 Unipolar mf 10

fn In fn In fn In
60 63.6 60 64.0 60 62.9
1140 1.41 2340 0.69 1020 1.0
1260 3.39 2460 1.7 1140 1.4
1380 1.15 2580 0.62 1260 1.24
1380 0.76
Irms 45.1 45.0 44.5
THD 6.1% 3.2% 3.6%
Note that the THD is relatively low in each of these PWM switching schemes, and
increasing the switching frequency (increasing mf) decreases the harmonic currents
in this type of a load.
8.15 THREE-PHASE INVERTERS

The Six-Step Inverter
Figure 8-28a shows a circuit that produces a three-phase ac output from a dc
input. A major application of this circuit is speed control of induction motors,
where the output frequency is varied. The switches are closed and opened in the
sequence shown in Fig. 8-28b.
Each switch has a duty ratio of 50 percent (not allowing for blanking time),
and a switching action takes place every T/6 time interval, or 60 angle interval.
Note that switches S1 and S4 close and open opposite of each other, as do switch
pairs (S2, S5) and (S3, S6). As with the single-phase inverter, these switch pairs
must coordinate so they are not closed at the same time, which would result in a
short circuit across the source. With this scheme, the instantaneous voltages vA0,
vB0, and vC0 are Vdc or zero, and line-to-line output voltages vAB, vBC, and vCA
are Vdc, 0, or Vdc. The switching sequence in Fig. 8-28b produces the output
voltages shown in Fig. 8-28c.
The three-phase load connected to this output voltage may be connected in
delta or ungrounded neutral wye. For a wye-connected load, which is the more
common load connection, the voltage across each phase of the load is a line-to-
neutral voltage, shown in Fig. 8-28d. Because of the six steps in the output wave-
forms for the line-to-neutral voltage resulting from the six switching transitions
per period, this circuit with this switching scheme is called a six-step inverter.
The Fourier series for the output voltage has a fundamental frequency equal
to the switching frequency. Harmonic frequencies are of order 6k 1 for k 1,
2, . . . (n 5, 7, 11, 13 . . .). The third harmonic and multiples of the third do not
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 374
Figure 8-28 (a)

Three-phase inverter;
(b) Switching S1 S3 S5
sequence for six-step iA
output; (c) Line-to-line
+ A
output voltages;
Vdc B
(d ) Line-to-neutral
–
voltages for an
C
ungrounded Y-
connected load; S4 S6 S2
(e) Current in phase A
for an RL load.
N
(a)
S1 Closed Open
S2
S3
S4
S5
S6
(b)
vAB
+Vdc
–Vdc
vBC
+Vdc
–Vdc
vCA
+Vdc
–Vdc
(c)
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 375
vAN
2–
V
1
–V 3 dc
3 dc
1 0
– – Vdc 2
3 – –V
3 dc
vBN
vCN
(d)
vAN
iA
(e)
exist, and even harmonics do not exist. For an input voltage of Vdc, the output for an
ungrounded wye-connected load has the following Fourier coefficients:
4V
Vn, LL 2 dc cos an b 2
n 6
2V 2
Vn, LN 2 dc c2 cos an b cos an b d 2 n 1, 5, 7, 11, 13, . . . (8-42)
3n 3 3
The THD of both the line-to-line and line-to-neutral voltages can be shown to be
31 percent from Eq. (8-17). The THD of the currents in load-dependent 15 are
smaller for an RL load. An example of the line-to-neutral voltage and line current
for an RL wye-connected load is shown in Fig. 8-28e.
The output frequency can be controlled by changing the switching frequency.
The magnitude of the output voltage depends on the value of the dc supply voltage.
To control the output voltage of the six-step inverter, the dc input voltage must
be adjusted.
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EXAMPLE 8-12
Six-Step Three-Phase Inverter

For the six-step three-phase inverter of Fig. 8-28a, the dc input is 100 V and the funda-
mental output frequency is 60 Hz. The load is wye-connected with each phase of the load
a series RL connection with R 10 and L 20 mH. Determine the total harmonic dis-
tortion of the load current.
■ Solution
The amplitude of load current at each frequency is
Vn, LN Vn, LN Vn, LN
In
Zn 2R (n
0 L)
2 2 210 [n (2 60)(0.02)]2
2
where Vn, LN is determined from Eq. (8-42). Table 8-7 summarizes the results of the
Fourier series computation.
Table 8.7 Fourier Components for the Six-Step Inverter of

Example 8-12
n Vn, L-N (V) Zn ( ) In (A) In, rms (A)
1 63.6 12.5 5.08 3.59
5 12.73 39.0 0.33 0.23
7 9.09 53.7 0.17 0.12
11 5.79 83.5 0.07 0.05
13 4.90 98.5 0.05 0.04
The THD of the load current is computed from Eq. (8-17) as

q
2
I n,
A a rms
n2 2(0.23)2 (0.12)2 (0.05)2 (0.04)2
THD1 L 0.07 7%
I1, rms 3.59
PWM Three-Phase Inverters

Pulse-width modulation can be used for three-phase inverters as well as for
single-phase inverters. The advantages of PWM switching are the same as for
the single-phase case: reduced filter requirements for harmonic reduction and the
controllability of the amplitude of the fundamental frequency.
PWM switching for the three-phase inverter is similar to that of the single-
phase inverter. Basically, each switch is controlled by comparing a sinusoidal
reference wave with a triangular carrier wave. The fundamental frequency of the
output is the same as that of the reference wave, and the amplitude of the output
is determined by the relative amplitudes of the reference and carrier waves.
As in the case of the six-step three-phase inverter, switches in Fig. 8-28a are
controlled in pairs (S1, S4), (S2, S5), and (S3, S6). When one switch in a pair is closed,
the other is open. Each pair of switches requires a separate sinusoidal reference
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 377
wave. The three reference sinusoids are 120 apart to produce a balanced three-
phase output. Figure 8-29a shows a triangular carrier and the three reference
waves. Switch controls are such that
S1 is on when va vtri
S2 is on when vc vtri
S3 is on when vb vtri
S4 is on when va vtri
S5 is on when vc vtri
S6 is on when vb vtri
Harmonics will be minimized if the carrier frequency is chosen to be an odd
triple multiple of the reference frequency, that is, 3, 9, 15, . . . times the reference.
Figure 8-29b shows the line-to-line output voltages for a PWM three-phase inverter.
vA, ref vcarrier
vB, ref vC, ref
(a)
VA0
VB0
VAB
VAN
iA
(b)
Figure 8-29 (a) Carrier and reference waves for PWM operation with mf 9 and ma 0.7 for the
three-phase inverter of Fig. 8-28a; (b) Output waveforms—current is for an RL load.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 378
The Fourier coefficients for the line-to-line voltages for the three-phase PWM
switching scheme are related to those of single-phase bipolar PWM (Vn in
Table 8-3) by
Vn3 2A2n3 B 2n3 (8-43)
where
n n
An3 Vn sin a b sin a b
2 3
(8-44)
n n
Bn3 Vn cos a b sin a b
2 3
Significant Fourier coefficients are listed in Table 8-8.
Table 8-8 Normalized Amplitudes Vn3/Vdc for Line-to-Line Three-Phase PWM Voltages
ma1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
n1 0.866 0.779 0.693 0.606 0.520 0.433 0.346 0.260 0.173 0.087
mf 2 0.275 0.232 0.190 0.150 0.114 0.081 0.053 0.030 0.013 0.003
2mf 1 0.157 0.221 0.272 0.307 0.321 0.313 0.282 0.232 0.165 0.086
Multilevel Three-Phase Inverters

Each of the multilevel inverters described in Sec. 8.9 can be expanded to three-
phase applications. Figure 8-30 shows a three-phase diode-clamped multilevel
inverter circuit. This circuit can be operated to have a stepped-level output simi-
lar to the six-step converter, or, as is most often the case, it can be operated to
have a pulse-width-modulated output.
8.16 PSPICE SIMULATION OF THREE-PHASE

INVERTERS
Six-Step Three-Phase Inverters
PSpice circuits that will simulate a six-step three-phase inverter are shown in
Fig. 8-31. The first circuit is for a complete switching scheme described in
Fig. 8-28. Voltage-controlled switches with feedback diodes are used for switch-
ing. (The full version of PSpice is required for this circuit.) The second circuit is
for generating the appropriate output voltages for the converter so load currents
can be analyzed. The output nodes of the inverter are nodes A, B, and C. The
parameters shown are those in Example 8-12.
PWM Three-Phase Inverters

The circuit in Fig. 8-32 produces the voltages of the PWM three-phase inverter
without showing the switching details. Dependent sources compare sine waves
to a triangular carrier wave, as in Example 8-8 for the single-phase case.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 379
8.17 Induction Motor Speed Control 379
a
Vdc b
c
Figure 8-30 A three-phase diode-clamped multilevel inverter.
8.17 INDUCTION MOTOR SPEED CONTROL

The speed of an induction motor can be controlled by adjusting the frequency
of the applied voltage. The synchronous speed
s of an induction motor is
related to the number of poles p and the applied electrical frequency
by
2

s (8-45)
p
Slip s, is defined in terms of the rotor speed
r

s
r
s (8-46)

s
and torque is proportional to slip.
If the applied electrical frequency is changed, the motor speed will change
proportionally. However, if the applied voltage is held constant when the fre-
quency is lowered, the magnetic flux in the air gap will increase to the point of
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 380
THREE–PHASE SIX-STEP INVERTER

PARAMETERS:
f = 60
S1 S3 S5 R = 10
++ ++ ++ L = 20m
–– D1 –– D3 –– D5
0 A 0 0
B
+ V1
C
100
– RA RB RC
S4 S6 S2 {R} {R} {R}
++ ++ ++ 1 1 1
–– D4 –– D6 –– D2
0 0 0 LA LB LC
{L} {L} {L}
2 2 N 2
0
V14 V36 V25
V1 = –1 + V1 = –1 + V1 = –1 +
V2 = 1 – V2 = 1 – V2 = 1 –
TD = 0 TD = {1/(3*f)} TD = {1/(6*f)} Set ITL4 = 100
TR = 1n TR = 1n TR = 1n
TF = 1n
0 TF = 1n
0 TF = 1n
0
PW = {1/(2*f)} PW = {1/(2*f)} PW = {1/(2*f)}
PER = {1/f} PER = {1/f} PER = {1/f}
(a)
SIX-STEP INVERTER EQUIVALENT PARAMETERS:

A Vdc = 100
freq = 60
B R = 10
C L = 20m
VA VB VC RA RB RC
+ + +
– – – {R} {R} {R}
1 1 1
V1 = 0 V1 = 0 V1 = 0
V2 = {Vdc} V2 = {Vdc} V2 = {Vdc} LA LB LC
TD = 0 TD = {1/(3*freq)} TD = {2/(3*freq)}
TR = 1n TR = 1n TR = 1n {L} {L} {L}
TF = 1n TF = 1n TF = 1n
PW = {1/(2*freq–2n)} PW = {1/(2*freq–2n)} PW = {1/(2*freq–2n)} 2 2 N 2
PER = {1/(freq)} PER = {1/(freq)} PER = {1/(freq)}
(b)
Figure 8-31 (a) A six-step inverter using switches and diodes (requires the full PSpice
version); (b) A PSpice circuit for generating three-phase six-step converter voltages.
saturation. It is desirable to keep the air-gap flux constant and equal to its rated
value. This is accomplished by varying the applied voltage proportionally with
frequency. The ratio of applied voltage to applied frequency should be constant.
V
constant (8-47)
f
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 381
8.17 Induction Motor Speed Control 381
THREE-PHASE PWM INVERTER

PARAMETERS:
f = 60
fc = {f*mf}
ma = 0.7
Vdc/2*V(%IN+, %IN–)/(abs(V(%IN+, %IN–))+1n)+1
mf = 9
Vdc = 100 IN+ OUT+
V1 = 1 IN– OUT–
V2 = –1
EVALUE
VA TD = 0 tri
VOFF = 0 + TR = {1/(2*fc)}
VAMPL = {ma} – TF = {1/(2*fc)} Vtri
FREQ = {f} +
PW = 1n
PHASE = {–90/mf} –
PER = {1/fc)}
IN+ OUT+
VB IN– OUT–
VOFF = 0 + tri EVALUE C B A
VAMPL = {ma} –
FREQ = {f} RC RB RA
PHASE = {–90/mf–120} 0 10 10 10
1 1 1
LC LB LA
IN+ OUT+ 20m 20m 20m
VC IN– OUT–
VOFF = 0 + tri EVALUE
VAMPL = {ma} – 2 2 2
FREQ = {f}
PHASE = {–90/mf–240} N
0
Figure 8-32 A PSpice functional circuit for generating three-phase PWM voltages.
The term volts/hertz control is often used for this situation. The induction motor
torque-speed curves of Fig. 8-33 are for different frequencies and constant
volts/hertz.
The six-step inverter can be used for this application if the dc input is
adjustable. In the configuration of Fig. 8-34, an adjustable dc voltage is produced
from a controlled rectifier, and an inverter produces an ac voltage at the desired
Torque
f4 f3 f2 f1
Speed
Figure 8-33 Induction motor torque-speed curves

for constant volts/hertz variable-speed control.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 382
ac
Vdc Motor
Source
Rectifier dc Link Inverter
Figure 8-34 AC-AC converter with a dc link.
frequency. If the dc source is not controllable, a dc-dc converter may be inserted

between the dc source and the inverter.
The PWM inverter is useful in a constant volts/hertz application because the
amplitude of the output voltage can be adjusted by changing the amplitude mod-
ulation ratio ma. The dc input to the inverter can come from an uncontrolled
source in this case. The configuration in Fig. 8-34 is classified as an ac-ac con-
verter with a dc link between the two ac voltages.
8.18 Summary
• The full- or half-bridge converters can be used to synthesize an ac output from a dc
input.
• A simple switching scheme produces a square wave voltage output, which has a
Fourier series that contains the odd harmonic frequencies of amplitudes
4Vdc
Vn
n
• Amplitude and harmonic control can be implemented by allowing a zero-voltage
interval of angle at each end of a pulse, resulting in Fourier coefficients
4Vdc
Vn a b cos(n )
n
• Multilevel inverters use more than one dc voltage source or split a single voltage
source with a capacitor voltage divider to produce multiple voltage levels on the
output of an inverter.
• Pulse-width modulation (PWM) provides amplitude control of the fundamental
output frequency. Although the harmonics have large amplitudes, they occur at
high frequencies and are filtered easily.
• Class D audio amplifiers use PWM techniques for high efficiency.
• The six-step inverter is the basic switching scheme for producing a three-phase ac
output from a dc source.
• A PWM switching scheme can be used with a three-phase inverter to reduce the
THD of the load current with modest filtering.
• Speed control of induction motors is a primary application of three-phase inverters.
har80679_ch08_331-386.qxd 12/17/09 2:56 PM Page 383
Problems 383
8.19 Bibliography
J. Almazan, N. Vazquez, C. Hernandez, J. Alvarez, and J. Arau, “Comparison between
the Buck, Boost and Buck-Boost Inverters,” International Power Electronics
Congress, Acapulco, Mexico, October 2000, pp. 341–346.
B. K. Bose, Power Electronics and Motor Drives: Advances and Trends, Elsevier/
Academic Press, 2006.
J. N. Chiasson, L. M. Tolbert, K. J. McKenzie, and D. Zhong, “A Unified Approach to
Solving the Harmonic Elimination Equations in Multilevel Converters,” IEEE
Transactions on Power Electronics, March 2004, pp. 478–490.
K. A. Corzine, “Topology and Control of Cascaded Multi-Level Converters,” Ph.D.
dissertation, University of Missouri, Rolla, 1997.
T. Kato, “Precise PWM Waveform Analysis of Inverter for Selected Harmonic
Elimination,” 1986 IEEE/IAS Annual Meeting, pp. 611–616.
L. G. Franquelo, “Multilevel Converters: Current Developments and Future Trends,”
IEEE International Conference on Industrial Technology, Chengdu, China, 2008.
J. R. Hauser, Numerical Methods for Nonlinear Engineering Models, Springer
Netherlands, Dordrecht, 2009.
J. Holtz, “Pulsewidth Modulation—A Survey,” IEEE Transactions on Industrial
Electronics, vol. 39, no. 5, Dec. 1992, pp. 410–420.
S. Miaosen, F. Z. Peng, and L. M. Tolbert, “Multi-level DC/DC Power Conversion
System with Multiple DC Sources,” IEEE 38th Annual Power Electronics
Specialists Conference, Orlando, Fla., 2007.
L. M. Tolbert, and F. Z. Peng, “Multilevel Converters for Large Electric Drives,”
Applied Power Electronics Conference and Exposition, anaheim, Calif., 1998.
L. Salazar and G. Joos, “PSpice Simulation of Three-Phase Inverters by Means of
Switching Functions,” IEEE Transactions on Power Electronics, vol. 9, no. 1,
Jan. 1994, pp. 35–42.
X. Yuan, and I. Barbi, “Fundamentals of a New Diode Clamping Multilevel Inverter,”
IEEE Transactions on Power Electronics, vol. 15, no. 4, July 2000, pp. 711–718.
Problems
Square-Wave Inverter
8-1. The square-wave inverter of Fig. 8-1a has Vdc ⫽ 125 V, an output frequency of
60 Hz, and a resistive load of 12.5 ⍀. Sketch the currents in the load, each
switch, and the source, and determine the average and rms values of each.
8-2. A square-wave inverter has a dc source of 96 V and an output frequency of 60 Hz.
The load is a series RL load with R ⫽ 5 ⍀ and L ⫽ 100 mH. When the load is
first energized, a transient precedes the steady-state waveform described
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 384
by Eq. (8-5). (a) Determine the peak value of the steady-state current. (b) Using
Eq. (8-1) and assuming zero initial inductor current, determine the maximum
current that occurs during the transient. (c) Simulate the circuit with the PSpice
input file of Fig. 8.4a and compare the results with parts (a) and (b). How many
periods must elapse before the current reaches steady state? How many L/R time
constants elapse before steady state?
8-3. The square-wave inverter of Fig. 8-3 has a dc input of 150 V and supplies a series
RL load with R 20 and L 40 mH. (a) Determine an expression for steady-
state load current. (b) Sketch the load current and indicate the time intervals
when each switch component (Q1, D1; . . . Q4, D4) is conducting. (c) Determine
the peak current in each switch component. (d) What is the maximum voltage
across each switch? Assume ideal components.
8-4. A square-wave inverter has a dc source of 125 V, an output frequency of 60 Hz,
and an RL series load with R 20 and L 25 mH. Determine (a) an
expression for load current, (b) rms load current, and (c) average source current.
8-5. A square-wave inverter has an RL load with R 15 and L 10 mH. The
inverter output frequency is 400 Hz. (a) Determine the value of the dc source
required to establish a load current that has a fundamental frequency component
of 8 A rms. (b) Determine the THD of the load current.
8-6. A square-wave inverter supplies an RL series load with R 25 and L 25 mH.
The output frequency is 120 Hz. (a) Specify the dc source voltage such that the
load current at the fundamental frequency is 2.0 A rms. (b) Verify your results
with PSpice. Determine the THD from PSpice.
8-7. A square-wave inverter has a dc input of 100 V, an output frequency of 60 Hz,
and a series RLC combination with R 10 , L 25 mH, and C 100 F. Use
the PSpice simplified square-wave inverter circuit of Fig. 8-4a to determine the
peak and rms value of the steady-state current. Determine the total harmonic
distortion of the load current. On a printout of one period of the current, indicate
the intervals where each switch component in the inverter circuit of Fig. 8-3 is
conducting for this load if that circuit were used to implement the converter.
Amplitude and Harmonic Control

8-8. For the full-bridge inverter, the dc source is 125 V, the load is a series RL
connection with R 10 and L 20 mH, and the switching frequency is 60 Hz.
(a) Use the switching scheme of Fig. 8-5 and determine the value of to produce
an output with an amplitude of 90 V at the fundamental frequency. (b) Determine
the THD of the load current.
8-9. An inverter that produces the type of output shown in Fig. 8-5a is used to supply
an RL series load with R 10 and L 35 mH. The dc input voltage is 200 V
and the output frequency is 60 Hz. (a) Determine the rms value of the
fundamental frequency of the load current when 0. (b) If the output
fundamental frequency is lowered to 30 Hz, determine the value of required to
keep the rms current at the fundamental frequency at the same value of part (a).
8-10. Use the PSpice circuit of Fig. 8-7a to verify that (a) the waveform of Fig. 8-5a
with 30 contains no third harmonic frequency and (b) the waveform of
Fig. 8-5a with 18 contains no fifth harmonic.
8-11. (a) Determine the value of that will eliminate the seventh harmonic from the
inverter output of Fig. 8-5a. (b) Verify your answer with a PSpice simulation.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 385
Problems 385
8-12. Determine the rms value of the notched waveform to eliminate the third and fifth
harmonics in Fig. 8-6.
8-13. Use PSpice to verify that the notched waveform of Fig. 8-6c contains no third or
fifth harmonic. What are the magnitudes of the fundamental frequency and the
first four nonzero harmonics? (The piecewise linear type of source may be useful.)
Multilevel Inverters
8-14. For a multilevel inverter having three separate dc sources of 48 V each, 1 15,
2 25, and 3 55. (a) Sketch the output voltage waveform. (b) Determine
the Fourier coefficients through n 9. (c) Determine the modulation index Mi.
8-15. For a three-source multilevel inverter, select values of 1, 2, and 3 such that the
third harmonic frequency (n 3) in the output voltage waveform is eliminated.
Determine the modulation index Mi for your selection.
8-16. The five-source multilevel inverter of Fig. 8-11 has 1 16.73, 2 26.64,
3 46.00, 4 60.69, and 5 62.69. Determine which harmonics will be
eliminated from the output voltage. Determine the amplitude of the fundamental-
frequency output voltage.
8-17. The concept of the two-source multilevel inverters of Figs. 8-9 and 8-11 is
extended to have three independent sources and H bridges and three delay angles
1, 2, and 3. Sketch the voltages at the output of each bridge of a three-source
multilevel converter such that the average power from each source is the same.
Pulse-Width-Modulated Inverters
8-18. The dc source supplying an inverter with a bipolar PWM output is 96 V. The load
is an RL series combination with R 32 and L 24 mH. The output has a
fundamental frequency of 60 Hz. (a) Specify the amplitude modulation ratio to
provide a 54-V rms fundamental frequency output. (b) If the frequency
modulation ratio is 17, determine the total harmonic distortion of the load current.
8-19. The dc source supplying an inverter with a bipolar PWM output is 250 V. The
load is an RL series combination with R 20 and L 50 mH. The output has
a fundamental frequency of 60 Hz. (a) Specify the amplitude modulation ratio to
provide a 160-V rms fundamental frequency output. (b) If the frequency
modulation ratio is 31, determine the total harmonic distortion of the load current.
8-20. Use PSpice to verify that the design in Example 8-9 meets the THD
specifications.
8-21. Design an inverter that has a PWM output across an RL series load with R 10
and L 20 mH. The fundamental frequency of the output voltage must be 120 V
rms at 60 Hz, and the total harmonic distortion of the load current must be less
than 8 percent. Specify the dc input voltage, the amplitude modulation ratio ma,
and the switching frequency (carrier frequency). Verify the validity of your
design with a PSpice simulation.
8-22. Design an inverter that has a PWM output across an RL series load with R 30
and L 25 mH. The fundamental frequency of the output voltage must be 100 V
rms at 60 Hz, and the total harmonic distortion of the load current must be less
than 10 percent. Specify the dc input voltage, the amplitude modulation ratio ma,
and the switching frequency (carrier frequency). Verify the validity of your
design with a PSpice simulation.
har80679_ch08_331-386.qxd 12/16/09 2:55 PM Page 386
8-23. Pulse-width modulation is used to provide a 60-Hz voltage across a series RL

load with R 12 and L 20 mH. The dc supply voltage is 150 V. The
amplitude of the 60-Hz voltage is to be 120 V. Use PSpice to obtain the current
waveform in the load and the THD of the current waveform in the load. Use
(a) bipolar PWM with mf 21, (b) bipolar PWM with mf 41, and (c) unipolar
PWM with mf 10.
Three-Phase Inverters
8-24. A six-step three-phase inverter has a 250-V dc source and an output frequency
of 60 Hz. A balanced Y-connected load consists of a series 25- resistance and
20-mH inductance in each phase. Determine (a) the rms value of the 60-Hz
component of load current and (b) the THD of the load current.
8-25. A six-step three-phase inverter has a 400-V dc source and an output frequency
that varies from 25 to 100 Hz. The load is a Y connection with a series 10-
resistance and 30-mH inductance in each phase. (a) Determine the range of the
rms value of the fundamental-frequency component of load current as the
frequency is varied. (b) What is the effect of varying frequency on the THD of
the load current and the THD of the line-to-neutral voltage?
8-26. A six-step three-phase inverter has an adjustable dc input. The load is a balanced
Y connection with a series RL combination in each phase, with R 5 and
L 50 mH. The output frequency is to be varied between 30 and 60 Hz.
(a) Determine the range of the dc input voltage required to maintain the
fundamental-frequency component of current at 10 A rms. (b) Use PSpice to
determine the THD of load current in each case. Determine the peak current and
rms load current for each case.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 387
C H A P T E R 9
Resonant Converters
9.1 INTRODUCTION
Imperfect switching is a major contributor to power loss in converters, as dis-
cussed in Chap. 6. Switching devices absorb power when they turn on or off if
they go through a transition when both voltage and current are nonzero. As the
switching frequency increases, these transitions occur more often and the aver-
age power loss in the device increases. High switching frequencies are otherwise
desirable because of the reduced size of filter components and transformers,
which reduces the size and weight of the converter.
In resonant switching circuits, switching takes place when voltage and/or
current is zero, thus avoiding simultaneous transitions of voltage and current
and thereby eliminating switching losses. This type of switching is called soft
switching, as opposed to hard switching in circuits such as the buck converter.
Resonant converters include resonant switch converters, load resonant convert-
ers, and resonant dc link converters. This chapter introduces the basic concept
of the resonant converter and gives a few examples.
9.2 A RESONANT SWITCH CONVERTER:

ZERO-CURRENT SWITCHING
Basic Operation
One method for taking advantage of the oscillations caused by an LC circuit for
reducing the switching losses in a dc-dc converter is shown in the circuit of
Fig. 9-1a. This circuit is similar to the buck converter described in Chap. 6. The
current in the output inductor Lo is assumed to be ripple-free and equal to the load
387
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 388
388 C H A P T E R 9 Resonant Converters
Lr Lo Io
iL iC Io
+ + +
Vs Cr vC Co RL Vo
− − −
id
(a)
+ vL = Vs −
iL iL iC
+ + +
Vs Io Vs vC Io
− − −
id
(b) (c)
iC = −Io
+ + +
Vs vC Io Vs Io
−
− −
id
(d ) (e)
Figure 9-1 (a) A resonant converter with zero-current switching; (b) Switch closed and diode
on (0 ⬍ t ⬍ t1); (c) Switch closed and diode off (t1 ⬍ t ⬍ t2); (d) Switch open and diode off
(t2 ⬍ t ⬍ t3); (e) Switch open and diode on (t3 ⬍ t ⬍ T ); ( f ) Waveforms; (g) Normalized
output vs. switching frequency with r ⫽ RL /Z0 as a parameter. © 1992 IEEE, B.K. Bose,
Modern Power Electronics: Evolution, Technology, and Applications. Reprinted with
permission.
current Io. When the switch is open, the diode is forward-biased to carry the out-
put inductor current, and the voltage across Cr is zero. When the switch closes,
the diode initially remains forward-biased to carry Io, and the voltage across Lr is
the same as the source voltage Vs (Fig. 9-1b). The current in Lr increases linearly,
and the diode remains forward-biased while iL is less than Io. When iL reaches Io,
the diode turns off, and the equivalent circuit is that of Fig. 9-1c. If Io is a con-
stant, the load appears as a current source, and the underdamped LC circuit oscil-
lates. Consequently, iL returns to zero and remains there, assuming the switch is
unidirectional. The switch is turned off after the current reaches zero, resulting in
zero-current switching and no switching power loss.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 389
9.2 A Resonant Switch Converter: Zero-Current Switching 389
iL
Io
0 t1 t2 t3 T
vC
0 t1 t2 t3 T
Switch Closed Open

(f )
10.0 5.0 2.0

1.00 1.0
0.80
0.60
r = 0.5
Vo /Vs
0.40
0.20
0.00 0.20 0.40 0.60 0.80 1.00

fs /f0
(g)
After the current in the switch reaches zero, the positive capacitor voltage
keeps the diode reverse-biased, so load current Io flows through Cr, with ic = ⫺Io
(Fig. 9-1d ). If Io is constant, the capacitor voltage decreases linearly. When the
capacitor voltage reaches zero, the diode becomes forward-biased to carry Io
(Fig. 9-1e). The circuit is then back at the starting point. The analysis for each
time interval is given next.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 390
Analysis for 0 £ t £ t1 The switch is closed at t ⫽ 0, the diode is on, and the
voltage across Lr is Vs (Fig. 9-1b). The current in Lr is initially zero and is
expressed as
t
1 Vs
i L(t) ⫽ Vs dl ⫽ t (9-1)
Lr 3 Lr
0
At t ⫽ t1, iL reaches Io, and the diode turns off. Solving for t1,
Vs
i L(t 1) ⫽ Io ⫽ t (9-2)
Lr 1
Io L r
or t1 ⫽ (9-3)
Vs
Capacitor voltage is zero in this interval.
Analysis for t1 £ t £ t2 (Fig. 9-1c) When the diode turns off at t ⫽ t1, the cir-
cuit is equivalent to that in Fig. 9-1c. In the circuit of Fig. 9-1c, these equations
apply:
di L(t)
vC (t) ⫽ Vs ⫺ L r (9-4)
dt
i C (t) ⫽ i L(t) ⫺ Io (9-5)
Differentiating Eq. (9-4) and using the voltage-current relationship for the
capacitor,
dvC (t) d 2i L(t) i C (t)
⫽ ⫺ Lr ⫽ (9-6)
dt dt 2 Cr
Substituting for iC using Eq. (9-5),
d 2i L(t) Io ⫺ i L(t)
Lr ⫽ (9-7)
dt 2 Cr
d 2i L(t) i L(t) I
or ⫹ ⫽ o (9-8)
dt 2 L rCr L rCr
The solution to the preceding equation with the initial condition iL(t1) ⫽ Io is
Vs
i L(t) ⫽ Io ⫹ sin ␻0(t ⫺ t 1) (9-9)
Zo
where Z0 is the characteristic impedance
Lr
Z0 ⫽ (9-10)
A Cr
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and ␻0 is the frequency of oscillation
1
␻0 ⫽ (9-11)
2L rCr
Equation (9-9) is valid until iL reaches zero at t ⫽ t2. Solving for the time inter-
val t2 ⫺ t1 when the oscillation occurs,
1 ⫺1 ⫺Io Z0
t2 ⫺ t1 ⫽ sin a b (9-12)
␻0 Vs
1 I Z
t2 ⫺ t1 ⫽ csin⫺1 a o 0 b ⫹ ␲ d (9-13)
␻0 Vs
Solving for capacitor voltage by substituting iL from Eq. (9-9) into Eq. (9-4) gives
vC (t) ⫽ Vs{1 ⫺ cos[␻0(t ⫺ t 1)]} (9-14)
which is also valid until t ⫽ t2. Maximum capacitor voltage is therefore 2Vs.
Analysis for t2 £ t £ t3 After the inductor current reaches zero at t2, switch cur-
rent is zero and it can be opened without power loss. The equivalent circuit is
shown in Fig. 9-1d. The diode is off because vC ⬎ 0. Capacitor current is ⫺Io,
resulting in a linearly decreasing capacitor voltage expressed as
t
1 I
vC (t) ⫽ ⫺ Io dl ⫹ vC (t 2) ⫽ o (t 2 ⫺ t) ⫹ vC (t 2) (9-15)
Cr 3 Cr
t2
Equation (9-15) is valid until the capacitor voltage reaches zero and the diode turns
on. Letting the time at which the capacitor voltage reaches zero be t3, Eq. (9-15)
gives an expression for the time interval t3 ⫺ t2:
CrvC (t 2) CrVs{1 ⫺ cos[␻0(t 2 ⫺ t 1)]}

t3 ⫺ t2 ⫽ ⫽ (9-16)
Io Io
where vC (t2) is obtained from Eq. (9-14).

Analysis for t3 £ t £ T In this time interval, iL is zero, the switch is open, the
diode is on to carry Io, and vC ⫽ 0 (Fig. 9-1e). The duration of this interval is the
difference between the switching period T and the other time intervals, which are
determined from other circuit parameters.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 392
Output Voltage
Output voltage can be determined from energy balance. Energy supplied by the
source is equal to energy absorbed by the load during a switching period. Energy
supplied by the source in one period is
T T
Ws ⫽ ps(t) d(t) ⫽ Vs i L(t) dt (9-17)

3 3
0 0
Energy absorbed by the load is

T
Vo Io
Wo ⫽ po(t) dt ⫽ Vo IoT ⫽ (9-18)
3 fs
0
where fs is the switching frequency. From Eqs. (9-1) and (9-9),

T t1 t2
Vs t V
i L(t) dt ⫽ dt ⫹ b Io ⫹ s sin[␻0 (t ⫺ t 1)] r dt (9-19)
3 3 Lr 3 Z0
0 0 t1
Using Ws ⫽ Wo and solving for Vo using Eqs. (9-17) to (9-19),
t1 VsCr
Vo ⫽ Vs fs a ⫹ (t 2 ⫺ t 1) ⫹ {1 ⫺ cos[␻0 (t 2 ⫺ t 1)]}b (9-20)
2 Io
Using Eq. (9-16), output voltage can be expressed in terms of the time intervals
for each circuit condition:
t1
Vo ⫽ Vs fs c ⫹ (t 2 ⫺ t 1) ⫹ (t 3 ⫺ t 2) d (9-21)
2
where the time intervals are determined from Eqs. (9-3), (9-13), and (9-16).
Equation (9-21) shows that the output voltage is a function of the switching
frequency. Increasing fs increases Vo. The switching period must be greater than t3,
and output voltage is less than input voltage, as is the case for the buck converter
of Chap. 6. Note that the time intervals are a function of output current Io, so out-
put voltage for this circuit is load-dependent. When the load is changed, the
switching frequency must be adjusted to maintain a constant output voltage.
Figure 9-1g shows the relationship between output voltage and switching fre-
quency. The quantity r ⫽ RL/Z0 is used as a parameter where RL is the load resis-
tance and Z0 is defined in Eq. (9-10).
A diode placed in antiparallel with the switch in Fig. 9-1a creates a resonant
switch converter which includes negative inductor current. For that circuit,
Vo/Vs is nearly a linear function of switching frequency independent of load
(that is, Vo/Vs ⫽ fs/f0).
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 393
The resonant switch converter with zero-current switching has theoretically

zero switching losses. However, junction capacitance in switching devices stores
energy which is dissipated in the device, resulting in small losses.
Note that output voltage is the average of the capacitor voltage vc, yielding
an alternate method of deriving Eq. (9-21).
EXAMPLE 9-1
Resonant Switch DC-DC Converter: Zero-Current Switching

In the circuit of Fig. 9-1a,
Vs ⫽ 12 V
Cr ⫽ 0.1 ␮F
Lr ⫽ 10 ␮H
Io ⫽ 1 A
fs ⫽ 100 kHz
(a) Determine the output voltage of the converter. (b) Determine the peak current
in Lr and the peak voltage across Cr. (c) What is the required switching frequency
to produce an output voltage of 6 V for the same load current? (d ) Determine the
maximum switching frequency. (e) If the load resistance is changed to 20 ⍀,
determine the switching frequency required to produce an output voltage of 8 V.
■ Solution
(a) Using the given circuit parameters,
1 1 6
␻0 ⫽ ⫽ ⫽ 10 rad/s
2L rCr 210 (10)⫺6 (0.1) (10)⫺6
Lr 10 (10)⫺6
Z0 ⫽ ⫽ ⫽ 10 Æ
A Cr A 0.1(10)⫺6
Output voltage is determined from Eq. (9-21). The time t1 is determined from Eq. (9-3):
Io L r (1)(10)(10)⫺6
t1 ⫽ ⫽ ⫽ 0.833 ␮s
Vs 12
From Eq. (9-13),

1 1 (1)(10)
csin⫺1 a
Io Z0
t2 ⫺ t1 ⫽ b ⫹ ␲ d ⫽ 6 csin⫺1 ⫹ ␲ d ⫽ 4.13 ␮s
␻0 Vs 10 12
From Eq. (9-16),

CrVs
t3 ⫺ t2 ⫽ {1 ⫺ cos[␻0 (t 2 ⫺ t 1)]}
Io
(0.1)(10)⫺6 (12)
⫽ {1 ⫺ cos[10 6 (4.13)(10)⫺6]} ⫽ 1.86 ␮s
1
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 394
Output voltage from Eq. (9-21) is then
Vo ⫽ Vs fs c
t1
⫹ (t 2 ⫺ t 1) ⫹ (t 3 ⫺ t 2) d
2
0.833
⫽ (12)(100)(10 5) a ⫹ 4.13 ⫹ 1.86b (10 ⫺6) ⫽ 7.69 V
2
(b) Peak current in Lr is determined from Eq. (9-9).
Vs 12
IL,peak ⫽ Io ⫹ ⫽ 1 ⫹ ⫽ 2.2 A
Z0 10
Peak voltage across Cr is determined from Eq. (9-14):
VC,peak ⫽ 2Vs ⫽ 2(12) ⫽ 24 V
(c) Since output voltage is proportional to frequency [Eq. (9-21)] if Io remains

unchanged, the required switching frequency for a 6-V output is
6V
fs ⫽ 100 kHz a b ⫽ 78 kHz
7.69 V
(d) Maximum switching frequency for this circuit occurs when the interval T ⫺ t3 is
zero. Time t3 ⫽ t1 ⫹ (t2 ⫺ t1) ⫹ (t3 ⫺ t2) ⫽ (0.833 ⫹ 4.13 ⫹ 1.86) ␮s ⫽ 6.82 ␮s,
resulting in
1 1 1
fs,max ⫽ ⫽ ⫽ ⫽ 146 kHz
Tmin t 3 (6.82)(10 ⫺6)
(e) The graph of Fig. 9-1g can be used to estimate the required switching frequency to
obtain an output of 8 V with the load at 20 ⍀. With Vo/Vs ⫽ 8/12 ⫽ 0.67, the curve
for the parameter r ⫽ RL /Z0 ⫽ 20/10 ⫽ 2 gives fs /f0 L 0.45. The switching
frequency is fs ⫽ 0.45f0 ⫽ 0.45(␻0/2␲) ⫽ 0.45(10)6/2␲ ⫽ 71.7 kHz. The method
used in part (a) of this problem can be used to verify the results. Note that Io is now
Vo/RL ⫽ 8/20 ⫽ 0.4 A.
9.3 A RESONANT SWITCH CONVERTER:

ZERO-VOLTAGE SWITCHING
Basic Operation
The circuit of Fig. 9-2a shows a method for using the oscillations of an LC cir-
cuit for switching at zero voltage. The analysis assumes that the output filter pro-
duces a ripple-free current Io in Lo. Beginning with the switch closed, the current
in the switch and in Lr is Io, the currents in D1 and Ds are zero, and the voltage
across Cr and the switch is zero.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 395
9.3 A Resonant Switch Converter: Zero-Voltage Switching 395
S Lr Lo
Ds iL Io Io +
+ +
Vs Cr D1 vx Co RL Vo
+ v - -
-
C
-
(a)
Cr Lr Cr Lr iL
+ v - + v -
C C
+ + + +
Vs vx Io Vs vx = 0 Io
- -
- -
(b) (c)
Lr iL Lr iL = Io
+ v =V - + v =0 -
L s L
+ +
Vs vx = 0 Io Vs vx = Vs Io
- -
(d) (e)
Figure 9-2 (a) A resonant converter with zero-voltage switching; (b) Switch open and D1 off
(0 < t < t1); (c) Switch open and D1 on (t1 < t < t2). (d ) Switch closed and D1 on (t2 < t < t3);
(e) Switch closed and D1 off (t3 < t < T ); ( f ) Waveforms (g) Normalized output vs.
switching frequency with r ⫽ RL/Z0 as a parameter. © 1992 IEEE, B.K. Bose, Modern Power
Electronics: Evolution, Technology, and Applications. Reprinted with permission.
The switch is opened (with zero voltage across it), and iL ⫽ Io flows through
the capacitor Cr, causing vC to increase linearly (Fig. 9-2b). When vC reaches the
source voltage Vs, the diode D1 becomes forward-biased, in effect forming a series
circuit with Vs, Cr, and Lr as shown in Fig. 9-2c. At this time, iL and vC in this
underdamped series circuit begin to oscillate.
When vC returns to zero, diode Ds turns on to carry iL, which is negative
(Fig. 9-2d). The voltage across Lr is Vs, causing iL to increase linearly. The
switch should be closed just after Ds turns on for zero-voltage turn-on. When iL
becomes positive, Ds turns off and iL is carried by the switch. When iL reaches
Io, D1 turns off, and circuit conditions are back at the starting point. The analysis
for each circuit condition is given next.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 396
Vs + IoZ0
vC
Vs
0 t1 t2 t3 T
Io
iL
vx
Vs
0 t1 t2 t3 T
Switch Open Closed

0 t1 t2 t3 T
(f)
1.00
0.90
0.80
0.80
0.60
0.50
Vo /Vs
0.40
0.20
0.20
r = 0.10
0.00
0.00 0.20 0.40 0.60 0.80 1.00
fs /fo
(g)

har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 397
Analysis for 0 £ t £ t1 The switch is opened at t ⫽ 0. The capacitor current is

then Io (Fig. 9-2b), causing the capacitor voltage, initially zero, to increase lin-
early. The voltage across Cr is
t
1 Io
vC (t) ⫽ Io dl ⫽ t (9-22)
Cr 3 Cr
0
The voltage across Lr is zero because inductor current is Io, which is assumed to
be constant. The voltage at the filter input vx is
Io
vx (t) ⫽ Vs ⫺ vC (t) ⫽ Vs ⫺ t (9-23)
Cr
which is a linearly decreasing function beginning at Vs. At t ⫽ t1, vx ⫽ 0 and the

diode turns on. Solving the preceding equation for t1,
Vs Cr
t1 ⫽ (9-24)
Io
Equation (9-23) can then be expressed as
t
vx(t) ⫽ Vs a 1 ⫺ b (9-25)
t1
Analysis for t1 £ t £ t2 Diode D1 is forward-biased and has 0 V across it, and the
equivalent circuit is shown in Fig. 9-2c. Kirchhoff’s voltage law is expressed as
di L(t)
Lr ⫹ vC (t) ⫽ Vs (9-26)
dt
Differentiating,
d 2i L(t) dvC (t)

Lr ⫹ ⫽0 (9-27)
dt 2 dt
Capacitor current is related to voltage by
dvC (t) i C (t)

⫽ (9-28)
dt Cr
Since inductor and capacitor currents are the same in this time interval, Eq. (9-27)
can be expressed as
d 2i L(t) i L(t)
⫹ ⫽0 (9-29)
dt 2 L rCr
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 398
Solving the preceding equation for iL by using the initial condition iL(t1) ⫽ Io,
i L(t) ⫽ Io cos[␻0(t ⫺ t 1)] (9-30)
where
1
␻0 ⫽ (9-31)
2L rCr
Capacitor voltage is expressed as
t t
1 1
vC (t) ⫽ i C (l) dl ⫹ vC (t 1) ⫽ I cos[␻0 (l ⫺ t 1)] dl ⫹ Vs
Cr 3 Cr 3 o
t1 t1
which simplifies to
vC (t) ⫽ Vs ⫹ Io Z0 sin[␻0 (t ⫺ t 1)] (9-32)
where
Lr
Z0 ⫽ (9-33)
A Cr
Note that the peak capacitor voltage is
Lr
VC,peak ⫽ Vs ⫹ Io Z0 ⫽ Vs ⫹ Io (9-34)
A Cr
which is also the maximum reverse voltage across diode Ds and is larger than the
source voltage.
With diode D1 forward-biased,
vx ⫽ 0 (9-35)
The diode Ds across Cr prevents vC from going negative, so Eq. (9-32) is valid for
vC ⬎ 0. Solving Eq. (9-32) for the time t ⫽ t2 when vC returns to zero,
1 ⫺Vs
t2 ⫽ c sin⫺1 a b d ⫹ t1
␻0 Io Z 0
1 V
t2 ⫽ c sin⫺1 a s b ⫹ ␲ d ⫹ t 1 (9-36)
␻0 Io Z0
At t ⫽ t2, diode Ds turns on.

har80679_ch09_387-430.qxd 12/17/09 2:57 PM Page 399
Analysis for t2 £ t £ t3 (Fig. 9-2d) After t2, both diodes are forward-biased
(Fig. 9-2d), the voltage across Lr is Vs, and iL increases linearly until it reaches
Io at t3. The switch is reclosed just after t2 when vC ⫽ 0 (zero-voltage turn-on)
and the diode is on to carry a negative iL. The current iL in the interval from t2 to
t3 is expressed as
t
1 V
i L(t) ⫽ Vs dl ⫹ i L(t 2) ⫽ s (t ⫺ t 2) ⫹ Io cos[␻0 (t 2 ⫺ t 1)] (9-37)
Lr 3 Lr
t2
where iL(t2) is from Eq. (9-30). Current at t3 is Io:

Vs
i L(t 3) ⫽ Io ⫽ (t ⫺ t 2) ⫹ Io cos[␻0(t 2 ⫺ t 1)] (9-38)
Lr 3
Solving for t3,
L r Io
t3 ⫽ a b {1 ⫺ cos[␻0(t 2 ⫺ t 1)]} ⫹ t 2 (9-39)
Vs
Voltage vx is zero in this interval:
vx ⫽ 0 (9-40)
At t ⫽ t3, diode D1 turns on.

Analysis for t3 £ t £ T In this interval, the switch is closed, both diodes are off,
the current in the switch is Io, and
vx ⫽ Vs (9-41)
The circuit remains in this condition until the switch is reopened. The time inter-
val T ⫺ t3 is determined by the switching frequency of the circuit. All other time
intervals are determined by other circuit parameters.
Output Voltage
The voltage vx(t) at the input of the output filter is shown in Fig. 9-2f. Summariz-
ing Eqs. (9-25), (9-35), (9-40), and (9-41),
t
Vs a1 ⫺ b 0 < t < t1
t1
vx(t) ⫽ d (9-42)
0 t1 < t < t3
Vs t3 < t < T
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 400
The output voltage is the average of vx(t). Output voltage is

T t1 T
1 1 t
Vo ⫽ vx dt ⫽ C Vs a 1 ⫺ b dt ⫹ Vs dt S (9-43)
T3 T 3 t1 3
0 0 t3
Vs t 1
⫽ c ⫹ (T ⫺ t 3) d
T 2
Using fs ⫽ 1/T,
t1
Vo ⫽ Vs c 1 ⫺ fs a t 3 ⫺ bd (9-44)
2
Times t1, and t3 in the preceding equation are determined from the circuit para-
meters as described by Eqs. (9-24), (9-36), and (9-39). The output voltage is
controlled by changing the switching frequency. The time interval when the
switch is open is fixed, and the time interval when the switch is closed is varied.
Times t1 and t3 are determined in part by the load current Io, so output voltage is
a function of load. Increasing the switching frequency decreases the time inter-
val T ⫺ t3 and thus reduces the output voltage. Normalized output voltage vs.
switching frequency with the parameter r ⫽ RL/Z0 is shown in the graph in
Fig. 9-2g. Output voltage is less than input voltage, as was the case for the buck
converter in Chap. 6.
EXAMPLE 9-2
Resonant Switch Converter: Zero-Voltage Switching

In the circuit of Fig. 9-2a,
Vs ⫽ 20 V
Lr ⫽ 1 ␮H
Cr ⫽ 0.047 ␮F
Io ⫽ 5 A
(a) Determine the switching frequency such that the output voltage is 10 V.
(b) Determine the peak voltage across Ds when it is reverse-biased.
■ Solution
(a) From the circuit parameters,
1
␻0 ⫽ ⫽ 4.61(10 6) rad/s
2(10) (0.047)(10)⫺6
⫺6
Lr 10 ⫺6
Z0 ⫽ ⫽ ⫽ 4.61 Æ
A Cr A 0.047(10 ⫺6)
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 401
9.4 The Series Resonant Inverter 401
Using Eq. (9-24) to solve for t1,

VsCr (20)(0.047)(10 ⫺6)
t1 ⫽ ⫽ ⫽ 0.188 ␮s
Io 5
From Eq. (9-36),
1
c sin⫺1 a
Vs
t2 ⫽ b ⫹ ␲ d ⫹ t1
␻0 Io 2L r /Cr
1 20
⫽ c sin⫺1 ⫹ ␲ d ⫹ 0.188 ␮s ⫽ 1.10 ␮s
4.61(10 6) (5)(4.61)
From Eq. (9-39),
t3 ⫽ a
L r Io
b{1 ⫺ cos[␻0 (t 2 ⫺ t 1)]} ⫹ t 2
Vs
10 ⫺6(5)
⫽a b{1 ⫺ cos[(4.61)(10 6)(1.10 ⫺ 0.188)(10 ⫺6)]} ⫹ 1.10 ␮s ⫽ 1.47 ␮s
20
Equation (9-44) is used to determine the proper switching frequency,
Vo ⫽ Vs c1 ⫺ fs a t 3 ⫺
t1
bd
2
0.188
10 ⫽ 20 c1 ⫺ fs a 1.47 ⫺ b(10 ⫺6) d
2
fs ⫽ 363 kHz
(b) Peak reverse voltage across D s is the same as peak capacitor voltage. From
Eq. (9-25),
Lr
VDs,peak ⫽ VC,peak ⫽ Vo ⫹ Io ⫽ 20 ⫹ (5)(4.61) ⫽ 33 V
A Cr
9.4 THE SERIES RESONANT INVERTER

The series resonant inverter (dc-to-ac converter) of Fig. 9-3a is one application
of resonant converters. In a series resonant inverter, an inductor and a capacitor
are placed in series with a load resistor. The switches produce a square wave volt-
age, and the inductor-capacitor combination is selected such that the resonant
frequency is the same as the switching frequency.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 402
+ L C
Vdc + vi
- +
- vo
-
(a)
1
jwL jwC
+ +
Vi Vo
- -
(b)
Normalized Output for Resonant Inverter

1.0
0.8
0.6
Vo Q=1
Vi
0.4
0.2 Q=2
Q=3
Q = 10
0.0
0.4 0.8 1.2 1.6 2.0
ws fs
=
w0 f0
(c)
Figure 9-3 (a) A series resonant inverter; (b) Phasor equivalent of a series RLC Circuit;
(c) Normalized frequency response.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 403
The analysis begins by considering the frequency response of the RLC cir-
cuit of Fig. 9-3b. The input and output voltage amplitudes are related by
Vo R 1
⫽ ⫽ (9-45)
Vi 2
2R ⫹ (␻L ⫺ (1>␻C ))2
21 ⫹ ((␻L>R) ⫺ (1>␻RC ))2
Resonance is at the frequency
1
␻0 ⫽ (9-46)
2LC
or
1
f0 ⫽ (9-47)
2␲ 2LC
At resonance, the impedances of the inductance and capacitance cancel, and
the load appears as a resistance. If the bridge output is a square wave at fre-
quency f0, the LC combination acts as a filter, passing the fundamental frequency
and attenuating the harmonics. If the third and higher harmonics of the square
wave bridge output are effectively removed, the voltage across the load resistor
is essentially a sinusoid at the square wave’s fundamental frequency.
The amplitude of the fundamental frequency of a square wave voltage of
⫾Vdc is
4Vdc
V1 ⫽ (9-48)
␲
The frequency response of the filter could be expressed in terms of bandwidth,
which is also characterized by the quality factor Q.
␻0 L 1
Q⫽ ⫽ (9-49)
R ␻0 RC
Equation (9-45) can be expressed in terms of ␻0 and Q:
Vo 1
⫽ (9-50)
Vi 21 ⫹ Q ((␻>␻0) ⫺ (␻0>␻))2
2
The normalized frequency response with Q as a parameter is shown in Fig. 9-3c.

The total harmonic distortion (THD, as defined in Chap. 2) of the voltage across
the load resistor is reduced by increasing the Q of the filter. Increasing induc-
tance and reducing capacitance increase Q.
Switching Losses
An important feature of the resonant inverter is that switch losses are reduced
over that of the inverters discussed in Chap. 8. If switching is at the resonant
frequency and the Q of the circuit is high, the switches operate when the load
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 404
current is at or near zero. This is significant because the power absorbed by the
switches is less than in the nonresonant inverter.
Amplitude Control
If the frequency of the load voltage is not critical, the amplitude of the funda-
mental frequency across the load resistor can be controlled by shifting the
switching frequency off of resonance. Power absorbed by the load resistor is thus
controlled by the switching frequency. Induction heating is an application.
The switching frequency should be shifted higher than resonance rather than
lower when controlling the output. Higher switching frequencies moves the har-
monics of the square wave higher, increasing the filter’s effectiveness in remov-
ing them. Conversely, shifting the frequency lower than resonance moves the
harmonics, particularly the third harmonic, closer to resonance and increases
their amplitudes in the output.
EXAMPLE 9-3
A Resonant Inverter
A 10-⍀ resistive load requires a 1000-Hz, 50-V rms sinusoidal voltage. The THD of the load
voltage must be no more than 5 percent. An adjustable dc source is available. (a) Design
an inverter for this application. (b) Determine the maximum voltage across the capacitor.
(c) Verify the design with a PSpice simulation.
■ Solution
(a) The full-bridge converter of Fig. 9-3a with 1000-Hz square wave switching and
series resonant LC filter is selected for this design. The amplitude of a 50-V rms
sinusoidal voltage is 22(50) ⫽ 70.7 V. The required dc input voltage is determined
from Eq. (9-48).
4Vdc
70.7 ⫽
␲
Vdc ⫽ 55.5 V
The resonant frequency of the filter must be 1000 Hz, establishing the LC product. The
Q of the filter and the THD limit are used to determine the values of L and C. The third
harmonic of the square wave is the largest and will be the least attenuated by the filter.
Estimating the THD from the third harmonic,
2
a Vn
A nZ1 V
THD ⫽ L 3 (9-51)
V1 V1
where V1 and V3 are the amplitudes of the fundamental and third harmonic frequencies,
respectively, across the load. Using the foregoing approximation, the amplitude of the
third harmonic of the load voltage must be at most
V3 < (THD)(V1) ⫽ (0.05)(70.7) ⫽ 3.54 V

har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 405
For the square wave, V3 ⫽ V1/3 ⫽ 70.7/3. Using Eq. (9-50), Q is determined from
the magnitude of the third harmonic output with the third harmonic input, 70.7/3, at
␻ ⫽ 3␻0.
Vo,3 3.54 1
⫽ ⫽
Vi,3 70.7/3 A 1 ⫹ Q ((3␻0>␻0) ⫺ (␻0>3␻0))2
2
Solving the preceding equation for Q results in Q ⫽ 2.47. Using Eq. (9-49),
QR (2.47)(10)
L⫽ ⫽ ⫽ 3.93 mH
␻0 2␲(1000)
1 1
C⫽ ⫽ ⫽ 6.44 ␮F
Q␻0 R (2.47)(2␲)(1000)(10)
2
Power delivered to the load resistor at the fundamental frequency is Vrms /R ⫽ 502/10 ⫽
2
250 W. Power delivered to the load at the third harmonic is (2.5 )/10 ⫽ 0.63 W,
showing that power at the harmonic frequencies is negligible.
(b) Voltage across the capacitor is estimated from phasor analysis at the fundamental
frequency:
VC ⫽ ` `⫽ 1 ⫽
I V /R 70.7/10
⫽ 175 V
j␻0C ␻0C (2␲)(1000)(6.44)(10 ⫺6)
At resonance, the inductor has the same impedance magnitude as the capacitor, so its
voltage is also 175 V. The inductor and capacitor voltages would be larger if Q were
increased. Note that these voltages are larger than the output or source voltage.
(c) One method of doing a PSpice simulation is to use a square wave voltage as the input to
the RLC circuit. This assumes that the switching is ideal, but it is a good starting point to
verify that the design meets the specifications. The circuit is shown in Fig. 9-4a.
Output begins after three periods (3 ms) to allow steady-state conditions to be
reached. The Probe output showing input and output voltages is seen in Fig. 9-4b,
and a Fourier analysis (FFT) from Probe is shown in Fig. 9-4c. The amplitudes of
the fundamental frequency and third harmonic are as predicted in part (a). The
Fourier analysis for the output voltage is as follows:
FOURIER COMPONENTS OF TRANSIENT RESPONSE V(OUTPUT)
DC COMPONENT ⫽ ⫺2.770561E-02

1 1.000E+03 7.056E+01 1.000E+00 1.079E-01 0.000E+00
2 2.000E+03 3.404E-02 4.825E-04 3.771E+01 3.749E+01
3 3.000E+03 3.528E+00 5.000E-02 -8.113E+01 -8.145E+01
4 4.000E+03 1.134E-02 1.608E-04 -5.983E+00 -6.414E+00
5 5.000E+03 1.186E+00 1.681E-02 -8.480E+01 -8.533E+01
6 6.000E+03 8.246E-03 1.169E-04 -2.894E+01 -2.959E+01
7 7.000E+03 5.943E-01 8.423E-03 -8.609E+01 -8.684E+01
8 8.000E+03 7.232E-03 1.025E-04 -4.302E+01 -4.388E+01
9 9.000E+03 3.572E-01 5.062E-03 -8.671E+01 -8.768E+01
TOTAL HARMONIC DISTORTION ⫽ 5.365782E+00 PERCENT

har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 406
L1 C1
input 1 2 output
V1 = –55.5 3.93m 6.44u
V2 = 55.5 Vs R1
TD = 0 + 10
TR = 1n -
TF = 1n
PW = {0.5/FS}
PER = {1/FS}
PARAMETERS:
FS = 1000
(a)
100 V
vo
vi
0V
–100 V
3.0 ms 3.5 ms 4.0 ms 4.5 ms 5.0 ms
V(INPUT) V(OUTPUT)
Time
(b)
77.5 V
(1.0000K, 70.805) FOURIER ANALYSIS
60.0 V
40.0 V
(3.0000K, 23.606)
20.0 V
(3.0000K, 3.5261)
0V
0 Hz 1.0 KHz 2.0 KHz 3.0 KHz 4.0 KHz 5.0 KHz
V(INPUT) V(OUTPUT)
Frequency
(c)
Figure 9-4 (a) PSpice circuit for Example 9-3; (b) Input and output voltages;
(c) Fourier analysis.
406
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 407
9.5 The Series Resonant DC-DC Converter 407
The output file shows that the THD is 5.37 percent, slightly larger than the 5 percent
specification. Frequencies larger than the third harmonic were neglected in the design
and have a small effect on the THD. A slight increase in L and corresponding decrease
in C would increase the Q of the circuit and reduce the THD to compensate for the
approximation. Note that switching occurs when the current is close to zero.
9.5 THE SERIES RESONANT DC-DC CONVERTER

Basic Operation
The upper switching frequency limit on dc-dc converters in Chaps. 6 and 7 is
largely due to the switching losses, which increase with frequency. A method for
using resonance to reduce the switching losses in dc-dc converters is to start with
a resonant inverter to produce an ac signal and then rectify the output to obtain a
dc voltage. Figure 9-5a shows a half-bridge inverter with a full-wave rectifier and
a capacitor output filter across the load resistor RL. The two capacitors on the input
are large and serve to split the voltage of the source. The input capacitors are not
part of the resonant circuit. The basic operation of the circuit is to use the switches
to produce a square wave voltage for va. The series combination of Lr and Cr
forms a filter for the current iL. The current iL oscillates and is rectified and filtered
to produce a dc voltage output. Converter operation is dependent on the relation-
ship between the switching frequency and the resonant frequency of the filter.
Operation for ␻s > ␻o

For the first analysis, assume that the switching frequency ␻s is slightly larger
than the resonant frequency ␻o of the series LC combination. If the switching
frequency is around the resonant frequency of the LC filter, iL is approximately
sinusoidal with frequency equal to the switching frequency.
Figure 9-5b shows the square wave input voltage va, the current iL, the switch
current iS1, and the input to the rectifier bridge vb. The current in the switches is
turned on at zero voltage to eliminate turn-on losses, but the switches are turned
off at nonzero current, so turnoff losses could exist. However, capacitors could
be placed across the switches to act as lossless snubbers (see Chap. 10) to prevent
turn off losses.
The series resonant dc-dc converter is analyzed by considering the funda-
mental frequency of the Fourier series for the voltages and currents. The input
voltage to the filter va is a square wave of ⫾Vs /2. If the output voltage is assumed
to be a constant Vo, then the input voltage to the bridge vb is Vo when iL is posi-
tive and is ⫺Vo when iL is negative because of the condition of the rectifier
diodes for each of these cases. The amplitudes of the fundamental frequencies of
the square waves va and vb are
4(Vs >2) 2Vs
Va1 ⫽ ⫽ (9-52)
␲ ␲
4V
Vb1 ⫽ o (9-53)
␲
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 408
ib Io
iS1
+
Vs
S1 D1 DR1 DR3
2
-
Lr Cr
+
+ + +
Vs va iL vb Co RL Vo
- - -
-
+
Vs
S2 D2 DR4 DR2
2
-
(a)
Vs
2
va
iL
Vs
-
2
iS
1
Vo vb
-Vo
(b)
jXL -jXC
+ +
Va1 Re Vb1
- -
(c)
Figure 9-5 (a) A series resonant dc-dc converter using a half-bridge inverter;
(b) Voltage and current waveforms for ␻s ⬍ ␻o; (c) Equivalent ac circuit for
series resonant dc-dc converter; (d) Normalized frequency response.
408
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 409
Series Resonant dc–dc Converter

0.6
0.5
0.4
Q=1
Vo
0.3
Vs
Q=2
0.2
Q=3
Q=4
0.1
0.0
0.6 0.8 1.0 1.2 1.4
ωs fs
=
ω0 f0
(d)
The current at the output of the bridge ib is the full-wave-rectified form of iL.
The average value of ib is output current Io. If iL is approximated as a sine wave
of amplitude IL1, the average value of ib is
2IL1
Ib ⫽ Io ⫽ (9-54)
␲
The relationship between input and output voltages is approximated from
ac circuit analysis using the fundamental frequencies of the voltage and current
waveforms. Figure 9-5c shows the equivalent ac circuit. The input voltage is the
fundamental of the input square wave, and the impedances are ac impedances
using ␻s of the input voltage. The value of output resistance in this equivalent
circuit is based on the ratio of voltage to current at the output. Using Eqs. (9-53)
and (9-54),
Vb1 (4Vo>␲) 8 V 8
Re ⫽ ⫽ ⫽ a 2 b a o b ⫽ a 2 b (RL) (9-55)
IL1 (␲Io>2) ␲ Io ␲
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 410
The ratio of output to input voltage is determined from phasor analysis of Fig. 9-5c,
Vb1 4Vo >␲ Re

⫽ ⫽2 2 (9-56)
Va1 2Vs >␲ Re ⫹ j(XL ⫺ XC)
or
1
a b
Vs
Vo ⫽ (9-57)
2 21 ⫹ [(XL ⫺ XC)>Re]2
where the reactances XL and XC are
XL ⫽ ␻s L r (9-58)
1
XC ⫽ (9-59)
␻s Cr
The reactances XL and XC depend on the switching frequency ␻s. Therefore, the
output voltage can be controlled by changing the switching frequency of the con-
verter. The sensitivity of the output to the switching frequency depends on the
values of Lr and Cr. If Q is defined as
␻0 L r
Q⫽ (9-60)
RL
Vo /Vs is plotted with Q as the parameter in Fig. 9-5d. The curves are more accurate
above resonance because iL has more of a sinusoidal quality for these frequencies.
Recall that the curves are based on the approximation that the current is sinusoidal
despite the square wave voltage excitation, and the results will be inexact.
EXAMPLE 9-4
Series Resonant DC-DC Converter

For the dc-dc converter of Fig. 9-5a,
Vs ⫽ 100 V
Lr ⫽ 30 ␮H
Cr ⫽ 0.08 ␮F
RL ⫽ 10 ⍀
fs ⫽ 120 kHz
Determine the output voltage of the converter. Verify the result with a PSpice simulation.
■ Solution
The resonant frequency of the filter is
1 1
f0 ⫽ ⫽ ⫽ 102.7 kHz
2␲2L rCr 2␲ 230(10 ⫺6)(0.08)(10 ⫺6)
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 411
Switching frequency is higher than resonance, and the equivalent circuit of Fig. 9-5c is
used to determine the output voltage. From Eq. (9-55), the equivalent resistance is
8 8
Re ⫽ (R ) ⫽ 2 (10) ⫽ 8.11 Æ
␲2 L ␲
The inductive and capacitive reactances are
XL ⫽ ␻s L r ⫽ 2␲(120,000)(30)(10 ⫺6) ⫽ 22.6 Æ
1 1
XC ⫽ ⫽ ⫽ 16.6 Æ
␻s Cr 2␲(120,000)(0.08)(10 ⫺6)
Using Eq. (9-57), the output voltage is
Vs 1
a
100 1
Vo ⫽ b⫽ a b ⫽ 40.1 V
2 21 ⫹ [(XL ⫺ XC)>Re]2 2 21 ⫹ [(22.6 ⫺ 16.6)>8.11]2
The output could also be approximated from the graph of Fig. 9-5d. The value of Q from
Eq. (9-60) is
␻0 L r 2␲(102.7)(10)3 30(10 ⫺6 )
Q⫽ ⫽ ⫽ 1.94
RL 10
Normalized switching frequency is
fs 120 kHz
⫽ ⫽ 1.17
f0 102.7 kHz
Normalized output is obtained from Fig. 9-5d as approximately 0.4, making the output
voltage (0.4)(100 V) ⫽ 40 V.
Simulation for this circuit could include various levels of detail. The simplest assumes
that switching takes place properly, and a square wave exists at the input to the filter as
shown in Fig. 9-6a. The source is then modeled as a square wave of ⫾Vs/2 without
including any details of the switches, as was done in Example 9-3. The small capacitors
across the diodes aid in convergence in the transient analysis.
Figure 9-6 shows the current in Lr and the output voltage. Note that the current is not
quite sinusoidal and that the output is approximately 40 V and contains some ripple. The
simulation verifies the foregoing analytic solution. Note that the results of the simulation
are very sensitive to the simulation parameters, include the step size of the transient
analysis. A step size of 0.1 ␮s was used here. The diodes are made ideal by setting n ⫽
0.001 in the PSpice diode model.
EXAMPLE 9-5

For the series resonant dc-dc converter of Fig. 9-5a, the dc source voltage is 75 V. The
desired output voltage is 25 V, and the desired switching frequency is 100 kHz. The load
resistance RL is 10 ⍀. Determine Lr and Cr.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 412
SERIES RESONANT DC–DC CONVERTER
PARAMETERS:
f = 120k
Vdc = 100 1n 1n
Lr Cr
1 2
V1 = {–Vdc/2} V1 30u 0.08u
V2 = {Vdc/2} + Co RL
-
TD = 0 100u 10
TR = 1n
TF = 1n 1n 1n
PW = {0.5/f}
PER = {1/f}
.model Dbreak D n = 0.001
(a)
CURRENT IN Lr
5.0 A
0A
–5.0 A
I (Lr)
40.00 V
OUTPUT VOLTAGE
39.95 V
SEL>>
39.90 V
3.900 ms 3.905 ms 3.910 ms 3.915 ms 3.920 ms
V(C4:2, RL:2)
Time
(b)
Figure 9-6 (a) PSpice circuit for the series resonant dc-dc converter with the source and
switches replaced with a square wave. The small capacitors across the diodes aid convergence;
(b) Probe output.
■ Solution
Select the resonant frequency ␻0 to be slightly less than the desired switching frequency
␻s. Let ␻s/␻0 ⫽ 1.2,
␻s 2␲fs 2␲10 5
␻0 ⫽ ⫽ ⫽ ⫽ 524(10 3) rad/s
1.2 1.2 1.2
From the graph of Fig. 9-5d with Vo /Vs ⫽ 25/75 ⫽ 0.33 and ␻s/␻0 ⫽ 1.2, the required Q
is approximately 2.5. From Eq. (9-60),
QRL (2.5)(10)
Lr ⫽ ⫽ ⫽ 47.7 ␮H
␻0 524(10 3)
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 413
va
iL
is1
vb
Figure 9-7 Voltage and current waveforms for the series resonant
dc-dc converter, ␻0/2 ⬍ ␻s ⬍ ␻0.
and
1 1 1
␻0 ⫽ Q Cr ⫽ ⫽ ⫽ 0.0764 ␮F
2L rCr ␻20 L r (524)(10 3)(47.7)(10 ⫺6)
Operation for w0 /2 < ws < w0

The series resonant dc-dc converter that has a switching frequency less than reso-
nance but greater than ␻0 /2 has the current waveform for iL as shown in Fig. 9-7.
The switches turn on with positive voltage and current, resulting in turn-on
switching losses. The switches turn off at zero current, resulting in no turnoff
losses. Furthermore, because the switches turn off at zero current, thyristors could
be used if the switching frequency is low. Analysis is done using the same tech-
nique as for ␻s ⬎ ␻0, but the harmonic content of the current waveform is now
higher, and the sinusoidal approximation is not as accurate.
Operation for ws < w 0 /2

With this switching frequency, the current in the series LC circuit is shown in
Fig. 9-8. When S1 in Fig. 9-5a is turned on, iL becomes positive and oscillates at
frequency ␻0. When the current reaches zero at t1 and becomes negative, diode
D1 carries the negative current. When the current again reaches zero at t2, S1 is
off, and the current remains at zero until S2 turns on at T/2. The current wave-
form for the second half-period is the negative of that of the first.
Switches turn on and off at zero current, resulting in zero switching losses.
Since the switches turn off at zero current, thyristors could be used in low-frequency
applications.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 414
iL
0 t1 t2
Figure 9-8 Current waveform for the

series resonant dc-dc converter, ␻s ⬍ ␻0.
Current in the LC series combination is discontinuous for this mode of oper-

ation. In the two previously described modes of operation, the current is contin-
uous. Since the average of the rectified inductor current must be the same as the
load current, the current in the LC branch will have a large peak value.
PSpice simulation for discontinuous current must include unidirectional
switch models because the voltage at the input to the circuit is not a square wave.
Variations on the Series Resonant DC-DC Converter

The series resonant dc-dc converter can be implemented using variations on the
basic topology in Fig. 9-5a. The capacitor Cr can be incorporated into the voltage-
divider capacitors in the half bridge, each being Cr /2. An isolation transformer
can be included as part of the full-wave rectifier on the output. Figure 9-9 shows
an alternate implementation of the series resonant dc-dc converter.
+
Cr
2
-
+ Lr +
Vs Co RL Vo
- -
+
Cr
2
-
Figure 9-9 An alternate implementation of the series resonant

dc-dc converter.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 415
9.6 The Parallel Resonant DC-DC Converter 415
9.6 THE PARALLEL RESONANT DC-DC CONVERTER

The converter in Fig. 9-10a is a parallel dc-dc converter. The capacitor Cr is
placed in parallel with the rectifier bridge rather than in series. An output filter
inductor Lo produces essentially a constant current from the bridge output to
Lo
+ + Io
Vs S1 D1
2
-
Lr ib
+ +
+ +
Vs va Co vb vx Co RL Vo
- -
- -
+
Vs S2
2 D2
-
-
(a)
jXL
+ +
Va1 -jXC Re Vb
1
- -
(b)
Q=5
2.4
Q=4
2.0
1.6 Q=3
Vo
Vs
1.2 Q=2
0.8
Q=1
0.4
0.6 0.8 1.0 1.2 1.4

ws fs
=
w0 f0
(c)
Figure 9-10 (a) Parallel resonant dc-dc converter; (b) Equivalent ac circuit for
parallel resonant dc-dc converter; (c) Normalized frequency response.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 416
the load. The switching action causes the voltage across the capacitor and
bridge input to oscillate. When the capacitor voltage is positive, rectifier diodes
DR1 and DR2 are forward-biased and carry current Io. When the capacitor voltage
is negative, DR3 and DR4 are forward-biased and carry current Io. The current
ib at the input to the bridge is therefore a square wave current of ⫾Io. The
bridge output voltage is the full-wave rectified waveform of voltage vb. The aver-
age voltage across the output inductor Lo is zero, so the output voltage is the
average of rectified vb.
The parallel dc-dc converter can be analyzed by assuming that the voltage
across the capacitor Cr is sinusoidal, taking only the fundamental frequencies of
the square wave voltage input and square wave current into the bridge. The
equivalent ac circuit is shown in Fig. 9-10b. The equivalent resistance for this
circuit is the ratio of capacitor voltage to the fundamental frequency of the square
wave current. Assuming that the capacitor voltage is sinusoidal, the average of
the rectified sine wave at the bridge output (vx) is the same as Vo,
2Vx1 2Vb1
Vo ⫽ Vx ⫽ ⫽ (9-61)
␲ ␲
where Vb1 is the amplitude of the fundamental frequency of vb. The equivalent
resistance is then
Vb1 Vo␲>2 ␲2 Vo ␲2
Re ⫽ ⫽ ⫽ a b ⫽ RL (9-62)
Ib1 4Io >␲ 8 Io 8
where Ib1 is the amplitude of the fundamental frequency of the square wave
current ib.
Solving for output voltage in the phasor circuit of Fig. 9-10b,
Vb1 2 1
⫽ 2 (9-63)
Va1 1 ⫺ (XL >XC ) ⫹ j(XL >Re)
Since Vo is the average of the full-wave rectified value of vb,

Vo␲
Vb1 ⫽ (9-64)
2
Va1 is the amplitude of the fundamental frequency of the input square wave:
4(Vs >2)
Va1 ⫽ (9-65)
␲
Combining Eqs. (9-64) and (9-65) with Eq. (9-63), the relationship between out-
put and input of the converter is
Vo 4 2 1
⫽ 2 (9-66)
Vs ␲2 1 ⫺ (XL >XC) ⫹ j(XL >Re)
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 417
9.6 The Parallel Resonant DC-DC Converter 417
or
4Vs
Vo ⫽ (9-67)
␲2 2[1 ⫺ (XL >XC)]2 ⫹ (XL >Re)2
Vo /Vs is plotted with Q as a parameter in Fig. 9-10c, where Q is defined as

RL
Q⫽ (9-68)
␻0 L r
and
1
␻0 ⫽ (9-69)
2L rCr
The curves are more accurate for switching frequencies larger than ␻0 because
of the sine-like quality of the capacitor voltage for these frequencies. Note that
the output can be larger than the input for the parallel resonant dc-dc converter, but
the output is limited to Vs /2 for the series resonant dc-dc converter.
EXAMPLE 9-6
Parallel Resonant DC-DC Converter

The circuit of Fig. 9-10a has the following parameters:
Vs ⫽ 100 V
Lr ⫽ 8 ␮H
Cr ⫽ 0.32 ␮F
RL ⫽ 10 ⍀
fs ⫽ 120 kHz
Determine the output voltage of the converter. Assume the output filter components Lo
and Co produce a ripple-free output current and voltage.
■ Solution
1 1
␻0 ⫽ ⫽ ⫺6
⫽ 625 krad/s
2L rCr 28(10 )0.32(10 ⫺6)
RL 10
Q⫽ ⫽ ⫽ 2.0
␻0 L r 625(10 3)8(10 ⫺6)
␻s 2␲(120 k)
⫽ ⫽ 1.21
␻0 625 k
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 418
The normalized output can be estimated from the graph in Fig. 9-10c as 0.6, making the
output approximately 60 V. The output voltage can also be obtained from Eq. (9-67).
The reactances are
XL ⫽ ␻s L r ⫽ 2␲(120)(10 3)8(10 ⫺6) ⫽ 6.03 Æ

1 1
XC ⫽ ⫽ ⫽ 4.14 Æ
␻sCr 2␲(120)(10 3)0.32(10 ⫺6)
The equivalent resistance is
␲2 ␲2
Re ⫽ RL ⫽ (10) ⫽ 12.3 Æ
8 8
Equation (9-67) for output voltage becomes
(4)(100)
Vo ⫽ ⫽ 60.7 V
␲ 2[1 ⫺ (6.03/4.14)]2 ⫹ (6.03>12.3)2
2
9.7 THE SERIES-PARALLEL DC-DC CONVERTER

The series-parallel dc-dc converter of Fig. 9-11a has both a series and a parallel
capacitor. The analysis is similar to the parallel converter discussed previously.
The switches produce a square wave voltage va, and the voltage vb at the input to
the rectifier is ideally a sinusoid at the fundamental frequency of the input square
wave. The output inductor Lo is assumed to produce a ripple-free current, causing
the input current ib to the rectifier bridge to be a square wave.
The relationship between input and output voltages is estimated from ac
analysis of the circuit for the fundamental frequency of the square waves. The ac
equivalent circuit is shown in Fig. 9-11b. A straightforward phasor analysis of
Fig. 9-11b gives
Vb1 2 1
⫽ 2 (9-70)
Va1 1 ⫹ (XCs >XCp) ⫺ (XL >XCp) ⫹ j(XL >Re ⫺ XCs >Re)
where Re is the same as for the parallel converter,
␲2
Re ⫽ R (9-71)
8 L
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 419
9.7 The Series-Parallel DC-DC Converter 419
Lo
+
Vs Io
2
- +
Cs L ib
+ +
Vs va Cp vb Co RL Vo
- -
+ -
Vs
2
-
(a)
-jXCs jXL
+ +
V a1 -jXCp Re Vb1
- -
(b)
1.0
0.8
0.6
Vo Q=1
Vs
0.4
Q=2
0.2 Q=3
Q=4
Q=5
0
0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
ws fs
=
w0 f0
(c)
Figure 9-11 (a) Series-parallel resonant dc-dc converter; (b) Equivalent ac circuit for the
series-parallel resonant dc-dc converter; (c) Normalized frequency response for output voltage.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 420
and the reactances at the switching frequency are
1
X Cs ⫽
␻sCs
1
X Cp ⫽ (9-72)
␻sCp
X L ⫽ ␻sL
Also Va1 and Vb1 are the amplitudes of the fundamental frequencies of the wave-
forms at va and vb. Using Eqs. (9-64) and (9-65), the relationship between input
and output of the converter is
Vo 4 2 1
⫽ 2 (9-73)
Vs ␲2 1 ⫹ (XCs >XCp) ⫺ (XL >XCp) ⫹ j(XL >Re ⫺ XCs >Re)
Rewriting the preceding equation in terms of ␻s,
Vo 4
⫽ 2
Vs Cp ␻s L 1 2 (9-74)
␲2 a1 ⫹ ⫺ ␻s LCp b ⫹ a b
2
⫺
A Cs Re ␻s ReCs
Equation (9-74) for Cs ⫽ Cp is plotted with Q as a parameter in Fig. 9-11c where

Q is defined as
␻0 L
Q⫽ (9-75)
RL
where
1
␻0 ⫽ (9-76)
2LCs
These curves are more accurate above ␻0 than below because the harmonics of
the square wave are more adequately filtered, resulting in the ac analysis being
more representative of the actual situation.
The series capacitor Cs can be incorporated into the voltage-divider capaci-
tors, each equal to Cs /2, for the half-bridge circuit as was shown in Fig. 9-9 for
the series resonant dc-dc converter.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 421
9.8 Resonant Converter Comparison 421
EXAMPLE 9-7
Series-Parallel Resonant DC-DC Converter

The series-parallel resonant dc-dc converter of Fig. 9-11a has the following parameters:
Vs ⫽ 100 V
Cp ⫽ Cs ⫽ 0.1 ␮F
L ⫽ 100 ␮H
RL ⫽ 10 ⍀
fs ⫽ 60 kHz
The output filter components Lo and Co are assumed to produce a ripple-free output.
Determine the output voltage of the converter.
■ Solution
The resonant frequency ␻0 is determined from Eq. (9-76) as
1 1
␻0 ⫽ ⫽ ⫽ 316 krad/s
2LCs 2(100)(10 ⫺6)(0.1)(10 ⫺6)
␻
f0 ⫽ 0 ⫽ 50.3 kHz
2␲
The Q of the circuit is determined from Eq. (9-75) as
␻0 L 3.16(103)(100)(10⫺6)
Q⫽ ⫽ ⫽ 3.16
RL 10
The normalized switching frequency is
fs 60(103)
⫽ ⫽ 1.19
f0 50.3(103)
From the graph of Fig. 9-11c, the normalized output is slightly less than 0.4, for an
estimated output of Vo ⬇ 100(0.4) ⫽ 40 V. Equation (9-74) is evaluated, using Re ⫽
␲2RL/8 ⫽ 12.34 ⍀,
Vo
⫽ 0.377
Vs
Vo ⫽ Vs(0.377) ⫽ (100)(0.377) ⫽ 37.7 V
9.8 RESONANT CONVERTER COMPARISON

A drawback of the series converter described previously is that the output cannot
be regulated for the no-load condition. As RL goes to infinity, Q in Eq. (9-60)
goes to zero. The output voltage is then independent of frequency. However, the
parallel converter is able to regulate the output at no load. In Eq. (9-68), for the
parallel converter Q becomes larger as the load resistor increases, and the output
remains dependent on the switching frequency.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 422
A drawback of the parallel converter is that the current in the resonant com-
ponents is relatively independent of load. The conduction losses are fixed, and
the efficiency of the converter is relatively poor for light loads.
The series-parallel converter combines the advantages of the series and par-
allel converters. The output is controllable for no load or light load, and the light-
load efficiency is relatively high.
9.9 THE RESONANT DC LINK CONVERTER

The circuit of Fig. 9-12a is the basic topology for a switching scheme for an
inverter that has zero-voltage switching. The analysis proceeds like that of the res-
onant switch converters. During the switching interval, the load current is assumed
to be essentially constant at Io. The resistance represents losses in the circuit.
When the switch is closed, the voltage across the RLr combination is Vs.
If the time constant Lr /R is large compared to the time that the switch is
closed, the current rises nearly linearly. When the switch is opened, the
equivalent circuit is shown in Fig. 9-12b. Kirchhoff’s voltage and current laws
yield the equations
di L(t)
Ri L(t) ⫹ L r ⫹ vC (t) ⫽ Vs (9-77)
dt
i C (t) ⫽ i L(t) ⫺ Io (9-78)
Differentiating Eq. (9-77),
d 2i L(t) di (t) dv (t)
Lr ⫹R L ⫹ C ⫽0 (9-79)
dt 2 dt dt
The derivative of the capacitor voltage is related to capacitor current by
dvC (t) i C (t) i L(t) ⫺ Io

⫽ ⫽ (9-80)
dt Cr Cr
Substituting into Eq. (9-79) and rearranging,
d 2i L R di L(t) i L(t) I
2 ⫹ ⫹ ⫽ o (9-81)
dt L r dt L rCr L rCr
If the initial conditions for inductor current and capacitor voltage are
i L(0) ⫽ I1 vC (0) ⫽ 0, (9-82)
the solution for current can be shown to be

2Vs ⫺ R(I1 ⫹ Io)
i L(t) ⫽ I1 ⫹ e ⫺␣t c (I1 ⫺ Io) cos(␻t) ⫹ sin(␻t) d (9-83)
2␻L r
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9.9 The Resonant DC Link Converter 423
R Lr
+
+ iL
Vs Cr vC Io
-
-
(a)
R Lr
+
iL iC
+
Vs Cr vC Io
-
(b)
vC
0
tx T
I1
iL I0
(c)
Figure 9-12 (a) Resonant dc link converter; (b) Equivalent

circuit with the switch open and diode off; (c) Capacitor
voltage and inductor current.
where
R
␣⫽ (9-84)
2L r
1
␻0 ⫽ (9-85)
2L rCr
␻ ⫽ 2␻20 ⫺ ␣ 2 (9-86)
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Capacitor voltage can be shown to be
R R
vC (t) ⫽ Vs ⫺ Io R ⫹ e ⫺␣t a (Io R ⫺ Vs)cos(␻t) ⫹ e c Vs ⫺ (I1 ⫹ Io) d
2␻L r 2
⫹ ␻L r(I1 ⫺ Io) f sin(␻t) b (9-87)
If the resistance is small, making R ⬍⬍ ␻; Lr, Eqs. (9-83) and (9-87) become
Vs
i L(t) L Io ⫹ e ⫺␣t c (I1 ⫺ Io)cos(␻0 t) ⫹ sin(␻0 t)d (9-88)
␻0 L r
vC (t) L Vs ⫹ e ⫺␣t[ ⫺Vs cos(␻0 t) ⫹ ␻0 L r(I1 ⫺ Io)sin(␻0 t)] (9-89)
When the switch is opened, the inductor current and capacitor voltage oscil-
late. The switch can be reclosed when the capacitor voltage returns to zero
and thereby avoids switching losses. The switch should remain closed until
the inductor current reaches some selected value I1 which is above the load
current Io. This allows the capacitor voltage to return to zero for lossless
switching.
An important application of this resonant switching principle is for in-
verter circuits. The three-phase inverter of Fig. 9-13 can have PWM switching
(see Chap. 8) and can include intervals when both switches in one of the three
legs are closed to cause the input voltage to the bridge to oscillate. The switches
can then turn on or off when the capacitor voltage is zero.
Lr
+ a
Vdc Cr b
c
-
Figure 9-13 Three-phase inverter with a resonant dc link.

har80679_ch09_387-430.qxd 12/17/09 2:58 PM Page 425
9.9 The Resonant DC Link Converter 425
EXAMPLE 9-8
Resonant DC Link
The single-switch resonant dc link converter of Fig. 9-12a has the parameters
Vs ⫽ 75 V
L ⫽ 100 ␮H
C ⫽ 0.1 ␮F
R⫽1⍀
Io ⫽ 10 A
I1 ⫽ 12 A
If the switch is opened at t ⫽ 0 with iL(0) ⫽ I1 and vC (0) ⫽ 0, determine when the switch
should be closed so the voltage across it is zero. If the switch is closed immediately after
the capacitor voltage becomes zero, how long should the switch remain closed so that the
inductor voltage returns to I1?
■ Solution
From the circuit parameters,
1 1
␻0 ⫽ ⫽ ⫽ 316 krad/s
2LC 2(10 ⫺4)(10 ⫺7)
R 1
␣⫽ ⫽ ⫽ 5000
2L 2(10 ⫺4)
␻ ⫽ 2␻20 ⫺ ␣ 2 L ␻0
␻L r ⫽ 316(10 3)(100)(10 ⫺6) ⫽ 31.6
Since ␣ ⬍⬍ ␻0, ␻ L ␻0, and Eqs. (9-88) and (9-89) are good approximations,
vC (t) L 75 ⫹ e ⫺5000t[⫺ 75 cos(␻0t) ⫹ 31.6(12 ⫺ 10) sin(␻0t)]

⫽ 75 ⫹ e ⫺5000t[⫺ 75 cos(␻0t) ⫹ 63.2 sin(␻0t)]
75
i L(t) L 10 ⫹ e ⫺5000t c(12 ⫺ 10) cos(␻0t) ⫹ sin(␻0t)d
31.6
⫽ 10 ⫹ e ⫺5000t [2 cos(␻0t) ⫹ 2.37 sin(␻0t)]
The above equations are graphed in Fig. 9-12c. The time at which the capacitor voltage
returns to zero is determined by setting vC equal to zero and solving for t numerically,
resulting in tx ⫽ 15.5 ␮s. Current is evaluated at t ⫽ 15.5 ␮s using Eq. (9-88), resulting
in iL(t ⫽15.5 ␮s) ⫽ 8.07 A.
If the switch is closed at 15.5 ␮s, voltage across the inductor is approximately Vs,
and the current increases linearly.
Vs
⌬i L ⫽ ⌬t (9-90)
L
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The switch must remain closed until iL is 12 A, requiring a time of
( ⌬i L)(L) (12 ⫺ 8.39)(100)(10 ⫺6)

⌬t ⫽ ⫽ ⫽ 4.81 ␮s
Vs 75
9.10 Summary
Resonant converters are used to reduce switching losses in various converter topologies.
Resonant converters reduce switching losses by taking advantage of voltage or current
oscillations. Switches are opened and closed when the voltage or current is at or near zero.
The topologies discussed in this chapter are resonant switch inverters; the series resonant
inverter; the series, parallel, and series-parallel dc-dc converters; and the resonant dc link
converter. Resonant converters are presently a topic of great interest in power electronics
because of increased efficiency and the possibility of higher switching frequencies with
associated smaller filter components. As was demonstrated in the examples, the voltage
stresses on the components may be quite high for resonant converters. The sources in the
Bibliography give further details on resonant converters.
9.11 Bibliography
Raton, Fla., 2005.
S. Basson, and G. Moschopoulos, “Zero-Current-Switching Techniques for Buck-Type
AC-DC Converters,” International Telecommunications Energy Conference, Rome,
Italy, pp. 506–513, 2007.
W. Chen, Z. Lu, and S. Ye, “A Comparative Study of the Control Type ZVT PWM Dual
Switch Forward Converters: Analysis, Summary and Topology Extensions,” IEEE
Applied Power Electronics Conference and Exposition (APEC), Washington, D.C.,
pp. 1404–9, 2009.
T. W. Ching. and K. U. Chan, “Review of Soft-Switching Techniques for High-Frequency
Switched-Mode Power Converters,” IEEE Vehicle Power and Propulsion
Conference, Austina, Tex., 2008.
D. M. Divan, “The Resonant DC Link Converter—A New Concept in Static Power
Conversion,” IEEE Transactions. on Industry Applications, vol. 25, no. 2, March/
April 1989, pp. 317–325.
S. Freeland and R. D. Middlebrook, “A Unified Analysis of Converters with Resonant
Switches,” IEEE Power Electronics Specialists Conference, New Orleans, La.,
1986, pp. 20–30.
J. Goo, J. A. Sabate, G. Hua, F. and C. Lee, “Zero-Voltage and Zero-Current-Switching
Full-Bridge PWM Converter for High-Power Applications,” IEEE Transactions on
Industry Applications, vol. 1, no. 4, July 1996, pp. 622–627.
G. Hua and F. C. Lee, “Soft-Switching Techniques in PWM Converters,” Industrial
Electronics Conference Proceedings, vol. 2, pp. 637–643, 1993.
R. L. Steigerwald, R. W. DeDoncker, and M. H. Kheraluwala, “A Comparison of High-
Power Dc-Dc Soft-Switched Converter Topologies,” IEEE Transactions on
Industry Applications, vol. 32, no. 5, September/October 1996, pp. 1139–1145.
har80679_ch09_387-430.qxd 12/16/09 3:25 PM Page 427
Problems 427
T. S. Wu, M. D. Bellar, A. Tchamdjou, J. Mahdavi, and M. Ehsani, “Review of Soft-

Switched DC-AC Converters,” IAS IEEE Industry Applications Society Annual
Meeting, vol. 2, pp. 1133–1144, 1996.
Problems
Zero-current Resonant Switch Converter
9-1 In the converter of Fig. 9-1a, Vs ⫽ 10 V, Io ⫽ 5 A, Lr ⫽ 1 ␮H, Cr ⫽ 0.3 ␮F, and
fs ⫽ 150 kHz. Determine the output voltage of the converter.
9-2 In the converter of Fig. 9-1a, Vs ⫽ 18 V, Io ⫽ 3 A, Lr ⫽ 0.5 ␮H, and Cr ⫽ 0.7 ␮F.
Determine the maximum switching frequency and the corresponding output
voltage. Determine the switching frequency such that the output voltage is 5 V.
9-3 In the converter of Fig. 9-1a, Vs ⫽ 36 V, Io ⫽ 5 A, Lr ⫽ 10 nH, Cr ⫽ 10 nF, and
fs ⫽ 750 kHz. (a) Determine the output voltage of the converter. (b) Determine
the maximum inductor current and capacitor voltage. (c) Determine the
switching frequency for an output of 12 V.
9-4 In the converter of Fig. 9-1a, Vs ⫽ 50 V, Io ⫽ 3 A, ␻0 ⫽ 7(107) rad/s, and Vo ⫽
36 V. Determine Lr and Cr such that the maximum current in Lr is 9 A. Determine
the required switching frequency.
9-5 In the converter of Fig. 9-1a, Vs ⫽ 100 V, Lr ⫽ 10 ␮H, and Cr ⫽ 0.01 ␮F. The
load current ranges from 0.5 to 3 A. Determine the range of switching frequency
required to regulate the output voltage at 50 V.
9-6 In the converter of Fig. 9-1a, Vs ⫽ 30 V, RL ⫽ 5 ⍀, and fs ⫽ 200 kHz. Determine
values for Lr and Cr such that Z0 is 2.5 ⍀ and Vo ⫽ 15 V.
9-7 Determine a PSpice input file to simulate the circuit of Fig. 9-1a using the
parameters in Probl. 9-1. Model the load current as a current source. Use the
voltage-controlled switch Sbreak for the switching device. Idealize the circuit by
using Ron ⫽ 0.001 ⍀ in the switch model and using n ⫽ 0.001 in the Dbreak diode
model. (a) Determine the (average) output voltage. (b) Determine the peak voltage
across Cr. (c) Determine the peak, average, and rms values of the current in Lr.
Zero-voltage Resonant Switch Converter

9-8 In Example 9-2, determine the required switching frequency to produce an
output voltage of 15 V. All other parameters are unchanged.
9-9 In Fig. 9-2a, Vs ⫽ 20, Lr ⫽ 0.1 ␮H, Cr ⫽ 1 nF, Io ⫽ 10 A, and fs ⫽ 2 MHz.
Determine the output voltage and the maximum capacitor voltage and maximum
inductor current.
9-10 In Fig. 9-2a, Vs ⫽ 5 V, Io ⫽ 3 A, Lr ⫽ 1 ␮H, and Cr ⫽ 0.01 ␮F. (a) Determine
the output voltage when fs ⫽ 500 kHz. (b) Determine the switching frequency
such that the output voltage is 2.5 V.
9-11 In Fig. 9-2a, Vs ⫽ 12 V, Lr ⫽ 0.5 ␮H, Cr ⫽ 0.01 ␮F, and Io ⫽ 10 A. (a) Determine
the output voltage when fs ⫽ 500 kHz. (b) The load current Io is expected to vary
between 8 and 15 A. Determine the range of switching frequency necessary to
regulate the output voltage at 5 V.
9-12 In Fig. 9-2a, Vs ⫽ 15 V and Io ⫽ 4 A. Determine Lr and Cr such that the
maximum capacitor voltage is 40 V and the resonant frequency is 1.6(106) rad/s.
Determine the switching frequency to produce an output voltage of 5 V.
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9-13 In Fig. 9-2a, Vs ⫽ 30 V, RL ⫽ 5 ⍀, and fs ⫽ 100 kHz. Determine values for Lr

and Cr such that Z0 is 25 ⍀ and Vo ⫽ 15 V.
9-14 Determine a PSpice circuit to simulate the circuit of Fig. 9-2a using the
parameters in Probl. 9-9. Model the load current as a current source. Use the
voltage-controlled switch Sbreak for the switching device, and make it
unidirectional by adding a series diode. Make the diode ideal by using n ⫽ 0.001
in the Dbreak model. (a) Determine the (average) output voltage. (b) Determine
the peak voltage across Cr. (c) Determine the energy transferred from the source
to the load in each switching period.
Resonant Inverter
9-15 The full-bridge resonant inverter of Fig. 9-3a has a 12-⍀ resistive load that
requires a 400-Hz, 80-V rms sinusoidal voltage. The THD of the load voltage
must be no more than 5 percent. Determine the required dc input and suitable
values for L and C. Determine the peak voltage across C and the peak current in
L.
9-16 The full-bridge resonant inverter of Fig. 9-3a has a 8-⍀ resistive load that
requires a 1200-Hz, 100-V rms sinusoidal voltage. The THD of the load voltage
must be no more than 10 percent. Determine the required dc input and suitable
values for L and C. Simulate the inverter in PSpice and determine the THD.
Adjust values of L and C if necessary so that the 10 percent THD is strictly
satisfied. What is the value of current when switching takes place?
9-17 The full-bridge resonant inverter of Fig. 9-3a is required to supply 500 W to a
15-⍀ load resistance. The load requires a 500-Hz ac current which has no more
than 10 percent total harmonic distortion. (a) Determine the required dc input
voltage. (b) Determine the values of L and C. (c) Estimate the peak voltage
across C and peak current in L using the fundamental frequency. (d) Simulate the
circuit in PSpice. Determine the THD, peak capacitor voltage, and peak inductor
current.

9-18 The series resonant dc-dc converter of Fig. 9-5a has the following operation
parameters: Vs ⫽ 10 V, Lr ⫽ 6 ␮H, Cr ⫽ 6 nF, fs ⫽ 900 kHz, and RL ⫽ 10 ⍀.
Determine the output voltage Vo.
9-19 The series resonant dc-dc converter of Fig. 9-5a has the following operation
parameters: Vs ⫽ 24 V, Lr ⫽ 1.2 ␮H, Cr ⫽ 12 nF, fs ⫽ 1.5 MHz, and RL ⫽ 5 ⍀.
Determine the output voltage Vo.
9-20 The series resonant dc-dc converter of Fig. 9-5a has an 18-V dc source and is to
have a 6-V output. The load resistance is 5 ⍀, and the desired switching
frequency is 800 kHz. Select suitable values of Lr and Cr.
9-21 The series resonant dc-dc converter of Fig. 9-5a has a 50-V dc source and is to
have an 18-V output. The load resistance is 9 ⍀, and the desired switching
frequency is 1 MHz. Select suitable values of Lr and Cr.
9-22 The series resonant dc-dc converter of Fig. 9-5a has a 40-V dc source and is to
have a 15-V output. The load resistance is 5 ⍀, and the desired switching
frequency is 800 kHz. Select suitable values of Lr and Cr. Verify your results with
a PSpice simulation.
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Problems 429
9-23 The series resonant dc-dc converter of Fig. 9-5a has a 150-V dc source and is
to have a 55-V output. The load resistance is 20 ⍀. Select a switching
frequency and suitable values of Lr and Cr. Verify your results with a PSpice
simulation.
Parallel Resonant dc-dc Converter

9-24 The parallel resonant dc-dc converter of Fig. 9-10a has the following operation
parameters: Vs ⫽ 15 V, RL ⫽ 10 ⍀, Lr ⫽ 1.3 ␮H, Cr ⫽ 0.12␮F, and fs ⫽ 500 kHz.
9-25 The parallel resonant dc-dc converter of Fig. 9-10a has the following operation
parameters: Vs ⫽ 30 V, RL ⫽ 15 ⍀, Lr ⫽ 1.2 ␮H, Cr ⫽ 26 nF, and fs ⫽ 1 MHz.
9-26 The parallel resonant dc-dc converter of Fig. 9-10a has Vs ⫽ 12 V, RL ⫽ 15 ⍀,
and fs ⫽ 500 kHz. The desired output voltage is 20 V. Determine suitable values
for Lr and Cr.
9-27 The parallel resonant dc-dc converter of Fig. 9-10a has Vs ⫽ 45 V, RL ⫽ 20 ⍀,
and fs ⫽ 900 kHz. The desired output voltage is 36 V. Determine suitable values
for Lr and Cr.
9-28 The parallel resonant dc-dc converter of Fig. 9-10a has a 50-V dc source and is to
have a 60-V output. The load resistance is 25 ⍀. Select a switching frequency
and suitable values of Lr and Cr.
Series-parallel dc-dc Converter

9-29 The series-parallel dc-dc converter of Fig. 9-11a has the following parameters:
Vs ⫽ 100 V, fs ⫽ 500 kHz, RL ⫽ 10 ⍀, L ⫽ 12 ␮H, and Cs ⫽ Cp ⫽ 12 nF.
Determine the output voltage.
9-30 The series-parallel dc-dc converter of Fig. 9-11a has Vs ⫽ 12 V, fs ⫽ 800 kHz,
and RL ⫽ 2 ⍀. Determine suitable values of L, Cs, and Cp such that the output
voltage is 5 V. Use Cs ⫽Cp.
9-31 The series-parallel dc-dc converter of Fig. 9-11a has Vs ⫽ 20 V and fs ⫽ 750 kHz.
The output voltage is to be 5 V and supply 1 A to a resistive load. Determine
suitable values of L, Cs, and Cp. Use Cs ⫽ Cp.
9-32 The series-parallel dc-dc converter of Fig. 9-11a has Vs ⫽ 25 V. The output
voltage is to be 10 V and supply 1 A to a resistive load. (a) Select a switching
frequency and determine suitable values of L, Cs, and Cp. (b) Verify your results
with a PSpice simulation.
Resonant dc Link
9-33 Create a PSpice simulation for the resonant dc link in Example 9-8. Use an
ideal diode model. (a) Verify the results of Example 9-8. (b) Determine the
energy supplied by the dc source during one switching period. (c) Determine
the average power supplied by the dc source. (d ) Determine the average power
absorbed by the resistance. (e) How do the results change if the resistance
is zero?
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9-34 For the resonant link dc converter of Fig. 9-12a, Vs ⫽ 75 V, Io ⫽ 5 A, R ⫽ 1 ⍀,

L ⫽ 250 ␮H, and C ⫽ 0.1 ␮F. If the switch is opened at t ⫽ 0 with iL(0) ⫽ I1 ⫽
7 A, and vC(0) ⫽ 0, determine time when the switch should be closed so the
voltage across it is zero. If the switch is closed immediately after the capacitor
voltage becomes zero, how long should the switch remain closed so that the
inductor voltage returns to 7 A?
9-35 For the resonant link dc converter of Fig. 9-12a, Vs ⫽ 100 V, Io ⫽ 10 A, R ⫽
0.5 ⍀, L ⫽ 150 ␮H, and C ⫽ 0.05 ␮F. If the switch is opened at t ⫽ 0 with
iL(0) ⫽ I1 ⫽ 12 A, and vC(0) ⫽ 0, determine time when the switch should be
closed so the voltage across it is zero. If the switch is closed immediately after
the capacitor voltage becomes zero, how long should the switch remain closed
so that the inductor voltage returns to 12 A?
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C H A P T E R 10
Drive Circuits, Snubber
Circuits, and Heat Sinks
10.1 INTRODUCTION
Minimizing power losses in electronic switches is an important objective when
designing power electronics circuits. On-state power losses occur because the
voltage across a conducting switch is not zero. Switching losses occur because a
device does not make a transition from one state to the other instantaneously, and
switching losses in many converters are larger than on-state losses.
Resonant converters (Chap. 9) reduce switch losses by taking advantage of
natural oscillations to switch when voltage or current is zero. Switches in cir-
cuits such as the dc-dc converters of Chaps. 6 and 7 go through a transition
when voltage and current are nonzero. Switch losses in those types of convert-
ers can be minimized by drive circuits designed to provide fast switching tran-
sitions. Snubber circuits are designed to alter the switching waveforms to
reduce power loss and to protect the switch. Power loss in an electronic switch
produces heat, and limiting device temperature is critical in the design of all
converter circuits.
10.2 MOSFET AND IGBT DRIVE CIRCUITS

Low-Side Drivers
The MOSFET is a voltage-controlled device and is relatively simple to turn on
and off, which gives it an advantage over a bipolar junction transistor (BJT). The
on state is achieved when the gate-to-source voltage sufficiently exceeds the
431
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432 C H A P T E R 10 Drive Circuits, Snubber Circuits, and Heat Sinks
threshold voltage, forcing the MOSFET into the triode (also called ohmic or non-
saturation) region of operation. Typically, the MOSFET gate-to-source voltage
for the on state in switching circuits is between 10 and 20 V, although some
MOSFETs are designed for logic-level control voltages. The off state is achieved
by a lower-than-threshold voltage. On- and off-state gate currents are essentially
zero. However, the parasitic input capacitance must be charged to turn the
MOSFET on and must be discharged to turn it off. Switching speeds are basi-
cally determined by how rapidly charge can be transferred to and from the gate.
Insulated gate bipolar transistors (IGBTs) are similar to MOSFETs in their drive
requirements, and the following discussion applies to them as well.
A MOSFET drive circuit must be capable of rapidly sourcing and sinking
currents for high-speed switching. The elementary drive circuit of Fig. 10-1a will
drive the transistor, but the switching time may be unacceptably high for some
applications. Moreover, if the input signal is from low-voltage digital logic
devices, the logic output may not be sufficient to turn on the MOSFET.
A better drive circuit is shown in Fig. 10-1b. The double emitter-follower
consists of a matched NPN and PNP bipolar transistor pair. When the drive
input voltage is high, Q1 is turned on and Q2 is off, turning the MOSFET on.
When the drive input signal is low, Q1 turns off, and Q2 turns on and removes
the charge from the gate and turns the MOSFET off. The input signal may
come from open-collector TTL used for control, with the double emitter-
follower used as a buffer to source and sink the required gate currents, as
shown in Fig. 10-1c.
Other arrangements for MOSFET drive circuits are shown in Fig. 10-2. These
are functionally equivalent to the BJT double emitter-follower of Fig. 10-1b. The
upper and lower transistors are driven as complementary on off transistors, with
one transistor sourcing current and the other sinking current to and from the gate
of the MOSFET to turn the power MOSFET on and off. Figure 10-2a shows NPN
BJT transistors, Fig. 10-2b shows N-channel MOSFETs, and Fig. 10-2c shows
complementary P- and N-channel MOSFETs.
Vs VG Vs VG Vs
Load Load Load

Q1 R2 Q1
R1 R1
vi vi Control Circuit
R1
Q2 vi Q2
(a) (b) (c)
Figure 10.1 (a) Elementary MOSFET drive circuit; (b) Double emitter-follower drive
circuit; (c) IC drive with double emitter-follower buffer.
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10.2 MOSFET and IGBT Drive Circuits 433
VG Vs VG Vs VG Vs
Load Load Load
(a) (b) (c)
Figure 10.2 Additional MOSFET drive circuits. (a) NPN transistors; (b) N-channel
MOSFETs; (c) P- and N-channel MOSFETs.
Example 10-1 illustrates the significance of the drive circuit on MOSFET

switching speeds and power loss.
EXAMPLE 10.1
MOSFET Drive Circuit Simulation

A PSpice model for the IRF150 power MOSFET is available in the PSpice demo version in
the EVAL file. (a) Use a PSpice simulation to determine the resulting turn-on and turnoff
times and the power dissipated in the MOSFET for the circuit of Fig. 10-1a. Use Vs 80 V
and a load resistance of 10 . The switch control voltage vi is a 0- to 15-V pulse, and R1
100 . (b) Repeat for the circuit of Fig. 10-1c with R1 R2 1 k. The switching frequency
for each case is 200 kHz, and the duty ratio of the switch control voltage is 50 percent.
■ Solution
(a) The elementary drive circuit is created for Fig. 10-1a using VPULSE for the
switch control voltage. The resulting switching waveforms from Probe are
shown in Fig. 10-3a. Switching transition times are roughly 1.7 and 0.5 s for
turnoff and turn-on, respectively. Average power absorbed by the MOSFET is
determined from Probe by entering AVG(W(M1)), which yields a result of
approximately 38 W.
(b) The emitter-follower drive circuit of Fig. 10-1c is created using 2N3904 NPN and
2N3906 PNP transistors from the evaluation library. The resulting switching wave-
forms are shown in Fig. 10-3b. The switching times are roughly 0.4 and 0.2 s for
turnoff and turn-on, and the power absorbed by the transistor is 7.8 W. Note that the
emitter-follower drive circuit removes the gate charge more rapidly than the ele-
mentary drive circuit in part (a).
High-Side Drivers
Some converter topologies, such as the buck converter using an N-channel
MOSFET, have high-side switches. The source terminal of the high-side MOSFET
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 434
20
MOSFET VOLTAGE/5
10
MOSFET CURRENT
0
TURN OFF TURN ON
2.0 us 3.0 us 4.0 us 5.0 us 6.0 us

V(A)/5 I(M1:d)
Time
(a)
18
MOSFET VOLTAGE
10
MOSFET CURRENT
0
TURN OFF TURN ON
–5
2.0 us 4.0 us 6.0 us 7.0 us
V(C)/5 I(M2:d)
Time
(b)
Figure 10.3 Switching waveforms for Example 10-1. (a) Elementary MOSFET
drive circuit of Fig. 10-1a; (b) Double emitter-follower drive circuit of Fig. 10-1b.
is not connected to the circuit ground, as it would be in a low-side switch in a con-

verter such as a boost converter. High-side switches require the MOSFET drive cir-
cuit to be floating with respect to the circuit ground. Drive circuits for these
applications are called high-side drivers. To turn on the MOSFET, the gate-to-source
voltage must be sufficiently high. When the MOSFET is on in a buck converter, for
example, the voltage at the source terminal of the MOSFET is the same as the supply
voltage Vs. Therefore, the gate voltage must be greater than the supply voltage.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 435
10.2 MOSFET and IGBT Drive Circuits 435
Vs Vs Vs
S3 S3 S3 2Vs
High-side + 0V +
Off + On
switch Vs C Vs
– – Vg –
0V Vs
Switch
control Load S2 S1 Load S2 S1 Load
S2 S1
(a) (b) (c)
Figure 10.4 (a) A bootstrap circuit for driving a high-side MOSFET or IGBT; (b) The circuit for the
switches closed, causing the capacitor to charge to Vs; (c) The circuit with the switches open, showing that the
gate-to-source voltage is Vs.
A way to achieve a voltage higher than the source is to use a charge pump
(switched-capacitor converter) as described in Chap. 6. One such high-side
driver configuration is shown in Fig. 10-4a. The two driver MOSFETs and the
diode are labeled as switches S1, S2, and S3. When the control signal is high,
S1 and S2 turn on, and the capacitor charges to Vs through the diode (Fig. 10-4b).
When the control signal goes low, S1 and S2 are off, and the capacitor voltage is
across the resistor and the gate of the power MOSFET, turning the MOSFET on.
The voltage at the load becomes the same as the source voltage Vs, causing the
voltage at the upper capacitor terminal to be 2Vs. This drive circuit is called a
bootstrap circuit.
MOSFET gate drivers are available as integrated-circuit (IC) packages.
An example is the International Rectifier IR2117 shown in Fig. 10-5a. The IC
with an external capacitor and diode provides the bootstrap circuit for the
MOSFET. Another example is the International Rectifier IR2110 that is
designed to drive both high-side and low-side switches (Fig. 10-5b). Half-
bridge and full-bridge converters are applications where both high-side and
low-side drivers are required.
Electrical isolation between the MOSFET and the control circuit is often
desirable because of elevated voltage levels of the MOSFET, as in the upper tran-
sistors in a full-bridge circuit or a buck converter. Magnetically coupled and opti-
cally coupled circuits are commonly used for electrical isolation. Figure 10-6a
shows a control and power circuit electrically isolated by a transformer. The
capacitor on the control side prevents a dc offset in the transformer. A typical
switching waveform is shown in Fig. 10-6b. Since the volt-second product must
be the same on the transformer primary and secondary, the circuit works best
when the duty ratio is around 50 percent. A basic optically isolated drive circuit
is shown in Fig. 10-6c.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 436
Up to 600 V
Vcc VCC VB
IN IN HO
COM VS TO
LOAD
IR2117
(a)
Up to 500 V or 600 V
HO
VDD VDD VB
HIN HIN VS TO
SD SD LOAD
LIN LIN VCC
VSS VSS COM
VCC LO
(b)
Figure 10.5 (a) International Rectifier IR2117 high-side driver; (b) International
Rectifier IR2110 high- and low-side driver. (Courtesy of International Rectifier
Corporation.)
VDD
Load
vG
+ +
Control
vi vG Signal
– – t
(a) (b) (c)
Figure 10.6 (a) Electrical isolation of control and power circuits; (b) Transformer secondary voltage;
(c) Optically isolated control and power circuits.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 437
10.3 Bipolar Transistor Drive Circuits 437
10.3 BIPOLAR TRANSISTOR DRIVE CIRCUITS

The bipolar junction transistor (BJT) has largely been replaced by MOSFETs and
IGBTs. However, BJTs can be used in many applications. The BJT is a current-
controlled device, requiring a base current to maintain the transistor in the con-
ducting state. Base current during the on state for a collector current IC must be at
least IC /. The turn-on time depends on how rapidly the required stored charge
can be delivered to the base region. Turn-on switching speeds can be decreased by
initially applying a large spike of base current and then reducing the current to that
required to keep the transistor on. Similarly, a negative current spike at turnoff is
desirable to remove the stored charge, decreasing transition time from on to off.
Figure 10-7a shows a circuit arrangement that is suitable for BJT drives.
When the input signal goes high, R2 is initially bypassed by the uncharged capac-
itor. The initial base current is
Vi vBE
IB1 (10-1)
R1
As the capacitor charges, the base current is reduced and reaches a final value of
Vi vBE
IB2 (10-2)
R1 R2
The desired charging time of the capacitor determines its value. Three to five
time constants are required to charge or discharge the capacitor. The charging
time constant is
R1R2
RE C a bC (10-3)
R1 R2
The input signal goes low at turnoff, and the charged capacitor provides a nega-
tive current spike as the base charge is removed. Figure 10-7b shows the base
current waveform.
iB
Vs IB1
Turn-on
Load On
C IB2
t
vi
R1 R2 iB Turnoff
(a) (b)
Figure 10.7 (a) Drive circuit for a bipolar transistor; (b) Transistor base current.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 438
EXAMPLE 10.2
Bipolar Transistor Drive Circuit

Design a BJT base drive circuit with the configuration of Fig. 10-7a that has a spike of
1 A at turn-on and maintains a base current of 0.2 A in the on state. The voltage vi is a
pulse of 0 to 15 V with a 50 percent duty ratio, and the switching frequency is 100 kHz.
Assume that vBE is 0.9 V when the transistor is on.
■ Solution
The value of R1 is determined from the initial current spike requirement. Solving for R1
in Eq. (10-1),
Vi vBE 15 0.9
R1 14.1 Æ
IB1 1
The steady-state base current in the on state determines R2. From Eq. (10-2),
Vi vBE 15 0.9
R2 R1 14.1 56.4 Æ
IB2 0.2
The value of C is determined from the required time constant. For a 50 percent duty ratio
at 100 kHz, the transistor is on for 5 s. Letting the on time for the transistor be five time
constants, 1 s. From Eq. (10-3),
RE C a
R1R2
b C 11.3 C 1 s
R1 R2
C 88.7 nF
EXAMPLE 10.3
PSpice Simulation for a BJT Drive Circuit

Use PSpice to simulate the circuit of Fig. 10-8a with Vs 80 V, a 10- load resistor, and
the base drive components from Example 10-2: (a) with the base capacitor omitted and
(b) with the base drive capacitor included. Determine the power absorbed by the transis-
tor for each case. Use the 2n5686 PSpice model from ON Semiconductor.
■ Solution
The circuit of Fig. 10-8a is created using VPULSE for the control voltage source. The
transistor model is obtained from the ON Semiconductor website, and the model is
copied and pasted into the QbreakN transistor model by choosing Edit, PSpice Model.
The resulting switching waveforms are shown in Fig. 10-8. Note the significant dif-
ference in switching times with and without the base drive capacitance. Power absorbed
by the transistor is determined by entering AVG(W(Q1)) which yields results of 30 W
without the base capacitor and 5 W with the capacitor.
Switching times can be reduced by keeping the transistor in the quasi-saturation

region, which is just past the linear region but not in hard saturation. This is
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 439
10.3 Bipolar Transistor Drive Circuits 439
BASE CIRCUIT WITHOUT A CAPACITOR

15
VOLTAGE
10
CURRENT
0
TURN ON TURN OFF
–5
40 us 80 us 120 us 160 us 200 us
IC(Ql) V(Q)/8
Time
(a)
BASE CIRCUIT WITH A CAPACITOR

15
VOLTAGE
10
CURRENT
0
TURN ON TURN OFF
–5
50 us 100 us 150 us 200 us
IC(Ql) V(Q)/8
Time
(b)
Figure 10.8 Switching waveforms for a bipolar junction transistor (a) without the base
capacitor and (b) with the base capacitor. The voltage is scaled by 18.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 440
Ds
D1 Dn
D0
Figure 10.9 Baker’s clamp to

control the degree of BJT saturation.
controlled by preventing vCE from going too low. However, on-state conduction
losses for the BJT are larger than if the transistor were further into saturation
where the collector-to-emitter voltage is lower.
A clamping circuit such as the Baker’s clamp of Fig. 10-9 can keep the tran-
sistor in quasi-saturation by limiting the collector-to-emitter voltage. There are n
diodes in series with the base, and a shunting diode Ds is connected from the
drive to the collector. The on-state collector-to-emitter voltage is determined
from Kirchhoff’s voltage law as
vCE vBE nvD vDs (10-4)
The desired value of vCE is determined by the number of diodes in series with the
base. Diode Do allows reverse base current during turnoff.
10.4 THYRISTOR DRIVE CIRCUITS

Thyristor devices such as SCRs require only a momentary gate current to turn the
device on, rather than the continuous drive signal required for transistors. The
voltage levels in a thyristor circuit may be quite large, requiring isolation
between the drive circuit and the device. Electrical isolation is accomplished by
magnetic or optical coupling. An elementary SCR drive circuit employing mag-
netic coupling is shown in Fig. 10-10a. The control circuit turns on the transistor
and establishes a voltage across the transformer primary and secondary, provid-
ing the gate current to turn on the SCR.
The simple gate drive circuit of Fig. 10-10b can be used in some applications
where electrical isolation is not required. The circuit is a single-phase voltage con-
troller (Chap. 5) of the type that might be used in a common light dimmer. An
SCR could be used in place of the triac T1 to form a controlled half-wave rectifier
(Chap. 3). The delay angle is controlled by the RC circuit connected to the gate
through the diac T2. The diac is a member of the thyristor family that operates as
a self-triggered triac. When the voltage across the diac reaches a specified value,
it begins to conduct and triggers the triac. As the sinusoidal source voltage goes
positive, the capacitor begins to charge. When the voltage across the capacitor
reaches the diac trigger voltage, gate current is established in the triac for turn-on.
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10.5 Transistor Snubber Circuits 441
Load
R T2 T1
Control
C
(a) (b)
Figure 10.10 (a) Magnetically coupled thyristor drive circuit; (b) Simple RC
drive circuit.
10.5 TRANSISTOR SNUBBER CIRCUITS

Snubber circuits reduce power losses in a transistor during switching (although
not necessarily total switching losses) and protect the device from the switching
stresses of high voltages and currents.
As discussed in Chap. 6, a large part of the power loss in a transistor occurs
during switching. Figure 10-11a shows a model for a converter that has a large
inductive load which can be approximated as a current source IL. The analysis of
switching transitions for this circuit relies on Kirchhoff’s laws: the load current
must divide between the transistor and the diode; and the source voltage must
divide between the transistor and the load.
In the transistor on state, the diode is off and the transistor carries the load
current. As the transistor turns off, the diode remains reverse-biased until the
vQ
Vs
Vs
iQ
IL
+
IL DL vL
– Turnoff Turn-on t
(b)
iQ
+
vQ p(t)
–
ts tf t
(a) (c)
Figure 10.11 (a) Converter model for switching inductive loads;

(b) Voltage and current during switching; (c) Instantaneous power
for the transistor.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 442
transistor voltage vQ increases to the source voltage Vs and the load voltage vL
decreases to zero. After the transistor voltage reaches Vs, the diode current
increases to IL while the transistor current decreases to zero. As a result, there is
a point during turnoff when the transistor voltage and current are high simulta-
neously (Fig. 10-11b), resulting in a triangularly shaped instantaneous power
waveform pQ(t), as in Fig. 10-11c.
In the transistor off state, the diode carries the entire load current. During
turn-on, the transistor voltage cannot fall below Vs until the diode turns off,
which is when the transistor carries the entire load current and the diode current
is zero. Again, there is a point when the transistor voltage and current are high
simultaneously.
A snubber circuit alters the transistor voltage and current waveforms to an
advantage. A typical snubber circuit is shown in Fig. 10-12a. The snubber pro-
vides another path for load current during turnoff. As the transistor is turning off
pQ (t)
Vs
vC
iQ
IL DL
i DL
0 tx tf t
iQ
(b)
Ds R
iC vC
+ iQ
C vC pQ (t)
–
0 tf = tx t
(a) (c)
vC
iQ
Vf
pQ(t)
0 tf tx t
(d)
Figure 10.12 (a) Converter with a transistor snubber circuit; (b–d) Turnoff waveforms
with a snubber with increasing values of capacitance.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 443
and the voltage across it is increasing, the snubber diode Ds becomes forward-
biased and the capacitor begins to charge. The rate of change of transistor volt-
age is reduced by the capacitor, delaying its voltage transition from low to high.
The capacitor charges to the final off-state voltage across the transistor and
remains charged while the transistor is off. When the transistor turns on, the
capacitor discharges through the snubber resistor and transistor.
The size of the snubber capacitor determines the rate of voltage rise across
the switch at turnoff. The transistor carries the load current prior to turnoff, and
during turnoff the transistor current decreases approximately linearly until it
reaches zero. The load diode remains off until the capacitor voltage reaches Vs.
The snubber capacitor carries the remainder of the load current until the load
diode turns on. The transistor and snubber-capacitor currents during turnoff are
expressed as
t
IL a 1 b for 0 t t f
tf
i Q (t) d (10-5)
0 t
tf
IL t
IL i Q(t) 0 t tf
tf
i C (t) d IL tf t tx (10-6)
0 t
tx
where tx is the time at which the capacitor voltage reaches its final value, which
is determined by the source voltage of the circuit. The capacitor (and transistor)
voltage is shown for different values of C in Fig. 10-12b to d. A small snubber
capacitor results in the voltage reaching Vs before the transistor current reaches
zero, whereas larger capacitance results in longer times for the voltage to reach
Vs. Note that the energy absorbed by the transistor (the area under the instanta-
neous power curve) during switching decreases as the snubber capacitance
increases.
The capacitor is chosen on the basis of the desired voltage at the instant the
transistor current reaches zero. The capacitor voltage in Fig. 10-12d is expressed as
t
1 IL t I t2
dt L 0 t tf
C L tf 2Ctf
0
t
1 I I t
vc (t) h IL dt vc (t f) L (t t f) L f tf t tx (10-7)
CL C 2C
tf
Vs t
tx
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If the switch current reaches zero before the capacitor fully charges, the capaci-
tor voltage is determined from the first part of Eq. (10-7). Letting vc(tf) Vf ,
IL(t f)2 ILt f
Vf
2Ct f 2C
Solving for C,
ILt f
C (10-8)
2Vf
where Vf is the desired capacitor voltage when the transistor current reaches zero
(Vf Vs). The capacitor is sometimes selected such that the switch voltage
reaches the final value at the same time that the current reaches zero, in which
case
ILt f
C (10-9)
2Vs
where Vs is the final voltage across the switch while it is open. Note that the
final voltage across the transistor may be different from the dc supply voltage in
some topologies. The forward and flyback converters (Chap. 7), for example,
have off-state switch voltages of twice the dc input.
The power absorbed by the transistor is reduced by the snubber circuit. The
power absorbed by the transistor before the snubber is added is determined from
the waveform of Fig. 10-11c. Turnoff power losses are determined from
T
1
PQ p (t) dt (10-10)
T3 Q
0
The integral is evaluated by determining the area under the triangle for turnoff,
resulting in an expression for turnoff power loss without a snubber of
1
PQ ILVs (t s t f) f (10-11)
2
where ts tf is the turnoff switching time and f 1/T is the switching frequency.
Power absorbed by the transistor during turnoff after the snubber is added is
determined from Eqs. (10-5), (10-7), and (10-10).
T tf
1 I t2 t I 2L t 2f f
PQ vQi Q dt f a L b IL a 1 b dt (10-12)
T3 3 2Ct f tf 24C
0 0
The above equation is valid for the case when tf tx, as in Fig. 10-12c or d.
The resistor is chosen such that the capacitor is discharged before the next
time the transistor turns off. A time interval of three to five time constants is
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 445
necessary for capacitor discharge. Assuming five time constants for complete
discharge, the on time for the transistor is
t on 5RC
or
t on
R (10-13)
5C
The capacitor discharges through the resistor and the transistor when the transis-
tor turns on. The energy stored in the capacitor is
W 12 CV 2s (10-14)
This energy is transferred mostly to the resistor during the on time of the transis-
tor. The power absorbed by the resistor is energy divided by time, with time
equal to the switching period:
1
CV 2s 1
PR 2 CV 2s f (10-15)
T 2
where f is the switching frequency. Equation (10-15) indicates that power dissi-
pation in the snubber resistor is proportional to the size of the snubber capacitor.
A large capacitor reduces the power loss in the transistor [Eq. (10-12)], but at
the expense of power loss in the snubber resistor. Note that the power in the snub-
ber resistor is independent of its value. The resistor value determines the dis-
charge rate of the capacitor when the transistor turns on.
The power absorbed by the transistor is lowest for large capacitance, but the
power absorbed by the snubber resistor is largest for this case. The total power
for transistor turnoff is the sum of the transistor and snubber powers. Figure 10-13
shows the relationship among transistor, snubber, and total losses. The use of the
Losses
Total
Snubber
Transistor
Figure 10.13 Transistor, snubber,

and total turnoff losses as a function
of snubber capacitance.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 446
snubber can reduce the total switching losses, but perhaps more importantly, the
snubber reduces the power loss in the transistor and reduces the cooling require-
ments for the device. The transistor is more prone to failure and is harder to cool
than the resistor, so the snubber makes the design more reliable.
EXAMPLE 10.4
Transistor Snubber Circuit Design

The converter and snubber in Fig. 10-12a has Vs 100 V and IL 5 A. The switching
frequency is 100 kHz with a duty ratio of 50 percent, and the transistor turns off in 0.5 s.
(a) Determine the turnoff losses without a snubber if the transistor voltage reaches Vs in
0.1 s. (b) Design a snubber using the criterion that the transistor voltage reaches its final
value at the same time that the transistor current reaches zero. (c) Determine the transis-
tor turnoff losses and the resistor power with the snubber added.
■ Solution
(a) The turnoff voltage, current, and instantaneous power waveforms without the snubber
are like those of Fig. 10-11. Transistor voltage reaches 100 V while the current is
still at 5 A, resulting in a peak instantaneous power of (100 V)(5 A) 500 W. The
base of the power triangle is 6 µs, making the area 0.5(500 W)(0.6 µs) 150 µJ.
The switching period is 1/f 1/100,000 s, so the turnoff power loss in the transis-
tor is W/T (150)(106)(100,000) 15 W. Equation (10-11) yields the same result:
1 1
PQ ILVs(t s t f) f (5)(100)(0.1 0.5)(10 6)(10 5) 15 W
2 2
(b) The snubber capacitance value is determined from Eq. (10-9):
IL t f (5)(0.5)(10 6)
C 1.25(10 8) 0.0125 F 12.5 nF
2Vs (2)(100)
The snubber resistor is chosen using Eq. (10-13). The switching frequency is 100 kHz
corresponding to a switching period of 10 s. The on time for the transistor is
approximately one-half of the period, or 5 s. The resistor value is then
t on 5 s
R 80 Æ
5C 5(0.0125 F)
The resistance value is not critical. Since five time constants is a conservative
design criterion, the resistance need not be exactly 80 .
(c) The power absorbed by the transistor is determined from Eq. (10-12):
I 2L t 2f f 52[(0.5)(10 6)]2(10 5)
PQ 2.08 W
24C 24(1.25)(10 8)
Power absorbed by the snubber resistor is determined from Eq. (10-15):
1 0.0125(10 6)(100 2)(100,000)

PR CV 2s f 6.25 W
2 2
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 447
Total power due to turnoff losses with the snubber is 2.08 6.25 8.33 W, reduced from
15 W without the snubber. The losses in the transistor are significantly reduced by the
snubber, and total turnoff losses are also reduced in this case.
The other function of the snubber circuit is to reduce voltage and current
stresses in the transistor. The voltage and current in a transistor must not exceed
the maximum values. Additionally, the transistor temperature must be kept
within allowable limits. High current at a high voltage must also be avoided in a
bipolar transistor because of a phenomenon called second breakdown. Second
breakdown is the result of nonuniform distribution of current in the collector-
base junction when both voltage and current are large, resulting in localized heat-
ing in the transistor and failure.
The forward-bias safe operating area (SOA or FBSOA) of a BJT is the area
enclosed by the voltage, current, thermal, and second breakdown limits, as
shown in Fig. 10-14a. The FBSOA indicates the capability of the transistor when
i i
Imax Temperature
Limit
Second Breakdown
Limit (BJT) RBSOA
SOA
Vmax v v
(a) (b)
Without snubber
isw
C1
C1 < C2 < C3
C2
C3
Vsw
(c)
Figure 10.14 Transistor. (a) Safe operation area; (b) Reverse-bias safe operating
area; (c) Switching trajectories for different snubber capacitance.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 448
+
Vs
–
Figure 10.15 Alternate placement of a

snubber for the forward converter
the base-emitter junction is forward-biased. The FBSOA indicates maximum

limits for steady-state and for turn-on. The SOA can be expanded vertically for
pulsed operation. That is, current can be greater if it is intermittent rather than
continuous. In addition, there is a reverse-bias safe operating area (RBSOA),
shown in Fig. 10-14b. Forward bias and reverse bias refer to the biasing of the
base-emitter junction. The voltage-current trajectory of the switching waveforms
of Fig. 10-12 is shown in Fig. 10-14c. A snubber can alter the trajectory and pre-
vent operation outside of the SOA and RBSOA. Second breakdown does not
occur in a MOSFET.
Alternative placements of the snubber circuit are possible. The forward
converter is shown in Fig. 10-15 with a snubber connected from the transistor
back to the positive input supply rather than to ground. The snubber functions
like that of Fig. 10-12, except that the final voltage across the capacitor is Vs
rather than 2Vs.
One source of voltage stress in a transistor switch is the energy stored in the
leakage inductance of a transformer. The flyback converter model of Fig. 10-16,
for example, includes the leakage inductance Ll, which was neglected in the
analysis of the converters in Chap. 7 but is important when analyzing the stresses
on the switch. The leakage inductance carries the same current as the transistor
switch when the transistor is on. When the transistor turns off, the current in the
leakage inductance cannot change instantaneously. The large di/dt from the
rapidly falling current can cause a large voltage across the transistor.
The snubber circuit of Fig. 10-12 can reduce the voltage stress across the
transistor in addition to reducing transistor losses. The diode-capacitor-resistor
combination provides a parallel current path with the transistor. When the tran-
sistor turns off, the current maintained by the transformer leakage inductance
forward-biases the diode and charges the capacitor. The capacitor absorbs energy
that was stored in the leakage inductance and reduces the voltage spike that
would appear across the transistor. This energy is dissipated in the snubber resis-
tor when the transistor turns on.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 449
Lm
+
Vs Ll
–
Figure 10.16 Flyback converter

with transformer leakage induc-
tance included.
Turn-on snubbers protect the device from simultaneously high voltage and
current during turn-on. As with the turnoff snubber, the purpose of the turn-on
snubber is to modify the voltage-current waveforms to reduce power loss. An
inductor in series with the transistor slows the rate of current rise and can reduce
the overlap of high current and high voltage. A turn-on snubber is shown in
Fig. 10-17. The snubber diode is off during turn-on. During turnoff, the energy
stored in the snubber inductor is dissipated in the resistor.
If a turnoff snubber is also used, the energy stored in the turn-on snubber
inductor can be transferred to the turnoff snubber without the need for the addi-
tional diode and resistor. Leakage or stray inductance that inherently exists in cir-
cuits may perform the function of a turn-on snubber without the need for an
additional inductor.
Vs
IL DL
R
Ls
Ds
Figure 10.17
Transistor turnon
snubber.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 450
10.6 ENERGY RECOVERY SNUBBER CIRCUITS

Snubber circuits reduce the power dissipated in the transistor, but the snubber
resistor also dissipates power that is lost as heat. The energy stored in the snub-
ber capacitance is eventually transferred to the snubber resistor. If the energy
stored in the snubber capacitor can be transferred to the load or back to the
source, the snubber resistor is not necessary, and the losses are reduced.
One method for energy recovery in a snubber is shown in Fig. 10-18. Both
Ds and Cs act like the snubber of Fig. 10-12a at turnoff: Cs charges to Vs and
delays the voltage rise across the transistor. At turn-on, a current path consisting
of Q, Cs, L, D1, and C1 is formed, and an oscillatory current results. The charge
initially stored in Cs is transferred to C1. At the next turnoff, C1 discharges
through D2 into the load while Cs charges again. Summarizing, the energy stored
in Cs at turnoff is first transferred to C1 and is then transferred to the load.
10.7 THYRISTOR SNUBBER CIRCUITS

The purpose of a thyristor snubber circuit is mainly to protect the device from
large rates of change of anode-to-cathode voltage and anode current. If dv/dt for
the thyristor is too large, the device will begin to conduct without a gate signal
present. If di/dt is too large during turn-on, localized heating will result from the
high current density in the region of the gate connection as the current spreads
out over the whole junction.
Thyristor snubber circuits can be like those used for the transistor, or they
may be of the unpolarized type shown in Fig. 10-19. The series inductor limits
di/dt, and the parallel RC connection limits dv/dt.
Vs
Load DL D2
C1 D1 Cs
L Rs
Ds
Q Cs
Ls
Figure 10.18 Snubber Figure 10.19

circuit with energy Thyristor snubber
recovery. circuit.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 451
10.8 Heat Sinks and Thermal Management 451
T1
P Rθ
T2
Figure 10.20 An elec-

tric circuit equivalent
to determine tempera-
ture difference.
10.8 HEAT SINKS AND THERMAL MANAGEMENT

Steady-State Temperatures
As discussed throughout this textbook, conduction and switching losses occur in
electronic devices. Those losses represent electrical-energy being converted to
thermal energy, and removal of thermal energy is essential in keeping the inter-
nal temperature of the device below its maximum rated value.
In general, the temperature difference between two points is a function of
thermal power and thermal resistance. Thermal resistance is defined as
T1 T2
R (10-16)
P
where R thermal resistance, C/W (also listed as K/W on some datasheets)
T1 T2 temperature difference, C
P thermal power, W
A useful electric circuit analog for steady-state thermal calculations that fits
Eq. (10-16) uses P as a current source, R as electrical resistance, and voltage dif-
ference as temperature difference, as illustrated in Fig. 10-20.
The internal temperature of an electronic switching device is referred to as
the junction temperature. Although devices such as MOSFETs do not have a
junction per se when conducting, the term is still used. In an electronic device
without a heat sink, the junction temperature is determined by thermal power and
the junction-to-ambient thermal resistance R ,JA. The ambient temperature is that
of the air in contact with the case. Manufacturers often include the value of R ,JA
on the datasheet for the device.
EXAMPLE 10.5
MOSFET Maximum Power Absorption

A MOSFET manufacturer’s datasheet lists the junction-to-ambient thermal resistance
R ,JA as 62C/W. The maximum junction temperature is listed at 175C, but the designer
wishes for it not to exceed 150C for increased reliability. If the ambient temperature is
40C, determine the maximum power that the MOSFET can absorb.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 452
■ Solution
From Eq. (10-16),
T1 T2 T TA 150 40
P J 1.77 W
R R , JA 62
In many instances, the power absorbed by a device results in an excessive

junction temperature, and a heat sink is required. A heat sink reduces the junction
temperature for a given power dissipation in a device by reducing the overall
thermal resistance from junction to ambient. The case of the device is often
attached to the heat sink with a thermal compound to fill the small voids between
the imperfect surfaces of the case and sink. Heat sinks are available in all sizes,
ranging from small clip-on devices to massive extruded aluminum shapes.
Typical heat sinks are shown in Fig. 10-21.
For an electronic device with a heat sink, thermal power flows from the junc-
tion to the case, from the case to the heat sink, and then from the heat sink to
ambient. The corresponding thermal resistances are R ,JC, R ,CS, and R ,SA, as
shown in Fig. 10-22.
The temperature at the heat sink near the mounting point of the electronic
device is
TS PR , SA TA (10-17)
the temperature at the device case is

TC PR , CS TS P(R , CS R , SA) TA (10-18)
and the temperature at the device junction is
TJ PR , JC TC P(R , JC R , CS R , SA) TA (10-19)
Semiconductor manufacturers’ datasheets list the junction-to-case thermal resis-

tance and often list the case-to-heat sink thermal resistance assuming a greased
surface. The heat sink-to-ambient thermal resistance is obtained from the heat
sink manufacturer.
Figure 10.21 Power transistors mounted on heat sinks.

har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 453
TJ Junction
Rq, JC
TC Case
P Rq,CS
TS Heat sink
Rq,SA
TA Ambient
Figure 10.22 The electrical

circuit equivalent for a
transistor mounted to a heat
sink.
EXAMPLE 10.6
MOSFET Junction Temperature with a Heat sink

The datasheet for the MOSFET in Example 10-5 lists the thermal resistance from the
junction to case as 1.87C/W and the thermal resistance from the case to the heat sink as
0.50C/W. (a) If the device is mounted on a heat sink that has a thermal resistance of
7.2C/W, determine the maximum power that can be absorbed without exceeding a junc-
tion temperature of 150C when the ambient temperature is 40C. (b) Determine the junc-
tion temperature when the absorbed power is 15 W. (c) Determine R ,SA of a heat sink that
would limit the junction temperature to 150C for 15 W absorbed.
■ Solution
(a) From Eq. (10-19),
TJ TA 150 40 110
P 11.5 W
R , JC R , CS R , SA 1.87 0.50 7.2 9.57
Comparing this result with that of Example 10-5, including a heat sink reduces the
junction-to-ambient thermal resistance from 62 to 9.57C/W and enables more
power to be absorbed by the device without exceeding a temperature limit. If the
MOSFET absorbs 1.77 W as in Example 10-5, the junction temperature with this
heat sink will be
TJ P(R , JC R , CS R , SA) TA
1.77(1.87 0.50 7.2) 40 56.9° C
compared to 150C without the heat sink.

(b) Also from Eq. (10-19), the junction temperature for 15 W is
TJ P(R , JC R , CS R , SA) TA 15(1.87 0.50 7.2) 40 184° C

har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 454
(c) Solving Eq. (10-19) for R ,SA for a heat sink that would limit the junction tempera-
ture to 150C,
TJ TA 150 40
R , SA R , JC R , CS 1.87 0.50 4.96°C>W
P 15
Time-Varying Temperatures
Temperatures resulting from a time-varying thermal power source are analyzed
using an equivalent circuit like that of Fig. 10-23a. The capacitors represent ther-
mal energy storage, resulting in exponential changes in temperatures for a step
change in the power source, as shown in Fig. 10-23b and c.
This RC model can represent the entire device-case-heat-sink system with
T1, T2, T3, and T4 representing the junction, case, heat sink, and ambient temper-
ature, respectively. The model could also represent just one of those components
T1 Rθ1 T2 Rθ2 T3 Rθ3 T4
P C1 C2 C3
(a)
p(t)
Pdm
0
0 t1 t
(b)
TJ (t)
ΔTJ
TC
(c) t
Figure 10.23 (a) An equivalent circuit representation for a time-

varying thermal power source; (b) A momentary power pulse;
(c) The temperature response due to a power pulse.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 455
10
1
Thermal Response (ZthJC)
D = 0.50
0.20
0.1 0.10 R1 R2 R3
Ri (°C/W) i (sec)
0.05 tJ tC 0.371 0.000272
0.02 t1 t2 t3
0.337 0.001375
0.01
0.01 Ci = ri-Ri 0.337 0.018713
Notes:
SINGLE PULSE 1. Duty Factor D = t1/t2
(THERMAL RESPONSE) 2. Peak Tj = Pdm × Zthjc + Tc
0.001
1E–006 1E–005 0.0001 0.001 0.01 0.1
t1, Rectangular Pulse Duration (sec)
Figure 10.24 Thermal impedance characteristics of the IRF4104 MOSFET. (Courtesy of International
Rectifier Corporation).
that has been subdivided into multiple sections. For example, it could represent
just the junction to case of the device divided into three sections.
Transient thermal impedance from the junction to the case Z ,JC is used to
determine the change in junction temperature due to momentary changes in
absorbed power. Manufacturers typically supply transient thermal impedance
information on datasheets. Figure 10-24 shows a graphical representation of Z ,JC
as well as the RC equivalent circuit representation for the junction to case for the
IRF4104 MOSFET. Transient thermal impedance is also denoted as Zth.
First, consider the increase in junction temperature due to a single power
pulse of amplitude Pdm lasting for a duration t1, as shown in Fig. 10-23b. The
thermal model of Fig. 10-23a produces an exponential junction temperature vari-
ation like that of Fig. 10-23c. The change in the temperature of the junction in the
time interval 0 to t1 is determined from
TJ Pdm Z , JC (10-20)
where Z ,JC is the transient thermal impedance from the device junction to case.
The maximum junction temperature is TJ plus the case temperature.
TJ, max Pdm Z ,JC TC (10-21)
EXAMPLE 10.7
Transient Thermal Impedance

A single power pulse of 100 W with a 100-s duration occurs in a MOSFET that has the
transient thermal resistance characteristics shown in Fig. 10-24. Determine the maximum
change in junction temperature.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 456
■ Solution
The bottom curve on the graph gives the thermal impedance for a single pulse. For 100 s
(0.0001 s), Z ,JC is approximately 0.11C/W. Using Eq. (10-20), the increase in junction
temperature is
TJ Pdm Z , JC 100(0.11) 11° C
Next, consider the pulsed power waveform shown in Fig. 10-25a. Junction
temperature increases during the power pulse and decreases when the power is
zero. After an initial start up interval, the junction temperature reaches equilib-
rium where thermal energy absorbed in one period matches the thermal energy
transferred. Maximum junction temperature TJ,max is found using Eq. (10-21) and
Z ,JC from Fig. 10-24. The horizontal axis is t1, the time duration of the pulse in
each period. The value of Z ,JC is read from the curve corresponding to the duty
ratio t1/t2. The temperature of the case is assumed constant and can be determined
from Eq. (10-18) using the average power for P.
If the power pulse is at a high frequency, such as the switching frequency
of a typical power converter, the fluctuation in the temperature waveform of
Fig. 10-25b becomes small, and temperatures can be analyzed by using R ,JC in
Eq. (10-19) with P equal to the average power.
EXAMPLE 10.8
Maximum Junction Temperature for Periodic Pulsed Power

The power absorbed by a MOSFET is the pulsed-power waveform like that of Fig. 10-25a
with Pdm 100 W, t1 200 s, and t2 2000 s. (a) Determine the peak temperature
difference between the junction and the case, using the transient thermal impedance from
p(t)
Pdm
0
0 t1 t2 t
(a)
TJ,max
TJ (t)
(b) t
Figure 10.25 (a) A pulsed power waveform; (b) The temperature

variation at the junction.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 457
Fig. 10-24. Assume that the case temperature is a constant 80C. (b) The thermal resis-
tance R ,JC for this MOSFET is 1.05C/W. Compare the result in (a) with a calculation
based on the average MOSFET and R ,JC.
■ Solution
(a) The duty ratio of the power waveform is
t1 200 s
D 0.1
t2 2000 s
Using the graph in Fig. 10-24, the transient thermal impedance Z ,JC for t1 200 s
and D 0.1 is approximately 0.3C/W. The maximum temperature difference
between the junction and the case is determined from Eq. 10-20 as
TJ Pdm Z , JC 100(0.3) 30°
making the maximum junction temperature
TJ, max Pdm Z ,JC TC 30 80 110°C
(b) Using the average power only, the temperature difference from the junction to case
would be calculated as TJ PR , JC (PdmD)R , JC (10 W)(1.05°C>W)
10.5°C. Therefore, a temperature calculation based on the average power greatly
underestimates the maximum temperature difference between the junction and the
case. Note that a period of 2000 µs corresponds to a frequency of only 500 Hz. For
much higher frequencies (e.g., 50 kHz), the temperature difference based on R ,JC
and average power is sufficiently accurate.
10.9 Summary
The switching speed of a transistor is determined not only by the device but also by the
gate or base drive circuit. The double emitter-follower drive circuit for the MOSFET (or
IGBT) significantly reduces the switching time by sourcing and sinking the required gate
currents to supply and remove the stored charge in the MOSFET rapidly. A base drive cir-
cuit that includes large current spikes at turn-on and turnoff for the bipolar transistor sig-
nificantly reduces switching times.
Snubber circuits reduce power losses in the device during switching and protect the
device from the switching stresses of high voltages and currents. Transistor switching
losses are reduced by snubbers, but total switching losses may or may not be reduced
because power is dissipated in the snubber circuit. Energy recovery snubber circuits can
further reduce the switching losses by eliminating the need for a snubber resistor.
Heat sinks reduce the internal temperature of an electronic device by reducing the total
thermal resistance between the device junction and ambient. Equivalently, a heat sink
enables a device to absorb more power without exceeding a maximum internal temperature.
10.10 Bibliography
M. S. J. Asghar, Power Electronics Handbook, edited by M. H. Rashid, Academic Press,
San Diego, Calif., 2001, Chapter 18.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 458
L. Edmunds, “Heatsink Characteristics,” International Rectifier Application Note

AN-1057, 2004, http://www.irf.com/technical-info/appnotes/an-1057.pdf.
Fundamentals of Power Semiconductors for Automotive Applications, 2d ed., Infineon
Technologies, Munich, Germany, 2008.
“HV Floating MOS-Gate Driver ICs,” Application Note AN-978, International Rectifier,
Inc., El Segunda, Calif., July 2001. http://www.irf.com/technical-info/ appnotes/
an-978.pdf.
A. Isurin and A. Cook, “Passive Soft-Switching Snubber Circuit with Energy
Recovery,” IEEE Applied Power Electronics Conference, austin, Tex., 2008.
S. Lee, “How to Select a Heat Sink,” Aavid Thermalloy, http://www.aavidthermalloy
.com/technical/papers/pdfs/select.pdf
W. McMurray, “Selection of Snubber and Clamps to Optimize the Design of Transistor
Switching Converters,” IEEE Transactions on Industry Applications, vol. IAI6,
no. 4, 1980, pp. 513–523.
R. E. Tarter, Solid-State Power Conversion Handbook, Wiley, New York, 1993.
Problems
MOSFET DRIVE CIRCUITS
10-1 (a) Run the PSpice simulation of the circuits of Example 10-1 and use Probe
to determine the turnoff and turn-on power loss separately. The restrict data
option will be useful. (b) From the PSpice simulations, determine the peak,
average, and rms values of the MOSFET gate current for each simulation.
10-2 Repeat the PSpice simulation in Example 10-1 for the MOSFET drive circuit
of Fig. 10-1a, using R1 75, 50, and 25 . What is the effect of reducing the
drive circuit output resistance?
BIPOLAR TRANSISTOR DRIVE CIRCUITS

10-3 Design a bipolar transistor drive circuit like that shown in Fig. 10-7 with an
initial base current of 5 A at turn-on which reduces to 0.5 A to maintain the
collector current in the on state. The switching frequency is 100 kHz and the
duty ratio is 50 percent.
10-4 Design a bipolar transistor drive circuit like that shown in Fig. 10-7 with an
initial base current of 3 A at turn-on which reduces to 0.6 A to maintain the
collector current in the on state. The switching frequency is 120 kHz and the
duty ratio is 30 percent.
SNUBBER CIRCUITS
10-5 For the snubber circuit of Fig. 10-12a, Vs 50, IL 4 A, C 0.05 F, R 5 .,
and tf 0.5 s. The switching frequency is 120 kHz, and the duty ratio is 0.4.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 459
Problems 459
(a) Determine expressions for iQ, ic, and vc during transistor turnoff. (b) Graph
the iQ and vC waveforms at turnoff. (c) Determine the turnoff losses in the
switch and the snubber.
10-6 Repeat Prob. 10-5, using C 0.01 F.
10-7 Design a turnoff snubber circuit like that of Fig. 10-12a for Vs 150 V, IL
10 A, and tf 0.1 s. The switching frequency is 100 kHz, and the duty ratio
is 0.4. Use the criteria that the switch voltage should reach Vs when the switch
current reaches zero and that five time constants are required for capacitor dis-
charge when the switch is open. Determine the turnoff losses for the switch
and snubber.
10-8 Repeat Prob. 10-7, using the criterion that the switch voltage must reach 75 V
when the switch current reaches zero.
10-9 Design a turnoff snubber circuit like that of Fig. 10-12a for Vs 170 V, IL
7 A, and tf 0.5 s. The switching frequency is 125 kHz, and the duty ratio is
0.4. Use the criteria that the switch voltage should reach Vs when the switch
current reaches zero and that five time constants are required for capacitor dis-
charge when the switch is open. Determine the turnoff losses for the switch
and snubber.
10-10 Repeat Prob. 10-9, using the criterion that the switch voltage must reach 125 V
when the switch current reaches zero.
10-11 A switch has a current fall time tf of 0.5 s and is used in a converter that is
modeled as in Fig. 10-11a. The source voltage and the final voltage across the
switch are 80 V, the load current is 5 A, the switching frequency is 200 kHz,
and the duty ratio is 0.35. Design a snubber circuit to limit the turnoff loss in
the switch to 1 W. Determine the power absorbed by the snubber resistor.
10-12 A switch has a current fall time tf of 1.0 s and is used in a converter that is
modeled as in Fig. 10-11a. The source voltage and the final voltage across the
switch are 120 V, the load current is 6 A, the switching frequency is 100 kHz,
and the duty ratio is 0.3. Design a snubber circuit to limit the turnoff loss in
the switch to 2 W. Determine the power absorbed by the snubber resistor.
HEAT SINKS
10-13 A MOSFET with no heat sink absorbs a thermal power of 2.0 W. The thermal
resistance from junction to ambient is 40C/W, if the ambient temperature is
30C. (a) Determine the junction temperature. (b) If the maximum junction
temperature is 150C, how much power can be absorbed without requiring a
heat sink?
10-14 A MOSFET with no heat sink absorbs a thermal power of 1.5 W. The thermal
resistance from junction to ambient is 55C/W, if the ambient temperature is
25C. (a) Determine the junction temperature. (b) If the maximum junction
temperature is 175C, how much power can be absorbed without requiring a
heat sink?
10-15 A MOSFET mounted on a heat sink absorbs a thermal power of 10 W. The
thermal resistances are 1.1C/W from the junction to the case, 0.9C/W for the
case to the heat sink, and 2.5C/W for the heat sink to ambient. The ambient
temperature is 40C. Determine the junction temperature.
har80679_ch10_431-460.qxd 12/16/09 3:58 PM Page 460
10-16 A MOSFET mounted on a heat sink absorbs a thermal power of 5 W. The ther-
mal resistances are 1.5C/W from the junction to the case, 1.2C/W for the
case to the heat sink, and 3.0C/W for the heat sink to ambient. The ambient
temperature is 25C. Determine the junction temperature.
10-17 A MOSFET mounted on a heat sink absorbs a thermal power of 18 W. The
thermal resistances are 0.7C/W from the junction to the case and 1.0C/W for
the case to the heat sink. The ambient temperature is 40C. Determine the
maximum thermal resistance from the heat sink to ambient such that the junc-
tion temperature does not exceed 110C.
10-18 A single thermal power pulse of 500 W with 10 s duration occurs in a MOS-
FET with the transient thermal impedance characteristic of Fig. 10-24.
Determine the change in junction temperature due to this pulse.
10-19 In Example 10-8, the switching frequency is 500 Hz. If the switching fre-
quency is increased to 50 kHz with D remaining at 0.1 and Pdm remaining at
100 W, determine the change in junction temperature, (a) using the transient
thermal impedance Z ,JC from Fig. 10-24 and (b) using R ,JC 1.05C/W and
the average transistor power.
har80679_appa_461-466.qxd 12/3/09 4:24 PM Page 461
A P P E N D I X A
Fourier Series for Some
Common Waveforms
FOURIER SERIES
The Fourier series for a periodic function f(t) can be expressed in trigonometric
form as
f(t) a0 a [an cos (n 0 t) bn sin (n 0 t)]

n1
T/2
1
where a0 f (t)dt
T 3
T/2
T/2
2
an f (t) cos(n 0 t) dt
T 3
T/2
T/2
2
bn f (t) sin (n 0 t) dt
T 3
T/2
Sines and cosines of the same frequency can be combined into one sinusoid,
resulting in an alternative expression for a Fourier series
461
462 APPENDIX A Fourier Series for Some Common Waveforms
f(t) a0 a Cn cos(n 0 t n)
n1
bn
where Cn 2a 2n b 2n and n tan1 a b
an
or
q
f(t) a0 a Cn sin (n 0 t n)

n1
an
where Cn 2a 2n b 2n and n tan1 a b
bn
The rms value of f(t) can be computed from the Fourier series.
C 2
a 20 a a n b
q q
2
Frms a F n, rms
A n0 B n1 12
HALF-WAVE RECTIFIED SINUSOID (FIG. A-1)
Vm
T T t
2
Figure A-1 Half-wave rectified sine wave.
Vm Vm q
2Vm
v(t) sin ( 0 t) a 2 cos (n 0 t)
2 n2,4,6Á (n 1)
FULL-WAVE RECTIFIED SINUSOID (FIG. A-2)
Vm
Figure A-2 Full-wave rectified sine wave.

Three-Phase Bridge Rectifier 463
vo(t) Vo a Vn cos (n 0 t )

n2,4, Á
2Vm
where Vo

2Vm 1 1
and Vn a b
n1 n1
THREE-PHASE BRIDGE RECTIFIER (FIG. A-3)

Vm
Figure A-3 Three-phase six-pulse bridge rectifier output.
The Fourier series for a six-pulse converter is

q
vo(t) Vo a Vn cos (n 0 t )

n6,12,18, Á
3Vm,LL
Vo 0.955 Vm,LL

6Vm,LL
Vn n 6, 12, 18, Á
(n 2 1)
where Vm,LL is the peak line-to-line voltage of the three-phase source, which is
12VLL,rms.
The Fourier series of the currents in phase a of the ac line (see Fig. 4-17) is
2 13 1 1 1 1
i a(t) I acos 0 t cos 5 0 t cos 7 0 t cos 11 0 t cos 13 0 t Á b
o 5 7 11 13
which consists of terms at the fundamental frequency of the ac system and

harmonics of order 6k 1, k 1, 2, 3, . . . .
PULSED WAVEFORM (FIG. A-4)
Vm
DT T t
Figure A-4 A pulsed waveform.
a0 Vm D
Vm
an a b sin (n2D)
n
Vm
bn a b [1 cos (n2D)]
n
12Vm
Cn a b 21 cos(n2D)
n
SQUARE WAVE (FIG. A-5)
Vdc
0 T T t
2
−Vdc
Figure A-5 Square wave.
The Fourier series contains the odd harmonics and can be represented as
4Vdc
vo (t) a a b sin(n0 t)
n odd n
Three-Phase Six-Step Inverter 465
MODIFIED SQUARE WAVE (FIG. A-6)
+Vdc
α α α α
0 π 2π wt
−Vdc
Figure A-6 A modified square wave.
The Fourier series of the waveform is expressed as
vo (t) a Vn sin (n0 t)

n odd
Taking advantage of half-wave symmetry, the amplitudes are
4Vdc
Vn a b cos (n )
n
where is the angle of zero voltage on each end of the pulse.
THREE-PHASE SIX-STEP INVERTER (FIG. A-7)
vAN
2
V
3 dc
1
Vdc
3
0
1
− Vdc
3
2
− Vdc
3
Figure A-7 Three-phase six-step inverter output.
The Fourier series for the output voltage has a fundamental frequency equal
to the switching frequency. Harmonic frequencies are of order 6k 1 for k 1,
2, . . . (n 5, 7, 11, 13, . . .). The third harmonic and multiples of the third do not
exist, and even harmonics do not exist. For an input voltage of Vdc, the output
for an ungrounded wye-connected load (see Fig. 8-17) has the following Fourier
coefficients:

Vn, LL `
4Vdc
cos a n b `
n 6
2Vdc 2
Vn, LN ` c 2 cos a n b cos a n b d ` n 1,5,7,11,13, Á
3n 3 3
har80679_appb_467-472.qxd 12/16/09 4:34 PM Page 467
A P P E N D I X B
State-Space Averaging
The results of the following development are used in Sec. 7.13 on control of dc
power supplies. A general method for describing a circuit that changes over a
switching period is called state-space averaging. The technique requires two sets
of state equations which describe the circuit: one set for the switch closed and
one set for the switch open. These state equations are then averaged over the
switching period. A state-variable description of a system is of the form
#
x Ac Bv (B-1)
v o C Tx (B-2)
The state equations for a switched circuit with two resulting topologies are as
follows:
switch closed switch open
# #
x A1x B1v x A2x B2v (B-3)
vo C T1 x vo C T2 x
L L
iL iC iR iL iC iR
+ rC rC
Vs R R
− + +
C vC C vC
− −
(a) (b)
Figure B-1 Circuits for developing the state equations for the buck converter circuit
(a) for the switch closed and (b) for the switch open.
467
468 APPENDIX B State-Space Averaging
For the switch closed for the time dT and open for (1 d)T, the above equations
have a weighted average of
#
x [A1d A2(1 d)]x [B1d B2(1 d)]v (B-4)
vo C C T1 d C T2 (1 d) Dx (B-5)
Therefore, an averaged state-variable description of the system is described as in

the general form of Eqs. (B-1) and (B-2) with
A A1d A2 (1 d)
B B1d B2 (1 d) (B-6)
C T C T1 d C T2 (1 d)
SMALL SIGNAL AND STEADY STATE

Small-signal and steady-state analyses of the system are separated by assuming
the variables are perturbed around the steady-state operating point, namely,
x X ~x
~
d D d (B-7)
v V ~v
where X, D, and V represent steady-state values and ~x, ~d, and ~v represent small-
#
signal values. For the steady state, x 0 and the small-signal values are zero.
Equation (B-1) becomes
or 0 AX BV
(B-8)
X A1BV
Vo C TA1BV (B-9)
where the matrices are the weighted averages of Eq. (B-6).

The small-signal analysis starts by recognizing that the derivative of the
steady-state component is zero.
. . .
x X ~x 0 ~x ~x
# #
(B-10)
Substituting steady-state and small-signal quantities into Eq. (B-4),

. ~ ~ ~ ~ ~
x~ {A1 (D d) A2 [1(D d)]}{B1 (D d)B2 [1 (D d)]}(V v ) (B-11)
~
If the products of small-signal terms ~x d can be neglected, and if the input is
assumed to be constant, v V and
.
~ ~
x [A1D A2(1 D)] ~
x [(A1 A2) X (B1 B2 )V ]d (B-12)
State Equations for the Buck Converter 469
Similarly, the output is obtained from Eq. (B-5).

~v C C T C T(1 D) D ~x C AC T C TB X D d~ (B-13)
o 1 2 1 2
STATE EQUATIONS FOR THE BUCK CONVERTER

State-space averaging is quite useful for developing transfer functions for
switched circuits such as dc-dc converters. The buck converter is used as an
example. State equations for the switch closed are developed from Fig. B-1a, and
state equations for the switch open are from Fig. B-1b.
Switch Closed
First, the state equations for the buck converter (also for the forward converter)
are determined for the switch closed. The outermost loop of the circuit in Fig. B-1a
has Kirchhoff’s voltage law equation
di L
L i RR Vs (B-14)
dt
Kirchhoff’s current law gives
dvC
iR iL iC iL C (B-15)
dt
Kirchhoff’s voltage law around the left inner loop gives
di L
L i CrC vC Vs (B-16)
dt
which gives the relation
dvC 1 di
iC C a Vs L L vC b (B-17)
dt rC dt
Combining Eqs. (B-14) through (B-17) gives the state equation

di L RrC R 1
iL vC Vs (B-18)
dt L(R rC) L(R rC) L
Kirchhoff’s voltage law around the right inner loop gives
vC i C rC i R R 0 (B-19)
Combining the above equation with Eq. (B-15) gives the state equation
dvC R 1
iL v (B-20)
dt C(R rC) C(R rC) C
Restating Eqs. (B-18) and (B-20) in state-variable form gives

#
x A1x B1Vs (B-21)
#
iL
x c # d
#
where
vC
RrC R

L(R rC) L(R rC)
A1 D T (B-22)
R 1

C(R rC) C(R rC)
1
B1 C L S
0
If rC R,
rC 1

L L
A1 L D T (B-23)
1 1

C RC
Switch Open
The filter is the same for the switch closed as for the switch open. Therefore, the
A matrix remains unchanged during the switching period.
A2 A1
The input to the filter is zero when the switch is open and the diode is conduct-
ing. State equation (B-16) is modified accordingly, resulting in
B2 0
Weighting the state variables over one switching period gives
#
xd A1xd B1Vs d
# (B-24)
x(1 d) A2x(1 d) B2Vs(1 d)
Adding the above equations and using A2 A1,
#
x A1x [B1d B2(1 d)]Vs (B-25)
In expanded form,
r 1
# C d
i L L i
c # L d D T c L d C L S Vs (B-26)
vC 1 1 vC
0
C RC
State Equations for the Buck Converter 471
Equation (B-26) gives the averaged state-space description of the output filter
and load of the forward converter or buck converter.
The output voltage vo is determined from
vo vC
vo Ri R R(i L i R) R a i L b (B-27)
rC
Rearranging to solve for vo,
RrC R
vo a b iL a b v L rCi L vC (B-28)
R rC R rC C
The above output equation is valid for both switch positions, resulting in C1T
C2T CT. In state-variable form
v o C Tx
RrC R (B-29)
where CT c d L [rC 1]
R rC R rC
iL
and x c d (B-30)
vC
The steady-state output is found from Eq. (B-9),
Vo C TA1BVs (B-31)
where A A1 A2, B B1D, and CT C1T C2T. The final result of this com-
putation results in a steady-state output of
Vo Vs D (B-32)
The small-signal transfer characteristic is developed from Eq. (B-12), which in
the case of the buck converter results in
. ~
x~ Ax~ BVs d (B-33)
Taking the Laplace transform,
~
sx~(s) Ax~(s) BVs d(s) (B-34)
Grouping ~x (s)
~
[sI A]x~(s) BVs d(s) (B-35)
where I is the identity matrix. Solving for ~x (s),
~x (s) [sI A]1BV d~(s) (B-36)
s
Expressing ~v o(s) in terms of ~x (s),

~v (s) C T~x (s) C T[sI A]1BV d~(s) (B-37)
o s
Finally, the transfer function of output to variations in the duty ratio is expressed as
~v (s)
o T 1
~ C [sI A] BVs (B-38)
d(s)
Upon substituting for the matrices in the above equation, a lengthy evaluation
process results in the transfer function
~
vo(s) Vs 1 srCC
~ c 2 d (B-39)
d(s) LC s s(1/RC rC /L) 1/LC
The above transfer function was used in the section on control of dc power sup-
plies in Chap. 7.
Bibliography
Raton, Fla., 2005.
R. D. Middlebrook and S. Ćuk, “A General Unified Approach to Modelling
Switching—Converter Power Stages,” IEEE Power Electronics Specialists
Conference Record, 1976.
Applications, and Design, 3d ed., Wiley, New Yorks, 2003.
har80679_ndx_473-482.qxd 12/16/09 4:49 PM Page 473
INDEX
A Carrier signal, 357

Ac voltage controller, 171, 172 Charge pump, 247
Ac-ac converter, 171 Chopper, dc, 197
Active power, 22 Class D amplifiers, 366
Adjustable-speed motor drives, 349 Commutation, 103, 160
Amplitude control, 346 Compensation, 308, 317
inverters, 342 Conduction angle, 97, 189
resonant converter, 404 Continuous current, 120, 126, 198
Amplitude modulation ratio, 360 Control, 302
Average power, 22 Control loop, 297, 303
Averaged circuit model, 254 Controlled full-wave rectifier, 131
Controlled half-wave rectifier, 94
Converter
B ac-ac, 2
Battery charger, 24, 120 ac-dc, 2
Bipolar junction transistor, 9, 437 classification, 1
Darlington, 10 dc-ac, 2
Bipolar PWM inverter, 361 dc-dc, 2
Body diode, 10, 207 selection, 298
Boost converter, 211, 244, 301 Crest factor, 50
Bridge rectifier, 111, 114, 131, 160 Cross-over frequency, 304
three phase, 463 Ćuk converter, 226
Buck converter, 198, 310 Current-fed converter, 294
control, 303
design, 207, 208, 210
Buck-boost converter, 221 D
Darlington, 10
Dc link, 382
C Dc link resonant converter, 422
Capacitors, 25 Dc power supplies, 265
average current, 26 complete, 325
average power, 26 off line, 326
ESR, 206 Dc power transmission, 1, 156
stored energy, 25 Dc-dc converter
Capture, 13 boost, 211
473
474 Index
Dc-dc converter —(Cont.) E

buck, 198 Electric arc furnaces, 192
buck-boost, 221 Electronic switch, 5, 65
Cuk, 226 Energy, 22
current-fed, 294 Energy recovery, 27, 32
double-ended forward, 285 Equivalent series resistance (ESR), 206,
flyback, 267 273, 307, 309, 323
forward, 277 Error amplifier, 303, 307, 308, 311
full-bridge, 291 Extinction angle, 70, 72, 77, 96
half-bridge, 291
multiple outputs, 297
push-pull, 287 F
SEPIC, 231 Fast Fourier transform (FFT), 55
switched capacitor, 247 Feedback, 302
Delay angle, 94, 131 Filter
Design capacitor, 88, 122
boost converter, 216 L-C, 126, 323, 404
buck converter, 207, 208, 210 transfer function, 306
Ćuk converter, 230 Flyback converter, 267
flyback converter, 274 Forced response, 67, 76
forward converter, 284 Form factor, 50
half-wave rectifier, 74 Forward converter, 277
inverter, 344, 364 Fourier series, 4, 43, 45
type 2 error amplifier, 311 amplitude control, 343
type 3 error amplifier, 318 common waveforms, 461
Diode, 6 controlled rectifier, 136
fast-recovery, 7 full-wave rectified sine wave, 115
freewheeling, 81 half-wave rectified sine wave, 82
ideal, 17, 72 multilevel inverter, 349
MOSFET body, 9 PSpice, 54
reverse recovery, 7 PWM inverter, 361
Schottky, 7 square-wave inverter, 337
Discontinuous current, 198 three-phase rectifier, 146
Displacement power factor, 49 Freewheeling diode, 81, 86, 103
Distortion factor, 49 Frequency modulation ratio, 360
Distortion volt-amps, 50 Fuel injector, 27
Double-ended forward converter, 285 Full-bridge converter, 291, 331
Drive circuits
BJT, 437
G
high side, 433
Gate turnoff thyristor (GTO), 7
low side, 431
MOSFET, 431
PSpice, 17 H
thyristor, 440 Half-bridge converter, 291
transistor, 8 Half-wave rectifier, 65
Duty ratio, 35, 198 controlled, 94, 95, 99
Index 475
Heat sinks, 450 Multilevel inverters, 348

steady-state temperatures, 450 diode clamped, 354
time-varying temperatures, 454 independent dc sources, 349
High-side drivers, 433 pattern swapping, 353
three phase, 378
I
Induction motor speed control, 379 N
Inductors, 25 National Semiconductor
average power, 25 LM2743 control circuit, 323
average voltage, 25 Natural response, 67, 76
stored energy, 25, 30
Insulated gate bipolar transistor (IGBT), 9,
336, 432
O
Orthogonal functions, 40
Interleaved converters, 237
International Rectifier
IR2110, 435 P
IR2117, 435 Parallel dc-dc resonant converter, 415
IRF150, 16 Passive sign convention, 21
IRF4104, 455 Phase control, 171
IRF9140, 16 Phase margin, 304, 311
Inverter, 2, 142, 331 Power
amplitude control, 342 apparent, 42
full bridge, 331 average, 22, 46, 70, 77, 79
half bridge, 346 complex, 44
harmonic control, 342 computations, 21
multilevel, 348 dc source, 24
PWM, 357 factor, 43, 96
six-step, 373 instantaneous, 21
square wave, 333 reactive, 44
real, 22
Power factor correction, 299
K Probe, 13, 52, 72
K factor, 312, 318
PSpice, 13
average power, 52
L control loop, 311, 315
Light dimmer, 192 controlled rectifier, 100
Linear voltage regulator, 196 convergence, 18
Low-side drivers, 431 dc power supplies, 301
default diode, 17
energy, 52
M Fourier analysis, 54
MOS-controlled thyristor (MCT), 7 half-wave rectifier, 72
MOSFET, 9 ideal diode, 17
drive circuits, 431 instantaneous power, 52
on-state resistance, 10 power computations, 51
476 Index
PSpice —(Cont.) S
rms, 54 Safe operating area (BJT), 447
Sbreak switch, 14 Schottky diode, 7, 207
SCR, 18, 100 Series resonant dc-dc converter, 407
THD, 56 Series resonant inverter, 401
voltage-controlled switch, 14 Series-parallel dc-dc converter, 418
Pulse-width modulation, 307, 357 Silicon controlled rectifier (SCR), 7
Push-pull converter, 287 Single-ended primary inductance converter
PWM control circuits, 323 (SEPIC), 231
Six-pulse rectifier, 145
Six-step three-phase inverter, 373
R Small-signal analysis, 304
Rectifier Snubber circuits
filter capacitor, 88, 122 energy recovery, 449
half-wave, 65 thyristor, 450
three-phase, 144 transistor, 441
Reference voltage, 361 Solenoid, 27
Resonant converter, 387 Solid-state relay, 179
comparison, 421 SPICE, 13
dc link, 422 Stability, 157, 303, 307, 311, 317
parallel resonant dc-dc, 415 State-space averaging, 307, 467
series resonant dc-dc, 407 Static VAR control, 191
series resonant inverter, 401 Stepped parameter, 73
series-parallel dc-dc, 418 Switch selection, 11
zero-current switching, 387 Switched-capacitor converter
zero-voltage switching, 394 inverting, 249
Reverse recovery, 7 step-down, 250
Ripple voltage step-up, 247
boost converter, 215 Switching losses, 240, 241
buck converter, 204 Synchronous rectification, 207
buck-boost converter, 225
Cuk converter, 228
effect of ESR, 206 T
flyback converter, 273 Thermal impedance, 455
Forward converter, 282 Thermal resistance, 451
full-wave rectifier, 124 Three phase
half-wave rectifier, 90, 91 controlled rectifier, 149
push-pull converter, 289 inverter, 154, 373
SEPIC, 234 neutral conductor, 38
Rms, 34 rectifiers, 144
PSpice, 54 voltage controller, 183
pulse waveform, 35 Thyristor, 7
sinusoids, 36 drive circuits, 440
sum of waveforms, 40 snubber circuit, 450
triangular waveform, 41 Time constant, 69, 93
Index 477
Total harmonic distortion (THD), 49, 339 Type 3 compensated error amplifier, 317
Transfer function placement of poles and zeros, 323
filter, 306
PWM, 307
switch, 305 U
Transformer Uninterruptible power supplies (UPS), 331
center tapped, 114 Unipolar PWM inverter, 365
dot convention, 266
leakage inductance, 267
magnetizing inductance, 266 V
models, 265 Voltage doubler, 125
Transient thermal impedance, 455 Vorperian’s model, 259
Transistor switch, 27
Transistors, 8
Triac, 7, 8 Z
Twelve-pulse rectifiers, 151 Zero-current switching, 387
Type 2 compensated error amplifier, 308 Zero-voltage switching, 394

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har80679_FC.

qxd 12/11/09 6:23 PM Page ii

Commonly used Power

Instantaneous power: p(t) ⫽ v(t)i(t)

Average power for a dc voltage source: Pdc ⫽ Vdc Iavg

rms for v ⫽ v1 ⫹ v2 ⫹ v3 ⫹ . . . : Vrms ⫽ 2V 1,2 rms ⫹ V 2,2 rms ⫹ V 3,2 rms ⫹ Á

This book is printed on acid-free paper.

Vice President & Editor-in-Chief: Marty Lange

This book was previously published by: Pearson Education, Inc.

Library of Congress Cataloging-in-Publication Data

To my family, friends, and the many students

Chapter 5 Appendix A Fourier Series for Some

Chapter 1 2.5 Effective Values: RMS 34

3.5 RL-Source Load 75 Capacitance Output Filter 122

5.3 Three-Phase Voltage 6.11 Discontinuous-Current Operation 241

7.8 Current-Fed Converters 294 8.7 Amplitude and Harmonic

of a laboratory experience. In a computer simulation, all the circuit’s voltages

Complete Online Solutions Manual Organization System (COSMOS). Pro-

1.1 POWER ELECTRONICS

1.2 CONVERTER CLASSIFICATION

Figure 1-1 A source and load interfaced by a power electronics converter.

Converters are classified by the relationship between input and output:

1.3 Power Electronics Concepts 3

Figure 1-3 Two converters are used in a multistep process.

1.3 POWER ELECTRONICS CONCEPTS

Figure 1-5 (a) A switched circuit; (b) a pulsed voltage waveform.

1.4 Electronic Switches 5

Vs vx(t) Low-Pass Filter Vo

1.4 ELECTRONIC SWITCHES

1.4 Electronic Switches 7

when it is forward-biased and is an open circuit when reverse-biased. The actual

The triac (Fig. 1-9d) is a thyristor that is capable of conducting current in

1.4 Electronic Switches 9

Figure 1-12 IGBT: (a) Equivalent circuit; (b) circuit symbols.

resulting in a small drain-to-source voltage. In the on state, the change in vDS is

1.5 Switch Selection 11

1.5 SWITCH SELECTION

1.6 SPICE, PSpice, and Capture 13

1.6 SPICE, PSPICE, AND CAPTURE

R = 106 Ω Off (Open)

Figure 1-14 Implementing a switch with a resistance in PSpice.

1.7 SWITCHES IN PSPICE

Parameter Description Default Value

A Voltage-Controlled Switch in PSpice

1.7 Switches in PSpice 15

Switch Control Voltage

Figure 1-15 (continued)

1.7 Switches in PSpice 17

Figure 1-16 An idealized MOSFET drive circuit in PSpice.

where n is the emission coefficient which has a default value of 1 in PSpice. An

model Dbreak D n ⫽ 0.001

Figure 1-17 Simplified thyristor (SCR) model for PSpice.

Convergence Problems in PSpice

Figure 1-19 RC circuit to aid in PSpice convergence.

• Add an RC “snubber” circuit. A series resistance and capacitance with a

L. S. Czarnecki, “Considerations on the Reactive Power in Nonsinusoidal Situations,”

2.2 POWER AND ENERGY

Figure 2-1 (a) Passive

2.2 Power and Energy 23

W p(t) dt 400 dt 300 dt 0 dt 2.4 1.2 1.2 J

(90 V)(450t A) 40,500t W 0 t 10 ms

P VrmsIrms cos ( ) (2-49)

P a Pn V0 I0 a Vn, rms In, rms cos ( n n)