Introduction of ATE

Automatic or Automated Test Equipment (ATE) is any apparatus that

performs tests on a device, known as the Device Under Test(DUT), using
automation to quickly perform measurements and evaluate the test results.
An ATE can be a simple computer controlled digital multi meter, or a
complicated system containing dozens of complex test instruments (real or
simulated electronic test equipment) capable of automatically testing and
diagnosing faults in sophisticated electronic packaged parts or on Wafer
testing, including System-On-Chips and Integrated circuits.

ATE is widely used in the electronic manufacturing industry to test electronic

components and systems after being fabricated. ATE is also used to test
avionics and the electronic modules in automobiles. It is used in military
applications like radar and wireless communication.

Semiconductor ATE, named for testing semiconductor devices, can test a

wide range of electronic devices and systems, from simple components
(resistors, capacitors, and inductors) to integrated circuits (ICs), printed
circuit boards (PCBs), and complex, completely-assembled electronic
systems. ATE systems are designed to reduce the amount of test time
needed to verify that a particular device works or to quickly find its faults
before the part has a chance to be used in a final consumer product. To
reduce manufacturing costs and improve yield, semiconductor devices should
to be tested after being fabricated to prevent even a small number of
defective devices ending up with consumer.

The Semiconductor ATE architecture consists of master controller (usually a

computer) that synchronizes one or more source and capture instruments
(listed below). Historically, custom-designed controllers or relays were used
by ATE systems. The Device under Test (DUT) is physically connected to the
ATE by another robotic machine called a Handler or Prober and through a
customized Interface Test Adapter (ITA) or "fixture" that adapts the ATE's
resources to the DUT.

Most modern semiconductor ATEs include multiple Digital Signal Processing

(DSP) instruments used to measure a wide range of parameters, including:
Digital Power Supply (DPS), Parametric Measurement Units (PMU), Arbitrary
Waveform Generators (AWG), Digitizers, Digital IOs, and utility supplies. Each
of these instruments perform different measurements on the DUT. All of
these instruments must be synchronized so the source and capture
waveforms very precisely aligned — a basic requirement in DSP-based ATE.
The DSP-based signal generation would require a number of sample patterns
to be calculated and be sent very specific times.

Not all devices are tested equally. Testing adds costs, so low cost
components are rarely tested completely, whereas medical or high costs
components (where reliability is important) are frequently tested.

But testing the device for all parameters may or may not be required
depending on the device functionality and end user. For example if the
device finds application in medical or life saving products then many of its
parameters must be tested, and some of the parameters must be
guaranteed. But deciding on the parameters to test is a complex decision
based on cost vs. yield. If the device is a complex digital device, with
thousands of gates, then test fault coverage has to be calculated. Here again
the decision is complex based on test economics, based on frequency,
number and type of I/Os in the device and the end-use application.

ATE automatic test equipment is a vital part of the electronics test scene
today. Automatic test equipment enables printed circuit board test, and
equipment test to be undertaken very swiftly - far faster than if it were done
manually. As time of production staff forms a major element of the overall
production cost of an item of electronics equipment, it is necessary to reduce
the production times as possible. This can be achieved with the use of ATE,
automatic test equipment.

Automatic test equipment can be expensive, and therefore it is necessary to

ensure that the correct philosophy and the correct type or types automatic
test equipment are used. Only by applying the use of automatic test
equipment correctly can the maximum benefits be gained.

There is a variety of different approaches that can be used for automatic test
equipment. Each type has its own advantages and disadvantages, and can be
used to great effect in certain circumstances. When choosing ATE systems it
is necessary to understand the different types of systems and to be able to
apply them correctly.

Types of ATE automatic test systems

There is a good variety of types of ATE systems that can be used. As they
approach electronics test in slightly different ways they are normally suited
to different stages in the production test cycle. The most widely used forms
of ATE, automatic test equipment used today are listed below:
• Automatic optical inspection, AOI: AOI, Automatic Optical
Inspection is widely used in many manufacturing environments. It is
essentially a form of inspection, but achieved automatically. This
provides a much greater degree of repeatability and speed when
compared to manual inspection. AOI, automatic optical inspection it is
particularly useful when situated at the end of a line producing
soldered boards. Here it can quickly locate production problems
including solder defects as well as whether the correct components
and fitted and also whether their orientation is correct. As AOI systems
are generally located immediately after the PCB solders process, any
solder process problems can be resolved quickly and before too many
printed circuit boards are affected.

AOI automatic optical inspection takes time to set up and for the test
equipment to learn the board. Once set it can process boards very
quickly and easily. It is ideal for high volume production. Although the
level of manual intervention is low, it takes time to set up correctly,
and there is a significant investment in the test system itself.

• Automated X-Ray inspection, AXI: Automated X-Ray inspection

has many similarities to AOI. However with the advent of BGA
packages it was necessary to be able to use a form of inspection that
could view items not visible optically. Automated X-Ray inspection, AXI
systems can look through IC packages and examine the solder joints
underneath the package to evaluate the solder joints.

• ICT In circuit test: In-Circuit Test, ICT is a form of ATE that has been
in use for many years and is a particularly effective form of printed
circuit board test. This test technique not only looks at short circuits,
open circuits, component values, but it also checks the operation of
ICs.

Although In Circuit Test, ICT is a very powerful tool, it is limited these

days by lack of access to boards as a result of the high density of
tracks and components in most designs. Pins for contact with the
nodes have to be very accurately placed in view of the very fine
pitches and may not always make good contact. In view of this and the
increasing number of nodes being found on many boards today it is
being used less than in previous years, although it is still widely used.

• Manufacturing Defect Analyzer, MDA: A Manufacturing Defect

Analyzer, MDA is another form of printed circuit board test and it is
effectively a simplified form of ICT. However this form of printed circuit
 board test only tests for manufacturing defects looking at short
circuits, open circuits and looks at some component values. As a result,
the cost of these test systems is much lower than that of a full ICT, but
the fault coverage is less.

• Functional testing, including rack and stack: Functional test can

be considered as any form of electronics testing that exercises the
function of a circuit. There are a number of different approaches that
can be adopted dependent upon the type of circuit (RF, digital,
analogue, etc), the degree of testing required. The main approaches
are outlined below:

1. Functional Automatic Test Equipment, FATE: This term

usually refers to the large functional automatic test equipment
in a specially designed console. These automatic test equipment
systems are generally used for testing digital boards but these
days these large testers are not widely used. The increasing
speeds at which many boards run these days cannot be
accommodated on these testers where leads between the board
under test and the tester measurement or stimulus point can
result in large capacitances that slow the rate of operation
down. In addition to this fixtures are expensive as is the
program development. Despite these drawbacks these testers
may still be used in areas where production volumes are high
and speeds not particularly high. They are generally used for
testing digital boards.

2. Rack and stack test equipment using GPIB: One way in

which boards or units themselves can be tested is using a stack
of remotely controlled test equipment. The most widely method
of controlling the test equipment is still to use the General
Purpose Interface Bus (GPIB). There may also be a test interface
adapter required to control and interface to the item under test.
Whilst the GPIB is relatively slow and has been in existence for
over 30 years it is still widely used as it provides a very flexible
method of test. Laboratory test equipment can often be used as
most items of lab test equipment have a GPIB port. The main
drawback of GPIB is its speed and the cost of writing the
program although packages like Lab View can be used to aid
program generation and execution in the test environment.
Fixtures or test interfaces can also be expensive.
 3. Chassis or rack based test equipment: One of the major
drawbacks of the GPIB rack and stack automatic test equipment
approach is that it occupies a large amount of space, and the
operating speed is limited by the speed of the GPIB. To
overcome these problems a variety of standards for systems
contained within a chassis have been developed.

The idea of containing test instruments within a chassis was first

developed under the VXI (VME extensions for Instrumentation)
guise. The system uses test instruments on a card that can be
slotted into a standard chassis. This saves both space and cost
when compared to the stand-alone instruments as well as
proving an increase in communications speed when compared
to other technologies such as GPIB. Later introductions of PXI
and then PXI Express provided for lower cost instrumentation
while still retaining the advantages of the chassis approach.

Although there is a variety of ATE, automatic test equipment

approaches that can be used, these are some of the more popular
systems in use. They can all use test management software such as
Lab View to assist in the running of the individual tests. This enables
facilities such as the ordering of tests, results collection and printout as
well as results logging, etc.

• JTAG Boundary scan testing: Boundary scan is a form of testing

that has come to the fore in recent years. Also known as JTAG, Joint
Test Action Group, or by its standard IEEE 1149.1, boundary scan
offers significant advantages over more traditional forms of testing and
as such has become one of the major tools in automatic testing.

With the requirement for testing circuit efficiently increasing while test
access is decreasing, efficient methods of testing are needed.
Boundary scan uses special boundary scan ICs that have a shift
register in the output. By connecting boundary scan compatible ICs
serially on a board (or just using the boundary scan chain in an IC for
individual IC testing) and enabling the boundary scan chain, it is
possible to send in a serial data word, and then monitor the exiting
data word. Analyzing the exit data train enables the test information to
be accessed. In this way it is possible to gain a high level of test access
without compromising the circuit.

As a result of its ability to test boards and even ICs with very limited
physical test access, Boundary Scan / JTAG have become very widely
used.
 • Combinational test: No single method of testing is able to provide a
complete solution these days. To help overcome this various ATE
automatic test equipment systems incorporate a variety of test
approaches. These combinational testers are generally used for printed
circuit board testing. By doing this, a single electronics test is able to
gain a much greater level of access for the printed circuit board test,
and the test coverage is much higher. Additionally a combinational
tester is able to undertake a variety of different types of test without
the need to mover the board from one tester to another. In this way a
single suite of tests may include In-circuit testing as well as some
functional tests and then some JTAG boundary scan testing.

Each type of automatic test philosophy has its strengths, and accordingly it is
necessary to choose the correct type of test approach for the testing that is
envisaged.

Test systems range in complexity from (a) labor-intensive manual testing to

(d) fully automatic test equipment. This article focuses on low-budget and
medium-scale test systems (b and c).

Digital Pattern generator

In the world of signal generators used for testing and debugging embedded
systems, we can find 3 categories of instruments, according to the
characteristics of the generated signals and the purpose of generating them.
'Embedded system' should be understood in its broad sense, that is an
electronic system with 'out of the PC' computing resources such as
microprocessor or microcontroller, ASIC, FPGA, SoC (System-on-Chip),
DSP, including analog, digital or mixed-analog/digital systems. Refer to the
table below for an overview.

Digital pattern generator improves semiconductor and digital

system testing during design.

During design, the digital pattern generator is an essential stimulus source

for almost every type of digital device: digital and mixed-signal ASIC, FPGA,
microprocessors and microcontrollers. The digital pattern generator is useful
for functional testing, debug of new designs and failure analysis of existing
designs.

The digital pattern generator can be used early in the design cycle to
substitute for system components that are not yet available. For example, a
digital pattern generator might be programmed to send interrupts and data
to a newly developed bus circuit when the processor that would normally
provide the signals doesn't yet exist.

It allows exploring new test cases – and create infrequently encountered test
conditions to help verify that a code works and is robust enough – and this,
before the complete hardware is even available.
A digital pattern generator can also be used to put a circuit into a desired
state and then let it operate at full speed or step the circuit through a
series of states. Generating the right specific initialization sequences
and configuring control register will help in exploring many modes of
operations of a circuit. Because nowadays circuits use digital interfaces that
may run at more than a few 10th of megahertz, the old way to do it with
microcontrollers coupled with a GPIO is not sufficient any more.

By substituting for missing pieces and offering maximal flexibility when

generating digital logic signals, digital pattern generators will speed up new
product's time-to-market. The digital pattern generator is an effective
solution just about anywhere that complex digital bit streams are needed to
stimulate a device under test (DUT).

Every engineer should have a digital pattern generator.

At Byte Paradigm, we consider that digital pattern generators help overcome

the many challenges of embedded system test, debug and validation.

We share the opinion of the engineers that going on prototype early in the
design cycle speeds up system debug and hence, helps shorten the overall
product design cycle.

Testing a prototyped system basically requires 2 types of tasks:

1) Generating the input stimulus to the system, and

2) Analyzing the system's response.

To solve the 'stimulus-and-response' challenge the engineer will save

valuable design time if he is correctly equipped. There is no doubt that
scopes, logic analyzers and perhaps more specialized analyzers will help
doing the 'analysis job'. They have an important companion for digital
systems: the digital Pattern generator.

Logic Analyzer

A logic analyzer is an electronic instrument which displays signals in a digital

circuit. A logic analyzer may convert the captured data into timing diagrams,
protocol decodes, state machine traces, assembly language, or correlate
assembly with source-level software.

Presently there are three distinct categories of logic analyzers available on

the market:

• The first is mainframes, which consist of a chassis containing the

display, controls, control computer, and multiple slots into which the
actual data capturing hardware is installed.
• The second category is standalone units which integrate everything
into a single package, with options installed at the factory.
• The third category is PC-based logic analyzers. The hardware connects
to a computer through a USB or Ethernet connection and then relays
the captured signals to the software on the computer. These devices
are typically much smaller and less expensive, because they do not
need dedicated displays or hardware input such as keyboards or
knobs.

Uses

Many digital designs, including those of ICs, are simulated to detect defects
before the unit is constructed. The simulation usually provides logic analysis
displays. Often, complex discrete logic is verified by simulating inputs and
testing outputs using boundary scan. Logic analyzers can uncover hardware
defects that are not found in simulation. These problems are typically too
difficult to model in simulation, or too time consuming to simulate and often
cross multiple clock domains.

Basic FPGA Architecture

CLB CLB I/O Blocks (IOBs)

S witch
Ma trix

Configurable
CLB CLB
Logic Blocks (CLBs)

Programmable
Interconnect

I/O Block (IOB)

 • Identical I/O Blocks line the periphery of die

– Input, output, or bi-directional

– Registered, latched, or combinatorial
– Three-state output
– Programmable output slew rate

Configurable Logic Block (CLB)

Y
FFX Q
G
G
1
G
2 G_LUT
G
3 Y
H
4
H
1
H
2 H_LUT
F
3
F
1
F
2
F
3 F_LUT X
4
X
FFY Q

• Combinatorial logic is implemented in Look-up Tables

– Also known as a function generator

– Capacity limited by number of inputs and outputs, not
complexity
– Look-up Tables can be used as synchronous RAM
 Look-Up Tables

• Combinatorial Logic is stored in Look-up Tables (LUTs) in a CLB

• Example

Combinatorial
Logic
A
B Z
C
D

A B C D
Z
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
. . .
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

• Capacity is limited by number of inputs, not complexity

• Delay through CLB is constant
Programmable Interconnect
 CLB CLB

Switch
Matrix

CLB CLB

• Resources to create arbitrary interconnection networks

• Various types of interconnect
– Flexible general-purpose interconnect
– Low-skew long lines
• Internal three-state buffers for buses and wide functions

Xilinx Tool Flow Lab

 Design Entry Synthesis or
HDL or Schematic Schematic Net list

Net list
Functional
Simulation

Implementation

Simulation
BIT File Reports
Net list

Timing
Configure Device
Simulation

Introduction

This lab provides a basic introduction to the ISE software tools. You
will complete and implement an existing Pico Blaze design. Pico Blaze
will be used in the labs throughout this workshop to illustrate the ISE
design flow and various point tools. This is by no means training on
designing with Pico Blaze.

Objectives

After participating in this lab, you will be able to:

• Create a new project
• Simulate a design
• Implement a design

Procedure

This lab comprises five primary steps:

1. Create a new project

2. Add an existing design
3. Complete the design
4. Simulate the design
5. Implement the design
 Below each general instruction for a given procedure, you will find
accompanying step-by-step directions and illustrated figures that
provide more detail for performing the general instruction. If you feel
confident about a specific instruction, feel free to skip the step-by-step
directions and move on to the next general instruction in the
procedure.

Create a New Project Step 1

Create a new project targeting the Spartan-2 device that is on the

Spartan-2 kit. Specify your language of choice, VHDL or Verilog, to
complete the lab.

 Launch ISE: Select Start → All Programs → Xilinx ISE Design

Suite 12 → ISE Design Tools → Project Navigator

 In the Project Navigator, select File → New Project… or click on

. The New Project Wizard opens

 For Project Location, use the “…” button to browse to one of the
following directories, and then click OK
• Verilog users: c:\xup\fpgaflow\labs\verilog\lab1
• VHDL users: c:\xup\fpgaflow\labs\vhdl\lab1

 For Project Name, type Flow_lab, leaving Top-level source type:

as HDL
Figure 1-1. New Project Wizard

 Click Next

 Select the following options and click Next:

Device Family: Spartan2

Device: XC2S200
Package: PQ208
Speed Grade: –5Q
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISE Simulator (VHDL/Verilog)
Preferred Language: Verilog or VHDL (select your preference)
 Select your
Preferred
Language

Figure 1-2. Device and Design Flow Dialog

 Click Finish
 Figure 1-3. Project Summary Dialog

Add an Existing Design to the Project Step 2

Add HDL source files for an example PicoBlaze design. You may review
the PicoBlaze documentation to become familiar with the 8-bit
microcontroller architecture and assembler. Refer to
KCPSM3_manual.pdf in the ..\KCPSM3\docs\ directory.

 Go to Project  Add Copy of Source or click on from the

side button window and browse to the
c:\xup\fpgaflow\KCPSM3\VHDL or Verilog folder

 Select the VHDL/Verilog files kcpsm3_int_test and kcpsm3 files

and click Open

The dialogue below should appear which allows you to select a flow
(none, implementation, simulation, or both) associated with each
source file
 Figure 1-4. Choose Source Type

 Click OK accepting the default setting of All for both source files

Note: You should see a module called int_test listed in the

hierarchy view with an orange question mark. This module is a
BlockRAM that will contain the instructions for the PicoBlaze
controller, which will be added in a later step

Figure 1-5. Design Hierarchy in Sources Window

Complete the Design Step 3

An example assembly (.psm) file called init_test.psm is included with

the PicoBlaze distribution. You will assemble this file to generate the
instruction ROM and add it to the design.

 Open up Windows Explorer and browse to the Assembler provided

in the KCPSM3 sub-directory (c:\xup\fpgaflow\KCPSM3\Assembler)

Note: The KCPSM3.exe assembler and ROM_form* template files

along with two example PSM files should reside in this directory.
Keep in mind that the assembled output files will be generated in
the directory containing the assembler and template files. It may
be beneficial to copy the assembler and template files to your
project directory. For the workshop, we will keep the files in the
current location
 Figure 1-6. PicoBlaze Assembler Files

 Open the int_test.psm file using a standard text editor, such as

Wordpad, and review the code, refering to the PicoBlaze 8-bit
Embedded Microcontroller User Guide or KCPSM3 manual for
technical guidance. These documents are provided in the docs
sub-directory

 Open a command window by going to Start  All Programs 

Accessories  Command Prompt

 Browse to the Assembler directory using the cd command

> cd c:\xup\fpgaflow\KCPSM3\Assembler

 Generate the ROM definition files by assembling the example

assembly application. Enter the following command at the
command prompt
> kcpsm3 int_test.psm

Note: You should now see several files in the Assembler sub-
directory starting with init_test*, including VHDL (int_test.vhd)
and Verilog (int_test.v) ROM definition files

 Add the Verilog or VHDL ROM definition file to the project. Go to

Project  Add Copy of Source or click on from the side button

window and select either int_test.vhd or int_test.v file (Figure 1-7)
 Verilog and VHDL
ROM Definition
Files

Figure 1-7. VHDL and Verilog ROM Definition Files

 Click Open and then OK to add INT_TEST as a VHDL/Verilog

Design File to the project (Figure 1-8)

Figure 1-8. Hierarchical view of PicoBlaze design

Note: The top-level kcpsm3_int_test file contains an instantiation

of the int_test ROM definition file. After adding this source code
for the int_test to the design, the red question mark in the module
view will disappear as it is no longer seen as a black box

Simulate the Design Step 4

Add the testbench and review the code. Run a behavioral simulation
using the Xilinx ISIM simulator and analyze the results.

 Go to Project  Add Copy of Source or click on and browse

to c:\xup\fpgaflow\KCPSM3\vhdl (or verilog)

 Select the testbench file (test_bench.vhd or testbench.v) and

click Open
 Set the association to Simulation and click OK to add the test
bench to the project. Click Simulation in the View pane, select
Behavioral and click testbench-behavior in the Hierarchy window.

Figure 1-9. Hierarchical View Including Test Bench

 Expand the ISim Simulator toolbox in the Processes window, right-

click on Simulate Behavioral Model, and select Process
Properties

 Enter the value of 25000 for the Simulation Run Time and click
OK

Figure 1-10. ISIM Behavioral Simulation Properties

 Double-click Simulate Behavioral Model to simulate the design

(Figure 1-11). Click on Zoom to Full View button. Click close to
1 us time in the waveform window. Click Zoom In couple of times
to see the activity happening between 0 and 3 us. Change radix of
waveforms signal by selecting it in the Name column of the
waveform window, right-click, select Radix followed by
 Hexadecimal. You should see three input interrupt pulses and the
displayed interrupt count value. You should also see an alternating
inverted pattern displayed

Figure 1-11. iSIM Behavioral Simulation Results

The steps below are for illustrative purposes only, and show how to
analyze the internal signals of the design. The first step shows how to
add internal signals to the waveform. The second step shows how to
analyze the interrupt process. The third step shows how to analyze the
output waveform process. You may optionally complete these steps if
you have additional time at the end of the lab.

 Monitor internal signals by adding them to the design

You need to expand the design hierarchy and select the desired
module entry [uut] in Instance and Process Name window, and
then select the desired signal [address] in Simulation Objects
window. Right-click on it and select Add to Wave Configuration.
Similarly add interrupt, interrupt_ack, and instruction signals
Figure 1-12. Accessing Internal Signals

 Change radix of address and instructions to hexadecimal. Enter

25.00us in in the tool buttons bar where 1.00us is
displayed; click Simulation  Restart, followed by Simulation 
Run to re-simulate the design. Using buttons from
toolbar, you can zoom into any area of the simulator waveform
window. Analyze the waveform for Interrupt Service Routine
process (Figure 1-13)
 Figure 1-13. Interrupt Service routine

 Add write_stribe signal and re-simulate the design. Analyze the

output waveform process (Figure 1-14)

Figure 1-14. Output Waveform

Note: The int_test.log file in the Assembly directory shows the

address and code for each instruction

 Close the simulator windows. Click Yes to quit the simulator

without saving the run

Implement the Design Step 5

Implement the design. During implementation, some reports will be

created. You will look more closely at some of these reports in a later
module.

 In the Sources in Project window, select Implementation in the

View pane and select the top-level design file
kcpsm3_int_test.vhd/v (Figure 1-15). Make sure that symbol
appears in front of uut instance. If not, right-click on the uut
instance and select Set as Top Module. Click OK on the message
Figure 1-15. Sources Window Pane

 In the Processes for Source window, double-click Implement

Design (Figure 1-16)

Notice that the tools run all of the processes required to implement
the design. In this case, the tools run Synthesis before going into
Implementation

Figure 1-16. Processes for Source Window

 While the implementation is running, click the + next to

Implement Design to expand the implementation step and view
the progress. We refer to this as expanding a process
 After each stage is completed, a symbol will appear next to each
stage:

Check mark for successful

Exclamation point for warnings
X for errors

For this particular design, there may be an exclamation point

(warnings) for some steps. The warnings here are okay to ignore.

 Read some of the messages in the message window located across

the bottom of the Project Navigator window

 When implementation is complete, double-click on

in Processes window to review the
design utilization in the Design Summary window (Figure 1-17)
Figure 1-17. Design Summary
 Kit manual Feature used

Seven Segment LED Display

The SPARTAN-II VTU board has a Six-character, seven segment LED

display controlled by FPGA user-I/O pins. Each digit shares eight
common control signals to light individual LED segments.Each
individual character has a separate cathode control input.
To light an individual signal, drive the individual segment control
signal High along with the associated cathode control signal for the
individual character. The control signal is high, enabling the control
inputs for the left-most character. The segment control inputs, A
through G and DP, drive the individual segments that comprise the
character. A High value lights the individual segment, a Low turns
off the segment.

The two types of the seven segment displays are as shown below
• Common Cathode Display: In this type of display the cathode of
all the LEDs are tied together and the anode terminals decides the
status of the LED, either ON or OFF.
• To turn ON the LED i.e. segment value of driven segment should
be 1 and 0 for turn OFF.

• Common Anode Display: In this type of display all the anode

terminals of LEDs are tied together and the cathode terminals
decide the status of the LED either ON or OFF.
• To turn ON the LED i.e. segment value of driven segment should
be 0 and 1 for turn OFF.

DIP Switches

The SPARTAN –II VTU board has 32 DIP switches.

A 4.7KΩ series resistor provides nominal input protection.
When in the UP or ON position, a switch connects the FPGA pin to V
CCO , a logic High. When DOWN or in the OFF position, the switch
connects the FPGA pin to ground, a logic Low. The switches
typically exhibit about 2 ms of mechanical bounce and there is no
active debouncing circuitry, although such circuitry could easily be
added to the FPGA design programmed on the board.
 LEDS
The SPARTAN II based VLSI Trainer Unit board has 32 multicoloured
LEDs located above the key switches, indicated in Figure 1. The
LEDs are labelled LED31 through LED0.Table 13 shows the FPGA
connections to the LEDs.
A series current limiting resistor of 270Ω is associated with every
LED. To light an individual LED, drive the associated FPGA control
signal High